hw-me.c 39.9 KB
Newer Older
1
// SPDX-License-Identifier: GPL-2.0
O
Oren Weil 已提交
2
/*
3
 * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
O
Oren Weil 已提交
4 5 6 7
 * Intel Management Engine Interface (Intel MEI) Linux driver
 */

#include <linux/pci.h>
8 9 10

#include <linux/kthread.h>
#include <linux/interrupt.h>
11
#include <linux/pm_runtime.h>
12
#include <linux/sizes.h>
13
#include <linux/delay.h>
14 15

#include "mei_dev.h"
16 17
#include "hbm.h"

18 19
#include "hw-me.h"
#include "hw-me-regs.h"
20

T
Tomas Winkler 已提交
21 22
#include "mei-trace.h"

23
/**
24
 * mei_me_reg_read - Reads 32bit data from the mei device
25
 *
26
 * @hw: the me hardware structure
27 28
 * @offset: offset from which to read the data
 *
29
 * Return: register value (u32)
30
 */
31
static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
32 33
			       unsigned long offset)
{
34
	return ioread32(hw->mem_addr + offset);
35 36 37 38
}


/**
39
 * mei_me_reg_write - Writes 32bit data to the mei device
40
 *
41
 * @hw: the me hardware structure
42 43 44
 * @offset: offset from which to write the data
 * @value: register value to write (u32)
 */
45
static inline void mei_me_reg_write(const struct mei_me_hw *hw,
46 47
				 unsigned long offset, u32 value)
{
48
	iowrite32(value, hw->mem_addr + offset);
49
}
O
Oren Weil 已提交
50

51
/**
52
 * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
T
Tomas Winkler 已提交
53
 *  read window register
54 55 56
 *
 * @dev: the device structure
 *
57
 * Return: ME_CB_RW register value (u32)
58
 */
59
static inline u32 mei_me_mecbrw_read(const struct mei_device *dev)
60
{
61
	return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
62
}
63 64 65 66 67 68 69 70 71 72 73 74

/**
 * mei_me_hcbww_write - write 32bit data to the host circular buffer
 *
 * @dev: the device structure
 * @data: 32bit data to be written to the host circular buffer
 */
static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data)
{
	mei_me_reg_write(to_me_hw(dev), H_CB_WW, data);
}

75
/**
76
 * mei_me_mecsr_read - Reads 32bit data from the ME CSR
77
 *
78
 * @dev: the device structure
79
 *
80
 * Return: ME_CSR_HA register value (u32)
81
 */
82
static inline u32 mei_me_mecsr_read(const struct mei_device *dev)
83
{
T
Tomas Winkler 已提交
84 85 86 87 88 89
	u32 reg;

	reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA);
	trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg);

	return reg;
90
}
O
Oren Weil 已提交
91 92

/**
T
Tomas Winkler 已提交
93 94
 * mei_hcsr_read - Reads 32bit data from the host CSR
 *
95
 * @dev: the device structure
T
Tomas Winkler 已提交
96
 *
97
 * Return: H_CSR register value (u32)
T
Tomas Winkler 已提交
98
 */
99
static inline u32 mei_hcsr_read(const struct mei_device *dev)
T
Tomas Winkler 已提交
100
{
T
Tomas Winkler 已提交
101 102 103 104 105 106
	u32 reg;

	reg = mei_me_reg_read(to_me_hw(dev), H_CSR);
	trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg);

	return reg;
107 108 109 110 111 112 113 114 115 116
}

/**
 * mei_hcsr_write - writes H_CSR register to the mei device
 *
 * @dev: the device structure
 * @reg: new register value
 */
static inline void mei_hcsr_write(struct mei_device *dev, u32 reg)
{
T
Tomas Winkler 已提交
117
	trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg);
118
	mei_me_reg_write(to_me_hw(dev), H_CSR, reg);
T
Tomas Winkler 已提交
119 120 121 122
}

/**
 * mei_hcsr_set - writes H_CSR register to the mei device,
O
Oren Weil 已提交
123 124
 * and ignores the H_IS bit for it is write-one-to-zero.
 *
125 126
 * @dev: the device structure
 * @reg: new register value
O
Oren Weil 已提交
127
 */
128
static inline void mei_hcsr_set(struct mei_device *dev, u32 reg)
O
Oren Weil 已提交
129
{
130
	reg &= ~H_CSR_IS_MASK;
131
	mei_hcsr_write(dev, reg);
O
Oren Weil 已提交
132 133
}

134 135 136 137 138 139 140 141 142 143 144 145 146
/**
 * mei_hcsr_set_hig - set host interrupt (set H_IG)
 *
 * @dev: the device structure
 */
static inline void mei_hcsr_set_hig(struct mei_device *dev)
{
	u32 hcsr;

	hcsr = mei_hcsr_read(dev) | H_IG;
	mei_hcsr_set(dev, hcsr);
}

147 148 149 150 151 152 153 154 155 156 157 158
/**
 * mei_me_d0i3c_read - Reads 32bit data from the D0I3C register
 *
 * @dev: the device structure
 *
 * Return: H_D0I3C register value (u32)
 */
static inline u32 mei_me_d0i3c_read(const struct mei_device *dev)
{
	u32 reg;

	reg = mei_me_reg_read(to_me_hw(dev), H_D0I3C);
159
	trace_mei_reg_read(dev->dev, "H_D0I3C", H_D0I3C, reg);
160 161 162 163 164 165 166 167 168 169 170 171

	return reg;
}

/**
 * mei_me_d0i3c_write - writes H_D0I3C register to device
 *
 * @dev: the device structure
 * @reg: new register value
 */
static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg)
{
172
	trace_mei_reg_write(dev->dev, "H_D0I3C", H_D0I3C, reg);
173 174 175
	mei_me_reg_write(to_me_hw(dev), H_D0I3C, reg);
}

176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196
/**
 * mei_me_trc_status - read trc status register
 *
 * @dev: mei device
 * @trc: trc status register value
 *
 * Return: 0 on success, error otherwise
 */
static int mei_me_trc_status(struct mei_device *dev, u32 *trc)
{
	struct mei_me_hw *hw = to_me_hw(dev);

	if (!hw->cfg->hw_trc_supported)
		return -EOPNOTSUPP;

	*trc = mei_me_reg_read(hw, ME_TRC);
	trace_mei_reg_read(dev->dev, "ME_TRC", ME_TRC, *trc);

	return 0;
}

197 198 199 200 201
/**
 * mei_me_fw_status - read fw status register from pci config space
 *
 * @dev: mei device
 * @fw_status: fw status register values
A
Alexander Usyskin 已提交
202 203
 *
 * Return: 0 on success, error otherwise
204 205 206 207
 */
static int mei_me_fw_status(struct mei_device *dev,
			    struct mei_fw_status *fw_status)
{
208 209
	struct mei_me_hw *hw = to_me_hw(dev);
	const struct mei_fw_status *fw_src = &hw->cfg->fw_status;
210 211 212
	int ret;
	int i;

213
	if (!fw_status || !hw->read_fws)
214 215 216 217
		return -EINVAL;

	fw_status->count = fw_src->count;
	for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
218 219 220
		ret = hw->read_fws(dev, fw_src->status[i],
				   &fw_status->status[i]);
		trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_X",
221 222
				       fw_src->status[i],
				       fw_status->status[i]);
223 224 225 226 227 228
		if (ret)
			return ret;
	}

	return 0;
}
229 230

/**
231
 * mei_me_hw_config - configure hw dependent settings
232 233
 *
 * @dev: mei device
234 235 236 237 238
 *
 * Return:
 *  * -EINVAL when read_fws is not set
 *  * 0 on success
 *
239
 */
240
static int mei_me_hw_config(struct mei_device *dev)
241
{
242
	struct mei_me_hw *hw = to_me_hw(dev);
243 244
	u32 hcsr, reg;

245 246 247
	if (WARN_ON(!hw->read_fws))
		return -EINVAL;

248
	/* Doesn't change in runtime */
249
	hcsr = mei_hcsr_read(dev);
250
	hw->hbuf_depth = (hcsr & H_CBD) >> 24;
251

252
	reg = 0;
253
	hw->read_fws(dev, PCI_CFG_HFS_1, &reg);
254
	trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg);
255 256
	hw->d0i3_supported =
		((reg & PCI_CFG_HFS_1_D0I3_MSK) == PCI_CFG_HFS_1_D0I3_MSK);
257 258 259 260 261 262 263

	hw->pg_state = MEI_PG_OFF;
	if (hw->d0i3_supported) {
		reg = mei_me_d0i3c_read(dev);
		if (reg & H_D0I3C_I3)
			hw->pg_state = MEI_PG_ON;
	}
264 265

	return 0;
266
}
267 268 269 270 271

/**
 * mei_me_pg_state  - translate internal pg state
 *   to the mei power gating state
 *
A
Alexander Usyskin 已提交
272 273 274
 * @dev:  mei device
 *
 * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
275 276 277
 */
static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)
{
278
	struct mei_me_hw *hw = to_me_hw(dev);
279

280
	return hw->pg_state;
281 282
}

283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301
static inline u32 me_intr_src(u32 hcsr)
{
	return hcsr & H_CSR_IS_MASK;
}

/**
 * me_intr_disable - disables mei device interrupts
 *      using supplied hcsr register value.
 *
 * @dev: the device structure
 * @hcsr: supplied hcsr register value
 */
static inline void me_intr_disable(struct mei_device *dev, u32 hcsr)
{
	hcsr &= ~H_CSR_IE_MASK;
	mei_hcsr_set(dev, hcsr);
}

/**
302
 * me_intr_clear - clear and stop interrupts
303 304 305 306 307 308 309 310 311 312
 *
 * @dev: the device structure
 * @hcsr: supplied hcsr register value
 */
static inline void me_intr_clear(struct mei_device *dev, u32 hcsr)
{
	if (me_intr_src(hcsr))
		mei_hcsr_write(dev, hcsr);
}

O
Oren Weil 已提交
313
/**
A
Alexander Usyskin 已提交
314
 * mei_me_intr_clear - clear and stop interrupts
315 316 317
 *
 * @dev: the device structure
 */
318
static void mei_me_intr_clear(struct mei_device *dev)
319
{
320
	u32 hcsr = mei_hcsr_read(dev);
321

322
	me_intr_clear(dev, hcsr);
323 324
}
/**
325
 * mei_me_intr_enable - enables mei device interrupts
O
Oren Weil 已提交
326 327 328
 *
 * @dev: the device structure
 */
329
static void mei_me_intr_enable(struct mei_device *dev)
O
Oren Weil 已提交
330
{
331 332 333 334
	u32 hcsr;

	if (mei_me_hw_use_polling(to_me_hw(dev)))
		return;
335

336
	hcsr = mei_hcsr_read(dev) | H_CSR_IE_MASK;
337
	mei_hcsr_set(dev, hcsr);
O
Oren Weil 已提交
338 339 340
}

/**
A
Alexander Usyskin 已提交
341
 * mei_me_intr_disable - disables mei device interrupts
O
Oren Weil 已提交
342 343 344
 *
 * @dev: the device structure
 */
345
static void mei_me_intr_disable(struct mei_device *dev)
O
Oren Weil 已提交
346
{
347
	u32 hcsr = mei_hcsr_read(dev);
348

349
	me_intr_disable(dev, hcsr);
O
Oren Weil 已提交
350 351
}

352 353 354 355 356 357 358
/**
 * mei_me_synchronize_irq - wait for pending IRQ handlers
 *
 * @dev: the device structure
 */
static void mei_me_synchronize_irq(struct mei_device *dev)
{
359
	struct mei_me_hw *hw = to_me_hw(dev);
360

361 362 363
	if (mei_me_hw_use_polling(hw))
		return;

364
	synchronize_irq(hw->irq);
365 366
}

367 368 369 370 371 372 373
/**
 * mei_me_hw_reset_release - release device from the reset
 *
 * @dev: the device structure
 */
static void mei_me_hw_reset_release(struct mei_device *dev)
{
374
	u32 hcsr = mei_hcsr_read(dev);
375 376 377

	hcsr |= H_IG;
	hcsr &= ~H_RST;
378
	mei_hcsr_set(dev, hcsr);
379
}
380

381
/**
382
 * mei_me_host_set_ready - enable device
383
 *
A
Alexander Usyskin 已提交
384
 * @dev: mei device
385
 */
386
static void mei_me_host_set_ready(struct mei_device *dev)
387
{
388
	u32 hcsr = mei_hcsr_read(dev);
389

390 391 392 393
	if (!mei_me_hw_use_polling(to_me_hw(dev)))
		hcsr |= H_CSR_IE_MASK;

	hcsr |=  H_IG | H_RDY;
394
	mei_hcsr_set(dev, hcsr);
395
}
A
Alexander Usyskin 已提交
396

397
/**
398
 * mei_me_host_is_ready - check whether the host has turned ready
399
 *
400 401
 * @dev: mei device
 * Return: bool
402
 */
403
static bool mei_me_host_is_ready(struct mei_device *dev)
404
{
405
	u32 hcsr = mei_hcsr_read(dev);
406

407
	return (hcsr & H_RDY) == H_RDY;
408 409 410
}

/**
411
 * mei_me_hw_is_ready - check whether the me(hw) has turned ready
412
 *
413 414
 * @dev: mei device
 * Return: bool
415
 */
416
static bool mei_me_hw_is_ready(struct mei_device *dev)
417
{
418
	u32 mecsr = mei_me_mecsr_read(dev);
419

420
	return (mecsr & ME_RDY_HRA) == ME_RDY_HRA;
421
}
422

423 424 425 426 427 428 429 430 431 432 433 434 435
/**
 * mei_me_hw_is_resetting - check whether the me(hw) is in reset
 *
 * @dev: mei device
 * Return: bool
 */
static bool mei_me_hw_is_resetting(struct mei_device *dev)
{
	u32 mecsr = mei_me_mecsr_read(dev);

	return (mecsr & ME_RST_HRA) == ME_RST_HRA;
}

436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458
/**
 * mei_gsc_pxp_check - check for gsc firmware entering pxp mode
 *
 * @dev: the device structure
 */
static void mei_gsc_pxp_check(struct mei_device *dev)
{
	struct mei_me_hw *hw = to_me_hw(dev);
	u32 fwsts5 = 0;

	if (dev->pxp_mode == MEI_DEV_PXP_DEFAULT)
		return;

	hw->read_fws(dev, PCI_CFG_HFS_5, &fwsts5);
	trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_5", PCI_CFG_HFS_5, fwsts5);
	if ((fwsts5 & GSC_CFG_HFS_5_BOOT_TYPE_MSK) == GSC_CFG_HFS_5_BOOT_TYPE_PXP) {
		dev_dbg(dev->dev, "pxp mode is ready 0x%08x\n", fwsts5);
		dev->pxp_mode = MEI_DEV_PXP_READY;
	} else {
		dev_dbg(dev->dev, "pxp mode is not ready 0x%08x\n", fwsts5);
	}
}

A
Alexander Usyskin 已提交
459 460 461 462 463 464 465
/**
 * mei_me_hw_ready_wait - wait until the me(hw) has turned ready
 *  or timeout is reached
 *
 * @dev: mei device
 * Return: 0 on success, error otherwise
 */
T
Tomas Winkler 已提交
466 467 468
static int mei_me_hw_ready_wait(struct mei_device *dev)
{
	mutex_unlock(&dev->device_lock);
469
	wait_event_timeout(dev->wait_hw_ready,
470
			dev->recvd_hw_ready,
471
			dev->timeouts.hw_ready);
T
Tomas Winkler 已提交
472
	mutex_lock(&dev->device_lock);
473
	if (!dev->recvd_hw_ready) {
474
		dev_err(dev->dev, "wait hw ready failed\n");
475
		return -ETIME;
T
Tomas Winkler 已提交
476 477
	}

478 479
	mei_gsc_pxp_check(dev);

480
	mei_me_hw_reset_release(dev);
T
Tomas Winkler 已提交
481 482 483 484
	dev->recvd_hw_ready = false;
	return 0;
}

A
Alexander Usyskin 已提交
485 486 487 488 489 490
/**
 * mei_me_hw_start - hw start routine
 *
 * @dev: mei device
 * Return: 0 on success, error otherwise
 */
T
Tomas Winkler 已提交
491 492 493
static int mei_me_hw_start(struct mei_device *dev)
{
	int ret = mei_me_hw_ready_wait(dev);
494

T
Tomas Winkler 已提交
495 496
	if (ret)
		return ret;
497
	dev_dbg(dev->dev, "hw is ready\n");
T
Tomas Winkler 已提交
498 499 500 501 502 503

	mei_me_host_set_ready(dev);
	return ret;
}


O
Oren Weil 已提交
504
/**
505
 * mei_hbuf_filled_slots - gets number of device filled buffer slots
O
Oren Weil 已提交
506
 *
507
 * @dev: the device structure
O
Oren Weil 已提交
508
 *
509
 * Return: number of filled slots
O
Oren Weil 已提交
510
 */
511
static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
O
Oren Weil 已提交
512
{
513
	u32 hcsr;
O
Oren Weil 已提交
514 515
	char read_ptr, write_ptr;

516
	hcsr = mei_hcsr_read(dev);
517

518 519
	read_ptr = (char) ((hcsr & H_CBRP) >> 8);
	write_ptr = (char) ((hcsr & H_CBWP) >> 16);
O
Oren Weil 已提交
520 521 522 523 524

	return (unsigned char) (write_ptr - read_ptr);
}

/**
525
 * mei_me_hbuf_is_empty - checks if host buffer is empty.
O
Oren Weil 已提交
526 527 528
 *
 * @dev: the device structure
 *
529
 * Return: true if empty, false - otherwise.
O
Oren Weil 已提交
530
 */
531
static bool mei_me_hbuf_is_empty(struct mei_device *dev)
O
Oren Weil 已提交
532
{
533
	return mei_hbuf_filled_slots(dev) == 0;
O
Oren Weil 已提交
534 535 536
}

/**
537
 * mei_me_hbuf_empty_slots - counts write empty slots.
O
Oren Weil 已提交
538 539 540
 *
 * @dev: the device structure
 *
541
 * Return: -EOVERFLOW if overflow, otherwise empty slots count
O
Oren Weil 已提交
542
 */
543
static int mei_me_hbuf_empty_slots(struct mei_device *dev)
O
Oren Weil 已提交
544
{
545
	struct mei_me_hw *hw = to_me_hw(dev);
546
	unsigned char filled_slots, empty_slots;
O
Oren Weil 已提交
547

548
	filled_slots = mei_hbuf_filled_slots(dev);
549
	empty_slots = hw->hbuf_depth - filled_slots;
O
Oren Weil 已提交
550 551

	/* check for overflow */
552
	if (filled_slots > hw->hbuf_depth)
O
Oren Weil 已提交
553 554 555 556 557
		return -EOVERFLOW;

	return empty_slots;
}

A
Alexander Usyskin 已提交
558
/**
559
 * mei_me_hbuf_depth - returns depth of the hw buffer.
A
Alexander Usyskin 已提交
560 561 562
 *
 * @dev: the device structure
 *
563
 * Return: size of hw buffer in slots
A
Alexander Usyskin 已提交
564
 */
565
static u32 mei_me_hbuf_depth(const struct mei_device *dev)
566
{
567 568 569
	struct mei_me_hw *hw = to_me_hw(dev);

	return hw->hbuf_depth;
570 571
}

O
Oren Weil 已提交
572
/**
573
 * mei_me_hbuf_write - writes a message to host hw buffer.
O
Oren Weil 已提交
574 575
 *
 * @dev: the device structure
576 577 578 579
 * @hdr: header of message
 * @hdr_len: header length in bytes: must be multiplication of a slot (4bytes)
 * @data: payload
 * @data_len: payload length in bytes
O
Oren Weil 已提交
580
 *
581
 * Return: 0 if success, < 0 - otherwise.
O
Oren Weil 已提交
582
 */
583
static int mei_me_hbuf_write(struct mei_device *dev,
584 585
			     const void *hdr, size_t hdr_len,
			     const void *data, size_t data_len)
O
Oren Weil 已提交
586
{
T
Tomas Winkler 已提交
587
	unsigned long rem;
588
	unsigned long i;
589
	const u32 *reg_buf;
T
Tomas Winkler 已提交
590
	u32 dw_cnt;
591
	int empty_slots;
O
Oren Weil 已提交
592

593 594 595 596
	if (WARN_ON(!hdr || !data || hdr_len & 0x3))
		return -EINVAL;

	dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr));
O
Oren Weil 已提交
597

598
	empty_slots = mei_hbuf_empty_slots(dev);
599
	dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots);
O
Oren Weil 已提交
600

601 602 603
	if (empty_slots < 0)
		return -EOVERFLOW;

604
	dw_cnt = mei_data2slots(hdr_len + data_len);
605
	if (dw_cnt > (u32)empty_slots)
606
		return -EMSGSIZE;
O
Oren Weil 已提交
607

608 609 610
	reg_buf = hdr;
	for (i = 0; i < hdr_len / MEI_SLOT_SIZE; i++)
		mei_me_hcbww_write(dev, reg_buf[i]);
O
Oren Weil 已提交
611

612 613
	reg_buf = data;
	for (i = 0; i < data_len / MEI_SLOT_SIZE; i++)
614
		mei_me_hcbww_write(dev, reg_buf[i]);
O
Oren Weil 已提交
615

616
	rem = data_len & 0x3;
617 618
	if (rem > 0) {
		u32 reg = 0;
619

620
		memcpy(&reg, (const u8 *)data + data_len - rem, rem);
621
		mei_me_hcbww_write(dev, reg);
O
Oren Weil 已提交
622 623
	}

624
	mei_hcsr_set_hig(dev);
625
	if (!mei_me_hw_is_ready(dev))
626
		return -EIO;
O
Oren Weil 已提交
627

628
	return 0;
O
Oren Weil 已提交
629 630 631
}

/**
632
 * mei_me_count_full_read_slots - counts read full slots.
O
Oren Weil 已提交
633 634 635
 *
 * @dev: the device structure
 *
636
 * Return: -EOVERFLOW if overflow, otherwise filled slots count
O
Oren Weil 已提交
637
 */
638
static int mei_me_count_full_read_slots(struct mei_device *dev)
O
Oren Weil 已提交
639
{
640
	u32 me_csr;
O
Oren Weil 已提交
641 642 643
	char read_ptr, write_ptr;
	unsigned char buffer_depth, filled_slots;

644
	me_csr = mei_me_mecsr_read(dev);
645 646 647
	buffer_depth = (unsigned char)((me_csr & ME_CBD_HRA) >> 24);
	read_ptr = (char) ((me_csr & ME_CBRP_HRA) >> 8);
	write_ptr = (char) ((me_csr & ME_CBWP_HRA) >> 16);
O
Oren Weil 已提交
648 649 650 651 652 653
	filled_slots = (unsigned char) (write_ptr - read_ptr);

	/* check for overflow */
	if (filled_slots > buffer_depth)
		return -EOVERFLOW;

654
	dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots);
O
Oren Weil 已提交
655 656 657 658
	return (int)filled_slots;
}

/**
659
 * mei_me_read_slots - reads a message from mei device.
O
Oren Weil 已提交
660 661 662 663
 *
 * @dev: the device structure
 * @buffer: message buffer will be written
 * @buffer_length: message size will be read
A
Alexander Usyskin 已提交
664 665
 *
 * Return: always 0
O
Oren Weil 已提交
666
 */
667
static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
668
			     unsigned long buffer_length)
O
Oren Weil 已提交
669
{
670
	u32 *reg_buf = (u32 *)buffer;
O
Oren Weil 已提交
671

672
	for (; buffer_length >= MEI_SLOT_SIZE; buffer_length -= MEI_SLOT_SIZE)
673
		*reg_buf++ = mei_me_mecbrw_read(dev);
O
Oren Weil 已提交
674 675

	if (buffer_length > 0) {
676
		u32 reg = mei_me_mecbrw_read(dev);
677

678
		memcpy(reg_buf, &reg, buffer_length);
O
Oren Weil 已提交
679 680
	}

681
	mei_hcsr_set_hig(dev);
682
	return 0;
O
Oren Weil 已提交
683 684
}

685
/**
686
 * mei_me_pg_set - write pg enter register
687 688 689
 *
 * @dev: the device structure
 */
690
static void mei_me_pg_set(struct mei_device *dev)
691 692
{
	struct mei_me_hw *hw = to_me_hw(dev);
T
Tomas Winkler 已提交
693 694 695 696
	u32 reg;

	reg = mei_me_reg_read(hw, H_HPG_CSR);
	trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
697

698
	reg |= H_HPG_CSR_PGI;
T
Tomas Winkler 已提交
699 700

	trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
701 702 703 704
	mei_me_reg_write(hw, H_HPG_CSR, reg);
}

/**
705
 * mei_me_pg_unset - write pg exit register
706 707 708
 *
 * @dev: the device structure
 */
709
static void mei_me_pg_unset(struct mei_device *dev)
710 711
{
	struct mei_me_hw *hw = to_me_hw(dev);
T
Tomas Winkler 已提交
712 713 714 715
	u32 reg;

	reg = mei_me_reg_read(hw, H_HPG_CSR);
	trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
716 717 718 719

	WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n");

	reg |= H_HPG_CSR_PGIHEXR;
T
Tomas Winkler 已提交
720 721

	trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
722 723 724
	mei_me_reg_write(hw, H_HPG_CSR, reg);
}

725
/**
726
 * mei_me_pg_legacy_enter_sync - perform legacy pg entry procedure
727 728 729
 *
 * @dev: the device structure
 *
730
 * Return: 0 on success an error code otherwise
731
 */
732
static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
733 734 735 736 737 738 739 740 741 742 743 744
{
	struct mei_me_hw *hw = to_me_hw(dev);
	int ret;

	dev->pg_event = MEI_PG_EVENT_WAIT;

	ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
	if (ret)
		return ret;

	mutex_unlock(&dev->device_lock);
	wait_event_timeout(dev->wait_pg,
745 746
		dev->pg_event == MEI_PG_EVENT_RECEIVED,
		dev->timeouts.pgi);
747 748 749
	mutex_lock(&dev->device_lock);

	if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
750
		mei_me_pg_set(dev);
751 752 753 754 755 756 757 758 759 760 761 762
		ret = 0;
	} else {
		ret = -ETIME;
	}

	dev->pg_event = MEI_PG_EVENT_IDLE;
	hw->pg_state = MEI_PG_ON;

	return ret;
}

/**
763
 * mei_me_pg_legacy_exit_sync - perform legacy pg exit procedure
764 765 766
 *
 * @dev: the device structure
 *
767
 * Return: 0 on success an error code otherwise
768
 */
769
static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
770 771 772 773 774 775 776 777 778
{
	struct mei_me_hw *hw = to_me_hw(dev);
	int ret;

	if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
		goto reply;

	dev->pg_event = MEI_PG_EVENT_WAIT;

779
	mei_me_pg_unset(dev);
780 781 782

	mutex_unlock(&dev->device_lock);
	wait_event_timeout(dev->wait_pg,
783 784
		dev->pg_event == MEI_PG_EVENT_RECEIVED,
		dev->timeouts.pgi);
785 786 787
	mutex_lock(&dev->device_lock);

reply:
788 789 790 791 792 793 794 795 796 797 798 799
	if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
		ret = -ETIME;
		goto out;
	}

	dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
	ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD);
	if (ret)
		return ret;

	mutex_unlock(&dev->device_lock);
	wait_event_timeout(dev->wait_pg,
800 801
		dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
		dev->timeouts.pgi);
802 803 804 805
	mutex_lock(&dev->device_lock);

	if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED)
		ret = 0;
806 807 808
	else
		ret = -ETIME;

809
out:
810 811 812 813 814 815
	dev->pg_event = MEI_PG_EVENT_IDLE;
	hw->pg_state = MEI_PG_OFF;

	return ret;
}

816 817 818 819 820 821 822 823 824 825 826 827 828
/**
 * mei_me_pg_in_transition - is device now in pg transition
 *
 * @dev: the device structure
 *
 * Return: true if in pg transition, false otherwise
 */
static bool mei_me_pg_in_transition(struct mei_device *dev)
{
	return dev->pg_event >= MEI_PG_EVENT_WAIT &&
	       dev->pg_event <= MEI_PG_EVENT_INTR_WAIT;
}

829 830 831 832 833
/**
 * mei_me_pg_is_enabled - detect if PG is supported by HW
 *
 * @dev: the device structure
 *
834
 * Return: true is pg supported, false otherwise
835 836 837
 */
static bool mei_me_pg_is_enabled(struct mei_device *dev)
{
838
	struct mei_me_hw *hw = to_me_hw(dev);
839
	u32 reg = mei_me_mecsr_read(dev);
840

841 842 843
	if (hw->d0i3_supported)
		return true;

844 845 846
	if ((reg & ME_PGIC_HRA) == 0)
		goto notsupported;

847
	if (!dev->hbm_f_pg_supported)
848 849 850 851 852
		goto notsupported;

	return true;

notsupported:
853 854
	dev_dbg(dev->dev, "pg: not supported: d0i3 = %d HGP = %d hbm version %d.%d ?= %d.%d\n",
		hw->d0i3_supported,
855 856 857 858 859 860 861 862 863
		!!(reg & ME_PGIC_HRA),
		dev->version.major_version,
		dev->version.minor_version,
		HBM_MAJOR_VERSION_PGI,
		HBM_MINOR_VERSION_PGI);

	return false;
}

864
/**
865
 * mei_me_d0i3_set - write d0i3 register bit on mei device.
866 867
 *
 * @dev: the device structure
868 869 870
 * @intr: ask for interrupt
 *
 * Return: D0I3C register value
871
 */
872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936
static u32 mei_me_d0i3_set(struct mei_device *dev, bool intr)
{
	u32 reg = mei_me_d0i3c_read(dev);

	reg |= H_D0I3C_I3;
	if (intr)
		reg |= H_D0I3C_IR;
	else
		reg &= ~H_D0I3C_IR;
	mei_me_d0i3c_write(dev, reg);
	/* read it to ensure HW consistency */
	reg = mei_me_d0i3c_read(dev);
	return reg;
}

/**
 * mei_me_d0i3_unset - clean d0i3 register bit on mei device.
 *
 * @dev: the device structure
 *
 * Return: D0I3C register value
 */
static u32 mei_me_d0i3_unset(struct mei_device *dev)
{
	u32 reg = mei_me_d0i3c_read(dev);

	reg &= ~H_D0I3C_I3;
	reg |= H_D0I3C_IR;
	mei_me_d0i3c_write(dev, reg);
	/* read it to ensure HW consistency */
	reg = mei_me_d0i3c_read(dev);
	return reg;
}

/**
 * mei_me_d0i3_enter_sync - perform d0i3 entry procedure
 *
 * @dev: the device structure
 *
 * Return: 0 on success an error code otherwise
 */
static int mei_me_d0i3_enter_sync(struct mei_device *dev)
{
	struct mei_me_hw *hw = to_me_hw(dev);
	int ret;
	u32 reg;

	reg = mei_me_d0i3c_read(dev);
	if (reg & H_D0I3C_I3) {
		/* we are in d0i3, nothing to do */
		dev_dbg(dev->dev, "d0i3 set not needed\n");
		ret = 0;
		goto on;
	}

	/* PGI entry procedure */
	dev->pg_event = MEI_PG_EVENT_WAIT;

	ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
	if (ret)
		/* FIXME: should we reset here? */
		goto out;

	mutex_unlock(&dev->device_lock);
	wait_event_timeout(dev->wait_pg,
937 938
		dev->pg_event == MEI_PG_EVENT_RECEIVED,
		dev->timeouts.pgi);
939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957
	mutex_lock(&dev->device_lock);

	if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
		ret = -ETIME;
		goto out;
	}
	/* end PGI entry procedure */

	dev->pg_event = MEI_PG_EVENT_INTR_WAIT;

	reg = mei_me_d0i3_set(dev, true);
	if (!(reg & H_D0I3C_CIP)) {
		dev_dbg(dev->dev, "d0i3 enter wait not needed\n");
		ret = 0;
		goto on;
	}

	mutex_unlock(&dev->device_lock);
	wait_event_timeout(dev->wait_pg,
958 959
		dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
		dev->timeouts.d0i3);
960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040
	mutex_lock(&dev->device_lock);

	if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
		reg = mei_me_d0i3c_read(dev);
		if (!(reg & H_D0I3C_I3)) {
			ret = -ETIME;
			goto out;
		}
	}

	ret = 0;
on:
	hw->pg_state = MEI_PG_ON;
out:
	dev->pg_event = MEI_PG_EVENT_IDLE;
	dev_dbg(dev->dev, "d0i3 enter ret = %d\n", ret);
	return ret;
}

/**
 * mei_me_d0i3_enter - perform d0i3 entry procedure
 *   no hbm PG handshake
 *   no waiting for confirmation; runs with interrupts
 *   disabled
 *
 * @dev: the device structure
 *
 * Return: 0 on success an error code otherwise
 */
static int mei_me_d0i3_enter(struct mei_device *dev)
{
	struct mei_me_hw *hw = to_me_hw(dev);
	u32 reg;

	reg = mei_me_d0i3c_read(dev);
	if (reg & H_D0I3C_I3) {
		/* we are in d0i3, nothing to do */
		dev_dbg(dev->dev, "already d0i3 : set not needed\n");
		goto on;
	}

	mei_me_d0i3_set(dev, false);
on:
	hw->pg_state = MEI_PG_ON;
	dev->pg_event = MEI_PG_EVENT_IDLE;
	dev_dbg(dev->dev, "d0i3 enter\n");
	return 0;
}

/**
 * mei_me_d0i3_exit_sync - perform d0i3 exit procedure
 *
 * @dev: the device structure
 *
 * Return: 0 on success an error code otherwise
 */
static int mei_me_d0i3_exit_sync(struct mei_device *dev)
{
	struct mei_me_hw *hw = to_me_hw(dev);
	int ret;
	u32 reg;

	dev->pg_event = MEI_PG_EVENT_INTR_WAIT;

	reg = mei_me_d0i3c_read(dev);
	if (!(reg & H_D0I3C_I3)) {
		/* we are not in d0i3, nothing to do */
		dev_dbg(dev->dev, "d0i3 exit not needed\n");
		ret = 0;
		goto off;
	}

	reg = mei_me_d0i3_unset(dev);
	if (!(reg & H_D0I3C_CIP)) {
		dev_dbg(dev->dev, "d0i3 exit wait not needed\n");
		ret = 0;
		goto off;
	}

	mutex_unlock(&dev->device_lock);
	wait_event_timeout(dev->wait_pg,
1041 1042
		dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
		dev->timeouts.d0i3);
1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069
	mutex_lock(&dev->device_lock);

	if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
		reg = mei_me_d0i3c_read(dev);
		if (reg & H_D0I3C_I3) {
			ret = -ETIME;
			goto out;
		}
	}

	ret = 0;
off:
	hw->pg_state = MEI_PG_OFF;
out:
	dev->pg_event = MEI_PG_EVENT_IDLE;

	dev_dbg(dev->dev, "d0i3 exit ret = %d\n", ret);
	return ret;
}

/**
 * mei_me_pg_legacy_intr - perform legacy pg processing
 *			   in interrupt thread handler
 *
 * @dev: the device structure
 */
static void mei_me_pg_legacy_intr(struct mei_device *dev)
1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081
{
	struct mei_me_hw *hw = to_me_hw(dev);

	if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT)
		return;

	dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED;
	hw->pg_state = MEI_PG_OFF;
	if (waitqueue_active(&dev->wait_pg))
		wake_up(&dev->wait_pg);
}

1082 1083 1084 1085
/**
 * mei_me_d0i3_intr - perform d0i3 processing in interrupt thread handler
 *
 * @dev: the device structure
1086
 * @intr_source: interrupt source
1087
 */
1088
static void mei_me_d0i3_intr(struct mei_device *dev, u32 intr_source)
1089 1090 1091 1092
{
	struct mei_me_hw *hw = to_me_hw(dev);

	if (dev->pg_event == MEI_PG_EVENT_INTR_WAIT &&
1093
	    (intr_source & H_D0I3C_IS)) {
1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111
		dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED;
		if (hw->pg_state == MEI_PG_ON) {
			hw->pg_state = MEI_PG_OFF;
			if (dev->hbm_state != MEI_HBM_IDLE) {
				/*
				 * force H_RDY because it could be
				 * wiped off during PG
				 */
				dev_dbg(dev->dev, "d0i3 set host ready\n");
				mei_me_host_set_ready(dev);
			}
		} else {
			hw->pg_state = MEI_PG_ON;
		}

		wake_up(&dev->wait_pg);
	}

1112
	if (hw->pg_state == MEI_PG_ON && (intr_source & H_IS)) {
1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126
		/*
		 * HW sent some data and we are in D0i3, so
		 * we got here because of HW initiated exit from D0i3.
		 * Start runtime pm resume sequence to exit low power state.
		 */
		dev_dbg(dev->dev, "d0i3 want resume\n");
		mei_hbm_pg_resume(dev);
	}
}

/**
 * mei_me_pg_intr - perform pg processing in interrupt thread handler
 *
 * @dev: the device structure
1127
 * @intr_source: interrupt source
1128
 */
1129
static void mei_me_pg_intr(struct mei_device *dev, u32 intr_source)
1130 1131 1132 1133
{
	struct mei_me_hw *hw = to_me_hw(dev);

	if (hw->d0i3_supported)
1134
		mei_me_d0i3_intr(dev, intr_source);
1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172
	else
		mei_me_pg_legacy_intr(dev);
}

/**
 * mei_me_pg_enter_sync - perform runtime pm entry procedure
 *
 * @dev: the device structure
 *
 * Return: 0 on success an error code otherwise
 */
int mei_me_pg_enter_sync(struct mei_device *dev)
{
	struct mei_me_hw *hw = to_me_hw(dev);

	if (hw->d0i3_supported)
		return mei_me_d0i3_enter_sync(dev);
	else
		return mei_me_pg_legacy_enter_sync(dev);
}

/**
 * mei_me_pg_exit_sync - perform runtime pm exit procedure
 *
 * @dev: the device structure
 *
 * Return: 0 on success an error code otherwise
 */
int mei_me_pg_exit_sync(struct mei_device *dev)
{
	struct mei_me_hw *hw = to_me_hw(dev);

	if (hw->d0i3_supported)
		return mei_me_d0i3_exit_sync(dev);
	else
		return mei_me_pg_legacy_exit_sync(dev);
}

1173 1174 1175 1176 1177 1178
/**
 * mei_me_hw_reset - resets fw via mei csr register.
 *
 * @dev: the device structure
 * @intr_enable: if interrupt should be enabled after reset.
 *
1179
 * Return: 0 on success an error code otherwise
1180 1181 1182
 */
static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
{
1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194
	struct mei_me_hw *hw = to_me_hw(dev);
	int ret;
	u32 hcsr;

	if (intr_enable) {
		mei_me_intr_enable(dev);
		if (hw->d0i3_supported) {
			ret = mei_me_d0i3_exit_sync(dev);
			if (ret)
				return ret;
		}
	}
1195

1196 1197
	pm_runtime_set_active(dev->dev);

1198
	hcsr = mei_hcsr_read(dev);
1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212
	/* H_RST may be found lit before reset is started,
	 * for example if preceding reset flow hasn't completed.
	 * In that case asserting H_RST will be ignored, therefore
	 * we need to clean H_RST bit to start a successful reset sequence.
	 */
	if ((hcsr & H_RST) == H_RST) {
		dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);
		hcsr &= ~H_RST;
		mei_hcsr_set(dev, hcsr);
		hcsr = mei_hcsr_read(dev);
	}

	hcsr |= H_RST | H_IG | H_CSR_IS_MASK;

1213
	if (!intr_enable || mei_me_hw_use_polling(to_me_hw(dev)))
1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230
		hcsr &= ~H_CSR_IE_MASK;

	dev->recvd_hw_ready = false;
	mei_hcsr_write(dev, hcsr);

	/*
	 * Host reads the H_CSR once to ensure that the
	 * posted write to H_CSR completes.
	 */
	hcsr = mei_hcsr_read(dev);

	if ((hcsr & H_RST) == 0)
		dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr);

	if ((hcsr & H_RDY) == H_RDY)
		dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr);

1231
	if (!intr_enable) {
1232
		mei_me_hw_reset_release(dev);
1233 1234 1235 1236 1237 1238
		if (hw->d0i3_supported) {
			ret = mei_me_d0i3_enter(dev);
			if (ret)
				return ret;
		}
	}
1239 1240 1241
	return 0;
}

1242 1243 1244 1245 1246 1247
/**
 * mei_me_irq_quick_handler - The ISR of the MEI device
 *
 * @irq: The irq number
 * @dev_id: pointer to the device structure
 *
1248
 * Return: irqreturn_t
1249 1250 1251
 */
irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
{
1252 1253
	struct mei_device *dev = (struct mei_device *)dev_id;
	u32 hcsr;
1254

1255
	hcsr = mei_hcsr_read(dev);
1256
	if (!me_intr_src(hcsr))
1257 1258
		return IRQ_NONE;

1259
	dev_dbg(dev->dev, "interrupt source 0x%08X\n", me_intr_src(hcsr));
1260

1261 1262
	/* disable interrupts on device */
	me_intr_disable(dev, hcsr);
1263 1264
	return IRQ_WAKE_THREAD;
}
1265
EXPORT_SYMBOL_GPL(mei_me_irq_quick_handler);
1266 1267 1268 1269 1270 1271 1272 1273

/**
 * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
 * processing.
 *
 * @irq: The irq number
 * @dev_id: pointer to the device structure
 *
1274
 * Return: irqreturn_t
1275 1276 1277 1278 1279
 *
 */
irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
{
	struct mei_device *dev = (struct mei_device *) dev_id;
1280
	struct list_head cmpl_list;
1281
	s32 slots;
1282
	u32 hcsr;
1283
	int rets = 0;
1284

1285
	dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n");
1286 1287
	/* initialize our complete list */
	mutex_lock(&dev->device_lock);
1288 1289 1290 1291

	hcsr = mei_hcsr_read(dev);
	me_intr_clear(dev, hcsr);

1292
	INIT_LIST_HEAD(&cmpl_list);
1293 1294

	/* check if ME wants a reset */
1295
	if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
1296 1297
		dev_warn(dev->dev, "FW not ready: resetting: dev_state = %d pxp = %d\n",
			 dev->dev_state, dev->pxp_mode);
1298 1299 1300 1301 1302
		if (dev->dev_state == MEI_DEV_POWERING_DOWN ||
		    dev->dev_state == MEI_DEV_POWER_DOWN)
			mei_cl_all_disconnect(dev);
		else if (dev->dev_state != MEI_DEV_DISABLED)
			schedule_work(&dev->reset_work);
1303
		goto end;
1304 1305
	}

1306 1307 1308
	if (mei_me_hw_is_resetting(dev))
		mei_hcsr_set_hig(dev);

1309
	mei_me_pg_intr(dev, me_intr_src(hcsr));
1310

1311 1312 1313
	/*  check if we need to start the dev */
	if (!mei_host_is_ready(dev)) {
		if (mei_hw_is_ready(dev)) {
1314
			dev_dbg(dev->dev, "we need to start the dev.\n");
T
Tomas Winkler 已提交
1315
			dev->recvd_hw_ready = true;
1316
			wake_up(&dev->wait_hw_ready);
1317
		} else {
1318
			dev_dbg(dev->dev, "Spurious Interrupt\n");
1319
		}
1320
		goto end;
1321 1322 1323 1324
	}
	/* check slots available for reading */
	slots = mei_count_full_read_slots(dev);
	while (slots > 0) {
1325
		dev_dbg(dev->dev, "slots to read = %08x\n", slots);
1326
		rets = mei_irq_read_handler(dev, &cmpl_list, &slots);
1327 1328 1329 1330 1331 1332 1333
		/* There is a race between ME write and interrupt delivery:
		 * Not all data is always available immediately after the
		 * interrupt, so try to read again on the next interrupt.
		 */
		if (rets == -ENODATA)
			break;

1334 1335 1336 1337 1338 1339 1340 1341
		if (rets) {
			dev_err(dev->dev, "mei_irq_read_handler ret = %d, state = %d.\n",
				rets, dev->dev_state);
			if (dev->dev_state != MEI_DEV_RESETTING &&
			    dev->dev_state != MEI_DEV_DISABLED &&
			    dev->dev_state != MEI_DEV_POWERING_DOWN &&
			    dev->dev_state != MEI_DEV_POWER_DOWN)
				schedule_work(&dev->reset_work);
1342
			goto end;
1343
		}
1344
	}
1345

1346 1347
	dev->hbuf_is_ready = mei_hbuf_is_ready(dev);

1348 1349 1350
	/*
	 * During PG handshake only allowed write is the replay to the
	 * PG exit message, so block calling write function
1351
	 * if the pg event is in PG handshake
1352
	 */
1353 1354
	if (dev->pg_event != MEI_PG_EVENT_WAIT &&
	    dev->pg_event != MEI_PG_EVENT_RECEIVED) {
1355
		rets = mei_irq_write_handler(dev, &cmpl_list);
1356 1357
		dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
	}
1358

1359
	mei_irq_compl_handler(dev, &cmpl_list);
1360

1361
end:
1362
	dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
1363
	mei_me_intr_enable(dev);
1364
	mutex_unlock(&dev->device_lock);
1365 1366
	return IRQ_HANDLED;
}
1367
EXPORT_SYMBOL_GPL(mei_me_irq_thread_handler);
1368

1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428
#define MEI_POLLING_TIMEOUT_ACTIVE 100
#define MEI_POLLING_TIMEOUT_IDLE   500

/**
 * mei_me_polling_thread - interrupt register polling thread
 *
 * The thread monitors the interrupt source register and calls
 * mei_me_irq_thread_handler() to handle the firmware
 * input.
 *
 * The function polls in MEI_POLLING_TIMEOUT_ACTIVE timeout
 * in case there was an event, in idle case the polling
 * time increases yet again by MEI_POLLING_TIMEOUT_ACTIVE
 * up to MEI_POLLING_TIMEOUT_IDLE.
 *
 * @_dev: mei device
 *
 * Return: always 0
 */
int mei_me_polling_thread(void *_dev)
{
	struct mei_device *dev = _dev;
	irqreturn_t irq_ret;
	long polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE;

	dev_dbg(dev->dev, "kernel thread is running\n");
	while (!kthread_should_stop()) {
		struct mei_me_hw *hw = to_me_hw(dev);
		u32 hcsr;

		wait_event_timeout(hw->wait_active,
				   hw->is_active || kthread_should_stop(),
				   msecs_to_jiffies(MEI_POLLING_TIMEOUT_IDLE));

		if (kthread_should_stop())
			break;

		hcsr = mei_hcsr_read(dev);
		if (me_intr_src(hcsr)) {
			polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE;
			irq_ret = mei_me_irq_thread_handler(1, dev);
			if (irq_ret != IRQ_HANDLED)
				dev_err(dev->dev, "irq_ret %d\n", irq_ret);
		} else {
			/*
			 * Increase timeout by MEI_POLLING_TIMEOUT_ACTIVE
			 * up to MEI_POLLING_TIMEOUT_IDLE
			 */
			polling_timeout = clamp_val(polling_timeout + MEI_POLLING_TIMEOUT_ACTIVE,
						    MEI_POLLING_TIMEOUT_ACTIVE,
						    MEI_POLLING_TIMEOUT_IDLE);
		}

		schedule_timeout_interruptible(msecs_to_jiffies(polling_timeout));
	}

	return 0;
}
EXPORT_SYMBOL_GPL(mei_me_polling_thread);

1429 1430
static const struct mei_hw_ops mei_me_hw_ops = {

1431
	.trc_status = mei_me_trc_status,
1432
	.fw_status = mei_me_fw_status,
1433 1434
	.pg_state  = mei_me_pg_state,

1435 1436 1437 1438
	.host_is_ready = mei_me_host_is_ready,

	.hw_is_ready = mei_me_hw_is_ready,
	.hw_reset = mei_me_hw_reset,
T
Tomas Winkler 已提交
1439 1440
	.hw_config = mei_me_hw_config,
	.hw_start = mei_me_hw_start,
1441

1442
	.pg_in_transition = mei_me_pg_in_transition,
1443 1444
	.pg_is_enabled = mei_me_pg_is_enabled,

1445 1446 1447
	.intr_clear = mei_me_intr_clear,
	.intr_enable = mei_me_intr_enable,
	.intr_disable = mei_me_intr_disable,
1448
	.synchronize_irq = mei_me_synchronize_irq,
1449 1450 1451

	.hbuf_free_slots = mei_me_hbuf_empty_slots,
	.hbuf_is_ready = mei_me_hbuf_is_empty,
1452
	.hbuf_depth = mei_me_hbuf_depth,
1453

1454
	.write = mei_me_hbuf_write,
1455 1456 1457 1458 1459 1460

	.rdbuf_full_slots = mei_me_count_full_read_slots,
	.read_hdr = mei_me_mecbrw_read,
	.read = mei_me_read_slots
};

1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471
/**
 * mei_me_fw_type_nm() - check for nm sku
 *
 * Read ME FW Status register to check for the Node Manager (NM) Firmware.
 * The NM FW is only signaled in PCI function 0.
 * __Note__: Deprecated by PCH8 and newer.
 *
 * @pdev: pci device
 *
 * Return: true in case of NM firmware
 */
1472
static bool mei_me_fw_type_nm(const struct pci_dev *pdev)
1473 1474
{
	u32 reg;
1475
	unsigned int devfn;
1476

1477 1478
	devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
	pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_2, &reg);
1479
	trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_2", PCI_CFG_HFS_2, reg);
1480 1481 1482 1483 1484 1485 1486
	/* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
	return (reg & 0x600) == 0x200;
}

#define MEI_CFG_FW_NM                           \
	.quirk_probe = mei_me_fw_type_nm

1487
/**
T
Tamar Mashiah 已提交
1488
 * mei_me_fw_type_sps_4() - check for sps 4.0 sku
1489 1490 1491 1492 1493 1494 1495 1496 1497
 *
 * Read ME FW Status register to check for SPS Firmware.
 * The SPS FW is only signaled in the PCI function 0.
 * __Note__: Deprecated by SPS 5.0 and newer.
 *
 * @pdev: pci device
 *
 * Return: true in case of SPS firmware
 */
1498
static bool mei_me_fw_type_sps_4(const struct pci_dev *pdev)
1499 1500
{
	u32 reg;
1501 1502 1503 1504
	unsigned int devfn;

	devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
	pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_1, &reg);
1505
	trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg);
1506
	return (reg & PCI_CFG_HFS_1_OPMODE_MSK) == PCI_CFG_HFS_1_OPMODE_SPS;
1507 1508
}

1509 1510 1511 1512
#define MEI_CFG_FW_SPS_4                          \
	.quirk_probe = mei_me_fw_type_sps_4

/**
1513
 * mei_me_fw_type_sps_ign() - check for sps or ign sku
1514
 *
1515 1516
 * Read ME FW Status register to check for SPS or IGN Firmware.
 * The SPS/IGN FW is only signaled in pci function 0
1517 1518 1519
 *
 * @pdev: pci device
 *
1520
 * Return: true in case of SPS/IGN firmware
1521
 */
1522
static bool mei_me_fw_type_sps_ign(const struct pci_dev *pdev)
1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534
{
	u32 reg;
	u32 fw_type;
	unsigned int devfn;

	devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
	pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_3, &reg);
	trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_3", PCI_CFG_HFS_3, reg);
	fw_type = (reg & PCI_CFG_HFS_3_FW_SKU_MSK);

	dev_dbg(&pdev->dev, "fw type is %d\n", fw_type);

1535 1536
	return fw_type == PCI_CFG_HFS_3_FW_SKU_IGN ||
	       fw_type == PCI_CFG_HFS_3_FW_SKU_SPS;
1537 1538
}

1539 1540 1541
#define MEI_CFG_KIND_ITOUCH                     \
	.kind = "itouch"

1542 1543 1544 1545 1546 1547
#define MEI_CFG_TYPE_GSC                        \
	.kind = "gsc"

#define MEI_CFG_TYPE_GSCFI                      \
	.kind = "gscfi"

1548 1549
#define MEI_CFG_FW_SPS_IGN                      \
	.quirk_probe = mei_me_fw_type_sps_ign
1550

1551 1552
#define MEI_CFG_FW_VER_SUPP                     \
	.fw_ver_supported = 1
1553

1554
#define MEI_CFG_ICH_HFS                      \
1555 1556
	.fw_status.count = 0

1557
#define MEI_CFG_ICH10_HFS                        \
1558 1559 1560 1561 1562 1563 1564 1565
	.fw_status.count = 1,                   \
	.fw_status.status[0] = PCI_CFG_HFS_1

#define MEI_CFG_PCH_HFS                         \
	.fw_status.count = 2,                   \
	.fw_status.status[0] = PCI_CFG_HFS_1,   \
	.fw_status.status[1] = PCI_CFG_HFS_2

1566 1567 1568 1569 1570 1571 1572 1573
#define MEI_CFG_PCH8_HFS                        \
	.fw_status.count = 6,                   \
	.fw_status.status[0] = PCI_CFG_HFS_1,   \
	.fw_status.status[1] = PCI_CFG_HFS_2,   \
	.fw_status.status[2] = PCI_CFG_HFS_3,   \
	.fw_status.status[3] = PCI_CFG_HFS_4,   \
	.fw_status.status[4] = PCI_CFG_HFS_5,   \
	.fw_status.status[5] = PCI_CFG_HFS_6
1574

1575 1576 1577 1578 1579
#define MEI_CFG_DMA_128 \
	.dma_size[DMA_DSCR_HOST] = SZ_128K, \
	.dma_size[DMA_DSCR_DEVICE] = SZ_128K, \
	.dma_size[DMA_DSCR_CTRL] = PAGE_SIZE

1580 1581 1582
#define MEI_CFG_TRC \
	.hw_trc_supported = 1

1583
/* ICH Legacy devices */
1584 1585
static const struct mei_cfg mei_me_ich_cfg = {
	MEI_CFG_ICH_HFS,
1586 1587 1588
};

/* ICH devices */
1589 1590
static const struct mei_cfg mei_me_ich10_cfg = {
	MEI_CFG_ICH10_HFS,
1591 1592
};

1593 1594
/* PCH6 devices */
static const struct mei_cfg mei_me_pch6_cfg = {
1595 1596 1597
	MEI_CFG_PCH_HFS,
};

1598 1599 1600 1601 1602 1603
/* PCH7 devices */
static const struct mei_cfg mei_me_pch7_cfg = {
	MEI_CFG_PCH_HFS,
	MEI_CFG_FW_VER_SUPP,
};

1604
/* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */
1605
static const struct mei_cfg mei_me_pch_cpt_pbg_cfg = {
1606
	MEI_CFG_PCH_HFS,
1607
	MEI_CFG_FW_VER_SUPP,
1608 1609 1610
	MEI_CFG_FW_NM,
};

1611
/* PCH8 Lynx Point and newer devices */
1612
static const struct mei_cfg mei_me_pch8_cfg = {
1613
	MEI_CFG_PCH8_HFS,
1614
	MEI_CFG_FW_VER_SUPP,
1615 1616
};

1617 1618 1619 1620 1621 1622 1623
/* PCH8 Lynx Point and newer devices - iTouch */
static const struct mei_cfg mei_me_pch8_itouch_cfg = {
	MEI_CFG_KIND_ITOUCH,
	MEI_CFG_PCH8_HFS,
	MEI_CFG_FW_VER_SUPP,
};

1624
/* PCH8 Lynx Point with quirk for SPS Firmware exclusion */
1625
static const struct mei_cfg mei_me_pch8_sps_4_cfg = {
1626
	MEI_CFG_PCH8_HFS,
1627
	MEI_CFG_FW_VER_SUPP,
1628 1629 1630 1631 1632 1633 1634 1635
	MEI_CFG_FW_SPS_4,
};

/* LBG with quirk for SPS (4.0) Firmware exclusion */
static const struct mei_cfg mei_me_pch12_sps_4_cfg = {
	MEI_CFG_PCH8_HFS,
	MEI_CFG_FW_VER_SUPP,
	MEI_CFG_FW_SPS_4,
1636 1637
};

1638 1639 1640
/* Cannon Lake and newer devices */
static const struct mei_cfg mei_me_pch12_cfg = {
	MEI_CFG_PCH8_HFS,
1641
	MEI_CFG_FW_VER_SUPP,
1642 1643 1644
	MEI_CFG_DMA_128,
};

1645
/* Cannon Lake with quirk for SPS 5.0 and newer Firmware exclusion */
1646
static const struct mei_cfg mei_me_pch12_sps_cfg = {
1647 1648 1649
	MEI_CFG_PCH8_HFS,
	MEI_CFG_FW_VER_SUPP,
	MEI_CFG_DMA_128,
1650
	MEI_CFG_FW_SPS_IGN,
1651 1652
};

1653 1654
/* Cannon Lake itouch with quirk for SPS 5.0 and newer Firmware exclusion
 * w/o DMA support.
1655
 */
1656 1657
static const struct mei_cfg mei_me_pch12_itouch_sps_cfg = {
	MEI_CFG_KIND_ITOUCH,
1658 1659
	MEI_CFG_PCH8_HFS,
	MEI_CFG_FW_VER_SUPP,
1660
	MEI_CFG_FW_SPS_IGN,
1661 1662
};

1663 1664 1665 1666 1667 1668 1669 1670
/* Tiger Lake and newer devices */
static const struct mei_cfg mei_me_pch15_cfg = {
	MEI_CFG_PCH8_HFS,
	MEI_CFG_FW_VER_SUPP,
	MEI_CFG_DMA_128,
	MEI_CFG_TRC,
};

1671 1672 1673 1674 1675 1676
/* Tiger Lake with quirk for SPS 5.0 and newer Firmware exclusion */
static const struct mei_cfg mei_me_pch15_sps_cfg = {
	MEI_CFG_PCH8_HFS,
	MEI_CFG_FW_VER_SUPP,
	MEI_CFG_DMA_128,
	MEI_CFG_TRC,
1677
	MEI_CFG_FW_SPS_IGN,
1678 1679
};

1680 1681 1682 1683
/* Graphics System Controller */
static const struct mei_cfg mei_me_gsc_cfg = {
	MEI_CFG_TYPE_GSC,
	MEI_CFG_PCH8_HFS,
1684
	MEI_CFG_FW_VER_SUPP,
1685 1686 1687 1688 1689 1690
};

/* Graphics System Controller Firmware Interface */
static const struct mei_cfg mei_me_gscfi_cfg = {
	MEI_CFG_TYPE_GSCFI,
	MEI_CFG_PCH8_HFS,
1691
	MEI_CFG_FW_VER_SUPP,
1692 1693
};

1694 1695 1696 1697 1698 1699 1700 1701
/*
 * mei_cfg_list - A list of platform platform specific configurations.
 * Note: has to be synchronized with  enum mei_cfg_idx.
 */
static const struct mei_cfg *const mei_cfg_list[] = {
	[MEI_ME_UNDEF_CFG] = NULL,
	[MEI_ME_ICH_CFG] = &mei_me_ich_cfg,
	[MEI_ME_ICH10_CFG] = &mei_me_ich10_cfg,
1702 1703
	[MEI_ME_PCH6_CFG] = &mei_me_pch6_cfg,
	[MEI_ME_PCH7_CFG] = &mei_me_pch7_cfg,
1704 1705
	[MEI_ME_PCH_CPT_PBG_CFG] = &mei_me_pch_cpt_pbg_cfg,
	[MEI_ME_PCH8_CFG] = &mei_me_pch8_cfg,
1706
	[MEI_ME_PCH8_ITOUCH_CFG] = &mei_me_pch8_itouch_cfg,
1707
	[MEI_ME_PCH8_SPS_4_CFG] = &mei_me_pch8_sps_4_cfg,
1708
	[MEI_ME_PCH12_CFG] = &mei_me_pch12_cfg,
1709
	[MEI_ME_PCH12_SPS_4_CFG] = &mei_me_pch12_sps_4_cfg,
1710
	[MEI_ME_PCH12_SPS_CFG] = &mei_me_pch12_sps_cfg,
1711
	[MEI_ME_PCH12_SPS_ITOUCH_CFG] = &mei_me_pch12_itouch_sps_cfg,
1712
	[MEI_ME_PCH15_CFG] = &mei_me_pch15_cfg,
1713
	[MEI_ME_PCH15_SPS_CFG] = &mei_me_pch15_sps_cfg,
1714 1715
	[MEI_ME_GSC_CFG] = &mei_me_gsc_cfg,
	[MEI_ME_GSCFI_CFG] = &mei_me_gscfi_cfg,
1716 1717 1718 1719 1720 1721 1722 1723 1724 1725
};

const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx)
{
	BUILD_BUG_ON(ARRAY_SIZE(mei_cfg_list) != MEI_ME_NUM_CFG);

	if (idx >= MEI_ME_NUM_CFG)
		return NULL;

	return mei_cfg_list[idx];
1726 1727
}
EXPORT_SYMBOL_GPL(mei_me_get_cfg);
1728

1729
/**
1730
 * mei_me_dev_init - allocates and initializes the mei device structure
1731
 *
1732
 * @parent: device associated with physical device (pci/platform)
1733
 * @cfg: per device generation config
1734
 * @slow_fw: configure longer timeouts as FW is slow
1735
 *
1736
 * Return: The mei_device pointer on success, NULL on failure.
1737
 */
1738
struct mei_device *mei_me_dev_init(struct device *parent,
1739
				   const struct mei_cfg *cfg, bool slow_fw)
1740 1741
{
	struct mei_device *dev;
1742
	struct mei_me_hw *hw;
T
Tomas Winkler 已提交
1743
	int i;
1744

1745
	dev = devm_kzalloc(parent, sizeof(*dev) + sizeof(*hw), GFP_KERNEL);
1746 1747
	if (!dev)
		return NULL;
T
Tomas Winkler 已提交
1748

1749
	hw = to_me_hw(dev);
1750

T
Tomas Winkler 已提交
1751 1752 1753
	for (i = 0; i < DMA_DSCR_NUM; i++)
		dev->dr_dscr[i].size = cfg->dma_size[i];

1754
	mei_device_init(dev, parent, slow_fw, &mei_me_hw_ops);
1755
	hw->cfg = cfg;
T
Tomas Winkler 已提交
1756

1757 1758
	dev->fw_f_fw_ver_supported = cfg->fw_ver_supported;

1759 1760
	dev->kind = cfg->kind;

1761 1762
	return dev;
}
1763
EXPORT_SYMBOL_GPL(mei_me_dev_init);