i915_drv.c 82.4 KB
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/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#include <linux/acpi.h>
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#include <linux/device.h>
#include <linux/oom.h>
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#include <linux/module.h>
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#include <linux/pci.h>
#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/pnp.h>
#include <linux/slab.h>
#include <linux/vgaarb.h>
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#include <linux/vga_switcheroo.h>
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#include <linux/vt.h>
#include <acpi/video.h>

#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/i915_drm.h>

#include "i915_drv.h"
#include "i915_trace.h"
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#include "i915_pmu.h"
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#include "i915_query.h"
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#include "i915_vgpu.h"
#include "intel_drv.h"
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#include "intel_uc.h"
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static struct drm_driver driver;

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#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
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static unsigned int i915_load_fail_count;

bool __i915_inject_load_failure(const char *func, int line)
{
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	if (i915_load_fail_count >= i915_modparams.inject_load_failure)
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		return false;

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	if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
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		DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
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			 i915_modparams.inject_load_failure, func, line);
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		return true;
	}

	return false;
}
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#endif
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#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
		    "providing the dmesg log by booting with drm.debug=0xf"

void
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...)
{
	static bool shown_bug_once;
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	struct device *kdev = dev_priv->drm.dev;
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	bool is_error = level[1] <= KERN_ERR[1];
	bool is_debug = level[1] == KERN_DEBUG[1];
	struct va_format vaf;
	va_list args;

	if (is_debug && !(drm_debug & DRM_UT_DRIVER))
		return;

	va_start(args, fmt);

	vaf.fmt = fmt;
	vaf.va = &args;

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	dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
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		   __builtin_return_address(0), &vaf);

	if (is_error && !shown_bug_once) {
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		/*
		 * Ask the user to file a bug report for the error, except
		 * if they may have caused the bug by fiddling with unsafe
		 * module parameters.
		 */
		if (!test_taint(TAINT_USER))
			dev_notice(kdev, "%s", FDO_BUG_MSG);
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		shown_bug_once = true;
	}

	va_end(args);
}

static bool i915_error_injected(struct drm_i915_private *dev_priv)
{
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#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
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	return i915_modparams.inject_load_failure &&
	       i915_load_fail_count == i915_modparams.inject_load_failure;
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#else
	return false;
#endif
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}

#define i915_load_error(dev_priv, fmt, ...)				     \
	__i915_printk(dev_priv,						     \
		      i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
		      fmt, ##__VA_ARGS__)

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/* Map PCH device id to PCH type, or PCH_NONE if unknown. */
static enum intel_pch
intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
{
	switch (id) {
	case INTEL_PCH_IBX_DEVICE_ID_TYPE:
		DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
		WARN_ON(!IS_GEN5(dev_priv));
		return PCH_IBX;
	case INTEL_PCH_CPT_DEVICE_ID_TYPE:
		DRM_DEBUG_KMS("Found CougarPoint PCH\n");
		WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
		return PCH_CPT;
	case INTEL_PCH_PPT_DEVICE_ID_TYPE:
		DRM_DEBUG_KMS("Found PantherPoint PCH\n");
		WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
		/* PantherPoint is CPT compatible */
		return PCH_CPT;
	case INTEL_PCH_LPT_DEVICE_ID_TYPE:
		DRM_DEBUG_KMS("Found LynxPoint PCH\n");
		WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
		WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
		return PCH_LPT;
	case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
		DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
		WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
		WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
		return PCH_LPT;
	case INTEL_PCH_WPT_DEVICE_ID_TYPE:
		DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
		WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
		WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
		/* WildcatPoint is LPT compatible */
		return PCH_LPT;
	case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
		DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
		WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
		WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
		/* WildcatPoint is LPT compatible */
		return PCH_LPT;
	case INTEL_PCH_SPT_DEVICE_ID_TYPE:
		DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
		WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
		return PCH_SPT;
	case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
		DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
		WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
		return PCH_SPT;
	case INTEL_PCH_KBP_DEVICE_ID_TYPE:
		DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
		WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
			!IS_COFFEELAKE(dev_priv));
		return PCH_KBP;
	case INTEL_PCH_CNP_DEVICE_ID_TYPE:
		DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
		WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
		return PCH_CNP;
	case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
		DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
		WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
		return PCH_CNP;
	case INTEL_PCH_ICP_DEVICE_ID_TYPE:
		DRM_DEBUG_KMS("Found Ice Lake PCH\n");
		WARN_ON(!IS_ICELAKE(dev_priv));
		return PCH_ICP;
	default:
		return PCH_NONE;
	}
}
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static bool intel_is_virt_pch(unsigned short id,
			      unsigned short svendor, unsigned short sdevice)
{
	return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
		id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
		(id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
		 svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
		 sdevice == PCI_SUBDEVICE_ID_QEMU));
}

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static unsigned short
intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
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{
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	unsigned short id = 0;
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	/*
	 * In a virtualized passthrough environment we can be in a
	 * setup where the ISA bridge is not able to be passed through.
	 * In this case, a south bridge can be emulated and we have to
	 * make an educated guess as to which PCH is really there.
	 */

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	if (IS_GEN5(dev_priv))
		id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
	else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
		id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
	else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
		id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
		id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
	else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
		id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
	else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
		id = INTEL_PCH_CNP_DEVICE_ID_TYPE;

	if (id)
		DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
	else
		DRM_DEBUG_KMS("Assuming no PCH\n");

	return id;
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}

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static void intel_detect_pch(struct drm_i915_private *dev_priv)
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{
	struct pci_dev *pch = NULL;

	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
	 * (which really amounts to a PCH but no South Display).
	 */
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	if (INTEL_INFO(dev_priv)->num_pipes == 0) {
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		dev_priv->pch_type = PCH_NOP;
		return;
	}

	/*
	 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
	 * make graphics device passthrough work easy for VMM, that only
	 * need to expose ISA bridge to let driver know the real hardware
	 * underneath. This is a requirement from virtualization team.
	 *
	 * In some virtualized environments (e.g. XEN), there is irrelevant
	 * ISA bridge in the system. To work reliably, we should scan trhough
	 * all the ISA bridge devices and check for the first match, instead
	 * of only checking the first one.
	 */
	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
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		unsigned short id;
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		enum intel_pch pch_type;
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		if (pch->vendor != PCI_VENDOR_ID_INTEL)
			continue;

		id = pch->device & INTEL_PCH_DEVICE_ID_MASK;

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		pch_type = intel_pch_type(dev_priv, id);
		if (pch_type != PCH_NONE) {
			dev_priv->pch_type = pch_type;
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			dev_priv->pch_id = id;
			break;
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		} else if (intel_is_virt_pch(id, pch->subsystem_vendor,
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					 pch->subsystem_device)) {
			id = intel_virt_detect_pch(dev_priv);
			if (id) {
				pch_type = intel_pch_type(dev_priv, id);
				if (WARN_ON(pch_type == PCH_NONE))
					pch_type = PCH_NOP;
			} else {
				pch_type = PCH_NOP;
			}
			dev_priv->pch_type = pch_type;
			dev_priv->pch_id = id;
			break;
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		}
	}
	if (!pch)
		DRM_DEBUG_KMS("No PCH found.\n");

	pci_dev_put(pch);
}

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static int i915_getparam_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file_priv)
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{
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	struct drm_i915_private *dev_priv = to_i915(dev);
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	struct pci_dev *pdev = dev_priv->drm.pdev;
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	drm_i915_getparam_t *param = data;
	int value;

	switch (param->param) {
	case I915_PARAM_IRQ_ACTIVE:
	case I915_PARAM_ALLOW_BATCHBUFFER:
	case I915_PARAM_LAST_DISPATCH:
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	case I915_PARAM_HAS_EXEC_CONSTANTS:
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		/* Reject all old ums/dri params. */
		return -ENODEV;
	case I915_PARAM_CHIPSET_ID:
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		value = pdev->device;
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		break;
	case I915_PARAM_REVISION:
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		value = pdev->revision;
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		break;
	case I915_PARAM_NUM_FENCES_AVAIL:
		value = dev_priv->num_fence_regs;
		break;
	case I915_PARAM_HAS_OVERLAY:
		value = dev_priv->overlay ? 1 : 0;
		break;
	case I915_PARAM_HAS_BSD:
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		value = !!dev_priv->engine[VCS];
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		break;
	case I915_PARAM_HAS_BLT:
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		value = !!dev_priv->engine[BCS];
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		break;
	case I915_PARAM_HAS_VEBOX:
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		value = !!dev_priv->engine[VECS];
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		break;
	case I915_PARAM_HAS_BSD2:
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		value = !!dev_priv->engine[VCS2];
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		break;
	case I915_PARAM_HAS_LLC:
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		value = HAS_LLC(dev_priv);
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		break;
	case I915_PARAM_HAS_WT:
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		value = HAS_WT(dev_priv);
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		break;
	case I915_PARAM_HAS_ALIASING_PPGTT:
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		value = USES_PPGTT(dev_priv);
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		break;
	case I915_PARAM_HAS_SEMAPHORES:
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		value = HAS_LEGACY_SEMAPHORES(dev_priv);
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		break;
	case I915_PARAM_HAS_SECURE_BATCHES:
		value = capable(CAP_SYS_ADMIN);
		break;
	case I915_PARAM_CMD_PARSER_VERSION:
		value = i915_cmd_parser_get_version(dev_priv);
		break;
	case I915_PARAM_SUBSLICE_TOTAL:
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		value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
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		if (!value)
			return -ENODEV;
		break;
	case I915_PARAM_EU_TOTAL:
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		value = INTEL_INFO(dev_priv)->sseu.eu_total;
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		if (!value)
			return -ENODEV;
		break;
	case I915_PARAM_HAS_GPU_RESET:
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		value = i915_modparams.enable_hangcheck &&
			intel_has_gpu_reset(dev_priv);
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		if (value && intel_has_reset_engine(dev_priv))
			value = 2;
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		break;
	case I915_PARAM_HAS_RESOURCE_STREAMER:
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		value = HAS_RESOURCE_STREAMER(dev_priv);
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		break;
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	case I915_PARAM_HAS_POOLED_EU:
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		value = HAS_POOLED_EU(dev_priv);
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		break;
	case I915_PARAM_MIN_EU_IN_POOL:
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		value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
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		break;
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	case I915_PARAM_HUC_STATUS:
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		value = intel_huc_check_status(&dev_priv->huc);
		if (value < 0)
			return value;
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		break;
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	case I915_PARAM_MMAP_GTT_VERSION:
		/* Though we've started our numbering from 1, and so class all
		 * earlier versions as 0, in effect their value is undefined as
		 * the ioctl will report EINVAL for the unknown param!
		 */
		value = i915_gem_mmap_gtt_version();
		break;
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	case I915_PARAM_HAS_SCHEDULER:
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		value = dev_priv->caps.scheduler;
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		break;
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	case I915_PARAM_MMAP_VERSION:
		/* Remember to bump this if the version changes! */
	case I915_PARAM_HAS_GEM:
	case I915_PARAM_HAS_PAGEFLIPPING:
	case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
	case I915_PARAM_HAS_RELAXED_FENCING:
	case I915_PARAM_HAS_COHERENT_RINGS:
	case I915_PARAM_HAS_RELAXED_DELTA:
	case I915_PARAM_HAS_GEN7_SOL_RESET:
	case I915_PARAM_HAS_WAIT_TIMEOUT:
	case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
	case I915_PARAM_HAS_PINNED_BATCHES:
	case I915_PARAM_HAS_EXEC_NO_RELOC:
	case I915_PARAM_HAS_EXEC_HANDLE_LUT:
	case I915_PARAM_HAS_COHERENT_PHYS_GTT:
	case I915_PARAM_HAS_EXEC_SOFTPIN:
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	case I915_PARAM_HAS_EXEC_ASYNC:
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	case I915_PARAM_HAS_EXEC_FENCE:
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	case I915_PARAM_HAS_EXEC_CAPTURE:
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	case I915_PARAM_HAS_EXEC_BATCH_FIRST:
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	case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
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		/* For the time being all of these are always true;
		 * if some supported hardware does not have one of these
		 * features this value needs to be provided from
		 * INTEL_INFO(), a feature macro, or similar.
		 */
		value = 1;
		break;
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	case I915_PARAM_HAS_CONTEXT_ISOLATION:
		value = intel_engines_has_context_isolation(dev_priv);
		break;
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	case I915_PARAM_SLICE_MASK:
		value = INTEL_INFO(dev_priv)->sseu.slice_mask;
		if (!value)
			return -ENODEV;
		break;
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	case I915_PARAM_SUBSLICE_MASK:
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		value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
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		if (!value)
			return -ENODEV;
		break;
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	case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
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		value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
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		break;
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	default:
		DRM_DEBUG("Unknown parameter %d\n", param->param);
		return -EINVAL;
	}

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	if (put_user(value, param->value))
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		return -EFAULT;

	return 0;
}

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static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
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{
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	int domain = pci_domain_nr(dev_priv->drm.pdev->bus);

	dev_priv->bridge_dev =
		pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
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	if (!dev_priv->bridge_dev) {
		DRM_ERROR("bridge device not found\n");
		return -1;
	}
	return 0;
}

/* Allocate space for the MCH regs if needed, return nonzero on error */
static int
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intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
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{
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	int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
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	u32 temp_lo, temp_hi = 0;
	u64 mchbar_addr;
	int ret;

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	if (INTEL_GEN(dev_priv) >= 4)
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		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
	pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;

	/* If ACPI doesn't have it, assume we need to allocate it ourselves */
#ifdef CONFIG_PNP
	if (mchbar_addr &&
	    pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
		return 0;
#endif

	/* Get some space for it */
	dev_priv->mch_res.name = "i915 MCHBAR";
	dev_priv->mch_res.flags = IORESOURCE_MEM;
	ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
				     &dev_priv->mch_res,
				     MCHBAR_SIZE, MCHBAR_SIZE,
				     PCIBIOS_MIN_MEM,
				     0, pcibios_align_resource,
				     dev_priv->bridge_dev);
	if (ret) {
		DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
		dev_priv->mch_res.start = 0;
		return ret;
	}

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	if (INTEL_GEN(dev_priv) >= 4)
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		pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
				       upper_32_bits(dev_priv->mch_res.start));

	pci_write_config_dword(dev_priv->bridge_dev, reg,
			       lower_32_bits(dev_priv->mch_res.start));
	return 0;
}

/* Setup MCHBAR if possible, return true if we should disable it again */
static void
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intel_setup_mchbar(struct drm_i915_private *dev_priv)
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{
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	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
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	u32 temp;
	bool enabled;

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	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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		return;

	dev_priv->mchbar_need_disable = false;

527
	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
528 529 530 531 532 533 534 535 536 537 538
		pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
		enabled = !!(temp & DEVEN_MCHBAR_EN);
	} else {
		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
		enabled = temp & 1;
	}

	/* If it's already enabled, don't have to do anything */
	if (enabled)
		return;

539
	if (intel_alloc_mchbar_resource(dev_priv))
540 541 542 543 544
		return;

	dev_priv->mchbar_need_disable = true;

	/* Space is allocated or reserved, so enable it. */
545
	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
546 547 548 549 550 551 552 553 554
		pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
				       temp | DEVEN_MCHBAR_EN);
	} else {
		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
		pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
	}
}

static void
555
intel_teardown_mchbar(struct drm_i915_private *dev_priv)
556
{
557
	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
558 559

	if (dev_priv->mchbar_need_disable) {
560
		if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585
			u32 deven_val;

			pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
					      &deven_val);
			deven_val &= ~DEVEN_MCHBAR_EN;
			pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
					       deven_val);
		} else {
			u32 mchbar_val;

			pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
					      &mchbar_val);
			mchbar_val &= ~1;
			pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
					       mchbar_val);
		}
	}

	if (dev_priv->mch_res.start)
		release_resource(&dev_priv->mch_res);
}

/* true = enable decode, false = disable decoder */
static unsigned int i915_vga_set_decode(void *cookie, bool state)
{
586
	struct drm_i915_private *dev_priv = cookie;
587

588
	intel_modeset_vga_set_state(dev_priv, state);
589 590 591 592 593 594 595
	if (state)
		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
	else
		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
}

596 597 598
static int i915_resume_switcheroo(struct drm_device *dev);
static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);

599 600 601 602 603 604 605 606 607
static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	pm_message_t pmm = { .event = PM_EVENT_SUSPEND };

	if (state == VGA_SWITCHEROO_ON) {
		pr_info("switched on\n");
		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
		/* i915 resume handler doesn't set to D0 */
D
David Weinehall 已提交
608
		pci_set_power_state(pdev, PCI_D0);
609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636
		i915_resume_switcheroo(dev);
		dev->switch_power_state = DRM_SWITCH_POWER_ON;
	} else {
		pr_info("switched off\n");
		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
		i915_suspend_switcheroo(dev, pmm);
		dev->switch_power_state = DRM_SWITCH_POWER_OFF;
	}
}

static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	/*
	 * FIXME: open_count is protected by drm_global_mutex but that would lead to
	 * locking inversion with the driver load path. And the access here is
	 * completely racy anyway. So don't bother with locking for now.
	 */
	return dev->open_count == 0;
}

static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
	.set_gpu_state = i915_switcheroo_set_state,
	.reprobe = NULL,
	.can_switch = i915_switcheroo_can_switch,
};

637
static void i915_gem_fini(struct drm_i915_private *dev_priv)
638
{
639 640
	i915_gem_suspend_late(dev_priv);

641 642
	/* Flush any outstanding unpin_work. */
	i915_gem_drain_workqueue(dev_priv);
643

644
	mutex_lock(&dev_priv->drm.struct_mutex);
645
	intel_uc_fini_hw(dev_priv);
646
	intel_uc_fini(dev_priv);
647
	i915_gem_cleanup_engines(dev_priv);
648
	i915_gem_contexts_fini(dev_priv);
649
	mutex_unlock(&dev_priv->drm.struct_mutex);
650

651
	intel_uc_fini_misc(dev_priv);
652 653
	i915_gem_cleanup_userptr(dev_priv);

654
	i915_gem_drain_freed_objects(dev_priv);
655

656
	WARN_ON(!list_empty(&dev_priv->contexts.list));
657 658 659 660
}

static int i915_load_modeset_init(struct drm_device *dev)
{
661
	struct drm_i915_private *dev_priv = to_i915(dev);
D
David Weinehall 已提交
662
	struct pci_dev *pdev = dev_priv->drm.pdev;
663 664 665 666 667
	int ret;

	if (i915_inject_load_failure())
		return -ENODEV;

668
	intel_bios_init(dev_priv);
669 670 671 672 673 674 675 676

	/* If we have > 1 VGA cards, then we need to arbitrate access
	 * to the common VGA resources.
	 *
	 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
	 * then we do not take part in VGA arbitration and the
	 * vga_client_register() fails with -ENODEV.
	 */
677
	ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
678 679 680 681 682
	if (ret && ret != -ENODEV)
		goto out;

	intel_register_dsm_handler();

D
David Weinehall 已提交
683
	ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
684 685 686 687 688 689 690 691 692 693 694 695 696 697
	if (ret)
		goto cleanup_vga_client;

	/* must happen before intel_power_domains_init_hw() on VLV/CHV */
	intel_update_rawclk(dev_priv);

	intel_power_domains_init_hw(dev_priv, false);

	intel_csr_ucode_init(dev_priv);

	ret = intel_irq_install(dev_priv);
	if (ret)
		goto cleanup_csr;

698
	intel_setup_gmbus(dev_priv);
699 700 701

	/* Important: The output setup functions called by modeset_init need
	 * working irqs for e.g. gmbus and dp aux transfers. */
702 703 704
	ret = intel_modeset_init(dev);
	if (ret)
		goto cleanup_irq;
705

706
	ret = i915_gem_init(dev_priv);
707
	if (ret)
708
		goto cleanup_irq;
709

710
	intel_setup_overlay(dev_priv);
711

712
	if (INTEL_INFO(dev_priv)->num_pipes == 0)
713 714 715 716 717 718 719 720 721 722 723 724
		return 0;

	ret = intel_fbdev_init(dev);
	if (ret)
		goto cleanup_gem;

	/* Only enable hotplug handling once the fbdev is fully set up. */
	intel_hpd_init(dev_priv);

	return 0;

cleanup_gem:
725
	if (i915_gem_suspend(dev_priv))
726
		DRM_ERROR("failed to idle hardware; continuing to unload!\n");
727
	i915_gem_fini(dev_priv);
728 729
cleanup_irq:
	drm_irq_uninstall(dev);
730
	intel_teardown_gmbus(dev_priv);
731 732 733
cleanup_csr:
	intel_csr_ucode_fini(dev_priv);
	intel_power_domains_fini(dev_priv);
D
David Weinehall 已提交
734
	vga_switcheroo_unregister_client(pdev);
735
cleanup_vga_client:
D
David Weinehall 已提交
736
	vga_client_register(pdev, NULL, NULL, NULL);
737 738 739 740 741 742 743
out:
	return ret;
}

static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
{
	struct apertures_struct *ap;
744
	struct pci_dev *pdev = dev_priv->drm.pdev;
745 746 747 748 749 750 751 752
	struct i915_ggtt *ggtt = &dev_priv->ggtt;
	bool primary;
	int ret;

	ap = alloc_apertures(1);
	if (!ap)
		return -ENOMEM;

753
	ap->ranges[0].base = ggtt->gmadr.start;
754 755 756 757 758
	ap->ranges[0].size = ggtt->mappable_end;

	primary =
		pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;

759
	ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818

	kfree(ap);

	return ret;
}

#if !defined(CONFIG_VGA_CONSOLE)
static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
{
	return 0;
}
#elif !defined(CONFIG_DUMMY_CONSOLE)
static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
{
	return -ENODEV;
}
#else
static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
{
	int ret = 0;

	DRM_INFO("Replacing VGA console driver\n");

	console_lock();
	if (con_is_bound(&vga_con))
		ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
	if (ret == 0) {
		ret = do_unregister_con_driver(&vga_con);

		/* Ignore "already unregistered". */
		if (ret == -ENODEV)
			ret = 0;
	}
	console_unlock();

	return ret;
}
#endif

static void intel_init_dpio(struct drm_i915_private *dev_priv)
{
	/*
	 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
	 * CHV x1 PHY (DP/HDMI D)
	 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
	 */
	if (IS_CHERRYVIEW(dev_priv)) {
		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
		DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
	} else if (IS_VALLEYVIEW(dev_priv)) {
		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
	}
}

static int i915_workqueues_init(struct drm_i915_private *dev_priv)
{
	/*
	 * The i915 workqueue is primarily used for batched retirement of
	 * requests (and thus managing bo) once the task has been completed
819
	 * by the GPU. i915_retire_requests() is called directly when we
820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847
	 * need high-priority retirement, such as waiting for an explicit
	 * bo.
	 *
	 * It is also used for periodic low-priority events, such as
	 * idle-timers and recording error state.
	 *
	 * All tasks on the workqueue are expected to acquire the dev mutex
	 * so there is no point in running more than one instance of the
	 * workqueue at any time.  Use an ordered one.
	 */
	dev_priv->wq = alloc_ordered_workqueue("i915", 0);
	if (dev_priv->wq == NULL)
		goto out_err;

	dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
	if (dev_priv->hotplug.dp_wq == NULL)
		goto out_free_wq;

	return 0;

out_free_wq:
	destroy_workqueue(dev_priv->wq);
out_err:
	DRM_ERROR("Failed to allocate workqueues.\n");

	return -ENOMEM;
}

848 849 850 851 852 853 854 855 856
static void i915_engines_cleanup(struct drm_i915_private *i915)
{
	struct intel_engine_cs *engine;
	enum intel_engine_id id;

	for_each_engine(engine, i915, id)
		kfree(engine);
}

857 858 859 860 861 862
static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
{
	destroy_workqueue(dev_priv->hotplug.dp_wq);
	destroy_workqueue(dev_priv->wq);
}

863 864 865 866
/*
 * We don't keep the workarounds for pre-production hardware, so we expect our
 * driver to fail on these machines in one way or another. A little warning on
 * dmesg may help both the user and the bug triagers.
867 868 869 870 871
 *
 * Our policy for removing pre-production workarounds is to keep the
 * current gen workarounds as a guide to the bring-up of the next gen
 * (workarounds have a habit of persisting!). Anything older than that
 * should be removed along with the complications they introduce.
872 873 874
 */
static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
{
875 876 877 878
	bool pre = false;

	pre |= IS_HSW_EARLY_SDV(dev_priv);
	pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
879
	pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
880

881
	if (pre) {
882 883
		DRM_ERROR("This is a pre-production stepping. "
			  "It may not be fully functional.\n");
884 885
		add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
	}
886 887
}

888 889 890
/**
 * i915_driver_init_early - setup state not requiring device access
 * @dev_priv: device private
891
 * @ent: the matching pci_device_id
892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910
 *
 * Initialize everything that is a "SW-only" state, that is state not
 * requiring accessing the device or exposing the driver via kernel internal
 * or userspace interfaces. Example steps belonging here: lock initialization,
 * system memory allocation, setting up device specific attributes and
 * function hooks not requiring accessing the device.
 */
static int i915_driver_init_early(struct drm_i915_private *dev_priv,
				  const struct pci_device_id *ent)
{
	const struct intel_device_info *match_info =
		(struct intel_device_info *)ent->driver_data;
	struct intel_device_info *device_info;
	int ret = 0;

	if (i915_inject_load_failure())
		return -ENODEV;

	/* Setup the write-once "constant" device info */
911
	device_info = mkwrite_device_info(dev_priv);
912 913 914
	memcpy(device_info, match_info, sizeof(*device_info));
	device_info->device_id = dev_priv->drm.pdev->device;

915 916
	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
		     sizeof(device_info->platform_mask) * BITS_PER_BYTE);
917 918 919 920 921
	BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
	spin_lock_init(&dev_priv->irq_lock);
	spin_lock_init(&dev_priv->gpu_error.lock);
	mutex_init(&dev_priv->backlight_lock);
	spin_lock_init(&dev_priv->uncore.lock);
L
Lyude 已提交
922

923 924 925 926 927 928
	mutex_init(&dev_priv->sb_lock);
	mutex_init(&dev_priv->modeset_restore_lock);
	mutex_init(&dev_priv->av_mutex);
	mutex_init(&dev_priv->wm.wm_mutex);
	mutex_init(&dev_priv->pps_mutex);

929 930
	i915_memcpy_init_early(dev_priv);

931 932
	ret = i915_workqueues_init(dev_priv);
	if (ret < 0)
933
		goto err_engines;
934

935 936 937 938
	ret = i915_gem_init_early(dev_priv);
	if (ret < 0)
		goto err_workqueues;

939
	/* This must be called before any calls to HAS_PCH_* */
940
	intel_detect_pch(dev_priv);
941

942 943
	intel_wopcm_init_early(&dev_priv->wopcm);
	intel_uc_init_early(dev_priv);
944
	intel_pm_setup(dev_priv);
945 946 947
	intel_init_dpio(dev_priv);
	intel_power_domains_init(dev_priv);
	intel_irq_init(dev_priv);
948
	intel_hangcheck_init(dev_priv);
949 950 951
	intel_init_display_hooks(dev_priv);
	intel_init_clock_gating_hooks(dev_priv);
	intel_init_audio_hooks(dev_priv);
952
	intel_display_crc_init(dev_priv);
953

954
	intel_detect_preproduction_hw(dev_priv);
955 956 957

	return 0;

958
err_workqueues:
959
	i915_workqueues_cleanup(dev_priv);
960 961
err_engines:
	i915_engines_cleanup(dev_priv);
962 963 964 965 966 967 968 969 970
	return ret;
}

/**
 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 * @dev_priv: device private
 */
static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
{
971
	intel_irq_fini(dev_priv);
972
	intel_uc_cleanup_early(dev_priv);
973
	i915_gem_cleanup_early(dev_priv);
974
	i915_workqueues_cleanup(dev_priv);
975
	i915_engines_cleanup(dev_priv);
976 977
}

978
static int i915_mmio_setup(struct drm_i915_private *dev_priv)
979
{
D
David Weinehall 已提交
980
	struct pci_dev *pdev = dev_priv->drm.pdev;
981 982 983
	int mmio_bar;
	int mmio_size;

984
	mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
985 986 987 988 989 990 991 992
	/*
	 * Before gen4, the registers and the GTT are behind different BARs.
	 * However, from gen4 onwards, the registers and the GTT are shared
	 * in the same BAR, so we want to restrict this ioremap from
	 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
	 * the register BAR remains the same size for all the earlier
	 * generations up to Ironlake.
	 */
993
	if (INTEL_GEN(dev_priv) < 5)
994 995 996
		mmio_size = 512 * 1024;
	else
		mmio_size = 2 * 1024 * 1024;
D
David Weinehall 已提交
997
	dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
998 999 1000 1001 1002 1003 1004
	if (dev_priv->regs == NULL) {
		DRM_ERROR("failed to map registers\n");

		return -EIO;
	}

	/* Try to make sure MCHBAR is enabled before poking at it */
1005
	intel_setup_mchbar(dev_priv);
1006 1007 1008 1009

	return 0;
}

1010
static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
1011
{
D
David Weinehall 已提交
1012
	struct pci_dev *pdev = dev_priv->drm.pdev;
1013

1014
	intel_teardown_mchbar(dev_priv);
D
David Weinehall 已提交
1015
	pci_iounmap(pdev, dev_priv->regs);
1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033
}

/**
 * i915_driver_init_mmio - setup device MMIO
 * @dev_priv: device private
 *
 * Setup minimal device state necessary for MMIO accesses later in the
 * initialization sequence. The setup here should avoid any other device-wide
 * side effects or exposing the driver via kernel internal or user space
 * interfaces.
 */
static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
{
	int ret;

	if (i915_inject_load_failure())
		return -ENODEV;

1034
	if (i915_get_bridge_dev(dev_priv))
1035 1036
		return -EIO;

1037
	ret = i915_mmio_setup(dev_priv);
1038
	if (ret < 0)
1039
		goto err_bridge;
1040 1041

	intel_uncore_init(dev_priv);
1042

1043 1044 1045 1046
	intel_device_info_init_mmio(dev_priv);

	intel_uncore_prune(dev_priv);

1047 1048
	intel_uc_init_mmio(dev_priv);

1049 1050 1051 1052
	ret = intel_engines_init_mmio(dev_priv);
	if (ret)
		goto err_uncore;

1053
	i915_gem_init_mmio(dev_priv);
1054 1055 1056

	return 0;

1057 1058 1059
err_uncore:
	intel_uncore_fini(dev_priv);
err_bridge:
1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071
	pci_dev_put(dev_priv->bridge_dev);

	return ret;
}

/**
 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 * @dev_priv: device private
 */
static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
{
	intel_uncore_fini(dev_priv);
1072
	i915_mmio_cleanup(dev_priv);
1073 1074 1075
	pci_dev_put(dev_priv->bridge_dev);
}

1076 1077 1078 1079 1080 1081 1082 1083
static void intel_sanitize_options(struct drm_i915_private *dev_priv)
{
	/*
	 * i915.enable_ppgtt is read-only, so do an early pass to validate the
	 * user's requested state against the hardware/driver capabilities.  We
	 * do this now so that we can print out any log messages once rather
	 * than every time we check intel_enable_ppgtt().
	 */
1084 1085 1086 1087
	i915_modparams.enable_ppgtt =
		intel_sanitize_enable_ppgtt(dev_priv,
					    i915_modparams.enable_ppgtt);
	DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1088

1089
	intel_gvt_sanitize_options(dev_priv);
1090 1091
}

1092 1093 1094 1095 1096 1097 1098 1099 1100
/**
 * i915_driver_init_hw - setup state requiring device access
 * @dev_priv: device private
 *
 * Setup state that requires accessing the device, but doesn't require
 * exposing the driver via kernel internal or userspace interfaces.
 */
static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
{
D
David Weinehall 已提交
1101
	struct pci_dev *pdev = dev_priv->drm.pdev;
1102 1103 1104 1105 1106
	int ret;

	if (i915_inject_load_failure())
		return -ENODEV;

1107
	intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
1108 1109

	intel_sanitize_options(dev_priv);
1110

1111 1112
	i915_perf_init(dev_priv);

1113
	ret = i915_ggtt_probe_hw(dev_priv);
1114
	if (ret)
1115
		goto err_perf;
1116

1117 1118 1119 1120
	/*
	 * WARNING: Apparently we must kick fbdev drivers before vgacon,
	 * otherwise the vga fbdev driver falls over.
	 */
1121 1122 1123
	ret = i915_kick_out_firmware_fb(dev_priv);
	if (ret) {
		DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1124
		goto err_ggtt;
1125 1126 1127 1128 1129
	}

	ret = i915_kick_out_vgacon(dev_priv);
	if (ret) {
		DRM_ERROR("failed to remove conflicting VGA console\n");
1130
		goto err_ggtt;
1131 1132
	}

1133
	ret = i915_ggtt_init_hw(dev_priv);
1134
	if (ret)
1135
		goto err_ggtt;
1136

1137
	ret = i915_ggtt_enable_hw(dev_priv);
1138 1139
	if (ret) {
		DRM_ERROR("failed to enable GGTT\n");
1140
		goto err_ggtt;
1141 1142
	}

D
David Weinehall 已提交
1143
	pci_set_master(pdev);
1144 1145

	/* overlay on gen2 is broken and can't address above 1G */
1146
	if (IS_GEN2(dev_priv)) {
D
David Weinehall 已提交
1147
		ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1148 1149 1150
		if (ret) {
			DRM_ERROR("failed to set DMA mask\n");

1151
			goto err_ggtt;
1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162
		}
	}

	/* 965GM sometimes incorrectly writes to hardware status page (HWS)
	 * using 32bit addressing, overwriting memory if HWS is located
	 * above 4GB.
	 *
	 * The documentation also mentions an issue with undefined
	 * behaviour if any general state is accessed within a page above 4GB,
	 * which also needs to be handled carefully.
	 */
1163
	if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
D
David Weinehall 已提交
1164
		ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1165 1166 1167 1168

		if (ret) {
			DRM_ERROR("failed to set DMA mask\n");

1169
			goto err_ggtt;
1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189
		}
	}

	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
			   PM_QOS_DEFAULT_VALUE);

	intel_uncore_sanitize(dev_priv);

	intel_opregion_setup(dev_priv);

	i915_gem_load_init_fences(dev_priv);

	/* On the 945G/GM, the chipset reports the MSI capability on the
	 * integrated graphics even though the support isn't actually there
	 * according to the published specs.  It doesn't appear to function
	 * correctly in testing on 945G.
	 * This may be a side effect of MSI having been made available for PEG
	 * and the registers being closely associated.
	 *
	 * According to chipset errata, on the 965GM, MSI interrupts may
1190 1191 1192 1193
	 * be lost or delayed, and was defeatured. MSI interrupts seem to
	 * get lost on g4x as well, and interrupt delivery seems to stay
	 * properly dead afterwards. So we'll just disable them for all
	 * pre-gen5 chipsets.
1194
	 */
1195
	if (INTEL_GEN(dev_priv) >= 5) {
D
David Weinehall 已提交
1196
		if (pci_enable_msi(pdev) < 0)
1197 1198 1199
			DRM_DEBUG_DRIVER("can't enable MSI");
	}

1200 1201
	ret = intel_gvt_init(dev_priv);
	if (ret)
1202
		goto err_ggtt;
1203

1204 1205
	return 0;

1206
err_ggtt:
1207
	i915_ggtt_cleanup_hw(dev_priv);
1208 1209
err_perf:
	i915_perf_fini(dev_priv);
1210 1211 1212 1213 1214 1215 1216 1217 1218
	return ret;
}

/**
 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
 * @dev_priv: device private
 */
static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
{
D
David Weinehall 已提交
1219
	struct pci_dev *pdev = dev_priv->drm.pdev;
1220

1221 1222
	i915_perf_fini(dev_priv);

D
David Weinehall 已提交
1223 1224
	if (pdev->msi_enabled)
		pci_disable_msi(pdev);
1225 1226

	pm_qos_remove_request(&dev_priv->pm_qos);
1227
	i915_ggtt_cleanup_hw(dev_priv);
1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238
}

/**
 * i915_driver_register - register the driver with the rest of the system
 * @dev_priv: device private
 *
 * Perform any steps necessary to make the driver available via kernel
 * internal or userspace interfaces.
 */
static void i915_driver_register(struct drm_i915_private *dev_priv)
{
1239
	struct drm_device *dev = &dev_priv->drm;
1240

1241
	i915_gem_shrinker_register(dev_priv);
1242
	i915_pmu_register(dev_priv);
1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253

	/*
	 * Notify a valid surface after modesetting,
	 * when running inside a VM.
	 */
	if (intel_vgpu_active(dev_priv))
		I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);

	/* Reveal our presence to userspace */
	if (drm_dev_register(dev, 0) == 0) {
		i915_debugfs_register(dev_priv);
D
David Weinehall 已提交
1254
		i915_setup_sysfs(dev_priv);
1255 1256 1257

		/* Depends on sysfs having been initialized */
		i915_perf_register(dev_priv);
1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269
	} else
		DRM_ERROR("Failed to register driver for userspace access!\n");

	if (INTEL_INFO(dev_priv)->num_pipes) {
		/* Must be done after probing outputs */
		intel_opregion_register(dev_priv);
		acpi_video_register();
	}

	if (IS_GEN5(dev_priv))
		intel_gpu_ips_init(dev_priv);

1270
	intel_audio_init(dev_priv);
1271 1272 1273 1274 1275 1276 1277 1278 1279

	/*
	 * Some ports require correctly set-up hpd registers for detection to
	 * work properly (leading to ghost connected connector status), e.g. VGA
	 * on gm45.  Hence we can only set up the initial fbdev config after hpd
	 * irqs are fully enabled. We do it last so that the async config
	 * cannot run before the connectors are registered.
	 */
	intel_fbdev_initial_config_async(dev);
1280 1281 1282 1283 1284 1285 1286

	/*
	 * We need to coordinate the hotplugs with the asynchronous fbdev
	 * configuration, for which we use the fbdev->async_cookie.
	 */
	if (INTEL_INFO(dev_priv)->num_pipes)
		drm_kms_helper_poll_init(dev);
1287 1288 1289 1290 1291 1292 1293 1294
}

/**
 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 * @dev_priv: device private
 */
static void i915_driver_unregister(struct drm_i915_private *dev_priv)
{
1295
	intel_fbdev_unregister(dev_priv);
1296
	intel_audio_deinit(dev_priv);
1297

1298 1299 1300 1301 1302 1303 1304
	/*
	 * After flushing the fbdev (incl. a late async config which will
	 * have delayed queuing of a hotplug event), then flush the hotplug
	 * events.
	 */
	drm_kms_helper_poll_fini(&dev_priv->drm);

1305 1306 1307 1308
	intel_gpu_ips_teardown();
	acpi_video_unregister();
	intel_opregion_unregister(dev_priv);

1309
	i915_perf_unregister(dev_priv);
1310
	i915_pmu_unregister(dev_priv);
1311

D
David Weinehall 已提交
1312
	i915_teardown_sysfs(dev_priv);
1313
	drm_dev_unregister(&dev_priv->drm);
1314

1315
	i915_gem_shrinker_unregister(dev_priv);
1316 1317
}

1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332
static void i915_welcome_messages(struct drm_i915_private *dev_priv)
{
	if (drm_debug & DRM_UT_DRIVER) {
		struct drm_printer p = drm_debug_printer("i915 device info:");

		intel_device_info_dump(&dev_priv->info, &p);
		intel_device_info_dump_runtime(&dev_priv->info, &p);
	}

	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
		DRM_INFO("DRM_I915_DEBUG enabled\n");
	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
		DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
}

1333 1334
/**
 * i915_driver_load - setup chip and create an initial config
1335 1336
 * @pdev: PCI device
 * @ent: matching PCI ID entry
1337 1338 1339 1340 1341 1342 1343
 *
 * The driver load routine has to do several things:
 *   - drive output discovery via intel_modeset_init()
 *   - initialize the memory manager
 *   - allocate initial config memory
 *   - setup the DRM framebuffer with the allocated memory
 */
1344
int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1345
{
1346 1347
	const struct intel_device_info *match_info =
		(struct intel_device_info *)ent->driver_data;
1348 1349
	struct drm_i915_private *dev_priv;
	int ret;
1350

1351
	/* Enable nuclear pageflip on ILK+ */
1352
	if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1353
		driver.driver_features &= ~DRIVER_ATOMIC;
1354

1355 1356 1357 1358 1359
	ret = -ENOMEM;
	dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
	if (dev_priv)
		ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
	if (ret) {
1360
		DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1361
		goto out_free;
1362
	}
1363

1364 1365
	dev_priv->drm.pdev = pdev;
	dev_priv->drm.dev_private = dev_priv;
1366

1367 1368
	ret = pci_enable_device(pdev);
	if (ret)
1369
		goto out_fini;
D
Damien Lespiau 已提交
1370

1371
	pci_set_drvdata(pdev, &dev_priv->drm);
1372 1373 1374 1375 1376 1377 1378 1379
	/*
	 * Disable the system suspend direct complete optimization, which can
	 * leave the device suspended skipping the driver's suspend handlers
	 * if the device was already runtime suspended. This is needed due to
	 * the difference in our runtime and system suspend sequence and
	 * becaue the HDA driver may require us to enable the audio power
	 * domain during system suspend.
	 */
1380
	dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
1381

1382 1383 1384
	ret = i915_driver_init_early(dev_priv, ent);
	if (ret < 0)
		goto out_pci_disable;
1385

1386
	intel_runtime_pm_get(dev_priv);
L
Linus Torvalds 已提交
1387

1388 1389 1390
	ret = i915_driver_init_mmio(dev_priv);
	if (ret < 0)
		goto out_runtime_pm_put;
J
Jesse Barnes 已提交
1391

1392 1393 1394
	ret = i915_driver_init_hw(dev_priv);
	if (ret < 0)
		goto out_cleanup_mmio;
1395 1396

	/*
1397 1398 1399
	 * TODO: move the vblank init and parts of modeset init steps into one
	 * of the i915_driver_init_/i915_driver_register functions according
	 * to the role/effect of the given init step.
1400
	 */
1401
	if (INTEL_INFO(dev_priv)->num_pipes) {
1402
		ret = drm_vblank_init(&dev_priv->drm,
1403 1404 1405
				      INTEL_INFO(dev_priv)->num_pipes);
		if (ret)
			goto out_cleanup_hw;
1406 1407
	}

1408
	ret = i915_load_modeset_init(&dev_priv->drm);
1409
	if (ret < 0)
1410
		goto out_cleanup_hw;
1411 1412 1413 1414 1415

	i915_driver_register(dev_priv);

	intel_runtime_pm_enable(dev_priv);

1416
	intel_init_ipc(dev_priv);
M
Mahesh Kumar 已提交
1417

1418 1419
	intel_runtime_pm_put(dev_priv);

1420 1421
	i915_welcome_messages(dev_priv);

1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432
	return 0;

out_cleanup_hw:
	i915_driver_cleanup_hw(dev_priv);
out_cleanup_mmio:
	i915_driver_cleanup_mmio(dev_priv);
out_runtime_pm_put:
	intel_runtime_pm_put(dev_priv);
	i915_driver_cleanup_early(dev_priv);
out_pci_disable:
	pci_disable_device(pdev);
1433
out_fini:
1434
	i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1435 1436 1437
	drm_dev_fini(&dev_priv->drm);
out_free:
	kfree(dev_priv);
1438 1439 1440
	return ret;
}

1441
void i915_driver_unload(struct drm_device *dev)
1442
{
1443
	struct drm_i915_private *dev_priv = to_i915(dev);
D
David Weinehall 已提交
1444
	struct pci_dev *pdev = dev_priv->drm.pdev;
1445

1446 1447
	i915_driver_unregister(dev_priv);

1448
	if (i915_gem_suspend(dev_priv))
1449
		DRM_ERROR("failed to idle hardware; continuing to unload!\n");
B
Ben Widawsky 已提交
1450

1451 1452
	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);

1453
	drm_atomic_helper_shutdown(dev);
1454

1455 1456
	intel_gvt_cleanup(dev_priv);

1457 1458
	intel_modeset_cleanup(dev);

1459
	intel_bios_cleanup(dev_priv);
1460

D
David Weinehall 已提交
1461 1462
	vga_switcheroo_unregister_client(pdev);
	vga_client_register(pdev, NULL, NULL, NULL);
1463

1464
	intel_csr_ucode_fini(dev_priv);
1465

1466 1467
	/* Free error state after interrupts are fully disabled. */
	cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1468
	i915_reset_error_state(dev_priv);
1469

1470
	i915_gem_fini(dev_priv);
1471 1472 1473 1474 1475 1476 1477 1478
	intel_fbc_cleanup_cfb(dev_priv);

	intel_power_domains_fini(dev_priv);

	i915_driver_cleanup_hw(dev_priv);
	i915_driver_cleanup_mmio(dev_priv);

	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1479 1480 1481 1482 1483
}

static void i915_driver_release(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
1484 1485

	i915_driver_cleanup_early(dev_priv);
1486 1487 1488
	drm_dev_fini(&dev_priv->drm);

	kfree(dev_priv);
1489 1490
}

1491
static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1492
{
1493
	struct drm_i915_private *i915 = to_i915(dev);
1494
	int ret;
1495

1496
	ret = i915_gem_open(i915, file);
1497 1498
	if (ret)
		return ret;
1499

1500 1501
	return 0;
}
1502

1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519
/**
 * i915_driver_lastclose - clean up after all DRM clients have exited
 * @dev: DRM device
 *
 * Take care of cleaning up after all DRM clients have exited.  In the
 * mode setting case, we want to restore the kernel's initial mode (just
 * in case the last client left us in a bad state).
 *
 * Additionally, in the non-mode setting case, we'll tear down the GTT
 * and DMA structures, since the kernel won't be using them, and clea
 * up any GEM state.
 */
static void i915_driver_lastclose(struct drm_device *dev)
{
	intel_fbdev_restore_mode(dev);
	vga_switcheroo_process_delayed_switch();
}
1520

1521
static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1522
{
1523 1524
	struct drm_i915_file_private *file_priv = file->driver_priv;

1525
	mutex_lock(&dev->struct_mutex);
1526
	i915_gem_context_close(file);
1527 1528 1529 1530
	i915_gem_release(dev, file);
	mutex_unlock(&dev->struct_mutex);

	kfree(file_priv);
1531 1532
}

1533 1534
static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
{
1535
	struct drm_device *dev = &dev_priv->drm;
1536
	struct intel_encoder *encoder;
1537 1538

	drm_modeset_lock_all(dev);
1539 1540 1541
	for_each_intel_encoder(dev, encoder)
		if (encoder->suspend)
			encoder->suspend(encoder);
1542 1543 1544
	drm_modeset_unlock_all(dev);
}

1545 1546
static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
			      bool rpm_resume);
1547
static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1548

1549 1550 1551 1552 1553 1554 1555 1556
static bool suspend_to_idle(struct drm_i915_private *dev_priv)
{
#if IS_ENABLED(CONFIG_ACPI_SLEEP)
	if (acpi_target_system_state() < ACPI_STATE_S3)
		return true;
#endif
	return false;
}
1557

1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576
static int i915_drm_prepare(struct drm_device *dev)
{
	struct drm_i915_private *i915 = to_i915(dev);
	int err;

	/*
	 * NB intel_display_suspend() may issue new requests after we've
	 * ostensibly marked the GPU as ready-to-sleep here. We need to
	 * split out that work and pull it forward so that after point,
	 * the GPU is not woken again.
	 */
	err = i915_gem_suspend(i915);
	if (err)
		dev_err(&i915->drm.pdev->dev,
			"GEM idle failed, suspend/resume might fail\n");

	return err;
}

1577
static int i915_drm_suspend(struct drm_device *dev)
J
Jesse Barnes 已提交
1578
{
1579
	struct drm_i915_private *dev_priv = to_i915(dev);
D
David Weinehall 已提交
1580
	struct pci_dev *pdev = dev_priv->drm.pdev;
1581
	pci_power_t opregion_target_state;
1582

1583 1584 1585 1586 1587
	/* ignore lid events during suspend */
	mutex_lock(&dev_priv->modeset_restore_lock);
	dev_priv->modeset_restore = MODESET_SUSPENDED;
	mutex_unlock(&dev_priv->modeset_restore_lock);

1588 1589
	disable_rpm_wakeref_asserts(dev_priv);

1590 1591
	/* We do a lot of poking in a lot of registers, make sure they work
	 * properly. */
1592
	intel_display_set_init_power(dev_priv, true);
1593

1594 1595
	drm_kms_helper_poll_disable(dev);

D
David Weinehall 已提交
1596
	pci_save_state(pdev);
J
Jesse Barnes 已提交
1597

1598
	intel_display_suspend(dev);
1599

1600
	intel_dp_mst_suspend(dev);
1601

1602 1603
	intel_runtime_pm_disable_interrupts(dev_priv);
	intel_hpd_cancel_work(dev_priv);
1604

1605
	intel_suspend_encoders(dev_priv);
1606

1607
	intel_suspend_hw(dev_priv);
1608

1609
	i915_gem_suspend_gtt_mappings(dev_priv);
1610

1611
	i915_save_state(dev_priv);
1612

1613
	opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1614
	intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1615

1616
	intel_opregion_unregister(dev_priv);
1617

1618
	intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1619

1620 1621
	dev_priv->suspend_count++;

1622
	intel_csr_ucode_suspend(dev_priv);
1623

1624 1625
	enable_rpm_wakeref_asserts(dev_priv);

1626
	return 0;
1627 1628
}

1629
static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1630
{
1631
	struct drm_i915_private *dev_priv = to_i915(dev);
D
David Weinehall 已提交
1632
	struct pci_dev *pdev = dev_priv->drm.pdev;
1633 1634
	int ret;

1635 1636
	disable_rpm_wakeref_asserts(dev_priv);

1637 1638
	i915_gem_suspend_late(dev_priv);

1639
	intel_display_set_init_power(dev_priv, false);
1640
	intel_uncore_suspend(dev_priv);
1641

1642 1643 1644 1645 1646 1647 1648
	/*
	 * In case of firmware assisted context save/restore don't manually
	 * deinit the power domains. This also means the CSR/DMC firmware will
	 * stay active, it will power down any HW resources as required and
	 * also enable deeper system power states that would be blocked if the
	 * firmware was inactive.
	 */
1649 1650
	if (IS_GEN9_LP(dev_priv) || hibernation || !suspend_to_idle(dev_priv) ||
	    dev_priv->csr.dmc_payload == NULL) {
1651
		intel_power_domains_suspend(dev_priv);
1652 1653
		dev_priv->power_domains_suspended = true;
	}
1654

1655
	ret = 0;
1656
	if (IS_GEN9_LP(dev_priv))
1657
		bxt_enable_dc9(dev_priv);
1658
	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1659 1660 1661
		hsw_enable_pc8(dev_priv);
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
		ret = vlv_suspend_complete(dev_priv);
1662 1663 1664

	if (ret) {
		DRM_ERROR("Suspend complete failed: %d\n", ret);
1665
		if (dev_priv->power_domains_suspended) {
1666
			intel_power_domains_init_hw(dev_priv, true);
1667 1668
			dev_priv->power_domains_suspended = false;
		}
1669

1670
		goto out;
1671 1672
	}

D
David Weinehall 已提交
1673
	pci_disable_device(pdev);
1674
	/*
1675
	 * During hibernation on some platforms the BIOS may try to access
1676 1677
	 * the device even though it's already in D3 and hang the machine. So
	 * leave the device in D0 on those platforms and hope the BIOS will
1678 1679 1680 1681 1682 1683 1684
	 * power down the device properly. The issue was seen on multiple old
	 * GENs with different BIOS vendors, so having an explicit blacklist
	 * is inpractical; apply the workaround on everything pre GEN6. The
	 * platforms where the issue was seen:
	 * Lenovo Thinkpad X301, X61s, X60, T60, X41
	 * Fujitsu FSC S7110
	 * Acer Aspire 1830T
1685
	 */
1686
	if (!(hibernation && INTEL_GEN(dev_priv) < 6))
D
David Weinehall 已提交
1687
		pci_set_power_state(pdev, PCI_D3hot);
1688

1689 1690 1691 1692
out:
	enable_rpm_wakeref_asserts(dev_priv);

	return ret;
1693 1694
}

1695
static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1696 1697 1698
{
	int error;

1699
	if (!dev) {
1700 1701 1702 1703 1704
		DRM_ERROR("dev: %p\n", dev);
		DRM_ERROR("DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}

1705 1706 1707
	if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
			 state.event != PM_EVENT_FREEZE))
		return -EINVAL;
1708 1709 1710

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
1711

1712
	error = i915_drm_suspend(dev);
1713 1714 1715
	if (error)
		return error;

1716
	return i915_drm_suspend_late(dev, false);
J
Jesse Barnes 已提交
1717 1718
}

1719
static int i915_drm_resume(struct drm_device *dev)
1720
{
1721
	struct drm_i915_private *dev_priv = to_i915(dev);
1722
	int ret;
1723

1724
	disable_rpm_wakeref_asserts(dev_priv);
1725
	intel_sanitize_gt_powersave(dev_priv);
1726

1727
	ret = i915_ggtt_enable_hw(dev_priv);
1728 1729 1730
	if (ret)
		DRM_ERROR("failed to re-enable GGTT\n");

1731 1732
	intel_csr_ucode_resume(dev_priv);

1733
	i915_restore_state(dev_priv);
1734
	intel_pps_unlock_regs_wa(dev_priv);
1735
	intel_opregion_setup(dev_priv);
1736

1737
	intel_init_pch_refclk(dev_priv);
1738

1739 1740 1741 1742 1743
	/*
	 * Interrupts have to be enabled before any batches are run. If not the
	 * GPU will hang. i915_gem_init_hw() will initiate batches to
	 * update/restore the context.
	 *
1744 1745
	 * drm_mode_config_reset() needs AUX interrupts.
	 *
1746 1747 1748 1749 1750
	 * Modeset enabling in intel_modeset_init_hw() also needs working
	 * interrupts.
	 */
	intel_runtime_pm_enable_interrupts(dev_priv);

1751 1752
	drm_mode_config_reset(dev);

1753
	i915_gem_resume(dev_priv);
1754

1755
	intel_modeset_init_hw(dev);
1756
	intel_init_clock_gating(dev_priv);
1757

1758 1759
	spin_lock_irq(&dev_priv->irq_lock);
	if (dev_priv->display.hpd_irq_setup)
1760
		dev_priv->display.hpd_irq_setup(dev_priv);
1761
	spin_unlock_irq(&dev_priv->irq_lock);
1762

1763
	intel_dp_mst_resume(dev);
1764

1765 1766
	intel_display_resume(dev);

1767 1768
	drm_kms_helper_poll_enable(dev);

1769 1770 1771 1772 1773 1774 1775
	/*
	 * ... but also need to make sure that hotplug processing
	 * doesn't cause havoc. Like in the driver load code we don't
	 * bother with the tiny race here where we might loose hotplug
	 * notifications.
	 * */
	intel_hpd_init(dev_priv);
1776

1777
	intel_opregion_register(dev_priv);
1778

1779
	intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1780

1781 1782 1783
	mutex_lock(&dev_priv->modeset_restore_lock);
	dev_priv->modeset_restore = MODESET_DONE;
	mutex_unlock(&dev_priv->modeset_restore_lock);
1784

1785
	intel_opregion_notify_adapter(dev_priv, PCI_D0);
1786

1787 1788
	enable_rpm_wakeref_asserts(dev_priv);

1789
	return 0;
1790 1791
}

1792
static int i915_drm_resume_early(struct drm_device *dev)
1793
{
1794
	struct drm_i915_private *dev_priv = to_i915(dev);
D
David Weinehall 已提交
1795
	struct pci_dev *pdev = dev_priv->drm.pdev;
1796
	int ret;
1797

1798 1799 1800 1801 1802 1803 1804 1805 1806
	/*
	 * We have a resume ordering issue with the snd-hda driver also
	 * requiring our device to be power up. Due to the lack of a
	 * parent/child relationship we currently solve this with an early
	 * resume hook.
	 *
	 * FIXME: This should be solved with a special hdmi sink device or
	 * similar so that power domains can be employed.
	 */
1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817

	/*
	 * Note that we need to set the power state explicitly, since we
	 * powered off the device during freeze and the PCI core won't power
	 * it back up for us during thaw. Powering off the device during
	 * freeze is not a hard requirement though, and during the
	 * suspend/resume phases the PCI core makes sure we get here with the
	 * device powered on. So in case we change our freeze logic and keep
	 * the device powered we can also remove the following set power state
	 * call.
	 */
D
David Weinehall 已提交
1818
	ret = pci_set_power_state(pdev, PCI_D0);
1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836
	if (ret) {
		DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
		goto out;
	}

	/*
	 * Note that pci_enable_device() first enables any parent bridge
	 * device and only then sets the power state for this device. The
	 * bridge enabling is a nop though, since bridge devices are resumed
	 * first. The order of enabling power and enabling the device is
	 * imposed by the PCI core as described above, so here we preserve the
	 * same order for the freeze/thaw phases.
	 *
	 * TODO: eventually we should remove pci_disable_device() /
	 * pci_enable_enable_device() from suspend/resume. Due to how they
	 * depend on the device enable refcount we can't anyway depend on them
	 * disabling/enabling the device.
	 */
D
David Weinehall 已提交
1837
	if (pci_enable_device(pdev)) {
1838 1839 1840
		ret = -EIO;
		goto out;
	}
1841

D
David Weinehall 已提交
1842
	pci_set_master(pdev);
1843

1844 1845
	disable_rpm_wakeref_asserts(dev_priv);

1846
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1847
		ret = vlv_resume_prepare(dev_priv, false);
1848
	if (ret)
1849 1850
		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
			  ret);
1851

1852
	intel_uncore_resume_early(dev_priv);
1853

1854
	if (IS_GEN9_LP(dev_priv)) {
1855
		gen9_sanitize_dc_state(dev_priv);
1856
		bxt_disable_dc9(dev_priv);
1857
	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1858
		hsw_disable_pc8(dev_priv);
1859
	}
1860

1861
	intel_uncore_sanitize(dev_priv);
1862

1863
	if (dev_priv->power_domains_suspended)
1864
		intel_power_domains_init_hw(dev_priv, true);
1865 1866
	else
		intel_display_set_init_power(dev_priv, true);
1867

1868 1869
	i915_gem_sanitize(dev_priv);

1870 1871
	enable_rpm_wakeref_asserts(dev_priv);

1872
out:
1873
	dev_priv->power_domains_suspended = false;
1874 1875

	return ret;
1876 1877
}

1878
static int i915_resume_switcheroo(struct drm_device *dev)
1879
{
1880
	int ret;
1881

1882 1883 1884
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

1885
	ret = i915_drm_resume_early(dev);
1886 1887 1888
	if (ret)
		return ret;

1889 1890 1891
	return i915_drm_resume(dev);
}

1892
/**
1893
 * i915_reset - reset chip after a hang
1894
 * @i915: #drm_i915_private to reset
1895 1896
 * @stalled_mask: mask of the stalled engines with the guilty requests
 * @reason: user error message for why we are resetting
1897
 *
1898 1899
 * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
 * on failure.
1900
 *
1901 1902
 * Caller must hold the struct_mutex.
 *
1903 1904 1905 1906 1907 1908 1909 1910
 * Procedure is fairly simple:
 *   - reset the chip using the reset reg
 *   - re-init context state
 *   - re-init hardware status page
 *   - re-init ring buffer
 *   - re-init interrupt state
 *   - re-init display
 */
1911 1912 1913
void i915_reset(struct drm_i915_private *i915,
		unsigned int stalled_mask,
		const char *reason)
1914
{
1915
	struct i915_gpu_error *error = &i915->gpu_error;
1916
	int ret;
1917
	int i;
1918

1919 1920
	GEM_TRACE("flags=%lx\n", error->flags);

1921
	might_sleep();
1922
	lockdep_assert_held(&i915->drm.struct_mutex);
1923
	GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1924

1925
	if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1926
		return;
1927

1928
	/* Clear any previous failed attempts at recovery. Time to try again. */
1929
	if (!i915_gem_unset_wedged(i915))
1930 1931
		goto wakeup;

1932 1933
	if (reason)
		dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
1934
	error->reset_count++;
1935

1936 1937
	disable_irq(i915->drm.irq);
	ret = i915_gem_reset_prepare(i915);
1938
	if (ret) {
1939 1940
		dev_err(i915->drm.dev, "GPU recovery failed\n");
		goto taint;
1941
	}
1942

1943
	if (!intel_has_gpu_reset(i915)) {
1944 1945 1946 1947
		if (i915_modparams.reset)
			dev_err(i915->drm.dev, "GPU reset not supported\n");
		else
			DRM_DEBUG_DRIVER("GPU reset disabled\n");
1948 1949 1950 1951 1952 1953 1954 1955 1956 1957
		goto error;
	}

	for (i = 0; i < 3; i++) {
		ret = intel_gpu_reset(i915, ALL_ENGINES);
		if (ret == 0)
			break;

		msleep(100);
	}
1958
	if (ret) {
1959
		dev_err(i915->drm.dev, "Failed to reset chip\n");
1960
		goto taint;
1961 1962 1963 1964 1965 1966
	}

	/* Ok, now get things going again... */

	/*
	 * Everything depends on having the GTT running, so we need to start
1967 1968 1969 1970
	 * there.
	 */
	ret = i915_ggtt_enable_hw(i915);
	if (ret) {
1971 1972
		DRM_ERROR("Failed to re-enable GGTT following reset (%d)\n",
			  ret);
1973 1974 1975
		goto error;
	}

1976
	i915_gem_reset(i915, stalled_mask);
1977 1978
	intel_overlay_reset(i915);

1979
	/*
1980 1981 1982 1983 1984 1985 1986
	 * Next we need to restore the context, but we don't use those
	 * yet either...
	 *
	 * Ring buffer needs to be re-initialized in the KMS case, or if X
	 * was running at the time of the reset (i.e. we weren't VT
	 * switched away).
	 */
1987
	ret = i915_gem_init_hw(i915);
1988
	if (ret) {
1989 1990
		DRM_ERROR("Failed to initialise HW following reset (%d)\n",
			  ret);
1991
		goto error;
1992 1993
	}

1994
	i915_queue_hangcheck(i915);
1995

1996
finish:
1997 1998
	i915_gem_reset_finish(i915);
	enable_irq(i915->drm.irq);
1999

2000
wakeup:
2001 2002
	clear_bit(I915_RESET_HANDOFF, &error->flags);
	wake_up_bit(&error->flags, I915_RESET_HANDOFF);
2003
	return;
2004

2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018
taint:
	/*
	 * History tells us that if we cannot reset the GPU now, we
	 * never will. This then impacts everything that is run
	 * subsequently. On failing the reset, we mark the driver
	 * as wedged, preventing further execution on the GPU.
	 * We also want to go one step further and add a taint to the
	 * kernel so that any subsequent faults can be traced back to
	 * this failure. This is important for CI, where if the
	 * GPU/driver fails we would like to reboot and restart testing
	 * rather than continue on into oblivion. For everyone else,
	 * the system should still plod along, but they have been warned!
	 */
	add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
2019
error:
2020
	i915_gem_set_wedged(i915);
2021
	i915_retire_requests(i915);
2022
	goto finish;
2023 2024
}

2025 2026 2027 2028 2029 2030
static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
					struct intel_engine_cs *engine)
{
	return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
}

2031 2032 2033
/**
 * i915_reset_engine - reset GPU engine to recover from a hang
 * @engine: engine to reset
2034
 * @msg: reason for GPU reset; or NULL for no dev_notice()
2035 2036 2037
 *
 * Reset a specific GPU engine. Useful if a hang is detected.
 * Returns zero on successful reset or otherwise an error code.
2038 2039 2040 2041 2042
 *
 * Procedure is:
 *  - identifies the request that caused the hang and it is dropped
 *  - reset engine (which will force the engine to idle)
 *  - re-init/configure engine
2043
 */
2044
int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
2045
{
2046
	struct i915_gpu_error *error = &engine->i915->gpu_error;
2047
	struct i915_request *active_request;
2048 2049
	int ret;

2050
	GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
2051 2052
	GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));

2053 2054 2055 2056 2057 2058 2059
	active_request = i915_gem_reset_prepare_engine(engine);
	if (IS_ERR_OR_NULL(active_request)) {
		/* Either the previous reset failed, or we pardon the reset. */
		ret = PTR_ERR(active_request);
		goto out;
	}

2060
	if (msg)
2061
		dev_notice(engine->i915->drm.dev,
2062
			   "Resetting %s for %s\n", engine->name, msg);
2063
	error->reset_engine_count[engine->id]++;
2064

2065 2066 2067 2068
	if (!engine->i915->guc.execbuf_client)
		ret = intel_gt_reset_engine(engine->i915, engine);
	else
		ret = intel_guc_reset_engine(&engine->i915->guc, engine);
2069 2070
	if (ret) {
		/* If we fail here, we expect to fallback to a global reset */
2071 2072
		DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
				 engine->i915->guc.execbuf_client ? "GuC " : "",
2073 2074 2075
				 engine->name, ret);
		goto out;
	}
2076

2077 2078 2079 2080 2081
	/*
	 * The request that caused the hang is stuck on elsp, we know the
	 * active request and can drop it, adjust head to skip the offending
	 * request to resume executing remaining requests in the queue.
	 */
2082
	i915_gem_reset_engine(engine, active_request, true);
2083 2084 2085 2086 2087 2088 2089

	/*
	 * The engine and its registers (and workarounds in case of render)
	 * have been reset to their default values. Follow the init_ring
	 * process to program RING_MODE, HWSP and re-enable submission.
	 */
	ret = engine->init_hw(engine);
2090 2091
	if (ret)
		goto out;
2092 2093

out:
2094
	i915_gem_reset_finish_engine(engine);
2095
	return ret;
2096 2097
}

2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113
static int i915_pm_prepare(struct device *kdev)
{
	struct pci_dev *pdev = to_pci_dev(kdev);
	struct drm_device *dev = pci_get_drvdata(pdev);

	if (!dev) {
		dev_err(kdev, "DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

	return i915_drm_prepare(dev);
}

2114
static int i915_pm_suspend(struct device *kdev)
2115
{
2116 2117
	struct pci_dev *pdev = to_pci_dev(kdev);
	struct drm_device *dev = pci_get_drvdata(pdev);
2118

2119 2120
	if (!dev) {
		dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2121 2122
		return -ENODEV;
	}
2123

2124
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2125 2126
		return 0;

2127
	return i915_drm_suspend(dev);
2128 2129
}

2130
static int i915_pm_suspend_late(struct device *kdev)
2131
{
2132
	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2133 2134

	/*
D
Damien Lespiau 已提交
2135
	 * We have a suspend ordering issue with the snd-hda driver also
2136 2137 2138 2139 2140 2141 2142
	 * requiring our device to be power up. Due to the lack of a
	 * parent/child relationship we currently solve this with an late
	 * suspend hook.
	 *
	 * FIXME: This should be solved with a special hdmi sink device or
	 * similar so that power domains can be employed.
	 */
2143
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2144
		return 0;
2145

2146
	return i915_drm_suspend_late(dev, false);
2147 2148
}

2149
static int i915_pm_poweroff_late(struct device *kdev)
2150
{
2151
	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2152

2153
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2154 2155
		return 0;

2156
	return i915_drm_suspend_late(dev, true);
2157 2158
}

2159
static int i915_pm_resume_early(struct device *kdev)
2160
{
2161
	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2162

2163
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2164 2165
		return 0;

2166
	return i915_drm_resume_early(dev);
2167 2168
}

2169
static int i915_pm_resume(struct device *kdev)
2170
{
2171
	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2172

2173
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2174 2175
		return 0;

2176
	return i915_drm_resume(dev);
2177 2178
}

2179
/* freeze: before creating the hibernation_image */
2180
static int i915_pm_freeze(struct device *kdev)
2181
{
2182
	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2183 2184
	int ret;

2185 2186 2187 2188 2189
	if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
		ret = i915_drm_suspend(dev);
		if (ret)
			return ret;
	}
2190 2191 2192 2193 2194 2195

	ret = i915_gem_freeze(kdev_to_i915(kdev));
	if (ret)
		return ret;

	return 0;
2196 2197
}

2198
static int i915_pm_freeze_late(struct device *kdev)
2199
{
2200
	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2201 2202
	int ret;

2203 2204 2205 2206 2207
	if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
		ret = i915_drm_suspend_late(dev, true);
		if (ret)
			return ret;
	}
2208

2209
	ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2210 2211 2212 2213
	if (ret)
		return ret;

	return 0;
2214 2215 2216
}

/* thaw: called after creating the hibernation image, but before turning off. */
2217
static int i915_pm_thaw_early(struct device *kdev)
2218
{
2219
	return i915_pm_resume_early(kdev);
2220 2221
}

2222
static int i915_pm_thaw(struct device *kdev)
2223
{
2224
	return i915_pm_resume(kdev);
2225 2226 2227
}

/* restore: called after loading the hibernation image. */
2228
static int i915_pm_restore_early(struct device *kdev)
2229
{
2230
	return i915_pm_resume_early(kdev);
2231 2232
}

2233
static int i915_pm_restore(struct device *kdev)
2234
{
2235
	return i915_pm_resume(kdev);
2236 2237
}

2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276
/*
 * Save all Gunit registers that may be lost after a D3 and a subsequent
 * S0i[R123] transition. The list of registers needing a save/restore is
 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
 * registers in the following way:
 * - Driver: saved/restored by the driver
 * - Punit : saved/restored by the Punit firmware
 * - No, w/o marking: no need to save/restore, since the register is R/O or
 *                    used internally by the HW in a way that doesn't depend
 *                    keeping the content across a suspend/resume.
 * - Debug : used for debugging
 *
 * We save/restore all registers marked with 'Driver', with the following
 * exceptions:
 * - Registers out of use, including also registers marked with 'Debug'.
 *   These have no effect on the driver's operation, so we don't save/restore
 *   them to reduce the overhead.
 * - Registers that are fully setup by an initialization function called from
 *   the resume path. For example many clock gating and RPS/RC6 registers.
 * - Registers that provide the right functionality with their reset defaults.
 *
 * TODO: Except for registers that based on the above 3 criteria can be safely
 * ignored, we save/restore all others, practically treating the HW context as
 * a black-box for the driver. Further investigation is needed to reduce the
 * saved/restored registers even further, by following the same 3 criteria.
 */
static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
{
	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
	int i;

	/* GAM 0x4000-0x4770 */
	s->wr_watermark		= I915_READ(GEN7_WR_WATERMARK);
	s->gfx_prio_ctrl	= I915_READ(GEN7_GFX_PRIO_CTRL);
	s->arb_mode		= I915_READ(ARB_MODE);
	s->gfx_pend_tlb0	= I915_READ(GEN7_GFX_PEND_TLB0);
	s->gfx_pend_tlb1	= I915_READ(GEN7_GFX_PEND_TLB1);

	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2277
		s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2278 2279

	s->media_max_req_count	= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2280
	s->gfx_max_req_count	= I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320

	s->render_hwsp		= I915_READ(RENDER_HWS_PGA_GEN7);
	s->ecochk		= I915_READ(GAM_ECOCHK);
	s->bsd_hwsp		= I915_READ(BSD_HWS_PGA_GEN7);
	s->blt_hwsp		= I915_READ(BLT_HWS_PGA_GEN7);

	s->tlb_rd_addr		= I915_READ(GEN7_TLB_RD_ADDR);

	/* MBC 0x9024-0x91D0, 0x8500 */
	s->g3dctl		= I915_READ(VLV_G3DCTL);
	s->gsckgctl		= I915_READ(VLV_GSCKGCTL);
	s->mbctl		= I915_READ(GEN6_MBCTL);

	/* GCP 0x9400-0x9424, 0x8100-0x810C */
	s->ucgctl1		= I915_READ(GEN6_UCGCTL1);
	s->ucgctl3		= I915_READ(GEN6_UCGCTL3);
	s->rcgctl1		= I915_READ(GEN6_RCGCTL1);
	s->rcgctl2		= I915_READ(GEN6_RCGCTL2);
	s->rstctl		= I915_READ(GEN6_RSTCTL);
	s->misccpctl		= I915_READ(GEN7_MISCCPCTL);

	/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
	s->gfxpause		= I915_READ(GEN6_GFXPAUSE);
	s->rpdeuhwtc		= I915_READ(GEN6_RPDEUHWTC);
	s->rpdeuc		= I915_READ(GEN6_RPDEUC);
	s->ecobus		= I915_READ(ECOBUS);
	s->pwrdwnupctl		= I915_READ(VLV_PWRDWNUPCTL);
	s->rp_down_timeout	= I915_READ(GEN6_RP_DOWN_TIMEOUT);
	s->rp_deucsw		= I915_READ(GEN6_RPDEUCSW);
	s->rcubmabdtmr		= I915_READ(GEN6_RCUBMABDTMR);
	s->rcedata		= I915_READ(VLV_RCEDATA);
	s->spare2gh		= I915_READ(VLV_SPAREG2H);

	/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
	s->gt_imr		= I915_READ(GTIMR);
	s->gt_ier		= I915_READ(GTIER);
	s->pm_imr		= I915_READ(GEN6_PMIMR);
	s->pm_ier		= I915_READ(GEN6_PMIER);

	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2321
		s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332

	/* GT SA CZ domain, 0x100000-0x138124 */
	s->tilectl		= I915_READ(TILECTL);
	s->gt_fifoctl		= I915_READ(GTFIFOCTL);
	s->gtlc_wake_ctrl	= I915_READ(VLV_GTLC_WAKE_CTRL);
	s->gtlc_survive		= I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	s->pmwgicz		= I915_READ(VLV_PMWGICZ);

	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
	s->gu_ctl0		= I915_READ(VLV_GU_CTL0);
	s->gu_ctl1		= I915_READ(VLV_GU_CTL1);
2333
	s->pcbr			= I915_READ(VLV_PCBR);
2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358
	s->clock_gate_dis2	= I915_READ(VLV_GUNIT_CLOCK_GATE2);

	/*
	 * Not saving any of:
	 * DFT,		0x9800-0x9EC0
	 * SARB,	0xB000-0xB1FC
	 * GAC,		0x5208-0x524C, 0x14000-0x14C000
	 * PCI CFG
	 */
}

static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
{
	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
	u32 val;
	int i;

	/* GAM 0x4000-0x4770 */
	I915_WRITE(GEN7_WR_WATERMARK,	s->wr_watermark);
	I915_WRITE(GEN7_GFX_PRIO_CTRL,	s->gfx_prio_ctrl);
	I915_WRITE(ARB_MODE,		s->arb_mode | (0xffff << 16));
	I915_WRITE(GEN7_GFX_PEND_TLB0,	s->gfx_pend_tlb0);
	I915_WRITE(GEN7_GFX_PEND_TLB1,	s->gfx_pend_tlb1);

	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2359
		I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2360 2361

	I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2362
	I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402

	I915_WRITE(RENDER_HWS_PGA_GEN7,	s->render_hwsp);
	I915_WRITE(GAM_ECOCHK,		s->ecochk);
	I915_WRITE(BSD_HWS_PGA_GEN7,	s->bsd_hwsp);
	I915_WRITE(BLT_HWS_PGA_GEN7,	s->blt_hwsp);

	I915_WRITE(GEN7_TLB_RD_ADDR,	s->tlb_rd_addr);

	/* MBC 0x9024-0x91D0, 0x8500 */
	I915_WRITE(VLV_G3DCTL,		s->g3dctl);
	I915_WRITE(VLV_GSCKGCTL,	s->gsckgctl);
	I915_WRITE(GEN6_MBCTL,		s->mbctl);

	/* GCP 0x9400-0x9424, 0x8100-0x810C */
	I915_WRITE(GEN6_UCGCTL1,	s->ucgctl1);
	I915_WRITE(GEN6_UCGCTL3,	s->ucgctl3);
	I915_WRITE(GEN6_RCGCTL1,	s->rcgctl1);
	I915_WRITE(GEN6_RCGCTL2,	s->rcgctl2);
	I915_WRITE(GEN6_RSTCTL,		s->rstctl);
	I915_WRITE(GEN7_MISCCPCTL,	s->misccpctl);

	/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
	I915_WRITE(GEN6_GFXPAUSE,	s->gfxpause);
	I915_WRITE(GEN6_RPDEUHWTC,	s->rpdeuhwtc);
	I915_WRITE(GEN6_RPDEUC,		s->rpdeuc);
	I915_WRITE(ECOBUS,		s->ecobus);
	I915_WRITE(VLV_PWRDWNUPCTL,	s->pwrdwnupctl);
	I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
	I915_WRITE(GEN6_RPDEUCSW,	s->rp_deucsw);
	I915_WRITE(GEN6_RCUBMABDTMR,	s->rcubmabdtmr);
	I915_WRITE(VLV_RCEDATA,		s->rcedata);
	I915_WRITE(VLV_SPAREG2H,	s->spare2gh);

	/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
	I915_WRITE(GTIMR,		s->gt_imr);
	I915_WRITE(GTIER,		s->gt_ier);
	I915_WRITE(GEN6_PMIMR,		s->pm_imr);
	I915_WRITE(GEN6_PMIER,		s->pm_ier);

	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2403
		I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427

	/* GT SA CZ domain, 0x100000-0x138124 */
	I915_WRITE(TILECTL,			s->tilectl);
	I915_WRITE(GTFIFOCTL,			s->gt_fifoctl);
	/*
	 * Preserve the GT allow wake and GFX force clock bit, they are not
	 * be restored, as they are used to control the s0ix suspend/resume
	 * sequence by the caller.
	 */
	val = I915_READ(VLV_GTLC_WAKE_CTRL);
	val &= VLV_GTLC_ALLOWWAKEREQ;
	val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
	I915_WRITE(VLV_GTLC_WAKE_CTRL, val);

	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	val &= VLV_GFX_CLK_FORCE_ON_BIT;
	val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);

	I915_WRITE(VLV_PMWGICZ,			s->pmwgicz);

	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
	I915_WRITE(VLV_GU_CTL0,			s->gu_ctl0);
	I915_WRITE(VLV_GU_CTL1,			s->gu_ctl1);
2428
	I915_WRITE(VLV_PCBR,			s->pcbr);
2429 2430 2431
	I915_WRITE(VLV_GUNIT_CLOCK_GATE2,	s->clock_gate_dis2);
}

2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445
static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
				  u32 mask, u32 val)
{
	/* The HW does not like us polling for PW_STATUS frequently, so
	 * use the sleeping loop rather than risk the busy spin within
	 * intel_wait_for_register().
	 *
	 * Transitioning between RC6 states should be at most 2ms (see
	 * valleyview_enable_rps) so use a 3ms timeout.
	 */
	return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
			3);
}

2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
{
	u32 val;
	int err;

	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
	if (force_on)
		val |= VLV_GFX_CLK_FORCE_ON_BIT;
	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);

	if (!force_on)
		return 0;

2460 2461 2462 2463 2464
	err = intel_wait_for_register(dev_priv,
				      VLV_GTLC_SURVIVABILITY_REG,
				      VLV_GFX_CLK_STATUS_BIT,
				      VLV_GFX_CLK_STATUS_BIT,
				      20);
2465 2466 2467 2468 2469 2470 2471
	if (err)
		DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
			  I915_READ(VLV_GTLC_SURVIVABILITY_REG));

	return err;
}

2472 2473
static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
{
2474
	u32 mask;
2475
	u32 val;
2476
	int err;
2477 2478 2479 2480 2481 2482 2483 2484

	val = I915_READ(VLV_GTLC_WAKE_CTRL);
	val &= ~VLV_GTLC_ALLOWWAKEREQ;
	if (allow)
		val |= VLV_GTLC_ALLOWWAKEREQ;
	I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
	POSTING_READ(VLV_GTLC_WAKE_CTRL);

2485 2486 2487 2488
	mask = VLV_GTLC_ALLOWWAKEACK;
	val = allow ? mask : 0;

	err = vlv_wait_for_pw_status(dev_priv, mask, val);
2489 2490
	if (err)
		DRM_ERROR("timeout disabling GT waking\n");
2491

2492 2493 2494
	return err;
}

2495 2496
static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
				  bool wait_for_on)
2497 2498 2499 2500 2501 2502 2503 2504 2505 2506
{
	u32 mask;
	u32 val;

	mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
	val = wait_for_on ? mask : 0;

	/*
	 * RC6 transitioning can be delayed up to 2 msec (see
	 * valleyview_enable_rps), use 3 msec for safety.
2507 2508 2509
	 *
	 * This can fail to turn off the rc6 if the GPU is stuck after a failed
	 * reset and we are trying to force the machine to sleep.
2510
	 */
2511
	if (vlv_wait_for_pw_status(dev_priv, mask, val))
2512 2513
		DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
				 onoff(wait_for_on));
2514 2515 2516 2517 2518 2519 2520
}

static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
{
	if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
		return;

2521
	DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2522 2523 2524
	I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
}

2525
static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2526 2527 2528 2529 2530 2531 2532 2533
{
	u32 mask;
	int err;

	/*
	 * Bspec defines the following GT well on flags as debug only, so
	 * don't treat them as hard failures.
	 */
2534
	vlv_wait_for_gt_wells(dev_priv, false);
2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547

	mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
	WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);

	vlv_check_no_gt_access(dev_priv);

	err = vlv_force_gfx_clock(dev_priv, true);
	if (err)
		goto err1;

	err = vlv_allow_gt_wake(dev_priv, false);
	if (err)
		goto err2;
2548

2549
	if (!IS_CHERRYVIEW(dev_priv))
2550
		vlv_save_gunit_s0ix_state(dev_priv);
2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566

	err = vlv_force_gfx_clock(dev_priv, false);
	if (err)
		goto err2;

	return 0;

err2:
	/* For safety always re-enable waking and disable gfx clock forcing */
	vlv_allow_gt_wake(dev_priv, true);
err1:
	vlv_force_gfx_clock(dev_priv, false);

	return err;
}

2567 2568
static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
				bool rpm_resume)
2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579
{
	int err;
	int ret;

	/*
	 * If any of the steps fail just try to continue, that's the best we
	 * can do at this point. Return the first error code (which will also
	 * leave RPM permanently disabled).
	 */
	ret = vlv_force_gfx_clock(dev_priv, true);

2580
	if (!IS_CHERRYVIEW(dev_priv))
2581
		vlv_restore_gunit_s0ix_state(dev_priv);
2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592

	err = vlv_allow_gt_wake(dev_priv, true);
	if (!ret)
		ret = err;

	err = vlv_force_gfx_clock(dev_priv, false);
	if (!ret)
		ret = err;

	vlv_check_no_gt_access(dev_priv);

2593
	if (rpm_resume)
2594
		intel_init_clock_gating(dev_priv);
2595 2596 2597 2598

	return ret;
}

2599
static int intel_runtime_suspend(struct device *kdev)
2600
{
2601
	struct pci_dev *pdev = to_pci_dev(kdev);
2602
	struct drm_device *dev = pci_get_drvdata(pdev);
2603
	struct drm_i915_private *dev_priv = to_i915(dev);
2604
	int ret;
2605

2606
	if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2607 2608
		return -ENODEV;

2609
	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2610 2611
		return -ENODEV;

2612 2613
	DRM_DEBUG_KMS("Suspending device\n");

2614 2615
	disable_rpm_wakeref_asserts(dev_priv);

2616 2617 2618 2619
	/*
	 * We are safe here against re-faults, since the fault handler takes
	 * an RPM reference.
	 */
2620
	i915_gem_runtime_suspend(dev_priv);
2621

2622
	intel_uc_suspend(dev_priv);
2623

2624
	intel_runtime_pm_disable_interrupts(dev_priv);
2625

2626 2627
	intel_uncore_suspend(dev_priv);

2628
	ret = 0;
2629
	if (IS_GEN9_LP(dev_priv)) {
2630 2631 2632 2633 2634 2635 2636 2637
		bxt_display_core_uninit(dev_priv);
		bxt_enable_dc9(dev_priv);
	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
		hsw_enable_pc8(dev_priv);
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
		ret = vlv_suspend_complete(dev_priv);
	}

2638 2639
	if (ret) {
		DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2640 2641
		intel_uncore_runtime_resume(dev_priv);

2642
		intel_runtime_pm_enable_interrupts(dev_priv);
2643

2644
		intel_uc_resume(dev_priv);
2645 2646 2647 2648

		i915_gem_init_swizzling(dev_priv);
		i915_gem_restore_fences(dev_priv);

2649 2650
		enable_rpm_wakeref_asserts(dev_priv);

2651 2652
		return ret;
	}
2653

2654
	enable_rpm_wakeref_asserts(dev_priv);
2655
	WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2656

2657
	if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2658 2659
		DRM_ERROR("Unclaimed access detected prior to suspending\n");

2660
	dev_priv->runtime_pm.suspended = true;
2661 2662

	/*
2663 2664
	 * FIXME: We really should find a document that references the arguments
	 * used below!
2665
	 */
2666
	if (IS_BROADWELL(dev_priv)) {
2667 2668 2669 2670 2671 2672
		/*
		 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
		 * being detected, and the call we do at intel_runtime_resume()
		 * won't be able to restore them. Since PCI_D3hot matches the
		 * actual specification and appears to be working, use it.
		 */
2673
		intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2674
	} else {
2675 2676 2677 2678 2679 2680 2681
		/*
		 * current versions of firmware which depend on this opregion
		 * notification have repurposed the D1 definition to mean
		 * "runtime suspended" vs. what you would normally expect (D3)
		 * to distinguish it from notifications that might be sent via
		 * the suspend path.
		 */
2682
		intel_opregion_notify_adapter(dev_priv, PCI_D1);
2683
	}
2684

2685
	assert_forcewakes_inactive(dev_priv);
2686

2687
	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2688 2689
		intel_hpd_poll_init(dev_priv);

2690
	DRM_DEBUG_KMS("Device suspended\n");
2691 2692 2693
	return 0;
}

2694
static int intel_runtime_resume(struct device *kdev)
2695
{
2696
	struct pci_dev *pdev = to_pci_dev(kdev);
2697
	struct drm_device *dev = pci_get_drvdata(pdev);
2698
	struct drm_i915_private *dev_priv = to_i915(dev);
2699
	int ret = 0;
2700

2701
	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2702
		return -ENODEV;
2703 2704 2705

	DRM_DEBUG_KMS("Resuming device\n");

2706
	WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2707 2708
	disable_rpm_wakeref_asserts(dev_priv);

2709
	intel_opregion_notify_adapter(dev_priv, PCI_D0);
2710
	dev_priv->runtime_pm.suspended = false;
2711 2712
	if (intel_uncore_unclaimed_mmio(dev_priv))
		DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2713

2714
	if (IS_GEN9_LP(dev_priv)) {
2715 2716
		bxt_disable_dc9(dev_priv);
		bxt_display_core_init(dev_priv, true);
2717 2718 2719
		if (dev_priv->csr.dmc_payload &&
		    (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
			gen9_enable_dc5(dev_priv);
2720
	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2721
		hsw_disable_pc8(dev_priv);
2722
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2723
		ret = vlv_resume_prepare(dev_priv, true);
2724
	}
2725

2726 2727
	intel_uncore_runtime_resume(dev_priv);

2728 2729
	intel_runtime_pm_enable_interrupts(dev_priv);

2730
	intel_uc_resume(dev_priv);
2731

2732 2733 2734 2735
	/*
	 * No point of rolling back things in case of an error, as the best
	 * we can do is to hope that things will still work (and disable RPM).
	 */
2736
	i915_gem_init_swizzling(dev_priv);
2737
	i915_gem_restore_fences(dev_priv);
2738

2739 2740 2741 2742 2743
	/*
	 * On VLV/CHV display interrupts are part of the display
	 * power well, so hpd is reinitialized from there. For
	 * everyone else do it here.
	 */
2744
	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2745 2746
		intel_hpd_init(dev_priv);

2747 2748
	intel_enable_ipc(dev_priv);

2749 2750
	enable_rpm_wakeref_asserts(dev_priv);

2751 2752 2753 2754 2755 2756
	if (ret)
		DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
	else
		DRM_DEBUG_KMS("Device resumed\n");

	return ret;
2757 2758
}

2759
const struct dev_pm_ops i915_pm_ops = {
2760 2761 2762 2763
	/*
	 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
	 * PMSG_RESUME]
	 */
2764
	.prepare = i915_pm_prepare,
2765
	.suspend = i915_pm_suspend,
2766 2767
	.suspend_late = i915_pm_suspend_late,
	.resume_early = i915_pm_resume_early,
2768
	.resume = i915_pm_resume,
2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784

	/*
	 * S4 event handlers
	 * @freeze, @freeze_late    : called (1) before creating the
	 *                            hibernation image [PMSG_FREEZE] and
	 *                            (2) after rebooting, before restoring
	 *                            the image [PMSG_QUIESCE]
	 * @thaw, @thaw_early       : called (1) after creating the hibernation
	 *                            image, before writing it [PMSG_THAW]
	 *                            and (2) after failing to create or
	 *                            restore the image [PMSG_RECOVER]
	 * @poweroff, @poweroff_late: called after writing the hibernation
	 *                            image, before rebooting [PMSG_HIBERNATE]
	 * @restore, @restore_early : called after rebooting and restoring the
	 *                            hibernation image [PMSG_RESTORE]
	 */
2785 2786 2787 2788
	.freeze = i915_pm_freeze,
	.freeze_late = i915_pm_freeze_late,
	.thaw_early = i915_pm_thaw_early,
	.thaw = i915_pm_thaw,
2789
	.poweroff = i915_pm_suspend,
2790
	.poweroff_late = i915_pm_poweroff_late,
2791 2792
	.restore_early = i915_pm_restore_early,
	.restore = i915_pm_restore,
2793 2794

	/* S0ix (via runtime suspend) event handlers */
2795 2796
	.runtime_suspend = intel_runtime_suspend,
	.runtime_resume = intel_runtime_resume,
2797 2798
};

2799
static const struct vm_operations_struct i915_gem_vm_ops = {
2800
	.fault = i915_gem_fault,
2801 2802
	.open = drm_gem_vm_open,
	.close = drm_gem_vm_close,
2803 2804
};

2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816
static const struct file_operations i915_driver_fops = {
	.owner = THIS_MODULE,
	.open = drm_open,
	.release = drm_release,
	.unlocked_ioctl = drm_ioctl,
	.mmap = drm_gem_mmap,
	.poll = drm_poll,
	.read = drm_read,
	.compat_ioctl = i915_compat_ioctl,
	.llseek = noop_llseek,
};

2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830
static int
i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file)
{
	return -ENODEV;
}

static const struct drm_ioctl_desc i915_ioctls[] = {
	DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2831
	DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842
	DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2843 2844
	DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859
	DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2860 2861
	DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2862
	DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2863
	DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2864 2865 2866
	DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2867
	DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2868 2869 2870 2871 2872 2873 2874 2875 2876
	DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2877
	DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2878 2879
	DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
L
Lionel Landwerlin 已提交
2880
	DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2881 2882
};

L
Linus Torvalds 已提交
2883
static struct drm_driver driver = {
2884 2885
	/* Don't use MTRRs here; the Xserver or userspace app should
	 * deal with them for Intel hardware.
D
Dave Airlie 已提交
2886
	 */
2887
	.driver_features =
2888
	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2889
	    DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2890
	.release = i915_driver_release,
2891
	.open = i915_driver_open,
2892
	.lastclose = i915_driver_lastclose,
2893
	.postclose = i915_driver_postclose,
2894

2895
	.gem_close_object = i915_gem_close_object,
C
Chris Wilson 已提交
2896
	.gem_free_object_unlocked = i915_gem_free_object,
2897
	.gem_vm_ops = &i915_gem_vm_ops,
2898 2899 2900 2901 2902 2903

	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
	.gem_prime_export = i915_gem_prime_export,
	.gem_prime_import = i915_gem_prime_import,

2904
	.dumb_create = i915_gem_dumb_create,
2905
	.dumb_map_offset = i915_gem_mmap_gtt,
L
Linus Torvalds 已提交
2906
	.ioctls = i915_ioctls,
2907
	.num_ioctls = ARRAY_SIZE(i915_ioctls),
2908
	.fops = &i915_driver_fops,
2909 2910 2911 2912 2913 2914
	.name = DRIVER_NAME,
	.desc = DRIVER_DESC,
	.date = DRIVER_DATE,
	.major = DRIVER_MAJOR,
	.minor = DRIVER_MINOR,
	.patchlevel = DRIVER_PATCHLEVEL,
L
Linus Torvalds 已提交
2915
};
2916 2917 2918 2919

#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/mock_drm.c"
#endif