1. 01 6月, 2018 1 次提交
  2. 25 5月, 2018 1 次提交
  3. 08 5月, 2018 1 次提交
  4. 03 5月, 2018 1 次提交
  5. 18 4月, 2018 1 次提交
  6. 15 4月, 2018 1 次提交
  7. 07 4月, 2018 2 次提交
    • C
      drm/i915: Pass the set of guilty engines to i915_reset() · d0667e9c
      Chris Wilson 提交于
      Currently, we rely on inspecting the hangcheck state from within the
      i915_reset() routines to determine which engines were guilty of the
      hang. This is problematic for cases where we want to run
      i915_handle_error() and call i915_reset() independently of hangcheck.
      Instead of relying on the indirect parameter passing, turn it into an
      explicit parameter providing the set of stalled engines which then are
      treated as guilty until proven innocent.
      
      While we are removing the implicit stalled parameter, also make the
      reason into an explicit parameter to i915_reset(). We still need a
      back-channel for i915_handle_error() to hand over the task to the locked
      waiter, but let's keep that its own channel rather than incriminate
      another.
      
      This leaves stalled/seqno as being private to hangcheck, with no more
      nefarious snooping by reset, be it whole-device or per-engine. \o/
      
      The only real issue now is that this makes it crystal clear that we
      don't actually do any testing of hangcheck per se in
      drv_selftest/live_hangcheck, merely of resets!
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Michel Thierry <michel.thierry@intel.com>
      Cc: Jeff McGee <jeff.mcgee@intel.com>
      Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
      Reviewed-by: NMichel Thierry <michel.thierry@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180406220354.18911-2-chris@chris-wilson.co.uk
      d0667e9c
    • C
      drm/i915: Treat i915_reset_engine() as guilty until proven innocent · bba0869b
      Chris Wilson 提交于
      If we are resetting just one engine, we know it has stalled. So we can
      pass the stalled parameter directly to i915_gem_reset_engine(), which
      alleviates the necessity to poke at the generic engine->hangcheck.stalled
      magic variable, leaving that under control of hangcheck as its name
      implies. Other than simplifying by removing the indirect parameter along
      this path, this allows us to introduce new reset mechanisms that run
      independently of hangcheck.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Michel Thierry <michel.thierry@intel.com>
      Cc: Jeff McGee <jeff.mcgee@intel.com>
      Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
      Reviewed-by: NMichel Thierry <michel.thierry@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180406220354.18911-1-chris@chris-wilson.co.uk
      bba0869b
  8. 06 4月, 2018 1 次提交
  9. 27 3月, 2018 1 次提交
    • I
      drm/i915: Fix hibernation with ACPI S0 target state · 300efa9e
      Imre Deak 提交于
      After
      
      commit dd9f31c7
      Author: Imre Deak <imre.deak@intel.com>
      Date:   Wed Aug 16 17:46:07 2017 +0300
      
          drm/i915/gen9+: Set same power state before hibernation image
          save/restore
      
      during hibernation/suspend the power domain functionality got disabled,
      after which resume could leave it incorrectly disabled if the ACPI
      target state was S0 during suspend and i915 was not loaded by the loader
      kernel.
      
      This was caused by not considering if we resumed from hibernation as the
      condition for power domains reiniting.
      
      Fix this by simply tracking if we suspended power domains during system
      suspend and reinit power domains accordingly during resume. This will
      result in reiniting power domains always when resuming from hibernation,
      regardless of the platform and whether or not i915 is loaded by the
      loader kernel.
      
      The reason we didn't catch this earlier is that the enabled/disabled
      state of power domains during PMSG_FREEZE/PMSG_QUIESCE is platform
      and kernel config dependent: on my SKL the target state is S4
      during PMSG_FREEZE and (with the driver loaded in the loader kernel)
      S0 during PMSG_QUIESCE. On the reporter's machine it's S0 during
      PMSG_FREEZE but (contrary to this) power domains are not initialized
      during PMSG_QUIESCE since i915 is not loaded in the loader kernel, or
      it's loaded but without the DMC firmware being available.
      
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105196
      Reported-and-tested-by: amn-bas@hotmail.com
      Fixes: dd9f31c7 ("drm/i915/gen9+: Set same power state before hibernation image save/restore")
      Cc: amn-bas@hotmail.com
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Cc: <stable@vger.kernel.org>
      Signed-off-by: NImre Deak <imre.deak@intel.com>
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180322143642.26883-1-imre.deak@intel.com
      (cherry picked from commit 0f90603c)
      Signed-off-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      300efa9e
  10. 24 3月, 2018 3 次提交
  11. 21 3月, 2018 1 次提交
  12. 20 3月, 2018 2 次提交
    • C
      drm/i915: Add control flags to i915_handle_error() · ce800754
      Chris Wilson 提交于
      Not all callers want the GPU error to handled in the same way, so expose
      a control parameter. In the first instance, some callers do not want the
      heavyweight error capture so add a bit to request the state to be
      captured and saved.
      
      v2: Pass msg down to i915_reset/i915_reset_engine so that we include the
      reason for the reset in the dev_notice(), superseding the earlier option
      to not print that notice.
      v3: Stash the reason inside the i915->gpu_error to handover to the direct
      reset from the blocking waiter.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Jeff McGee <jeff.mcgee@intel.com>
      Cc: Mika Kuoppala <mika.kuoppala@intel.com>
      Cc: Michel Thierry <michel.thierry@intel.com>
      Reviewed-by: NMichel Thierry <michel.thierry@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180320100449.1360-2-chris@chris-wilson.co.uk
      ce800754
    • O
      drm/i915/icl: Check for fused-off VDBOX and VEBOX instances · 26376a7e
      Oscar Mateo 提交于
      In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the
      Video Enhancement engines (aka VEBOX, aka VECS) could be fused off. Also,
      each VDBOX and VEBOX has its own power well, which only exist if the
      related engine exists in the HW.
      
      Unfortunately, we have a Catch-22 situation going on: we need the blitter
      forcewake to read the register with the fuse info, but we cannot initialize
      the forcewake domains without knowin about the engines present in the HW.
      We workaround this problem by allowing the initialization of all forcewake
      domains and then pruning the fused off ones, as per the fuse information.
      
      Bspec: 20680
      
      v2: We were shifting incorrectly for vebox disable (Vinay)
      
      v3: Assert mmio is ready and warn if we have attempted to initialize
          forcewake for fused-off engines (Paulo)
      
      v4:
        - Use INTEL_GEN in new code (Tvrtko)
        - Shorter local variable (Tvrtko, Michal)
        - Keep "if (!...) continue" style (Tvrtko)
        - No unnecessary BUG_ON (Tvrtko)
        - WARN_ON and cleanup if wrong mask (Tvrtko, Michal)
        - Use I915_READ_FW (Michal)
        - Use I915_MAX_VCS/VECS macros (Michal)
      
      v5: Rebased by Rodrigo fixing conflicts on top of:
          "drm/i915: Simplify intel_engines_init"
      
      v6: Fix v5. Remove info->num_rings. (by Oscar)
      
      v7: Rebase (Rodrigo).
      
      v8:
        - s/intel_device_info_fused_off_engines/
          intel_device_info_init_mmio (Chris)
        - Make vdbox_disable & vebox_disable local variables (Chris)
      
      v9:
        - Move function declaration to intel_device_info.h (Michal)
        - Missing indent in bit fields definitions (Michal)
        - When RC6 is enabled by BIOS, the fuse register cannot be read until
          the blitter powerwell is awake. Shuffle where the fuse is read, prune
          the forcewake domains after the fact and change the commit message
          accordingly (Vinay, Sagar, Chris).
      
      v10:
        - Improved commit message (Sagar)
        - New line in header file (Sagar)
        - Specify the message in fw_domain_reset applies to ICL+ (Sagar)
      
      Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
      Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
      Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
      Signed-off-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: NOscar Mateo <oscar.mateo@intel.com>
      Reviewed-by: NSagar Arun Kamble <sagar.a.kamble@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180316121456.11577-1-mika.kuoppala@linux.intel.com
      [Mika: soothe checkpatch on commit msg]
      Signed-off-by: NMika Kuoppala <mika.kuoppala@linux.intel.com>
      26376a7e
  13. 19 3月, 2018 1 次提交
  14. 16 3月, 2018 1 次提交
    • C
      drm/i915: Stop engines when declaring the machine wedged · ac697ae8
      Chris Wilson 提交于
      If we fail to reset the GPU, we declare the machine wedged. However, the
      GPU may well still be running in the background with an in-flight
      request. So despite our efforts in cleaning up the request queue and
      faking the breadcrumb in the HWSP, the GPU may eventually write the
      in-flght seqno there breaking all of our assumptions and throwing the
      driver into a deep turmoil, wedging beyond wedged.
      
      To avoid this we ideally want to reset the GPU. Since that has already
      failed, make sure the rings have the stop bit set instead. This is part
      of the normal GPU reset sequence, but that is actually disabled by
      igt/gem_eio to force the wedged state. If we assume the worst, we must
      poke at the bit again before we give up.
      
      v2: Move the intel_gpu_reset() from set-wedged in the reset error path
      into i915_gem_set_wedged() itself. Even if the reset fails (e.g. if it is
      disabled by gem_eio), it still tries to make sure the engines are
      stopped. For i915_gem_set_wedged() callers from outside of i915_reset(),
      this should make sure the GPU is disabled while the driver is marked as
      being wedged.
      
      Testcase: igt/gem_eio
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
      Cc: Michał Winiarski <michal.winiarski@intel.com>
      Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
      Cc: Michel Thierry <michel.thierry@intel.com>
      Reviewed-by: NMika Kuoppala <mika.kuoppala@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180315151015.22741-1-chris@chris-wilson.co.uk
      ac697ae8
  15. 14 3月, 2018 1 次提交
    • J
      drm/i915: Implement dynamic GuC WOPCM offset and size calculation · 6b0478fb
      Jackie Li 提交于
      Hardware may have specific restrictions on GuC WOPCM offset and size. On
      Gen9, the value of the GuC WOPCM size register needs to be larger than the
      value of GuC WOPCM offset register + a Gen9 specific offset (144KB) for
      reserved GuC WOPCM. Fail to enforce such a restriction on GuC WOPCM size
      will lead to GuC firmware execution failures. On the other hand, with
      current static GuC WOPCM offset and size values (512KB for both offset and
      size), the GuC WOPCM size verification will fail on Gen9 even if it can be
      fixed by lowering the GuC WOPCM offset by calculating its value based on
      HuC firmware size (which is likely less than 200KB on Gen9), so that we can
      have a GuC WOPCM size value which is large enough to pass the GuC WOPCM
      size check.
      
      This patch updates the reserved GuC WOPCM size for RC6 context on Gen9 to
      24KB to strictly align with the Gen9 GuC WOPCM layout. It also adds support
      to verify the GuC WOPCM size aganist the Gen9 hardware restrictions. To
      meet all above requirements, let's provide dynamic partitioning of the
      WOPCM that will be based on platform specific HuC/GuC firmware sizes.
      
      v2:
       - Removed intel_wopcm_init (Ville/Sagar/Joonas)
       - Renamed and Moved the intel_wopcm_partition into intel_guc (Sagar)
       - Removed unnecessary function calls (Joonas)
       - Init GuC WOPCM partition as soon as firmware fetching is completed
      
      v3:
       - Fixed indentation issues (Chris)
       - Removed layering violation code (Chris/Michal)
       - Created separat files for GuC wopcm code  (Michal)
       - Used inline function to avoid code duplication (Michal)
      
      v4:
       - Preset the GuC WOPCM top during early GuC init (Chris)
       - Fail intel_uc_init_hw() as soon as GuC WOPCM partitioning failed
      
      v5:
       - Moved GuC DMA WOPCM register updating code into intel_wopcm.c
       - Took care of the locking status before writing to GuC DMA
         Write-Once registers. (Joonas)
      
      v6:
       - Made sure the GuC WOPCM size to be multiple of 4K (4K aligned)
      
      v8:
       - Updated comments and fixed naming issues (Sagar/Joonas)
       - Updated commit message to include more description about the hardware
         restriction on GuC WOPCM size (Sagar)
      
      v9:
       - Minor changes variable names and code comments (Sagar)
       - Added detailed GuC WOPCM layout drawing (Sagar/Michal)
       - Refined macro definitions to be reader friendly (Michal)
       - Removed redundent check to valid flag (Michal)
       - Unified first parameter for exported GuC WOPCM functions (Michal)
       - Refined the name and parameter list of hardware restriction checking
         functions (Michal)
      
      v10:
       - Used shorter function name for internal functions (Joonas)
       - Moved init-ealry function into c file (Joonas)
       - Consolidated and removed redundant size checks (Joonas/Michal)
       - Removed unnecessary unlikely() from code which is only called once
         during boot (Joonas)
       - More fixes to kernel-doc format and content (Michal)
       - Avoided the use of PAGE_MASK for 4K pages (Michal)
       - Added error log messages to error paths (Michal)
      
      v11:
       - Replaced intel_guc_wopcm with more generic intel_wopcm and attached
         intel_wopcm to drm_i915_private instead intel_guc (Michal)
       - dynamic calculation of GuC non-wopcm memory start (a.k.a WOPCM Top
         offset from GuC WOPCM base) (Michal)
       - Moved WOPCM marco definitions into .c source file (Michal)
       - Exported WOPCM layout diagram as kernel-doc (Michal)
      
      v12:
       - Updated naming, function kernel-doc to align with new changes (Michal)
      
      v13:
       - Updated the ordering of s-o-b/cc/r-b tags (Sagar)
       - Corrected one tense error in comment (Sagar)
       - Corrected typos and removed spurious comments (Joonas)
      
      Bspec: 12690
      Signed-off-by: NJackie Li <yaodong.li@intel.com>
      Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
      Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
      Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
      Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
      Cc: John Spotswood <john.a.spotswood@intel.com>
      Cc: Oscar Mateo <oscar.mateo@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> (v8)
      Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v9)
      Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> (v11)
      Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v12)
      Reviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Signed-off-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/1520987574-19351-2-git-send-email-yaodong.li@intel.com
      6b0478fb
  16. 13 3月, 2018 1 次提交
  17. 10 3月, 2018 1 次提交
  18. 08 3月, 2018 2 次提交
    • L
      drm/i915: add query uAPI · a446ae2c
      Lionel Landwerlin 提交于
      There are a number of information that are readable from hardware
      registers and that we would like to make accessible to userspace. One
      particular example is the topology of the execution units (how are
      execution units grouped in subslices and slices and also which ones
      have been fused off for die recovery).
      
      At the moment the GET_PARAM ioctl covers some basic needs, but
      generally is only able to return a single value for each defined
      parameter. This is a bit problematic with topology descriptions which
      are array/maps of available units.
      
      This change introduces a new ioctl that can deal with requests to fill
      structures of potentially variable lengths. The user is expected fill
      a query with length fields set at 0 on the first call, the kernel then
      sets the length fields to the their expected values. A second call to
      the kernel with length fields at their expected values will trigger a
      copy of the data to the pointed memory locations.
      
      The scope of this uAPI is only to provide information to userspace,
      not to allow configuration of the device.
      
      v2: Simplify dispatcher code iteration (Tvrtko)
          Tweak uapi drm_i915_query_item structure (Tvrtko)
      
      v3: Rename pad fields into flags (Chris)
          Return error on flags field != 0 (Chris)
          Only copy length back to userspace in drm_i915_query_item (Chris)
      
      v4: Use array of functions instead of switch (Chris)
      
      v5: More comments in uapi (Tvrtko)
          Return query item errors in length field (All)
      
      v6: Tweak uapi comments style to match the coding style (Lionel)
      
      v7: Add i915_query.h (Joonas)
      
      v8: (Lionel) Change the behavior of the item iterator to report
          invalid queries into the query item rather than stopping the
          iteration. This enables userspace applications to query newer
          items on older kernels and only have failure on the items that are
          not supported.
      
      v9: Edit copyright headers (Joonas)
      
      v10: Typos & comments in uapi (Joonas)
      Signed-off-by: NLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Acked-by: NChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180306122857.27317-6-lionel.g.landwerlin@intel.com
      a446ae2c
    • L
      drm/i915: store all subslice masks · 8cc76693
      Lionel Landwerlin 提交于
      Up to now, subslice mask was assumed to be uniform across slices. But
      starting with Cannonlake, slices can be asymmetric (for example slice0
      has different number of subslices as slice1+). This change stores all
      subslices masks for all slices rather than having a single mask that
      applies to all slices.
      
      v2: Rework how we store total numbers in sseu_dev_info (Tvrtko)
          Fix CHV eu masks, was reading disabled as enabled (Tvrtko)
          Readability changes (Tvrtko)
          Add EU index helper (Tvrtko)
      
      v3: Turn ALIGN(v, 8) / 8 into DIV_ROUND_UP(v, BITS_PER_BYTE) (Tvrtko)
          Reuse sseu_eu_idx() for setting eu_mask on CHV (Tvrtko)
          Reformat debug prints for subslices (Tvrtko)
      
      v4: Change eu_mask helper into sseu_set_eus() (Tvrtko)
      
      v5: With Haswell reporting masks & counts, bump sseu_*_eus() functions
          to use u16 (Lionel)
      
      v6: Fix sseu_get_eus() for > 8 EUs per subslice (Lionel)
      
      v7: Change debugfs enabels for number of subslices per slice, will
          need a small igt/pm_sseu change (Lionel)
          Drop subslice_total field from sseu_dev_info, rely on
          sseu_subslice_total() to recompute the value instead (Lionel)
      
      v8: Remove unused function compute_subslice_total() (Lionel)
      Signed-off-by: NLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Acked-by: NChris Wilson <chris@chris-wilson.co.uk>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180306122857.27317-2-lionel.g.landwerlin@intel.com
      8cc76693
  19. 03 3月, 2018 1 次提交
  20. 22 2月, 2018 1 次提交
  21. 16 2月, 2018 3 次提交
  22. 15 2月, 2018 1 次提交
  23. 14 2月, 2018 1 次提交
  24. 13 2月, 2018 3 次提交
  25. 12 2月, 2018 1 次提交
  26. 10 2月, 2018 1 次提交
  27. 08 2月, 2018 2 次提交
  28. 07 2月, 2018 1 次提交
  29. 02 2月, 2018 2 次提交