i915_drv.c 80.9 KB
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/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#include <linux/acpi.h>
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#include <linux/device.h>
#include <linux/oom.h>
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#include <linux/module.h>
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#include <linux/pci.h>
#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/pnp.h>
#include <linux/slab.h>
#include <linux/vgaarb.h>
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#include <linux/vga_switcheroo.h>
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#include <linux/vt.h>
#include <acpi/video.h>

#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/i915_drm.h>

#include "i915_drv.h"
#include "i915_trace.h"
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#include "i915_pmu.h"
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#include "i915_vgpu.h"
#include "intel_drv.h"
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#include "intel_uc.h"
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static struct drm_driver driver;

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static unsigned int i915_load_fail_count;

bool __i915_inject_load_failure(const char *func, int line)
{
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	if (i915_load_fail_count >= i915_modparams.inject_load_failure)
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		return false;

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	if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
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		DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
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			 i915_modparams.inject_load_failure, func, line);
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		return true;
	}

	return false;
}

#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
		    "providing the dmesg log by booting with drm.debug=0xf"

void
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...)
{
	static bool shown_bug_once;
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	struct device *kdev = dev_priv->drm.dev;
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	bool is_error = level[1] <= KERN_ERR[1];
	bool is_debug = level[1] == KERN_DEBUG[1];
	struct va_format vaf;
	va_list args;

	if (is_debug && !(drm_debug & DRM_UT_DRIVER))
		return;

	va_start(args, fmt);

	vaf.fmt = fmt;
	vaf.va = &args;

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	dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
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		   __builtin_return_address(0), &vaf);

	if (is_error && !shown_bug_once) {
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		dev_notice(kdev, "%s", FDO_BUG_MSG);
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		shown_bug_once = true;
	}

	va_end(args);
}

static bool i915_error_injected(struct drm_i915_private *dev_priv)
{
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	return i915_modparams.inject_load_failure &&
	       i915_load_fail_count == i915_modparams.inject_load_failure;
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}

#define i915_load_error(dev_priv, fmt, ...)				     \
	__i915_printk(dev_priv,						     \
		      i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
		      fmt, ##__VA_ARGS__)


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static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
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{
	enum intel_pch ret = PCH_NOP;

	/*
	 * In a virtualized passthrough environment we can be in a
	 * setup where the ISA bridge is not able to be passed through.
	 * In this case, a south bridge can be emulated and we have to
	 * make an educated guess as to which PCH is really there.
	 */

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	if (IS_GEN5(dev_priv)) {
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		ret = PCH_IBX;
		DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
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	} else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
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		ret = PCH_CPT;
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		DRM_DEBUG_KMS("Assuming CougarPoint PCH\n");
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	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
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		ret = PCH_LPT;
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		if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
			dev_priv->pch_id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
		else
			dev_priv->pch_id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
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		DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
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	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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		ret = PCH_SPT;
		DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
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	} else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
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		ret = PCH_CNP;
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		DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
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	}

	return ret;
}

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static void intel_detect_pch(struct drm_i915_private *dev_priv)
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{
	struct pci_dev *pch = NULL;

	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
	 * (which really amounts to a PCH but no South Display).
	 */
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	if (INTEL_INFO(dev_priv)->num_pipes == 0) {
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		dev_priv->pch_type = PCH_NOP;
		return;
	}

	/*
	 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
	 * make graphics device passthrough work easy for VMM, that only
	 * need to expose ISA bridge to let driver know the real hardware
	 * underneath. This is a requirement from virtualization team.
	 *
	 * In some virtualized environments (e.g. XEN), there is irrelevant
	 * ISA bridge in the system. To work reliably, we should scan trhough
	 * all the ISA bridge devices and check for the first match, instead
	 * of only checking the first one.
	 */
	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
		if (pch->vendor == PCI_VENDOR_ID_INTEL) {
			unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
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			dev_priv->pch_id = id;
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			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_IBX;
				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
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				WARN_ON(!IS_GEN5(dev_priv));
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			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_CPT;
				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
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				WARN_ON(!IS_GEN6(dev_priv) &&
					!IS_IVYBRIDGE(dev_priv));
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			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
				/* PantherPoint is CPT compatible */
				dev_priv->pch_type = PCH_CPT;
				DRM_DEBUG_KMS("Found PantherPoint PCH\n");
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				WARN_ON(!IS_GEN6(dev_priv) &&
					!IS_IVYBRIDGE(dev_priv));
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			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_LPT;
				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
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				WARN_ON(!IS_HASWELL(dev_priv) &&
					!IS_BROADWELL(dev_priv));
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				WARN_ON(IS_HSW_ULT(dev_priv) ||
					IS_BDW_ULT(dev_priv));
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			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_LPT;
				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
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				WARN_ON(!IS_HASWELL(dev_priv) &&
					!IS_BROADWELL(dev_priv));
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				WARN_ON(!IS_HSW_ULT(dev_priv) &&
					!IS_BDW_ULT(dev_priv));
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			} else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) {
				/* WildcatPoint is LPT compatible */
				dev_priv->pch_type = PCH_LPT;
				DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
				WARN_ON(!IS_HASWELL(dev_priv) &&
					!IS_BROADWELL(dev_priv));
				WARN_ON(IS_HSW_ULT(dev_priv) ||
					IS_BDW_ULT(dev_priv));
			} else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) {
				/* WildcatPoint is LPT compatible */
				dev_priv->pch_type = PCH_LPT;
				DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
				WARN_ON(!IS_HASWELL(dev_priv) &&
					!IS_BROADWELL(dev_priv));
				WARN_ON(!IS_HSW_ULT(dev_priv) &&
					!IS_BDW_ULT(dev_priv));
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			} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_SPT;
				DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
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				WARN_ON(!IS_SKYLAKE(dev_priv) &&
					!IS_KABYLAKE(dev_priv));
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			} else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
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				dev_priv->pch_type = PCH_SPT;
				DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
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				WARN_ON(!IS_SKYLAKE(dev_priv) &&
					!IS_KABYLAKE(dev_priv));
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			} else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_KBP;
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				DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
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				WARN_ON(!IS_SKYLAKE(dev_priv) &&
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					!IS_KABYLAKE(dev_priv) &&
					!IS_COFFEELAKE(dev_priv));
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			} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_CNP;
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				DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
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				WARN_ON(!IS_CANNONLAKE(dev_priv) &&
					!IS_COFFEELAKE(dev_priv));
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			} else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
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				dev_priv->pch_type = PCH_CNP;
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				DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
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				WARN_ON(!IS_CANNONLAKE(dev_priv) &&
					!IS_COFFEELAKE(dev_priv));
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			} else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
				   id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
				   (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
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				    pch->subsystem_vendor ==
					    PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
				    pch->subsystem_device ==
					    PCI_SUBDEVICE_ID_QEMU)) {
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				dev_priv->pch_type =
					intel_virt_detect_pch(dev_priv);
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			} else
				continue;

			break;
		}
	}
	if (!pch)
		DRM_DEBUG_KMS("No PCH found.\n");

	pci_dev_put(pch);
}

static int i915_getparam(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
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	struct drm_i915_private *dev_priv = to_i915(dev);
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	struct pci_dev *pdev = dev_priv->drm.pdev;
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	drm_i915_getparam_t *param = data;
	int value;

	switch (param->param) {
	case I915_PARAM_IRQ_ACTIVE:
	case I915_PARAM_ALLOW_BATCHBUFFER:
	case I915_PARAM_LAST_DISPATCH:
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	case I915_PARAM_HAS_EXEC_CONSTANTS:
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		/* Reject all old ums/dri params. */
		return -ENODEV;
	case I915_PARAM_CHIPSET_ID:
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		value = pdev->device;
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		break;
	case I915_PARAM_REVISION:
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		value = pdev->revision;
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		break;
	case I915_PARAM_NUM_FENCES_AVAIL:
		value = dev_priv->num_fence_regs;
		break;
	case I915_PARAM_HAS_OVERLAY:
		value = dev_priv->overlay ? 1 : 0;
		break;
	case I915_PARAM_HAS_BSD:
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		value = !!dev_priv->engine[VCS];
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		break;
	case I915_PARAM_HAS_BLT:
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		value = !!dev_priv->engine[BCS];
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		break;
	case I915_PARAM_HAS_VEBOX:
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		value = !!dev_priv->engine[VECS];
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		break;
	case I915_PARAM_HAS_BSD2:
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		value = !!dev_priv->engine[VCS2];
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		break;
	case I915_PARAM_HAS_LLC:
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		value = HAS_LLC(dev_priv);
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		break;
	case I915_PARAM_HAS_WT:
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		value = HAS_WT(dev_priv);
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		break;
	case I915_PARAM_HAS_ALIASING_PPGTT:
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		value = USES_PPGTT(dev_priv);
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		break;
	case I915_PARAM_HAS_SEMAPHORES:
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		value = HAS_LEGACY_SEMAPHORES(dev_priv);
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		break;
	case I915_PARAM_HAS_SECURE_BATCHES:
		value = capable(CAP_SYS_ADMIN);
		break;
	case I915_PARAM_CMD_PARSER_VERSION:
		value = i915_cmd_parser_get_version(dev_priv);
		break;
	case I915_PARAM_SUBSLICE_TOTAL:
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		value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
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		if (!value)
			return -ENODEV;
		break;
	case I915_PARAM_EU_TOTAL:
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		value = INTEL_INFO(dev_priv)->sseu.eu_total;
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		if (!value)
			return -ENODEV;
		break;
	case I915_PARAM_HAS_GPU_RESET:
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		value = i915_modparams.enable_hangcheck &&
			intel_has_gpu_reset(dev_priv);
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		if (value && intel_has_reset_engine(dev_priv))
			value = 2;
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		break;
	case I915_PARAM_HAS_RESOURCE_STREAMER:
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		value = HAS_RESOURCE_STREAMER(dev_priv);
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		break;
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	case I915_PARAM_HAS_POOLED_EU:
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		value = HAS_POOLED_EU(dev_priv);
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		break;
	case I915_PARAM_MIN_EU_IN_POOL:
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		value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
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		break;
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	case I915_PARAM_HUC_STATUS:
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		intel_runtime_pm_get(dev_priv);
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		value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
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		intel_runtime_pm_put(dev_priv);
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		break;
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	case I915_PARAM_MMAP_GTT_VERSION:
		/* Though we've started our numbering from 1, and so class all
		 * earlier versions as 0, in effect their value is undefined as
		 * the ioctl will report EINVAL for the unknown param!
		 */
		value = i915_gem_mmap_gtt_version();
		break;
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	case I915_PARAM_HAS_SCHEDULER:
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		value = 0;
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		if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule) {
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			value |= I915_SCHEDULER_CAP_ENABLED;
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			value |= I915_SCHEDULER_CAP_PRIORITY;
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			if (HAS_LOGICAL_RING_PREEMPTION(dev_priv))
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				value |= I915_SCHEDULER_CAP_PREEMPTION;
		}
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		break;
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	case I915_PARAM_MMAP_VERSION:
		/* Remember to bump this if the version changes! */
	case I915_PARAM_HAS_GEM:
	case I915_PARAM_HAS_PAGEFLIPPING:
	case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
	case I915_PARAM_HAS_RELAXED_FENCING:
	case I915_PARAM_HAS_COHERENT_RINGS:
	case I915_PARAM_HAS_RELAXED_DELTA:
	case I915_PARAM_HAS_GEN7_SOL_RESET:
	case I915_PARAM_HAS_WAIT_TIMEOUT:
	case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
	case I915_PARAM_HAS_PINNED_BATCHES:
	case I915_PARAM_HAS_EXEC_NO_RELOC:
	case I915_PARAM_HAS_EXEC_HANDLE_LUT:
	case I915_PARAM_HAS_COHERENT_PHYS_GTT:
	case I915_PARAM_HAS_EXEC_SOFTPIN:
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	case I915_PARAM_HAS_EXEC_ASYNC:
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	case I915_PARAM_HAS_EXEC_FENCE:
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	case I915_PARAM_HAS_EXEC_CAPTURE:
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	case I915_PARAM_HAS_EXEC_BATCH_FIRST:
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	case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
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		/* For the time being all of these are always true;
		 * if some supported hardware does not have one of these
		 * features this value needs to be provided from
		 * INTEL_INFO(), a feature macro, or similar.
		 */
		value = 1;
		break;
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	case I915_PARAM_HAS_CONTEXT_ISOLATION:
		value = intel_engines_has_context_isolation(dev_priv);
		break;
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	case I915_PARAM_SLICE_MASK:
		value = INTEL_INFO(dev_priv)->sseu.slice_mask;
		if (!value)
			return -ENODEV;
		break;
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	case I915_PARAM_SUBSLICE_MASK:
		value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
		if (!value)
			return -ENODEV;
		break;
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	case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
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		value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
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		break;
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	default:
		DRM_DEBUG("Unknown parameter %d\n", param->param);
		return -EINVAL;
	}

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	if (put_user(value, param->value))
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		return -EFAULT;

	return 0;
}

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static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
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{
	dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
	if (!dev_priv->bridge_dev) {
		DRM_ERROR("bridge device not found\n");
		return -1;
	}
	return 0;
}

/* Allocate space for the MCH regs if needed, return nonzero on error */
static int
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intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
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{
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	int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
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	u32 temp_lo, temp_hi = 0;
	u64 mchbar_addr;
	int ret;

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	if (INTEL_GEN(dev_priv) >= 4)
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		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
	pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;

	/* If ACPI doesn't have it, assume we need to allocate it ourselves */
#ifdef CONFIG_PNP
	if (mchbar_addr &&
	    pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
		return 0;
#endif

	/* Get some space for it */
	dev_priv->mch_res.name = "i915 MCHBAR";
	dev_priv->mch_res.flags = IORESOURCE_MEM;
	ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
				     &dev_priv->mch_res,
				     MCHBAR_SIZE, MCHBAR_SIZE,
				     PCIBIOS_MIN_MEM,
				     0, pcibios_align_resource,
				     dev_priv->bridge_dev);
	if (ret) {
		DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
		dev_priv->mch_res.start = 0;
		return ret;
	}

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	if (INTEL_GEN(dev_priv) >= 4)
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		pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
				       upper_32_bits(dev_priv->mch_res.start));

	pci_write_config_dword(dev_priv->bridge_dev, reg,
			       lower_32_bits(dev_priv->mch_res.start));
	return 0;
}

/* Setup MCHBAR if possible, return true if we should disable it again */
static void
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intel_setup_mchbar(struct drm_i915_private *dev_priv)
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{
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	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
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	u32 temp;
	bool enabled;

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	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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		return;

	dev_priv->mchbar_need_disable = false;

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	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
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		pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
		enabled = !!(temp & DEVEN_MCHBAR_EN);
	} else {
		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
		enabled = temp & 1;
	}

	/* If it's already enabled, don't have to do anything */
	if (enabled)
		return;

515
	if (intel_alloc_mchbar_resource(dev_priv))
516 517 518 519 520
		return;

	dev_priv->mchbar_need_disable = true;

	/* Space is allocated or reserved, so enable it. */
521
	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
522 523 524 525 526 527 528 529 530
		pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
				       temp | DEVEN_MCHBAR_EN);
	} else {
		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
		pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
	}
}

static void
531
intel_teardown_mchbar(struct drm_i915_private *dev_priv)
532
{
533
	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
534 535

	if (dev_priv->mchbar_need_disable) {
536
		if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561
			u32 deven_val;

			pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
					      &deven_val);
			deven_val &= ~DEVEN_MCHBAR_EN;
			pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
					       deven_val);
		} else {
			u32 mchbar_val;

			pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
					      &mchbar_val);
			mchbar_val &= ~1;
			pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
					       mchbar_val);
		}
	}

	if (dev_priv->mch_res.start)
		release_resource(&dev_priv->mch_res);
}

/* true = enable decode, false = disable decoder */
static unsigned int i915_vga_set_decode(void *cookie, bool state)
{
562
	struct drm_i915_private *dev_priv = cookie;
563

564
	intel_modeset_vga_set_state(dev_priv, state);
565 566 567 568 569 570 571
	if (state)
		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
	else
		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
}

572 573 574
static int i915_resume_switcheroo(struct drm_device *dev);
static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);

575 576 577 578 579 580 581 582 583
static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	pm_message_t pmm = { .event = PM_EVENT_SUSPEND };

	if (state == VGA_SWITCHEROO_ON) {
		pr_info("switched on\n");
		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
		/* i915 resume handler doesn't set to D0 */
D
David Weinehall 已提交
584
		pci_set_power_state(pdev, PCI_D0);
585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612
		i915_resume_switcheroo(dev);
		dev->switch_power_state = DRM_SWITCH_POWER_ON;
	} else {
		pr_info("switched off\n");
		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
		i915_suspend_switcheroo(dev, pmm);
		dev->switch_power_state = DRM_SWITCH_POWER_OFF;
	}
}

static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	/*
	 * FIXME: open_count is protected by drm_global_mutex but that would lead to
	 * locking inversion with the driver load path. And the access here is
	 * completely racy anyway. So don't bother with locking for now.
	 */
	return dev->open_count == 0;
}

static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
	.set_gpu_state = i915_switcheroo_set_state,
	.reprobe = NULL,
	.can_switch = i915_switcheroo_can_switch,
};

613
static void i915_gem_fini(struct drm_i915_private *dev_priv)
614
{
615 616
	/* Flush any outstanding unpin_work. */
	i915_gem_drain_workqueue(dev_priv);
617

618
	mutex_lock(&dev_priv->drm.struct_mutex);
619
	intel_uc_fini_hw(dev_priv);
620
	intel_uc_fini(dev_priv);
621
	i915_gem_cleanup_engines(dev_priv);
622
	i915_gem_contexts_fini(dev_priv);
623
	mutex_unlock(&dev_priv->drm.struct_mutex);
624

625
	intel_uc_fini_wq(dev_priv);
626 627
	i915_gem_cleanup_userptr(dev_priv);

628
	i915_gem_drain_freed_objects(dev_priv);
629

630
	WARN_ON(!list_empty(&dev_priv->contexts.list));
631 632 633 634
}

static int i915_load_modeset_init(struct drm_device *dev)
{
635
	struct drm_i915_private *dev_priv = to_i915(dev);
D
David Weinehall 已提交
636
	struct pci_dev *pdev = dev_priv->drm.pdev;
637 638 639 640 641
	int ret;

	if (i915_inject_load_failure())
		return -ENODEV;

642
	intel_bios_init(dev_priv);
643 644 645 646 647 648 649 650

	/* If we have > 1 VGA cards, then we need to arbitrate access
	 * to the common VGA resources.
	 *
	 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
	 * then we do not take part in VGA arbitration and the
	 * vga_client_register() fails with -ENODEV.
	 */
651
	ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
652 653 654 655 656
	if (ret && ret != -ENODEV)
		goto out;

	intel_register_dsm_handler();

D
David Weinehall 已提交
657
	ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
658 659 660 661 662 663 664 665 666 667 668 669 670 671
	if (ret)
		goto cleanup_vga_client;

	/* must happen before intel_power_domains_init_hw() on VLV/CHV */
	intel_update_rawclk(dev_priv);

	intel_power_domains_init_hw(dev_priv, false);

	intel_csr_ucode_init(dev_priv);

	ret = intel_irq_install(dev_priv);
	if (ret)
		goto cleanup_csr;

672
	intel_setup_gmbus(dev_priv);
673 674 675

	/* Important: The output setup functions called by modeset_init need
	 * working irqs for e.g. gmbus and dp aux transfers. */
676 677 678
	ret = intel_modeset_init(dev);
	if (ret)
		goto cleanup_irq;
679

680
	intel_uc_init_fw(dev_priv);
681

682
	ret = i915_gem_init(dev_priv);
683
	if (ret)
684
		goto cleanup_uc;
685

686
	intel_setup_overlay(dev_priv);
687

688
	if (INTEL_INFO(dev_priv)->num_pipes == 0)
689 690 691 692 693 694 695 696 697 698 699 700
		return 0;

	ret = intel_fbdev_init(dev);
	if (ret)
		goto cleanup_gem;

	/* Only enable hotplug handling once the fbdev is fully set up. */
	intel_hpd_init(dev_priv);

	return 0;

cleanup_gem:
701
	if (i915_gem_suspend(dev_priv))
702
		DRM_ERROR("failed to idle hardware; continuing to unload!\n");
703
	i915_gem_fini(dev_priv);
704 705
cleanup_uc:
	intel_uc_fini_fw(dev_priv);
706 707
cleanup_irq:
	drm_irq_uninstall(dev);
708
	intel_teardown_gmbus(dev_priv);
709 710 711
cleanup_csr:
	intel_csr_ucode_fini(dev_priv);
	intel_power_domains_fini(dev_priv);
D
David Weinehall 已提交
712
	vga_switcheroo_unregister_client(pdev);
713
cleanup_vga_client:
D
David Weinehall 已提交
714
	vga_client_register(pdev, NULL, NULL, NULL);
715 716 717 718 719 720 721
out:
	return ret;
}

static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
{
	struct apertures_struct *ap;
722
	struct pci_dev *pdev = dev_priv->drm.pdev;
723 724 725 726 727 728 729 730
	struct i915_ggtt *ggtt = &dev_priv->ggtt;
	bool primary;
	int ret;

	ap = alloc_apertures(1);
	if (!ap)
		return -ENOMEM;

731
	ap->ranges[0].base = ggtt->gmadr.start;
732 733 734 735 736
	ap->ranges[0].size = ggtt->mappable_end;

	primary =
		pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;

737
	ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825

	kfree(ap);

	return ret;
}

#if !defined(CONFIG_VGA_CONSOLE)
static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
{
	return 0;
}
#elif !defined(CONFIG_DUMMY_CONSOLE)
static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
{
	return -ENODEV;
}
#else
static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
{
	int ret = 0;

	DRM_INFO("Replacing VGA console driver\n");

	console_lock();
	if (con_is_bound(&vga_con))
		ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
	if (ret == 0) {
		ret = do_unregister_con_driver(&vga_con);

		/* Ignore "already unregistered". */
		if (ret == -ENODEV)
			ret = 0;
	}
	console_unlock();

	return ret;
}
#endif

static void intel_init_dpio(struct drm_i915_private *dev_priv)
{
	/*
	 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
	 * CHV x1 PHY (DP/HDMI D)
	 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
	 */
	if (IS_CHERRYVIEW(dev_priv)) {
		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
		DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
	} else if (IS_VALLEYVIEW(dev_priv)) {
		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
	}
}

static int i915_workqueues_init(struct drm_i915_private *dev_priv)
{
	/*
	 * The i915 workqueue is primarily used for batched retirement of
	 * requests (and thus managing bo) once the task has been completed
	 * by the GPU. i915_gem_retire_requests() is called directly when we
	 * need high-priority retirement, such as waiting for an explicit
	 * bo.
	 *
	 * It is also used for periodic low-priority events, such as
	 * idle-timers and recording error state.
	 *
	 * All tasks on the workqueue are expected to acquire the dev mutex
	 * so there is no point in running more than one instance of the
	 * workqueue at any time.  Use an ordered one.
	 */
	dev_priv->wq = alloc_ordered_workqueue("i915", 0);
	if (dev_priv->wq == NULL)
		goto out_err;

	dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
	if (dev_priv->hotplug.dp_wq == NULL)
		goto out_free_wq;

	return 0;

out_free_wq:
	destroy_workqueue(dev_priv->wq);
out_err:
	DRM_ERROR("Failed to allocate workqueues.\n");

	return -ENOMEM;
}

826 827 828 829 830 831 832 833 834
static void i915_engines_cleanup(struct drm_i915_private *i915)
{
	struct intel_engine_cs *engine;
	enum intel_engine_id id;

	for_each_engine(engine, i915, id)
		kfree(engine);
}

835 836 837 838 839 840
static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
{
	destroy_workqueue(dev_priv->hotplug.dp_wq);
	destroy_workqueue(dev_priv->wq);
}

841 842 843 844
/*
 * We don't keep the workarounds for pre-production hardware, so we expect our
 * driver to fail on these machines in one way or another. A little warning on
 * dmesg may help both the user and the bug triagers.
845 846 847 848 849
 *
 * Our policy for removing pre-production workarounds is to keep the
 * current gen workarounds as a guide to the bring-up of the next gen
 * (workarounds have a habit of persisting!). Anything older than that
 * should be removed along with the complications they introduce.
850 851 852
 */
static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
{
853 854 855 856
	bool pre = false;

	pre |= IS_HSW_EARLY_SDV(dev_priv);
	pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
857
	pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
858

859
	if (pre) {
860 861
		DRM_ERROR("This is a pre-production stepping. "
			  "It may not be fully functional.\n");
862 863
		add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
	}
864 865
}

866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887
/**
 * i915_driver_init_early - setup state not requiring device access
 * @dev_priv: device private
 *
 * Initialize everything that is a "SW-only" state, that is state not
 * requiring accessing the device or exposing the driver via kernel internal
 * or userspace interfaces. Example steps belonging here: lock initialization,
 * system memory allocation, setting up device specific attributes and
 * function hooks not requiring accessing the device.
 */
static int i915_driver_init_early(struct drm_i915_private *dev_priv,
				  const struct pci_device_id *ent)
{
	const struct intel_device_info *match_info =
		(struct intel_device_info *)ent->driver_data;
	struct intel_device_info *device_info;
	int ret = 0;

	if (i915_inject_load_failure())
		return -ENODEV;

	/* Setup the write-once "constant" device info */
888
	device_info = mkwrite_device_info(dev_priv);
889 890 891
	memcpy(device_info, match_info, sizeof(*device_info));
	device_info->device_id = dev_priv->drm.pdev->device;

892 893 894 895
	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
		     sizeof(device_info->platform_mask) * BITS_PER_BYTE);
	device_info->platform_mask = BIT(device_info->platform);

896 897 898 899 900 901 902
	BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
	device_info->gen_mask = BIT(device_info->gen - 1);

	spin_lock_init(&dev_priv->irq_lock);
	spin_lock_init(&dev_priv->gpu_error.lock);
	mutex_init(&dev_priv->backlight_lock);
	spin_lock_init(&dev_priv->uncore.lock);
L
Lyude 已提交
903

904 905 906 907 908 909
	mutex_init(&dev_priv->sb_lock);
	mutex_init(&dev_priv->modeset_restore_lock);
	mutex_init(&dev_priv->av_mutex);
	mutex_init(&dev_priv->wm.wm_mutex);
	mutex_init(&dev_priv->pps_mutex);

910
	intel_uc_init_early(dev_priv);
911 912
	i915_memcpy_init_early(dev_priv);

913 914
	ret = i915_workqueues_init(dev_priv);
	if (ret < 0)
915
		goto err_engines;
916 917

	/* This must be called before any calls to HAS_PCH_* */
918
	intel_detect_pch(dev_priv);
919

920
	intel_pm_setup(dev_priv);
921 922 923
	intel_init_dpio(dev_priv);
	intel_power_domains_init(dev_priv);
	intel_irq_init(dev_priv);
924
	intel_hangcheck_init(dev_priv);
925 926 927
	intel_init_display_hooks(dev_priv);
	intel_init_clock_gating_hooks(dev_priv);
	intel_init_audio_hooks(dev_priv);
928
	ret = i915_gem_load_init(dev_priv);
929
	if (ret < 0)
930
		goto err_irq;
931

932
	intel_display_crc_init(dev_priv);
933

934
	intel_device_info_dump(dev_priv);
935

936
	intel_detect_preproduction_hw(dev_priv);
937 938 939

	return 0;

940 941
err_irq:
	intel_irq_fini(dev_priv);
942
	i915_workqueues_cleanup(dev_priv);
943 944
err_engines:
	i915_engines_cleanup(dev_priv);
945 946 947 948 949 950 951 952 953
	return ret;
}

/**
 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 * @dev_priv: device private
 */
static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
{
954
	i915_gem_load_cleanup(dev_priv);
955
	intel_irq_fini(dev_priv);
956
	i915_workqueues_cleanup(dev_priv);
957
	i915_engines_cleanup(dev_priv);
958 959
}

960
static int i915_mmio_setup(struct drm_i915_private *dev_priv)
961
{
D
David Weinehall 已提交
962
	struct pci_dev *pdev = dev_priv->drm.pdev;
963 964 965
	int mmio_bar;
	int mmio_size;

966
	mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
967 968 969 970 971 972 973 974
	/*
	 * Before gen4, the registers and the GTT are behind different BARs.
	 * However, from gen4 onwards, the registers and the GTT are shared
	 * in the same BAR, so we want to restrict this ioremap from
	 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
	 * the register BAR remains the same size for all the earlier
	 * generations up to Ironlake.
	 */
975
	if (INTEL_GEN(dev_priv) < 5)
976 977 978
		mmio_size = 512 * 1024;
	else
		mmio_size = 2 * 1024 * 1024;
D
David Weinehall 已提交
979
	dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
980 981 982 983 984 985 986
	if (dev_priv->regs == NULL) {
		DRM_ERROR("failed to map registers\n");

		return -EIO;
	}

	/* Try to make sure MCHBAR is enabled before poking at it */
987
	intel_setup_mchbar(dev_priv);
988 989 990 991

	return 0;
}

992
static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
993
{
D
David Weinehall 已提交
994
	struct pci_dev *pdev = dev_priv->drm.pdev;
995

996
	intel_teardown_mchbar(dev_priv);
D
David Weinehall 已提交
997
	pci_iounmap(pdev, dev_priv->regs);
998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015
}

/**
 * i915_driver_init_mmio - setup device MMIO
 * @dev_priv: device private
 *
 * Setup minimal device state necessary for MMIO accesses later in the
 * initialization sequence. The setup here should avoid any other device-wide
 * side effects or exposing the driver via kernel internal or user space
 * interfaces.
 */
static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
{
	int ret;

	if (i915_inject_load_failure())
		return -ENODEV;

1016
	if (i915_get_bridge_dev(dev_priv))
1017 1018
		return -EIO;

1019
	ret = i915_mmio_setup(dev_priv);
1020
	if (ret < 0)
1021
		goto err_bridge;
1022 1023

	intel_uncore_init(dev_priv);
1024

1025 1026
	intel_uc_init_mmio(dev_priv);

1027 1028 1029 1030
	ret = intel_engines_init_mmio(dev_priv);
	if (ret)
		goto err_uncore;

1031
	i915_gem_init_mmio(dev_priv);
1032 1033 1034

	return 0;

1035 1036 1037
err_uncore:
	intel_uncore_fini(dev_priv);
err_bridge:
1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049
	pci_dev_put(dev_priv->bridge_dev);

	return ret;
}

/**
 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 * @dev_priv: device private
 */
static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
{
	intel_uncore_fini(dev_priv);
1050
	i915_mmio_cleanup(dev_priv);
1051 1052 1053
	pci_dev_put(dev_priv->bridge_dev);
}

1054 1055 1056 1057 1058 1059 1060 1061
static void intel_sanitize_options(struct drm_i915_private *dev_priv)
{
	/*
	 * i915.enable_ppgtt is read-only, so do an early pass to validate the
	 * user's requested state against the hardware/driver capabilities.  We
	 * do this now so that we can print out any log messages once rather
	 * than every time we check intel_enable_ppgtt().
	 */
1062 1063 1064 1065
	i915_modparams.enable_ppgtt =
		intel_sanitize_enable_ppgtt(dev_priv,
					    i915_modparams.enable_ppgtt);
	DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1066

1067
	intel_uc_sanitize_options(dev_priv);
1068 1069

	intel_gvt_sanitize_options(dev_priv);
1070 1071
}

1072 1073 1074 1075 1076 1077 1078 1079 1080
/**
 * i915_driver_init_hw - setup state requiring device access
 * @dev_priv: device private
 *
 * Setup state that requires accessing the device, but doesn't require
 * exposing the driver via kernel internal or userspace interfaces.
 */
static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
{
D
David Weinehall 已提交
1081
	struct pci_dev *pdev = dev_priv->drm.pdev;
1082 1083 1084 1085 1086
	int ret;

	if (i915_inject_load_failure())
		return -ENODEV;

1087 1088 1089
	intel_device_info_runtime_init(dev_priv);

	intel_sanitize_options(dev_priv);
1090

1091 1092
	i915_perf_init(dev_priv);

1093
	ret = i915_ggtt_probe_hw(dev_priv);
1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110
	if (ret)
		return ret;

	/* WARNING: Apparently we must kick fbdev drivers before vgacon,
	 * otherwise the vga fbdev driver falls over. */
	ret = i915_kick_out_firmware_fb(dev_priv);
	if (ret) {
		DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
		goto out_ggtt;
	}

	ret = i915_kick_out_vgacon(dev_priv);
	if (ret) {
		DRM_ERROR("failed to remove conflicting VGA console\n");
		goto out_ggtt;
	}

1111
	ret = i915_ggtt_init_hw(dev_priv);
1112 1113 1114
	if (ret)
		return ret;

1115
	ret = i915_ggtt_enable_hw(dev_priv);
1116 1117 1118 1119 1120
	if (ret) {
		DRM_ERROR("failed to enable GGTT\n");
		goto out_ggtt;
	}

D
David Weinehall 已提交
1121
	pci_set_master(pdev);
1122 1123

	/* overlay on gen2 is broken and can't address above 1G */
1124
	if (IS_GEN2(dev_priv)) {
D
David Weinehall 已提交
1125
		ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140
		if (ret) {
			DRM_ERROR("failed to set DMA mask\n");

			goto out_ggtt;
		}
	}

	/* 965GM sometimes incorrectly writes to hardware status page (HWS)
	 * using 32bit addressing, overwriting memory if HWS is located
	 * above 4GB.
	 *
	 * The documentation also mentions an issue with undefined
	 * behaviour if any general state is accessed within a page above 4GB,
	 * which also needs to be handled carefully.
	 */
1141
	if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
D
David Weinehall 已提交
1142
		ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167

		if (ret) {
			DRM_ERROR("failed to set DMA mask\n");

			goto out_ggtt;
		}
	}

	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
			   PM_QOS_DEFAULT_VALUE);

	intel_uncore_sanitize(dev_priv);

	intel_opregion_setup(dev_priv);

	i915_gem_load_init_fences(dev_priv);

	/* On the 945G/GM, the chipset reports the MSI capability on the
	 * integrated graphics even though the support isn't actually there
	 * according to the published specs.  It doesn't appear to function
	 * correctly in testing on 945G.
	 * This may be a side effect of MSI having been made available for PEG
	 * and the registers being closely associated.
	 *
	 * According to chipset errata, on the 965GM, MSI interrupts may
1168 1169 1170 1171
	 * be lost or delayed, and was defeatured. MSI interrupts seem to
	 * get lost on g4x as well, and interrupt delivery seems to stay
	 * properly dead afterwards. So we'll just disable them for all
	 * pre-gen5 chipsets.
1172
	 */
1173
	if (INTEL_GEN(dev_priv) >= 5) {
D
David Weinehall 已提交
1174
		if (pci_enable_msi(pdev) < 0)
1175 1176 1177
			DRM_DEBUG_DRIVER("can't enable MSI");
	}

1178 1179 1180 1181
	ret = intel_gvt_init(dev_priv);
	if (ret)
		goto out_ggtt;

1182 1183 1184
	return 0;

out_ggtt:
1185
	i915_ggtt_cleanup_hw(dev_priv);
1186 1187 1188 1189 1190 1191 1192 1193 1194 1195

	return ret;
}

/**
 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
 * @dev_priv: device private
 */
static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
{
D
David Weinehall 已提交
1196
	struct pci_dev *pdev = dev_priv->drm.pdev;
1197

1198 1199
	i915_perf_fini(dev_priv);

D
David Weinehall 已提交
1200 1201
	if (pdev->msi_enabled)
		pci_disable_msi(pdev);
1202 1203

	pm_qos_remove_request(&dev_priv->pm_qos);
1204
	i915_ggtt_cleanup_hw(dev_priv);
1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215
}

/**
 * i915_driver_register - register the driver with the rest of the system
 * @dev_priv: device private
 *
 * Perform any steps necessary to make the driver available via kernel
 * internal or userspace interfaces.
 */
static void i915_driver_register(struct drm_i915_private *dev_priv)
{
1216
	struct drm_device *dev = &dev_priv->drm;
1217

1218
	i915_gem_shrinker_register(dev_priv);
1219
	i915_pmu_register(dev_priv);
1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230

	/*
	 * Notify a valid surface after modesetting,
	 * when running inside a VM.
	 */
	if (intel_vgpu_active(dev_priv))
		I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);

	/* Reveal our presence to userspace */
	if (drm_dev_register(dev, 0) == 0) {
		i915_debugfs_register(dev_priv);
1231
		i915_guc_log_register(dev_priv);
D
David Weinehall 已提交
1232
		i915_setup_sysfs(dev_priv);
1233 1234 1235

		/* Depends on sysfs having been initialized */
		i915_perf_register(dev_priv);
1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247
	} else
		DRM_ERROR("Failed to register driver for userspace access!\n");

	if (INTEL_INFO(dev_priv)->num_pipes) {
		/* Must be done after probing outputs */
		intel_opregion_register(dev_priv);
		acpi_video_register();
	}

	if (IS_GEN5(dev_priv))
		intel_gpu_ips_init(dev_priv);

1248
	intel_audio_init(dev_priv);
1249 1250 1251 1252 1253 1254 1255 1256 1257

	/*
	 * Some ports require correctly set-up hpd registers for detection to
	 * work properly (leading to ghost connected connector status), e.g. VGA
	 * on gm45.  Hence we can only set up the initial fbdev config after hpd
	 * irqs are fully enabled. We do it last so that the async config
	 * cannot run before the connectors are registered.
	 */
	intel_fbdev_initial_config_async(dev);
1258 1259 1260 1261 1262 1263 1264

	/*
	 * We need to coordinate the hotplugs with the asynchronous fbdev
	 * configuration, for which we use the fbdev->async_cookie.
	 */
	if (INTEL_INFO(dev_priv)->num_pipes)
		drm_kms_helper_poll_init(dev);
1265 1266 1267 1268 1269 1270 1271 1272
}

/**
 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 * @dev_priv: device private
 */
static void i915_driver_unregister(struct drm_i915_private *dev_priv)
{
1273
	intel_fbdev_unregister(dev_priv);
1274
	intel_audio_deinit(dev_priv);
1275

1276 1277 1278 1279 1280 1281 1282
	/*
	 * After flushing the fbdev (incl. a late async config which will
	 * have delayed queuing of a hotplug event), then flush the hotplug
	 * events.
	 */
	drm_kms_helper_poll_fini(&dev_priv->drm);

1283 1284 1285 1286
	intel_gpu_ips_teardown();
	acpi_video_unregister();
	intel_opregion_unregister(dev_priv);

1287
	i915_perf_unregister(dev_priv);
1288
	i915_pmu_unregister(dev_priv);
1289

D
David Weinehall 已提交
1290
	i915_teardown_sysfs(dev_priv);
1291
	i915_guc_log_unregister(dev_priv);
1292
	drm_dev_unregister(&dev_priv->drm);
1293

1294
	i915_gem_shrinker_unregister(dev_priv);
1295 1296 1297 1298
}

/**
 * i915_driver_load - setup chip and create an initial config
1299 1300
 * @pdev: PCI device
 * @ent: matching PCI ID entry
1301 1302 1303 1304 1305 1306 1307
 *
 * The driver load routine has to do several things:
 *   - drive output discovery via intel_modeset_init()
 *   - initialize the memory manager
 *   - allocate initial config memory
 *   - setup the DRM framebuffer with the allocated memory
 */
1308
int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1309
{
1310 1311
	const struct intel_device_info *match_info =
		(struct intel_device_info *)ent->driver_data;
1312 1313
	struct drm_i915_private *dev_priv;
	int ret;
1314

1315
	/* Enable nuclear pageflip on ILK+ */
1316
	if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1317
		driver.driver_features &= ~DRIVER_ATOMIC;
1318

1319 1320 1321 1322 1323
	ret = -ENOMEM;
	dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
	if (dev_priv)
		ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
	if (ret) {
1324
		DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1325
		goto out_free;
1326
	}
1327

1328 1329
	dev_priv->drm.pdev = pdev;
	dev_priv->drm.dev_private = dev_priv;
1330

1331 1332
	ret = pci_enable_device(pdev);
	if (ret)
1333
		goto out_fini;
D
Damien Lespiau 已提交
1334

1335
	pci_set_drvdata(pdev, &dev_priv->drm);
1336 1337 1338 1339 1340 1341 1342 1343
	/*
	 * Disable the system suspend direct complete optimization, which can
	 * leave the device suspended skipping the driver's suspend handlers
	 * if the device was already runtime suspended. This is needed due to
	 * the difference in our runtime and system suspend sequence and
	 * becaue the HDA driver may require us to enable the audio power
	 * domain during system suspend.
	 */
1344
	dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
1345

1346 1347 1348
	ret = i915_driver_init_early(dev_priv, ent);
	if (ret < 0)
		goto out_pci_disable;
1349

1350
	intel_runtime_pm_get(dev_priv);
L
Linus Torvalds 已提交
1351

1352 1353 1354
	ret = i915_driver_init_mmio(dev_priv);
	if (ret < 0)
		goto out_runtime_pm_put;
J
Jesse Barnes 已提交
1355

1356 1357 1358
	ret = i915_driver_init_hw(dev_priv);
	if (ret < 0)
		goto out_cleanup_mmio;
1359 1360

	/*
1361 1362 1363
	 * TODO: move the vblank init and parts of modeset init steps into one
	 * of the i915_driver_init_/i915_driver_register functions according
	 * to the role/effect of the given init step.
1364
	 */
1365
	if (INTEL_INFO(dev_priv)->num_pipes) {
1366
		ret = drm_vblank_init(&dev_priv->drm,
1367 1368 1369
				      INTEL_INFO(dev_priv)->num_pipes);
		if (ret)
			goto out_cleanup_hw;
1370 1371
	}

1372
	ret = i915_load_modeset_init(&dev_priv->drm);
1373
	if (ret < 0)
1374
		goto out_cleanup_hw;
1375 1376 1377 1378 1379

	i915_driver_register(dev_priv);

	intel_runtime_pm_enable(dev_priv);

1380
	intel_init_ipc(dev_priv);
M
Mahesh Kumar 已提交
1381

1382 1383 1384 1385
	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
		DRM_INFO("DRM_I915_DEBUG enabled\n");
	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
		DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1386

1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399
	intel_runtime_pm_put(dev_priv);

	return 0;

out_cleanup_hw:
	i915_driver_cleanup_hw(dev_priv);
out_cleanup_mmio:
	i915_driver_cleanup_mmio(dev_priv);
out_runtime_pm_put:
	intel_runtime_pm_put(dev_priv);
	i915_driver_cleanup_early(dev_priv);
out_pci_disable:
	pci_disable_device(pdev);
1400
out_fini:
1401
	i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1402 1403 1404
	drm_dev_fini(&dev_priv->drm);
out_free:
	kfree(dev_priv);
1405 1406 1407
	return ret;
}

1408
void i915_driver_unload(struct drm_device *dev)
1409
{
1410
	struct drm_i915_private *dev_priv = to_i915(dev);
D
David Weinehall 已提交
1411
	struct pci_dev *pdev = dev_priv->drm.pdev;
1412

1413 1414
	i915_driver_unregister(dev_priv);

1415
	if (i915_gem_suspend(dev_priv))
1416
		DRM_ERROR("failed to idle hardware; continuing to unload!\n");
B
Ben Widawsky 已提交
1417

1418 1419
	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);

1420
	drm_atomic_helper_shutdown(dev);
1421

1422 1423
	intel_gvt_cleanup(dev_priv);

1424 1425
	intel_modeset_cleanup(dev);

1426
	/*
1427 1428
	 * free the memory space allocated for the child device
	 * config parsed from VBT
1429
	 */
1430 1431 1432 1433 1434 1435 1436 1437 1438
	if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
		kfree(dev_priv->vbt.child_dev);
		dev_priv->vbt.child_dev = NULL;
		dev_priv->vbt.child_dev_num = 0;
	}
	kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
	dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
	kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
	dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1439

D
David Weinehall 已提交
1440 1441
	vga_switcheroo_unregister_client(pdev);
	vga_client_register(pdev, NULL, NULL, NULL);
1442

1443
	intel_csr_ucode_fini(dev_priv);
1444

1445 1446
	/* Free error state after interrupts are fully disabled. */
	cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1447
	i915_reset_error_state(dev_priv);
1448

1449
	i915_gem_fini(dev_priv);
1450
	intel_uc_fini_fw(dev_priv);
1451 1452 1453 1454 1455 1456 1457 1458
	intel_fbc_cleanup_cfb(dev_priv);

	intel_power_domains_fini(dev_priv);

	i915_driver_cleanup_hw(dev_priv);
	i915_driver_cleanup_mmio(dev_priv);

	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1459 1460 1461 1462 1463
}

static void i915_driver_release(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
1464 1465

	i915_driver_cleanup_early(dev_priv);
1466 1467 1468
	drm_dev_fini(&dev_priv->drm);

	kfree(dev_priv);
1469 1470
}

1471
static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1472
{
1473
	struct drm_i915_private *i915 = to_i915(dev);
1474
	int ret;
1475

1476
	ret = i915_gem_open(i915, file);
1477 1478
	if (ret)
		return ret;
1479

1480 1481
	return 0;
}
1482

1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499
/**
 * i915_driver_lastclose - clean up after all DRM clients have exited
 * @dev: DRM device
 *
 * Take care of cleaning up after all DRM clients have exited.  In the
 * mode setting case, we want to restore the kernel's initial mode (just
 * in case the last client left us in a bad state).
 *
 * Additionally, in the non-mode setting case, we'll tear down the GTT
 * and DMA structures, since the kernel won't be using them, and clea
 * up any GEM state.
 */
static void i915_driver_lastclose(struct drm_device *dev)
{
	intel_fbdev_restore_mode(dev);
	vga_switcheroo_process_delayed_switch();
}
1500

1501
static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1502
{
1503 1504
	struct drm_i915_file_private *file_priv = file->driver_priv;

1505
	mutex_lock(&dev->struct_mutex);
1506
	i915_gem_context_close(file);
1507 1508 1509 1510
	i915_gem_release(dev, file);
	mutex_unlock(&dev->struct_mutex);

	kfree(file_priv);
1511 1512
}

1513 1514
static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
{
1515
	struct drm_device *dev = &dev_priv->drm;
1516
	struct intel_encoder *encoder;
1517 1518

	drm_modeset_lock_all(dev);
1519 1520 1521
	for_each_intel_encoder(dev, encoder)
		if (encoder->suspend)
			encoder->suspend(encoder);
1522 1523 1524
	drm_modeset_unlock_all(dev);
}

1525 1526
static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
			      bool rpm_resume);
1527
static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1528

1529 1530 1531 1532 1533 1534 1535 1536
static bool suspend_to_idle(struct drm_i915_private *dev_priv)
{
#if IS_ENABLED(CONFIG_ACPI_SLEEP)
	if (acpi_target_system_state() < ACPI_STATE_S3)
		return true;
#endif
	return false;
}
1537

1538
static int i915_drm_suspend(struct drm_device *dev)
J
Jesse Barnes 已提交
1539
{
1540
	struct drm_i915_private *dev_priv = to_i915(dev);
D
David Weinehall 已提交
1541
	struct pci_dev *pdev = dev_priv->drm.pdev;
1542
	pci_power_t opregion_target_state;
1543
	int error;
1544

1545 1546 1547 1548 1549
	/* ignore lid events during suspend */
	mutex_lock(&dev_priv->modeset_restore_lock);
	dev_priv->modeset_restore = MODESET_SUSPENDED;
	mutex_unlock(&dev_priv->modeset_restore_lock);

1550 1551
	disable_rpm_wakeref_asserts(dev_priv);

1552 1553
	/* We do a lot of poking in a lot of registers, make sure they work
	 * properly. */
1554
	intel_display_set_init_power(dev_priv, true);
1555

1556 1557
	drm_kms_helper_poll_disable(dev);

D
David Weinehall 已提交
1558
	pci_save_state(pdev);
J
Jesse Barnes 已提交
1559

1560
	error = i915_gem_suspend(dev_priv);
1561
	if (error) {
D
David Weinehall 已提交
1562
		dev_err(&pdev->dev,
1563
			"GEM idle failed, resume might fail\n");
1564
		goto out;
1565
	}
1566

1567
	intel_display_suspend(dev);
1568

1569
	intel_dp_mst_suspend(dev);
1570

1571 1572
	intel_runtime_pm_disable_interrupts(dev_priv);
	intel_hpd_cancel_work(dev_priv);
1573

1574
	intel_suspend_encoders(dev_priv);
1575

1576
	intel_suspend_hw(dev_priv);
1577

1578
	i915_gem_suspend_gtt_mappings(dev_priv);
1579

1580
	i915_save_state(dev_priv);
1581

1582
	opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1583
	intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1584

1585
	intel_uncore_suspend(dev_priv);
1586
	intel_opregion_unregister(dev_priv);
1587

1588
	intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1589

1590 1591
	dev_priv->suspend_count++;

1592
	intel_csr_ucode_suspend(dev_priv);
1593

1594 1595 1596 1597
out:
	enable_rpm_wakeref_asserts(dev_priv);

	return error;
1598 1599
}

1600
static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1601
{
1602
	struct drm_i915_private *dev_priv = to_i915(dev);
D
David Weinehall 已提交
1603
	struct pci_dev *pdev = dev_priv->drm.pdev;
1604
	bool fw_csr;
1605 1606
	int ret;

1607 1608
	disable_rpm_wakeref_asserts(dev_priv);

1609 1610
	intel_display_set_init_power(dev_priv, false);

1611
	fw_csr = !IS_GEN9_LP(dev_priv) && !hibernation &&
1612
		suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1613 1614 1615 1616 1617 1618 1619 1620 1621
	/*
	 * In case of firmware assisted context save/restore don't manually
	 * deinit the power domains. This also means the CSR/DMC firmware will
	 * stay active, it will power down any HW resources as required and
	 * also enable deeper system power states that would be blocked if the
	 * firmware was inactive.
	 */
	if (!fw_csr)
		intel_power_domains_suspend(dev_priv);
1622

1623
	ret = 0;
1624
	if (IS_GEN9_LP(dev_priv))
1625
		bxt_enable_dc9(dev_priv);
1626
	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1627 1628 1629
		hsw_enable_pc8(dev_priv);
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
		ret = vlv_suspend_complete(dev_priv);
1630 1631 1632

	if (ret) {
		DRM_ERROR("Suspend complete failed: %d\n", ret);
1633 1634
		if (!fw_csr)
			intel_power_domains_init_hw(dev_priv, true);
1635

1636
		goto out;
1637 1638
	}

D
David Weinehall 已提交
1639
	pci_disable_device(pdev);
1640
	/*
1641
	 * During hibernation on some platforms the BIOS may try to access
1642 1643
	 * the device even though it's already in D3 and hang the machine. So
	 * leave the device in D0 on those platforms and hope the BIOS will
1644 1645 1646 1647 1648 1649 1650
	 * power down the device properly. The issue was seen on multiple old
	 * GENs with different BIOS vendors, so having an explicit blacklist
	 * is inpractical; apply the workaround on everything pre GEN6. The
	 * platforms where the issue was seen:
	 * Lenovo Thinkpad X301, X61s, X60, T60, X41
	 * Fujitsu FSC S7110
	 * Acer Aspire 1830T
1651
	 */
1652
	if (!(hibernation && INTEL_GEN(dev_priv) < 6))
D
David Weinehall 已提交
1653
		pci_set_power_state(pdev, PCI_D3hot);
1654

1655 1656
	dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);

1657 1658 1659 1660
out:
	enable_rpm_wakeref_asserts(dev_priv);

	return ret;
1661 1662
}

1663
static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1664 1665 1666
{
	int error;

1667
	if (!dev) {
1668 1669 1670 1671 1672
		DRM_ERROR("dev: %p\n", dev);
		DRM_ERROR("DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}

1673 1674 1675
	if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
			 state.event != PM_EVENT_FREEZE))
		return -EINVAL;
1676 1677 1678

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
1679

1680
	error = i915_drm_suspend(dev);
1681 1682 1683
	if (error)
		return error;

1684
	return i915_drm_suspend_late(dev, false);
J
Jesse Barnes 已提交
1685 1686
}

1687
static int i915_drm_resume(struct drm_device *dev)
1688
{
1689
	struct drm_i915_private *dev_priv = to_i915(dev);
1690
	int ret;
1691

1692
	disable_rpm_wakeref_asserts(dev_priv);
1693
	intel_sanitize_gt_powersave(dev_priv);
1694

1695
	ret = i915_ggtt_enable_hw(dev_priv);
1696 1697 1698
	if (ret)
		DRM_ERROR("failed to re-enable GGTT\n");

1699 1700
	intel_csr_ucode_resume(dev_priv);

1701
	i915_restore_state(dev_priv);
1702
	intel_pps_unlock_regs_wa(dev_priv);
1703
	intel_opregion_setup(dev_priv);
1704

1705
	intel_init_pch_refclk(dev_priv);
1706

1707 1708 1709 1710 1711
	/*
	 * Interrupts have to be enabled before any batches are run. If not the
	 * GPU will hang. i915_gem_init_hw() will initiate batches to
	 * update/restore the context.
	 *
1712 1713
	 * drm_mode_config_reset() needs AUX interrupts.
	 *
1714 1715 1716 1717 1718
	 * Modeset enabling in intel_modeset_init_hw() also needs working
	 * interrupts.
	 */
	intel_runtime_pm_enable_interrupts(dev_priv);

1719 1720
	drm_mode_config_reset(dev);

1721
	i915_gem_resume(dev_priv);
1722

1723
	intel_modeset_init_hw(dev);
1724
	intel_init_clock_gating(dev_priv);
1725

1726 1727
	spin_lock_irq(&dev_priv->irq_lock);
	if (dev_priv->display.hpd_irq_setup)
1728
		dev_priv->display.hpd_irq_setup(dev_priv);
1729
	spin_unlock_irq(&dev_priv->irq_lock);
1730

1731
	intel_dp_mst_resume(dev);
1732

1733 1734
	intel_display_resume(dev);

1735 1736
	drm_kms_helper_poll_enable(dev);

1737 1738 1739 1740 1741 1742 1743
	/*
	 * ... but also need to make sure that hotplug processing
	 * doesn't cause havoc. Like in the driver load code we don't
	 * bother with the tiny race here where we might loose hotplug
	 * notifications.
	 * */
	intel_hpd_init(dev_priv);
1744

1745
	intel_opregion_register(dev_priv);
1746

1747
	intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1748

1749 1750 1751
	mutex_lock(&dev_priv->modeset_restore_lock);
	dev_priv->modeset_restore = MODESET_DONE;
	mutex_unlock(&dev_priv->modeset_restore_lock);
1752

1753
	intel_opregion_notify_adapter(dev_priv, PCI_D0);
1754

1755 1756
	enable_rpm_wakeref_asserts(dev_priv);

1757
	return 0;
1758 1759
}

1760
static int i915_drm_resume_early(struct drm_device *dev)
1761
{
1762
	struct drm_i915_private *dev_priv = to_i915(dev);
D
David Weinehall 已提交
1763
	struct pci_dev *pdev = dev_priv->drm.pdev;
1764
	int ret;
1765

1766 1767 1768 1769 1770 1771 1772 1773 1774
	/*
	 * We have a resume ordering issue with the snd-hda driver also
	 * requiring our device to be power up. Due to the lack of a
	 * parent/child relationship we currently solve this with an early
	 * resume hook.
	 *
	 * FIXME: This should be solved with a special hdmi sink device or
	 * similar so that power domains can be employed.
	 */
1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785

	/*
	 * Note that we need to set the power state explicitly, since we
	 * powered off the device during freeze and the PCI core won't power
	 * it back up for us during thaw. Powering off the device during
	 * freeze is not a hard requirement though, and during the
	 * suspend/resume phases the PCI core makes sure we get here with the
	 * device powered on. So in case we change our freeze logic and keep
	 * the device powered we can also remove the following set power state
	 * call.
	 */
D
David Weinehall 已提交
1786
	ret = pci_set_power_state(pdev, PCI_D0);
1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804
	if (ret) {
		DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
		goto out;
	}

	/*
	 * Note that pci_enable_device() first enables any parent bridge
	 * device and only then sets the power state for this device. The
	 * bridge enabling is a nop though, since bridge devices are resumed
	 * first. The order of enabling power and enabling the device is
	 * imposed by the PCI core as described above, so here we preserve the
	 * same order for the freeze/thaw phases.
	 *
	 * TODO: eventually we should remove pci_disable_device() /
	 * pci_enable_enable_device() from suspend/resume. Due to how they
	 * depend on the device enable refcount we can't anyway depend on them
	 * disabling/enabling the device.
	 */
D
David Weinehall 已提交
1805
	if (pci_enable_device(pdev)) {
1806 1807 1808
		ret = -EIO;
		goto out;
	}
1809

D
David Weinehall 已提交
1810
	pci_set_master(pdev);
1811

1812 1813
	disable_rpm_wakeref_asserts(dev_priv);

1814
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1815
		ret = vlv_resume_prepare(dev_priv, false);
1816
	if (ret)
1817 1818
		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
			  ret);
1819

1820
	intel_uncore_resume_early(dev_priv);
1821

1822
	if (IS_GEN9_LP(dev_priv)) {
1823 1824
		if (!dev_priv->suspended_to_idle)
			gen9_sanitize_dc_state(dev_priv);
1825
		bxt_disable_dc9(dev_priv);
1826
	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1827
		hsw_disable_pc8(dev_priv);
1828
	}
1829

1830
	intel_uncore_sanitize(dev_priv);
1831

1832
	if (IS_GEN9_LP(dev_priv) ||
1833
	    !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1834 1835
		intel_power_domains_init_hw(dev_priv, true);

1836 1837
	i915_gem_sanitize(dev_priv);

1838 1839
	enable_rpm_wakeref_asserts(dev_priv);

1840 1841
out:
	dev_priv->suspended_to_idle = false;
1842 1843

	return ret;
1844 1845
}

1846
static int i915_resume_switcheroo(struct drm_device *dev)
1847
{
1848
	int ret;
1849

1850 1851 1852
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

1853
	ret = i915_drm_resume_early(dev);
1854 1855 1856
	if (ret)
		return ret;

1857 1858 1859
	return i915_drm_resume(dev);
}

1860
/**
1861
 * i915_reset - reset chip after a hang
1862 1863
 * @i915: #drm_i915_private to reset
 * @flags: Instructions
1864
 *
1865 1866
 * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
 * on failure.
1867
 *
1868 1869
 * Caller must hold the struct_mutex.
 *
1870 1871 1872 1873 1874 1875 1876 1877
 * Procedure is fairly simple:
 *   - reset the chip using the reset reg
 *   - re-init context state
 *   - re-init hardware status page
 *   - re-init ring buffer
 *   - re-init interrupt state
 *   - re-init display
 */
1878
void i915_reset(struct drm_i915_private *i915, unsigned int flags)
1879
{
1880
	struct i915_gpu_error *error = &i915->gpu_error;
1881
	int ret;
1882
	int i;
1883

1884
	might_sleep();
1885
	lockdep_assert_held(&i915->drm.struct_mutex);
1886
	GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1887

1888
	if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1889
		return;
1890

1891
	/* Clear any previous failed attempts at recovery. Time to try again. */
1892
	if (!i915_gem_unset_wedged(i915))
1893 1894
		goto wakeup;

1895 1896
	if (!(flags & I915_RESET_QUIET))
		dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
1897
	error->reset_count++;
1898

1899 1900
	disable_irq(i915->drm.irq);
	ret = i915_gem_reset_prepare(i915);
1901
	if (ret) {
1902
		dev_err(i915->drm.dev, "GPU recovery failed\n");
1903
		intel_gpu_reset(i915, ALL_ENGINES);
1904
		goto taint;
1905
	}
1906

1907
	if (!intel_has_gpu_reset(i915)) {
1908 1909 1910 1911
		if (i915_modparams.reset)
			dev_err(i915->drm.dev, "GPU reset not supported\n");
		else
			DRM_DEBUG_DRIVER("GPU reset disabled\n");
1912 1913 1914 1915 1916 1917 1918 1919 1920 1921
		goto error;
	}

	for (i = 0; i < 3; i++) {
		ret = intel_gpu_reset(i915, ALL_ENGINES);
		if (ret == 0)
			break;

		msleep(100);
	}
1922
	if (ret) {
1923
		dev_err(i915->drm.dev, "Failed to reset chip\n");
1924
		goto taint;
1925 1926
	}

1927 1928
	i915_gem_reset(i915);
	intel_overlay_reset(i915);
1929

1930 1931 1932 1933
	/* Ok, now get things going again... */

	/*
	 * Everything depends on having the GTT running, so we need to start
1934 1935 1936 1937 1938 1939 1940 1941 1942
	 * there.
	 */
	ret = i915_ggtt_enable_hw(i915);
	if (ret) {
		DRM_ERROR("Failed to re-enable GGTT following reset %d\n", ret);
		goto error;
	}

	/*
1943 1944 1945 1946 1947 1948 1949
	 * Next we need to restore the context, but we don't use those
	 * yet either...
	 *
	 * Ring buffer needs to be re-initialized in the KMS case, or if X
	 * was running at the time of the reset (i.e. we weren't VT
	 * switched away).
	 */
1950
	ret = i915_gem_init_hw(i915);
1951 1952
	if (ret) {
		DRM_ERROR("Failed hw init on reset %d\n", ret);
1953
		goto error;
1954 1955
	}

1956
	i915_queue_hangcheck(i915);
1957

1958
finish:
1959 1960
	i915_gem_reset_finish(i915);
	enable_irq(i915->drm.irq);
1961

1962
wakeup:
1963 1964
	clear_bit(I915_RESET_HANDOFF, &error->flags);
	wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1965
	return;
1966

1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980
taint:
	/*
	 * History tells us that if we cannot reset the GPU now, we
	 * never will. This then impacts everything that is run
	 * subsequently. On failing the reset, we mark the driver
	 * as wedged, preventing further execution on the GPU.
	 * We also want to go one step further and add a taint to the
	 * kernel so that any subsequent faults can be traced back to
	 * this failure. This is important for CI, where if the
	 * GPU/driver fails we would like to reboot and restart testing
	 * rather than continue on into oblivion. For everyone else,
	 * the system should still plod along, but they have been warned!
	 */
	add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
1981
error:
1982 1983
	i915_gem_set_wedged(i915);
	i915_gem_retire_requests(i915);
1984
	goto finish;
1985 1986
}

1987 1988 1989 1990 1991 1992
static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
					struct intel_engine_cs *engine)
{
	return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
}

1993 1994 1995
/**
 * i915_reset_engine - reset GPU engine to recover from a hang
 * @engine: engine to reset
1996
 * @flags: options
1997 1998 1999
 *
 * Reset a specific GPU engine. Useful if a hang is detected.
 * Returns zero on successful reset or otherwise an error code.
2000 2001 2002 2003 2004
 *
 * Procedure is:
 *  - identifies the request that caused the hang and it is dropped
 *  - reset engine (which will force the engine to idle)
 *  - re-init/configure engine
2005
 */
2006
int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
2007
{
2008 2009 2010 2011 2012 2013
	struct i915_gpu_error *error = &engine->i915->gpu_error;
	struct drm_i915_gem_request *active_request;
	int ret;

	GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));

2014 2015 2016 2017 2018 2019 2020
	active_request = i915_gem_reset_prepare_engine(engine);
	if (IS_ERR_OR_NULL(active_request)) {
		/* Either the previous reset failed, or we pardon the reset. */
		ret = PTR_ERR(active_request);
		goto out;
	}

2021 2022 2023 2024
	if (!(flags & I915_RESET_QUIET)) {
		dev_notice(engine->i915->drm.dev,
			   "Resetting %s after gpu hang\n", engine->name);
	}
2025
	error->reset_engine_count[engine->id]++;
2026

2027 2028 2029 2030
	if (!engine->i915->guc.execbuf_client)
		ret = intel_gt_reset_engine(engine->i915, engine);
	else
		ret = intel_guc_reset_engine(&engine->i915->guc, engine);
2031 2032
	if (ret) {
		/* If we fail here, we expect to fallback to a global reset */
2033 2034
		DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
				 engine->i915->guc.execbuf_client ? "GuC " : "",
2035 2036 2037
				 engine->name, ret);
		goto out;
	}
2038

2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051
	/*
	 * The request that caused the hang is stuck on elsp, we know the
	 * active request and can drop it, adjust head to skip the offending
	 * request to resume executing remaining requests in the queue.
	 */
	i915_gem_reset_engine(engine, active_request);

	/*
	 * The engine and its registers (and workarounds in case of render)
	 * have been reset to their default values. Follow the init_ring
	 * process to program RING_MODE, HWSP and re-enable submission.
	 */
	ret = engine->init_hw(engine);
2052 2053
	if (ret)
		goto out;
2054 2055

out:
2056
	i915_gem_reset_finish_engine(engine);
2057
	return ret;
2058 2059
}

2060
static int i915_pm_suspend(struct device *kdev)
2061
{
2062 2063
	struct pci_dev *pdev = to_pci_dev(kdev);
	struct drm_device *dev = pci_get_drvdata(pdev);
2064

2065 2066
	if (!dev) {
		dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2067 2068
		return -ENODEV;
	}
2069

2070
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2071 2072
		return 0;

2073
	return i915_drm_suspend(dev);
2074 2075
}

2076
static int i915_pm_suspend_late(struct device *kdev)
2077
{
2078
	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2079 2080

	/*
D
Damien Lespiau 已提交
2081
	 * We have a suspend ordering issue with the snd-hda driver also
2082 2083 2084 2085 2086 2087 2088
	 * requiring our device to be power up. Due to the lack of a
	 * parent/child relationship we currently solve this with an late
	 * suspend hook.
	 *
	 * FIXME: This should be solved with a special hdmi sink device or
	 * similar so that power domains can be employed.
	 */
2089
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2090
		return 0;
2091

2092
	return i915_drm_suspend_late(dev, false);
2093 2094
}

2095
static int i915_pm_poweroff_late(struct device *kdev)
2096
{
2097
	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2098

2099
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2100 2101
		return 0;

2102
	return i915_drm_suspend_late(dev, true);
2103 2104
}

2105
static int i915_pm_resume_early(struct device *kdev)
2106
{
2107
	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2108

2109
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2110 2111
		return 0;

2112
	return i915_drm_resume_early(dev);
2113 2114
}

2115
static int i915_pm_resume(struct device *kdev)
2116
{
2117
	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2118

2119
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2120 2121
		return 0;

2122
	return i915_drm_resume(dev);
2123 2124
}

2125
/* freeze: before creating the hibernation_image */
2126
static int i915_pm_freeze(struct device *kdev)
2127
{
2128
	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2129 2130
	int ret;

2131 2132 2133 2134 2135
	if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
		ret = i915_drm_suspend(dev);
		if (ret)
			return ret;
	}
2136 2137 2138 2139 2140 2141

	ret = i915_gem_freeze(kdev_to_i915(kdev));
	if (ret)
		return ret;

	return 0;
2142 2143
}

2144
static int i915_pm_freeze_late(struct device *kdev)
2145
{
2146
	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2147 2148
	int ret;

2149 2150 2151 2152 2153
	if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
		ret = i915_drm_suspend_late(dev, true);
		if (ret)
			return ret;
	}
2154

2155
	ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2156 2157 2158 2159
	if (ret)
		return ret;

	return 0;
2160 2161 2162
}

/* thaw: called after creating the hibernation image, but before turning off. */
2163
static int i915_pm_thaw_early(struct device *kdev)
2164
{
2165
	return i915_pm_resume_early(kdev);
2166 2167
}

2168
static int i915_pm_thaw(struct device *kdev)
2169
{
2170
	return i915_pm_resume(kdev);
2171 2172 2173
}

/* restore: called after loading the hibernation image. */
2174
static int i915_pm_restore_early(struct device *kdev)
2175
{
2176
	return i915_pm_resume_early(kdev);
2177 2178
}

2179
static int i915_pm_restore(struct device *kdev)
2180
{
2181
	return i915_pm_resume(kdev);
2182 2183
}

2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222
/*
 * Save all Gunit registers that may be lost after a D3 and a subsequent
 * S0i[R123] transition. The list of registers needing a save/restore is
 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
 * registers in the following way:
 * - Driver: saved/restored by the driver
 * - Punit : saved/restored by the Punit firmware
 * - No, w/o marking: no need to save/restore, since the register is R/O or
 *                    used internally by the HW in a way that doesn't depend
 *                    keeping the content across a suspend/resume.
 * - Debug : used for debugging
 *
 * We save/restore all registers marked with 'Driver', with the following
 * exceptions:
 * - Registers out of use, including also registers marked with 'Debug'.
 *   These have no effect on the driver's operation, so we don't save/restore
 *   them to reduce the overhead.
 * - Registers that are fully setup by an initialization function called from
 *   the resume path. For example many clock gating and RPS/RC6 registers.
 * - Registers that provide the right functionality with their reset defaults.
 *
 * TODO: Except for registers that based on the above 3 criteria can be safely
 * ignored, we save/restore all others, practically treating the HW context as
 * a black-box for the driver. Further investigation is needed to reduce the
 * saved/restored registers even further, by following the same 3 criteria.
 */
static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
{
	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
	int i;

	/* GAM 0x4000-0x4770 */
	s->wr_watermark		= I915_READ(GEN7_WR_WATERMARK);
	s->gfx_prio_ctrl	= I915_READ(GEN7_GFX_PRIO_CTRL);
	s->arb_mode		= I915_READ(ARB_MODE);
	s->gfx_pend_tlb0	= I915_READ(GEN7_GFX_PEND_TLB0);
	s->gfx_pend_tlb1	= I915_READ(GEN7_GFX_PEND_TLB1);

	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2223
		s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2224 2225

	s->media_max_req_count	= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2226
	s->gfx_max_req_count	= I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266

	s->render_hwsp		= I915_READ(RENDER_HWS_PGA_GEN7);
	s->ecochk		= I915_READ(GAM_ECOCHK);
	s->bsd_hwsp		= I915_READ(BSD_HWS_PGA_GEN7);
	s->blt_hwsp		= I915_READ(BLT_HWS_PGA_GEN7);

	s->tlb_rd_addr		= I915_READ(GEN7_TLB_RD_ADDR);

	/* MBC 0x9024-0x91D0, 0x8500 */
	s->g3dctl		= I915_READ(VLV_G3DCTL);
	s->gsckgctl		= I915_READ(VLV_GSCKGCTL);
	s->mbctl		= I915_READ(GEN6_MBCTL);

	/* GCP 0x9400-0x9424, 0x8100-0x810C */
	s->ucgctl1		= I915_READ(GEN6_UCGCTL1);
	s->ucgctl3		= I915_READ(GEN6_UCGCTL3);
	s->rcgctl1		= I915_READ(GEN6_RCGCTL1);
	s->rcgctl2		= I915_READ(GEN6_RCGCTL2);
	s->rstctl		= I915_READ(GEN6_RSTCTL);
	s->misccpctl		= I915_READ(GEN7_MISCCPCTL);

	/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
	s->gfxpause		= I915_READ(GEN6_GFXPAUSE);
	s->rpdeuhwtc		= I915_READ(GEN6_RPDEUHWTC);
	s->rpdeuc		= I915_READ(GEN6_RPDEUC);
	s->ecobus		= I915_READ(ECOBUS);
	s->pwrdwnupctl		= I915_READ(VLV_PWRDWNUPCTL);
	s->rp_down_timeout	= I915_READ(GEN6_RP_DOWN_TIMEOUT);
	s->rp_deucsw		= I915_READ(GEN6_RPDEUCSW);
	s->rcubmabdtmr		= I915_READ(GEN6_RCUBMABDTMR);
	s->rcedata		= I915_READ(VLV_RCEDATA);
	s->spare2gh		= I915_READ(VLV_SPAREG2H);

	/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
	s->gt_imr		= I915_READ(GTIMR);
	s->gt_ier		= I915_READ(GTIER);
	s->pm_imr		= I915_READ(GEN6_PMIMR);
	s->pm_ier		= I915_READ(GEN6_PMIER);

	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2267
		s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278

	/* GT SA CZ domain, 0x100000-0x138124 */
	s->tilectl		= I915_READ(TILECTL);
	s->gt_fifoctl		= I915_READ(GTFIFOCTL);
	s->gtlc_wake_ctrl	= I915_READ(VLV_GTLC_WAKE_CTRL);
	s->gtlc_survive		= I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	s->pmwgicz		= I915_READ(VLV_PMWGICZ);

	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
	s->gu_ctl0		= I915_READ(VLV_GU_CTL0);
	s->gu_ctl1		= I915_READ(VLV_GU_CTL1);
2279
	s->pcbr			= I915_READ(VLV_PCBR);
2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304
	s->clock_gate_dis2	= I915_READ(VLV_GUNIT_CLOCK_GATE2);

	/*
	 * Not saving any of:
	 * DFT,		0x9800-0x9EC0
	 * SARB,	0xB000-0xB1FC
	 * GAC,		0x5208-0x524C, 0x14000-0x14C000
	 * PCI CFG
	 */
}

static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
{
	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
	u32 val;
	int i;

	/* GAM 0x4000-0x4770 */
	I915_WRITE(GEN7_WR_WATERMARK,	s->wr_watermark);
	I915_WRITE(GEN7_GFX_PRIO_CTRL,	s->gfx_prio_ctrl);
	I915_WRITE(ARB_MODE,		s->arb_mode | (0xffff << 16));
	I915_WRITE(GEN7_GFX_PEND_TLB0,	s->gfx_pend_tlb0);
	I915_WRITE(GEN7_GFX_PEND_TLB1,	s->gfx_pend_tlb1);

	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2305
		I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2306 2307

	I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2308
	I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348

	I915_WRITE(RENDER_HWS_PGA_GEN7,	s->render_hwsp);
	I915_WRITE(GAM_ECOCHK,		s->ecochk);
	I915_WRITE(BSD_HWS_PGA_GEN7,	s->bsd_hwsp);
	I915_WRITE(BLT_HWS_PGA_GEN7,	s->blt_hwsp);

	I915_WRITE(GEN7_TLB_RD_ADDR,	s->tlb_rd_addr);

	/* MBC 0x9024-0x91D0, 0x8500 */
	I915_WRITE(VLV_G3DCTL,		s->g3dctl);
	I915_WRITE(VLV_GSCKGCTL,	s->gsckgctl);
	I915_WRITE(GEN6_MBCTL,		s->mbctl);

	/* GCP 0x9400-0x9424, 0x8100-0x810C */
	I915_WRITE(GEN6_UCGCTL1,	s->ucgctl1);
	I915_WRITE(GEN6_UCGCTL3,	s->ucgctl3);
	I915_WRITE(GEN6_RCGCTL1,	s->rcgctl1);
	I915_WRITE(GEN6_RCGCTL2,	s->rcgctl2);
	I915_WRITE(GEN6_RSTCTL,		s->rstctl);
	I915_WRITE(GEN7_MISCCPCTL,	s->misccpctl);

	/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
	I915_WRITE(GEN6_GFXPAUSE,	s->gfxpause);
	I915_WRITE(GEN6_RPDEUHWTC,	s->rpdeuhwtc);
	I915_WRITE(GEN6_RPDEUC,		s->rpdeuc);
	I915_WRITE(ECOBUS,		s->ecobus);
	I915_WRITE(VLV_PWRDWNUPCTL,	s->pwrdwnupctl);
	I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
	I915_WRITE(GEN6_RPDEUCSW,	s->rp_deucsw);
	I915_WRITE(GEN6_RCUBMABDTMR,	s->rcubmabdtmr);
	I915_WRITE(VLV_RCEDATA,		s->rcedata);
	I915_WRITE(VLV_SPAREG2H,	s->spare2gh);

	/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
	I915_WRITE(GTIMR,		s->gt_imr);
	I915_WRITE(GTIER,		s->gt_ier);
	I915_WRITE(GEN6_PMIMR,		s->pm_imr);
	I915_WRITE(GEN6_PMIER,		s->pm_ier);

	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2349
		I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373

	/* GT SA CZ domain, 0x100000-0x138124 */
	I915_WRITE(TILECTL,			s->tilectl);
	I915_WRITE(GTFIFOCTL,			s->gt_fifoctl);
	/*
	 * Preserve the GT allow wake and GFX force clock bit, they are not
	 * be restored, as they are used to control the s0ix suspend/resume
	 * sequence by the caller.
	 */
	val = I915_READ(VLV_GTLC_WAKE_CTRL);
	val &= VLV_GTLC_ALLOWWAKEREQ;
	val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
	I915_WRITE(VLV_GTLC_WAKE_CTRL, val);

	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	val &= VLV_GFX_CLK_FORCE_ON_BIT;
	val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);

	I915_WRITE(VLV_PMWGICZ,			s->pmwgicz);

	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
	I915_WRITE(VLV_GU_CTL0,			s->gu_ctl0);
	I915_WRITE(VLV_GU_CTL1,			s->gu_ctl1);
2374
	I915_WRITE(VLV_PCBR,			s->pcbr);
2375 2376 2377
	I915_WRITE(VLV_GUNIT_CLOCK_GATE2,	s->clock_gate_dis2);
}

2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391
static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
				  u32 mask, u32 val)
{
	/* The HW does not like us polling for PW_STATUS frequently, so
	 * use the sleeping loop rather than risk the busy spin within
	 * intel_wait_for_register().
	 *
	 * Transitioning between RC6 states should be at most 2ms (see
	 * valleyview_enable_rps) so use a 3ms timeout.
	 */
	return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
			3);
}

2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
{
	u32 val;
	int err;

	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
	if (force_on)
		val |= VLV_GFX_CLK_FORCE_ON_BIT;
	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);

	if (!force_on)
		return 0;

2406 2407 2408 2409 2410
	err = intel_wait_for_register(dev_priv,
				      VLV_GTLC_SURVIVABILITY_REG,
				      VLV_GFX_CLK_STATUS_BIT,
				      VLV_GFX_CLK_STATUS_BIT,
				      20);
2411 2412 2413 2414 2415 2416 2417
	if (err)
		DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
			  I915_READ(VLV_GTLC_SURVIVABILITY_REG));

	return err;
}

2418 2419
static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
{
2420
	u32 mask;
2421
	u32 val;
2422
	int err;
2423 2424 2425 2426 2427 2428 2429 2430

	val = I915_READ(VLV_GTLC_WAKE_CTRL);
	val &= ~VLV_GTLC_ALLOWWAKEREQ;
	if (allow)
		val |= VLV_GTLC_ALLOWWAKEREQ;
	I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
	POSTING_READ(VLV_GTLC_WAKE_CTRL);

2431 2432 2433 2434
	mask = VLV_GTLC_ALLOWWAKEACK;
	val = allow ? mask : 0;

	err = vlv_wait_for_pw_status(dev_priv, mask, val);
2435 2436
	if (err)
		DRM_ERROR("timeout disabling GT waking\n");
2437

2438 2439 2440
	return err;
}

2441 2442
static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
				  bool wait_for_on)
2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453
{
	u32 mask;
	u32 val;

	mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
	val = wait_for_on ? mask : 0;

	/*
	 * RC6 transitioning can be delayed up to 2 msec (see
	 * valleyview_enable_rps), use 3 msec for safety.
	 */
2454
	if (vlv_wait_for_pw_status(dev_priv, mask, val))
2455
		DRM_ERROR("timeout waiting for GT wells to go %s\n",
2456
			  onoff(wait_for_on));
2457 2458 2459 2460 2461 2462 2463
}

static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
{
	if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
		return;

2464
	DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2465 2466 2467
	I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
}

2468
static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2469 2470 2471 2472 2473 2474 2475 2476
{
	u32 mask;
	int err;

	/*
	 * Bspec defines the following GT well on flags as debug only, so
	 * don't treat them as hard failures.
	 */
2477
	vlv_wait_for_gt_wells(dev_priv, false);
2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490

	mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
	WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);

	vlv_check_no_gt_access(dev_priv);

	err = vlv_force_gfx_clock(dev_priv, true);
	if (err)
		goto err1;

	err = vlv_allow_gt_wake(dev_priv, false);
	if (err)
		goto err2;
2491

2492
	if (!IS_CHERRYVIEW(dev_priv))
2493
		vlv_save_gunit_s0ix_state(dev_priv);
2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509

	err = vlv_force_gfx_clock(dev_priv, false);
	if (err)
		goto err2;

	return 0;

err2:
	/* For safety always re-enable waking and disable gfx clock forcing */
	vlv_allow_gt_wake(dev_priv, true);
err1:
	vlv_force_gfx_clock(dev_priv, false);

	return err;
}

2510 2511
static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
				bool rpm_resume)
2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522
{
	int err;
	int ret;

	/*
	 * If any of the steps fail just try to continue, that's the best we
	 * can do at this point. Return the first error code (which will also
	 * leave RPM permanently disabled).
	 */
	ret = vlv_force_gfx_clock(dev_priv, true);

2523
	if (!IS_CHERRYVIEW(dev_priv))
2524
		vlv_restore_gunit_s0ix_state(dev_priv);
2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535

	err = vlv_allow_gt_wake(dev_priv, true);
	if (!ret)
		ret = err;

	err = vlv_force_gfx_clock(dev_priv, false);
	if (!ret)
		ret = err;

	vlv_check_no_gt_access(dev_priv);

2536
	if (rpm_resume)
2537
		intel_init_clock_gating(dev_priv);
2538 2539 2540 2541

	return ret;
}

2542
static int intel_runtime_suspend(struct device *kdev)
2543
{
2544
	struct pci_dev *pdev = to_pci_dev(kdev);
2545
	struct drm_device *dev = pci_get_drvdata(pdev);
2546
	struct drm_i915_private *dev_priv = to_i915(dev);
2547
	int ret;
2548

2549
	if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2550 2551
		return -ENODEV;

2552
	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2553 2554
		return -ENODEV;

2555 2556
	DRM_DEBUG_KMS("Suspending device\n");

2557 2558
	disable_rpm_wakeref_asserts(dev_priv);

2559 2560 2561 2562
	/*
	 * We are safe here against re-faults, since the fault handler takes
	 * an RPM reference.
	 */
2563
	i915_gem_runtime_suspend(dev_priv);
2564

2565
	intel_guc_suspend(dev_priv);
2566

2567
	intel_runtime_pm_disable_interrupts(dev_priv);
2568

2569 2570
	intel_uncore_suspend(dev_priv);

2571
	ret = 0;
2572
	if (IS_GEN9_LP(dev_priv)) {
2573 2574 2575 2576 2577 2578 2579 2580
		bxt_display_core_uninit(dev_priv);
		bxt_enable_dc9(dev_priv);
	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
		hsw_enable_pc8(dev_priv);
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
		ret = vlv_suspend_complete(dev_priv);
	}

2581 2582
	if (ret) {
		DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2583 2584
		intel_uncore_runtime_resume(dev_priv);

2585
		intel_runtime_pm_enable_interrupts(dev_priv);
2586

2587 2588
		enable_rpm_wakeref_asserts(dev_priv);

2589 2590
		return ret;
	}
2591

2592
	enable_rpm_wakeref_asserts(dev_priv);
2593
	WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2594

2595
	if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2596 2597
		DRM_ERROR("Unclaimed access detected prior to suspending\n");

2598
	dev_priv->runtime_pm.suspended = true;
2599 2600

	/*
2601 2602
	 * FIXME: We really should find a document that references the arguments
	 * used below!
2603
	 */
2604
	if (IS_BROADWELL(dev_priv)) {
2605 2606 2607 2608 2609 2610
		/*
		 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
		 * being detected, and the call we do at intel_runtime_resume()
		 * won't be able to restore them. Since PCI_D3hot matches the
		 * actual specification and appears to be working, use it.
		 */
2611
		intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2612
	} else {
2613 2614 2615 2616 2617 2618 2619
		/*
		 * current versions of firmware which depend on this opregion
		 * notification have repurposed the D1 definition to mean
		 * "runtime suspended" vs. what you would normally expect (D3)
		 * to distinguish it from notifications that might be sent via
		 * the suspend path.
		 */
2620
		intel_opregion_notify_adapter(dev_priv, PCI_D1);
2621
	}
2622

2623
	assert_forcewakes_inactive(dev_priv);
2624

2625
	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2626 2627
		intel_hpd_poll_init(dev_priv);

2628
	DRM_DEBUG_KMS("Device suspended\n");
2629 2630 2631
	return 0;
}

2632
static int intel_runtime_resume(struct device *kdev)
2633
{
2634
	struct pci_dev *pdev = to_pci_dev(kdev);
2635
	struct drm_device *dev = pci_get_drvdata(pdev);
2636
	struct drm_i915_private *dev_priv = to_i915(dev);
2637
	int ret = 0;
2638

2639
	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2640
		return -ENODEV;
2641 2642 2643

	DRM_DEBUG_KMS("Resuming device\n");

2644
	WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2645 2646
	disable_rpm_wakeref_asserts(dev_priv);

2647
	intel_opregion_notify_adapter(dev_priv, PCI_D0);
2648
	dev_priv->runtime_pm.suspended = false;
2649 2650
	if (intel_uncore_unclaimed_mmio(dev_priv))
		DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2651

2652
	intel_guc_resume(dev_priv);
2653

2654
	if (IS_GEN9_LP(dev_priv)) {
2655 2656
		bxt_disable_dc9(dev_priv);
		bxt_display_core_init(dev_priv, true);
2657 2658 2659
		if (dev_priv->csr.dmc_payload &&
		    (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
			gen9_enable_dc5(dev_priv);
2660
	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2661
		hsw_disable_pc8(dev_priv);
2662
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2663
		ret = vlv_resume_prepare(dev_priv, true);
2664
	}
2665

2666 2667
	intel_uncore_runtime_resume(dev_priv);

2668 2669 2670 2671
	/*
	 * No point of rolling back things in case of an error, as the best
	 * we can do is to hope that things will still work (and disable RPM).
	 */
2672
	i915_gem_init_swizzling(dev_priv);
2673
	i915_gem_restore_fences(dev_priv);
2674

2675
	intel_runtime_pm_enable_interrupts(dev_priv);
2676 2677 2678 2679 2680 2681

	/*
	 * On VLV/CHV display interrupts are part of the display
	 * power well, so hpd is reinitialized from there. For
	 * everyone else do it here.
	 */
2682
	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2683 2684
		intel_hpd_init(dev_priv);

2685 2686
	intel_enable_ipc(dev_priv);

2687 2688
	enable_rpm_wakeref_asserts(dev_priv);

2689 2690 2691 2692 2693 2694
	if (ret)
		DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
	else
		DRM_DEBUG_KMS("Device resumed\n");

	return ret;
2695 2696
}

2697
const struct dev_pm_ops i915_pm_ops = {
2698 2699 2700 2701
	/*
	 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
	 * PMSG_RESUME]
	 */
2702
	.suspend = i915_pm_suspend,
2703 2704
	.suspend_late = i915_pm_suspend_late,
	.resume_early = i915_pm_resume_early,
2705
	.resume = i915_pm_resume,
2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721

	/*
	 * S4 event handlers
	 * @freeze, @freeze_late    : called (1) before creating the
	 *                            hibernation image [PMSG_FREEZE] and
	 *                            (2) after rebooting, before restoring
	 *                            the image [PMSG_QUIESCE]
	 * @thaw, @thaw_early       : called (1) after creating the hibernation
	 *                            image, before writing it [PMSG_THAW]
	 *                            and (2) after failing to create or
	 *                            restore the image [PMSG_RECOVER]
	 * @poweroff, @poweroff_late: called after writing the hibernation
	 *                            image, before rebooting [PMSG_HIBERNATE]
	 * @restore, @restore_early : called after rebooting and restoring the
	 *                            hibernation image [PMSG_RESTORE]
	 */
2722 2723 2724 2725
	.freeze = i915_pm_freeze,
	.freeze_late = i915_pm_freeze_late,
	.thaw_early = i915_pm_thaw_early,
	.thaw = i915_pm_thaw,
2726
	.poweroff = i915_pm_suspend,
2727
	.poweroff_late = i915_pm_poweroff_late,
2728 2729
	.restore_early = i915_pm_restore_early,
	.restore = i915_pm_restore,
2730 2731

	/* S0ix (via runtime suspend) event handlers */
2732 2733
	.runtime_suspend = intel_runtime_suspend,
	.runtime_resume = intel_runtime_resume,
2734 2735
};

2736
static const struct vm_operations_struct i915_gem_vm_ops = {
2737
	.fault = i915_gem_fault,
2738 2739
	.open = drm_gem_vm_open,
	.close = drm_gem_vm_close,
2740 2741
};

2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753
static const struct file_operations i915_driver_fops = {
	.owner = THIS_MODULE,
	.open = drm_open,
	.release = drm_release,
	.unlocked_ioctl = drm_ioctl,
	.mmap = drm_gem_mmap,
	.poll = drm_poll,
	.read = drm_read,
	.compat_ioctl = i915_compat_ioctl,
	.llseek = noop_llseek,
};

2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780
static int
i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file)
{
	return -ENODEV;
}

static const struct drm_ioctl_desc i915_ioctls[] = {
	DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2781
	DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796
	DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2797 2798
	DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813
	DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
	DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2814
	DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2815 2816
	DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2817 2818
};

L
Linus Torvalds 已提交
2819
static struct drm_driver driver = {
2820 2821
	/* Don't use MTRRs here; the Xserver or userspace app should
	 * deal with them for Intel hardware.
D
Dave Airlie 已提交
2822
	 */
2823
	.driver_features =
2824
	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2825
	    DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2826
	.release = i915_driver_release,
2827
	.open = i915_driver_open,
2828
	.lastclose = i915_driver_lastclose,
2829
	.postclose = i915_driver_postclose,
2830

2831
	.gem_close_object = i915_gem_close_object,
C
Chris Wilson 已提交
2832
	.gem_free_object_unlocked = i915_gem_free_object,
2833
	.gem_vm_ops = &i915_gem_vm_ops,
2834 2835 2836 2837 2838 2839

	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
	.gem_prime_export = i915_gem_prime_export,
	.gem_prime_import = i915_gem_prime_import,

2840
	.dumb_create = i915_gem_dumb_create,
2841
	.dumb_map_offset = i915_gem_mmap_gtt,
L
Linus Torvalds 已提交
2842
	.ioctls = i915_ioctls,
2843
	.num_ioctls = ARRAY_SIZE(i915_ioctls),
2844
	.fops = &i915_driver_fops,
2845 2846 2847 2848 2849 2850
	.name = DRIVER_NAME,
	.desc = DRIVER_DESC,
	.date = DRIVER_DATE,
	.major = DRIVER_MAJOR,
	.minor = DRIVER_MINOR,
	.patchlevel = DRIVER_PATCHLEVEL,
L
Linus Torvalds 已提交
2851
};
2852 2853 2854 2855

#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/mock_drm.c"
#endif