i915_drv.c 75.1 KB
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/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#include <linux/acpi.h>
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#include <linux/device.h>
#include <linux/oom.h>
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#include <linux/module.h>
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#include <linux/pci.h>
#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/pnp.h>
#include <linux/slab.h>
#include <linux/vgaarb.h>
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#include <linux/vga_switcheroo.h>
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#include <linux/vt.h>
#include <acpi/video.h>

#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/i915_drm.h>

#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
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#include "intel_uc.h"
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static struct drm_driver driver;

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static unsigned int i915_load_fail_count;

bool __i915_inject_load_failure(const char *func, int line)
{
	if (i915_load_fail_count >= i915.inject_load_failure)
		return false;

	if (++i915_load_fail_count == i915.inject_load_failure) {
		DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
			 i915.inject_load_failure, func, line);
		return true;
	}

	return false;
}

#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
		    "providing the dmesg log by booting with drm.debug=0xf"

void
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...)
{
	static bool shown_bug_once;
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	struct device *kdev = dev_priv->drm.dev;
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	bool is_error = level[1] <= KERN_ERR[1];
	bool is_debug = level[1] == KERN_DEBUG[1];
	struct va_format vaf;
	va_list args;

	if (is_debug && !(drm_debug & DRM_UT_DRIVER))
		return;

	va_start(args, fmt);

	vaf.fmt = fmt;
	vaf.va = &args;

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	dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
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		   __builtin_return_address(0), &vaf);

	if (is_error && !shown_bug_once) {
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		dev_notice(kdev, "%s", FDO_BUG_MSG);
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		shown_bug_once = true;
	}

	va_end(args);
}

static bool i915_error_injected(struct drm_i915_private *dev_priv)
{
	return i915.inject_load_failure &&
	       i915_load_fail_count == i915.inject_load_failure;
}

#define i915_load_error(dev_priv, fmt, ...)				     \
	__i915_printk(dev_priv,						     \
		      i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
		      fmt, ##__VA_ARGS__)


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static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
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{
	enum intel_pch ret = PCH_NOP;

	/*
	 * In a virtualized passthrough environment we can be in a
	 * setup where the ISA bridge is not able to be passed through.
	 * In this case, a south bridge can be emulated and we have to
	 * make an educated guess as to which PCH is really there.
	 */

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	if (IS_GEN5(dev_priv)) {
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		ret = PCH_IBX;
		DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
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	} else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
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		ret = PCH_CPT;
		DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
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	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
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		ret = PCH_LPT;
		DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
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	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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		ret = PCH_SPT;
		DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
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	} else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
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		ret = PCH_CNP;
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		DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
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	}

	return ret;
}

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static void intel_detect_pch(struct drm_i915_private *dev_priv)
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{
	struct pci_dev *pch = NULL;

	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
	 * (which really amounts to a PCH but no South Display).
	 */
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	if (INTEL_INFO(dev_priv)->num_pipes == 0) {
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		dev_priv->pch_type = PCH_NOP;
		return;
	}

	/*
	 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
	 * make graphics device passthrough work easy for VMM, that only
	 * need to expose ISA bridge to let driver know the real hardware
	 * underneath. This is a requirement from virtualization team.
	 *
	 * In some virtualized environments (e.g. XEN), there is irrelevant
	 * ISA bridge in the system. To work reliably, we should scan trhough
	 * all the ISA bridge devices and check for the first match, instead
	 * of only checking the first one.
	 */
	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
		if (pch->vendor == PCI_VENDOR_ID_INTEL) {
			unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
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			unsigned short id_ext = pch->device &
				INTEL_PCH_DEVICE_ID_MASK_EXT;

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			dev_priv->pch_id = id;

			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_IBX;
				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
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				WARN_ON(!IS_GEN5(dev_priv));
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			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_CPT;
				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
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				WARN_ON(!(IS_GEN6(dev_priv) ||
					IS_IVYBRIDGE(dev_priv)));
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			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
				/* PantherPoint is CPT compatible */
				dev_priv->pch_type = PCH_CPT;
				DRM_DEBUG_KMS("Found PantherPoint PCH\n");
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				WARN_ON(!(IS_GEN6(dev_priv) ||
					IS_IVYBRIDGE(dev_priv)));
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			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_LPT;
				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
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				WARN_ON(!IS_HASWELL(dev_priv) &&
					!IS_BROADWELL(dev_priv));
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				WARN_ON(IS_HSW_ULT(dev_priv) ||
					IS_BDW_ULT(dev_priv));
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			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_LPT;
				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
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				WARN_ON(!IS_HASWELL(dev_priv) &&
					!IS_BROADWELL(dev_priv));
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				WARN_ON(!IS_HSW_ULT(dev_priv) &&
					!IS_BDW_ULT(dev_priv));
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			} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_SPT;
				DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
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				WARN_ON(!IS_SKYLAKE(dev_priv) &&
					!IS_KABYLAKE(dev_priv));
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			} else if (id_ext == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
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				dev_priv->pch_type = PCH_SPT;
				DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
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				WARN_ON(!IS_SKYLAKE(dev_priv) &&
					!IS_KABYLAKE(dev_priv));
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			} else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_KBP;
				DRM_DEBUG_KMS("Found KabyPoint PCH\n");
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				WARN_ON(!IS_SKYLAKE(dev_priv) &&
					!IS_KABYLAKE(dev_priv));
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			} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_CNP;
				DRM_DEBUG_KMS("Found CannonPoint PCH\n");
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				WARN_ON(!IS_CANNONLAKE(dev_priv) &&
					!IS_COFFEELAKE(dev_priv));
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			} else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_CNP;
				DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
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				WARN_ON(!IS_CANNONLAKE(dev_priv) &&
					!IS_COFFEELAKE(dev_priv));
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			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
				   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
				    pch->subsystem_vendor ==
					    PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
				    pch->subsystem_device ==
					    PCI_SUBDEVICE_ID_QEMU)) {
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				dev_priv->pch_type =
					intel_virt_detect_pch(dev_priv);
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			} else
				continue;

			break;
		}
	}
	if (!pch)
		DRM_DEBUG_KMS("No PCH found.\n");

	pci_dev_put(pch);
}

static int i915_getparam(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
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	struct drm_i915_private *dev_priv = to_i915(dev);
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	struct pci_dev *pdev = dev_priv->drm.pdev;
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	drm_i915_getparam_t *param = data;
	int value;

	switch (param->param) {
	case I915_PARAM_IRQ_ACTIVE:
	case I915_PARAM_ALLOW_BATCHBUFFER:
	case I915_PARAM_LAST_DISPATCH:
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	case I915_PARAM_HAS_EXEC_CONSTANTS:
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		/* Reject all old ums/dri params. */
		return -ENODEV;
	case I915_PARAM_CHIPSET_ID:
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		value = pdev->device;
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		break;
	case I915_PARAM_REVISION:
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		value = pdev->revision;
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		break;
	case I915_PARAM_NUM_FENCES_AVAIL:
		value = dev_priv->num_fence_regs;
		break;
	case I915_PARAM_HAS_OVERLAY:
		value = dev_priv->overlay ? 1 : 0;
		break;
	case I915_PARAM_HAS_BSD:
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		value = !!dev_priv->engine[VCS];
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		break;
	case I915_PARAM_HAS_BLT:
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		value = !!dev_priv->engine[BCS];
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		break;
	case I915_PARAM_HAS_VEBOX:
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		value = !!dev_priv->engine[VECS];
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		break;
	case I915_PARAM_HAS_BSD2:
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		value = !!dev_priv->engine[VCS2];
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		break;
	case I915_PARAM_HAS_LLC:
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		value = HAS_LLC(dev_priv);
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		break;
	case I915_PARAM_HAS_WT:
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		value = HAS_WT(dev_priv);
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		break;
	case I915_PARAM_HAS_ALIASING_PPGTT:
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		value = USES_PPGTT(dev_priv);
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		break;
	case I915_PARAM_HAS_SEMAPHORES:
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		value = i915.semaphores;
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		break;
	case I915_PARAM_HAS_SECURE_BATCHES:
		value = capable(CAP_SYS_ADMIN);
		break;
	case I915_PARAM_CMD_PARSER_VERSION:
		value = i915_cmd_parser_get_version(dev_priv);
		break;
	case I915_PARAM_SUBSLICE_TOTAL:
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		value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
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		if (!value)
			return -ENODEV;
		break;
	case I915_PARAM_EU_TOTAL:
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		value = INTEL_INFO(dev_priv)->sseu.eu_total;
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		if (!value)
			return -ENODEV;
		break;
	case I915_PARAM_HAS_GPU_RESET:
		value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
		break;
	case I915_PARAM_HAS_RESOURCE_STREAMER:
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		value = HAS_RESOURCE_STREAMER(dev_priv);
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		break;
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	case I915_PARAM_HAS_POOLED_EU:
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		value = HAS_POOLED_EU(dev_priv);
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		break;
	case I915_PARAM_MIN_EU_IN_POOL:
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		value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
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		break;
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	case I915_PARAM_HUC_STATUS:
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		intel_runtime_pm_get(dev_priv);
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		value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
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		intel_runtime_pm_put(dev_priv);
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		break;
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	case I915_PARAM_MMAP_GTT_VERSION:
		/* Though we've started our numbering from 1, and so class all
		 * earlier versions as 0, in effect their value is undefined as
		 * the ioctl will report EINVAL for the unknown param!
		 */
		value = i915_gem_mmap_gtt_version();
		break;
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	case I915_PARAM_HAS_SCHEDULER:
		value = dev_priv->engine[RCS] &&
			dev_priv->engine[RCS]->schedule;
		break;
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	case I915_PARAM_MMAP_VERSION:
		/* Remember to bump this if the version changes! */
	case I915_PARAM_HAS_GEM:
	case I915_PARAM_HAS_PAGEFLIPPING:
	case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
	case I915_PARAM_HAS_RELAXED_FENCING:
	case I915_PARAM_HAS_COHERENT_RINGS:
	case I915_PARAM_HAS_RELAXED_DELTA:
	case I915_PARAM_HAS_GEN7_SOL_RESET:
	case I915_PARAM_HAS_WAIT_TIMEOUT:
	case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
	case I915_PARAM_HAS_PINNED_BATCHES:
	case I915_PARAM_HAS_EXEC_NO_RELOC:
	case I915_PARAM_HAS_EXEC_HANDLE_LUT:
	case I915_PARAM_HAS_COHERENT_PHYS_GTT:
	case I915_PARAM_HAS_EXEC_SOFTPIN:
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	case I915_PARAM_HAS_EXEC_ASYNC:
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	case I915_PARAM_HAS_EXEC_FENCE:
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	case I915_PARAM_HAS_EXEC_CAPTURE:
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		/* For the time being all of these are always true;
		 * if some supported hardware does not have one of these
		 * features this value needs to be provided from
		 * INTEL_INFO(), a feature macro, or similar.
		 */
		value = 1;
		break;
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	default:
		DRM_DEBUG("Unknown parameter %d\n", param->param);
		return -EINVAL;
	}

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	if (put_user(value, param->value))
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		return -EFAULT;

	return 0;
}

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static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
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{
	dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
	if (!dev_priv->bridge_dev) {
		DRM_ERROR("bridge device not found\n");
		return -1;
	}
	return 0;
}

/* Allocate space for the MCH regs if needed, return nonzero on error */
static int
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intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
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{
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	int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
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	u32 temp_lo, temp_hi = 0;
	u64 mchbar_addr;
	int ret;

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	if (INTEL_GEN(dev_priv) >= 4)
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		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
	pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;

	/* If ACPI doesn't have it, assume we need to allocate it ourselves */
#ifdef CONFIG_PNP
	if (mchbar_addr &&
	    pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
		return 0;
#endif

	/* Get some space for it */
	dev_priv->mch_res.name = "i915 MCHBAR";
	dev_priv->mch_res.flags = IORESOURCE_MEM;
	ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
				     &dev_priv->mch_res,
				     MCHBAR_SIZE, MCHBAR_SIZE,
				     PCIBIOS_MIN_MEM,
				     0, pcibios_align_resource,
				     dev_priv->bridge_dev);
	if (ret) {
		DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
		dev_priv->mch_res.start = 0;
		return ret;
	}

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	if (INTEL_GEN(dev_priv) >= 4)
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		pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
				       upper_32_bits(dev_priv->mch_res.start));

	pci_write_config_dword(dev_priv->bridge_dev, reg,
			       lower_32_bits(dev_priv->mch_res.start));
	return 0;
}

/* Setup MCHBAR if possible, return true if we should disable it again */
static void
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intel_setup_mchbar(struct drm_i915_private *dev_priv)
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{
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	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
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	u32 temp;
	bool enabled;

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	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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		return;

	dev_priv->mchbar_need_disable = false;

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	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
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		pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
		enabled = !!(temp & DEVEN_MCHBAR_EN);
	} else {
		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
		enabled = temp & 1;
	}

	/* If it's already enabled, don't have to do anything */
	if (enabled)
		return;

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	if (intel_alloc_mchbar_resource(dev_priv))
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		return;

	dev_priv->mchbar_need_disable = true;

	/* Space is allocated or reserved, so enable it. */
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	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
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		pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
				       temp | DEVEN_MCHBAR_EN);
	} else {
		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
		pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
	}
}

static void
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intel_teardown_mchbar(struct drm_i915_private *dev_priv)
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{
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	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
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	if (dev_priv->mchbar_need_disable) {
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		if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
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			u32 deven_val;

			pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
					      &deven_val);
			deven_val &= ~DEVEN_MCHBAR_EN;
			pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
					       deven_val);
		} else {
			u32 mchbar_val;

			pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
					      &mchbar_val);
			mchbar_val &= ~1;
			pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
					       mchbar_val);
		}
	}

	if (dev_priv->mch_res.start)
		release_resource(&dev_priv->mch_res);
}

/* true = enable decode, false = disable decoder */
static unsigned int i915_vga_set_decode(void *cookie, bool state)
{
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	struct drm_i915_private *dev_priv = cookie;
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	intel_modeset_vga_set_state(dev_priv, state);
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	if (state)
		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
	else
		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
}

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static int i915_resume_switcheroo(struct drm_device *dev);
static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);

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static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	pm_message_t pmm = { .event = PM_EVENT_SUSPEND };

	if (state == VGA_SWITCHEROO_ON) {
		pr_info("switched on\n");
		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
		/* i915 resume handler doesn't set to D0 */
D
David Weinehall 已提交
537
		pci_set_power_state(pdev, PCI_D0);
538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565
		i915_resume_switcheroo(dev);
		dev->switch_power_state = DRM_SWITCH_POWER_ON;
	} else {
		pr_info("switched off\n");
		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
		i915_suspend_switcheroo(dev, pmm);
		dev->switch_power_state = DRM_SWITCH_POWER_OFF;
	}
}

static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	/*
	 * FIXME: open_count is protected by drm_global_mutex but that would lead to
	 * locking inversion with the driver load path. And the access here is
	 * completely racy anyway. So don't bother with locking for now.
	 */
	return dev->open_count == 0;
}

static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
	.set_gpu_state = i915_switcheroo_set_state,
	.reprobe = NULL,
	.can_switch = i915_switcheroo_can_switch,
};

566
static void i915_gem_fini(struct drm_i915_private *dev_priv)
567
{
568
	mutex_lock(&dev_priv->drm.struct_mutex);
569
	intel_uc_fini_hw(dev_priv);
570 571
	i915_gem_cleanup_engines(dev_priv);
	i915_gem_context_fini(dev_priv);
572
	mutex_unlock(&dev_priv->drm.struct_mutex);
573

574
	i915_gem_drain_freed_objects(dev_priv);
575 576

	WARN_ON(!list_empty(&dev_priv->context_list));
577 578 579 580
}

static int i915_load_modeset_init(struct drm_device *dev)
{
581
	struct drm_i915_private *dev_priv = to_i915(dev);
D
David Weinehall 已提交
582
	struct pci_dev *pdev = dev_priv->drm.pdev;
583 584 585 586 587
	int ret;

	if (i915_inject_load_failure())
		return -ENODEV;

588
	intel_bios_init(dev_priv);
589 590 591 592 593 594 595 596

	/* If we have > 1 VGA cards, then we need to arbitrate access
	 * to the common VGA resources.
	 *
	 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
	 * then we do not take part in VGA arbitration and the
	 * vga_client_register() fails with -ENODEV.
	 */
597
	ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
598 599 600 601 602
	if (ret && ret != -ENODEV)
		goto out;

	intel_register_dsm_handler();

D
David Weinehall 已提交
603
	ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
604 605 606 607 608 609 610 611 612 613 614 615 616 617
	if (ret)
		goto cleanup_vga_client;

	/* must happen before intel_power_domains_init_hw() on VLV/CHV */
	intel_update_rawclk(dev_priv);

	intel_power_domains_init_hw(dev_priv, false);

	intel_csr_ucode_init(dev_priv);

	ret = intel_irq_install(dev_priv);
	if (ret)
		goto cleanup_csr;

618
	intel_setup_gmbus(dev_priv);
619 620 621

	/* Important: The output setup functions called by modeset_init need
	 * working irqs for e.g. gmbus and dp aux transfers. */
622 623 624
	ret = intel_modeset_init(dev);
	if (ret)
		goto cleanup_irq;
625

626
	intel_uc_init_fw(dev_priv);
627

628
	ret = i915_gem_init(dev_priv);
629
	if (ret)
630
		goto cleanup_uc;
631 632 633

	intel_modeset_gem_init(dev);

634
	if (INTEL_INFO(dev_priv)->num_pipes == 0)
635 636 637 638 639 640 641 642 643 644 645 646 647 648
		return 0;

	ret = intel_fbdev_init(dev);
	if (ret)
		goto cleanup_gem;

	/* Only enable hotplug handling once the fbdev is fully set up. */
	intel_hpd_init(dev_priv);

	drm_kms_helper_poll_init(dev);

	return 0;

cleanup_gem:
649
	if (i915_gem_suspend(dev_priv))
650
		DRM_ERROR("failed to idle hardware; continuing to unload!\n");
651
	i915_gem_fini(dev_priv);
652 653
cleanup_uc:
	intel_uc_fini_fw(dev_priv);
654 655
cleanup_irq:
	drm_irq_uninstall(dev);
656
	intel_teardown_gmbus(dev_priv);
657 658 659
cleanup_csr:
	intel_csr_ucode_fini(dev_priv);
	intel_power_domains_fini(dev_priv);
D
David Weinehall 已提交
660
	vga_switcheroo_unregister_client(pdev);
661
cleanup_vga_client:
D
David Weinehall 已提交
662
	vga_client_register(pdev, NULL, NULL, NULL);
663 664 665 666 667 668 669
out:
	return ret;
}

static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
{
	struct apertures_struct *ap;
670
	struct pci_dev *pdev = dev_priv->drm.pdev;
671 672 673 674 675 676 677 678 679 680 681 682 683 684
	struct i915_ggtt *ggtt = &dev_priv->ggtt;
	bool primary;
	int ret;

	ap = alloc_apertures(1);
	if (!ap)
		return -ENOMEM;

	ap->ranges[0].base = ggtt->mappable_base;
	ap->ranges[0].size = ggtt->mappable_end;

	primary =
		pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;

685
	ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773

	kfree(ap);

	return ret;
}

#if !defined(CONFIG_VGA_CONSOLE)
static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
{
	return 0;
}
#elif !defined(CONFIG_DUMMY_CONSOLE)
static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
{
	return -ENODEV;
}
#else
static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
{
	int ret = 0;

	DRM_INFO("Replacing VGA console driver\n");

	console_lock();
	if (con_is_bound(&vga_con))
		ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
	if (ret == 0) {
		ret = do_unregister_con_driver(&vga_con);

		/* Ignore "already unregistered". */
		if (ret == -ENODEV)
			ret = 0;
	}
	console_unlock();

	return ret;
}
#endif

static void intel_init_dpio(struct drm_i915_private *dev_priv)
{
	/*
	 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
	 * CHV x1 PHY (DP/HDMI D)
	 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
	 */
	if (IS_CHERRYVIEW(dev_priv)) {
		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
		DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
	} else if (IS_VALLEYVIEW(dev_priv)) {
		DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
	}
}

static int i915_workqueues_init(struct drm_i915_private *dev_priv)
{
	/*
	 * The i915 workqueue is primarily used for batched retirement of
	 * requests (and thus managing bo) once the task has been completed
	 * by the GPU. i915_gem_retire_requests() is called directly when we
	 * need high-priority retirement, such as waiting for an explicit
	 * bo.
	 *
	 * It is also used for periodic low-priority events, such as
	 * idle-timers and recording error state.
	 *
	 * All tasks on the workqueue are expected to acquire the dev mutex
	 * so there is no point in running more than one instance of the
	 * workqueue at any time.  Use an ordered one.
	 */
	dev_priv->wq = alloc_ordered_workqueue("i915", 0);
	if (dev_priv->wq == NULL)
		goto out_err;

	dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
	if (dev_priv->hotplug.dp_wq == NULL)
		goto out_free_wq;

	return 0;

out_free_wq:
	destroy_workqueue(dev_priv->wq);
out_err:
	DRM_ERROR("Failed to allocate workqueues.\n");

	return -ENOMEM;
}

774 775 776 777 778 779 780 781 782
static void i915_engines_cleanup(struct drm_i915_private *i915)
{
	struct intel_engine_cs *engine;
	enum intel_engine_id id;

	for_each_engine(engine, i915, id)
		kfree(engine);
}

783 784 785 786 787 788
static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
{
	destroy_workqueue(dev_priv->hotplug.dp_wq);
	destroy_workqueue(dev_priv->wq);
}

789 790 791 792 793 794 795
/*
 * We don't keep the workarounds for pre-production hardware, so we expect our
 * driver to fail on these machines in one way or another. A little warning on
 * dmesg may help both the user and the bug triagers.
 */
static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
{
796 797 798 799
	bool pre = false;

	pre |= IS_HSW_EARLY_SDV(dev_priv);
	pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
800
	pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
801

802
	if (pre) {
803 804
		DRM_ERROR("This is a pre-production stepping. "
			  "It may not be fully functional.\n");
805 806
		add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
	}
807 808
}

809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830
/**
 * i915_driver_init_early - setup state not requiring device access
 * @dev_priv: device private
 *
 * Initialize everything that is a "SW-only" state, that is state not
 * requiring accessing the device or exposing the driver via kernel internal
 * or userspace interfaces. Example steps belonging here: lock initialization,
 * system memory allocation, setting up device specific attributes and
 * function hooks not requiring accessing the device.
 */
static int i915_driver_init_early(struct drm_i915_private *dev_priv,
				  const struct pci_device_id *ent)
{
	const struct intel_device_info *match_info =
		(struct intel_device_info *)ent->driver_data;
	struct intel_device_info *device_info;
	int ret = 0;

	if (i915_inject_load_failure())
		return -ENODEV;

	/* Setup the write-once "constant" device info */
831
	device_info = mkwrite_device_info(dev_priv);
832 833 834 835 836 837 838 839 840 841
	memcpy(device_info, match_info, sizeof(*device_info));
	device_info->device_id = dev_priv->drm.pdev->device;

	BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
	device_info->gen_mask = BIT(device_info->gen - 1);

	spin_lock_init(&dev_priv->irq_lock);
	spin_lock_init(&dev_priv->gpu_error.lock);
	mutex_init(&dev_priv->backlight_lock);
	spin_lock_init(&dev_priv->uncore.lock);
L
Lyude 已提交
842

843 844 845 846 847 848 849 850
	spin_lock_init(&dev_priv->mm.object_stat_lock);
	spin_lock_init(&dev_priv->mmio_flip_lock);
	mutex_init(&dev_priv->sb_lock);
	mutex_init(&dev_priv->modeset_restore_lock);
	mutex_init(&dev_priv->av_mutex);
	mutex_init(&dev_priv->wm.wm_mutex);
	mutex_init(&dev_priv->pps_mutex);

851
	intel_uc_init_early(dev_priv);
852 853
	i915_memcpy_init_early(dev_priv);

854 855
	ret = i915_workqueues_init(dev_priv);
	if (ret < 0)
856
		goto err_engines;
857 858

	/* This must be called before any calls to HAS_PCH_* */
859
	intel_detect_pch(dev_priv);
860

861
	intel_pm_setup(dev_priv);
862 863 864
	intel_init_dpio(dev_priv);
	intel_power_domains_init(dev_priv);
	intel_irq_init(dev_priv);
865
	intel_hangcheck_init(dev_priv);
866 867 868
	intel_init_display_hooks(dev_priv);
	intel_init_clock_gating_hooks(dev_priv);
	intel_init_audio_hooks(dev_priv);
869
	ret = i915_gem_load_init(dev_priv);
870
	if (ret < 0)
871
		goto err_irq;
872

873
	intel_display_crc_init(dev_priv);
874

875
	intel_device_info_dump(dev_priv);
876

877
	intel_detect_preproduction_hw(dev_priv);
878

879 880
	i915_perf_init(dev_priv);

881 882
	return 0;

883 884
err_irq:
	intel_irq_fini(dev_priv);
885
	i915_workqueues_cleanup(dev_priv);
886 887
err_engines:
	i915_engines_cleanup(dev_priv);
888 889 890 891 892 893 894 895 896
	return ret;
}

/**
 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 * @dev_priv: device private
 */
static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
{
897
	i915_perf_fini(dev_priv);
898
	i915_gem_load_cleanup(dev_priv);
899
	intel_irq_fini(dev_priv);
900
	i915_workqueues_cleanup(dev_priv);
901
	i915_engines_cleanup(dev_priv);
902 903
}

904
static int i915_mmio_setup(struct drm_i915_private *dev_priv)
905
{
D
David Weinehall 已提交
906
	struct pci_dev *pdev = dev_priv->drm.pdev;
907 908 909
	int mmio_bar;
	int mmio_size;

910
	mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
911 912 913 914 915 916 917 918
	/*
	 * Before gen4, the registers and the GTT are behind different BARs.
	 * However, from gen4 onwards, the registers and the GTT are shared
	 * in the same BAR, so we want to restrict this ioremap from
	 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
	 * the register BAR remains the same size for all the earlier
	 * generations up to Ironlake.
	 */
919
	if (INTEL_GEN(dev_priv) < 5)
920 921 922
		mmio_size = 512 * 1024;
	else
		mmio_size = 2 * 1024 * 1024;
D
David Weinehall 已提交
923
	dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
924 925 926 927 928 929 930
	if (dev_priv->regs == NULL) {
		DRM_ERROR("failed to map registers\n");

		return -EIO;
	}

	/* Try to make sure MCHBAR is enabled before poking at it */
931
	intel_setup_mchbar(dev_priv);
932 933 934 935

	return 0;
}

936
static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
937
{
D
David Weinehall 已提交
938
	struct pci_dev *pdev = dev_priv->drm.pdev;
939

940
	intel_teardown_mchbar(dev_priv);
D
David Weinehall 已提交
941
	pci_iounmap(pdev, dev_priv->regs);
942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959
}

/**
 * i915_driver_init_mmio - setup device MMIO
 * @dev_priv: device private
 *
 * Setup minimal device state necessary for MMIO accesses later in the
 * initialization sequence. The setup here should avoid any other device-wide
 * side effects or exposing the driver via kernel internal or user space
 * interfaces.
 */
static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
{
	int ret;

	if (i915_inject_load_failure())
		return -ENODEV;

960
	if (i915_get_bridge_dev(dev_priv))
961 962
		return -EIO;

963
	ret = i915_mmio_setup(dev_priv);
964
	if (ret < 0)
965
		goto err_bridge;
966 967

	intel_uncore_init(dev_priv);
968 969 970 971 972

	ret = intel_engines_init_mmio(dev_priv);
	if (ret)
		goto err_uncore;

973
	i915_gem_init_mmio(dev_priv);
974 975 976

	return 0;

977 978 979
err_uncore:
	intel_uncore_fini(dev_priv);
err_bridge:
980 981 982 983 984 985 986 987 988 989 990 991
	pci_dev_put(dev_priv->bridge_dev);

	return ret;
}

/**
 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 * @dev_priv: device private
 */
static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
{
	intel_uncore_fini(dev_priv);
992
	i915_mmio_cleanup(dev_priv);
993 994 995
	pci_dev_put(dev_priv->bridge_dev);
}

996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010
static void intel_sanitize_options(struct drm_i915_private *dev_priv)
{
	i915.enable_execlists =
		intel_sanitize_enable_execlists(dev_priv,
						i915.enable_execlists);

	/*
	 * i915.enable_ppgtt is read-only, so do an early pass to validate the
	 * user's requested state against the hardware/driver capabilities.  We
	 * do this now so that we can print out any log messages once rather
	 * than every time we check intel_enable_ppgtt().
	 */
	i915.enable_ppgtt =
		intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
	DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
1011 1012

	i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
1013
	DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
1014 1015

	intel_uc_sanitize_options(dev_priv);
1016 1017

	intel_gvt_sanitize_options(dev_priv);
1018 1019
}

1020 1021 1022 1023 1024 1025 1026 1027 1028
/**
 * i915_driver_init_hw - setup state requiring device access
 * @dev_priv: device private
 *
 * Setup state that requires accessing the device, but doesn't require
 * exposing the driver via kernel internal or userspace interfaces.
 */
static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
{
D
David Weinehall 已提交
1029
	struct pci_dev *pdev = dev_priv->drm.pdev;
1030 1031 1032 1033 1034
	int ret;

	if (i915_inject_load_failure())
		return -ENODEV;

1035 1036 1037
	intel_device_info_runtime_init(dev_priv);

	intel_sanitize_options(dev_priv);
1038

1039
	ret = i915_ggtt_probe_hw(dev_priv);
1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056
	if (ret)
		return ret;

	/* WARNING: Apparently we must kick fbdev drivers before vgacon,
	 * otherwise the vga fbdev driver falls over. */
	ret = i915_kick_out_firmware_fb(dev_priv);
	if (ret) {
		DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
		goto out_ggtt;
	}

	ret = i915_kick_out_vgacon(dev_priv);
	if (ret) {
		DRM_ERROR("failed to remove conflicting VGA console\n");
		goto out_ggtt;
	}

1057
	ret = i915_ggtt_init_hw(dev_priv);
1058 1059 1060
	if (ret)
		return ret;

1061
	ret = i915_ggtt_enable_hw(dev_priv);
1062 1063 1064 1065 1066
	if (ret) {
		DRM_ERROR("failed to enable GGTT\n");
		goto out_ggtt;
	}

D
David Weinehall 已提交
1067
	pci_set_master(pdev);
1068 1069

	/* overlay on gen2 is broken and can't address above 1G */
1070
	if (IS_GEN2(dev_priv)) {
D
David Weinehall 已提交
1071
		ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086
		if (ret) {
			DRM_ERROR("failed to set DMA mask\n");

			goto out_ggtt;
		}
	}

	/* 965GM sometimes incorrectly writes to hardware status page (HWS)
	 * using 32bit addressing, overwriting memory if HWS is located
	 * above 4GB.
	 *
	 * The documentation also mentions an issue with undefined
	 * behaviour if any general state is accessed within a page above 4GB,
	 * which also needs to be handled carefully.
	 */
1087
	if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
D
David Weinehall 已提交
1088
		ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116

		if (ret) {
			DRM_ERROR("failed to set DMA mask\n");

			goto out_ggtt;
		}
	}

	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
			   PM_QOS_DEFAULT_VALUE);

	intel_uncore_sanitize(dev_priv);

	intel_opregion_setup(dev_priv);

	i915_gem_load_init_fences(dev_priv);

	/* On the 945G/GM, the chipset reports the MSI capability on the
	 * integrated graphics even though the support isn't actually there
	 * according to the published specs.  It doesn't appear to function
	 * correctly in testing on 945G.
	 * This may be a side effect of MSI having been made available for PEG
	 * and the registers being closely associated.
	 *
	 * According to chipset errata, on the 965GM, MSI interrupts may
	 * be lost or delayed, but we use them anyways to avoid
	 * stuck interrupts on some machines.
	 */
1117
	if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
D
David Weinehall 已提交
1118
		if (pci_enable_msi(pdev) < 0)
1119 1120 1121
			DRM_DEBUG_DRIVER("can't enable MSI");
	}

1122 1123 1124 1125
	ret = intel_gvt_init(dev_priv);
	if (ret)
		goto out_ggtt;

1126 1127 1128
	return 0;

out_ggtt:
1129
	i915_ggtt_cleanup_hw(dev_priv);
1130 1131 1132 1133 1134 1135 1136 1137 1138 1139

	return ret;
}

/**
 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
 * @dev_priv: device private
 */
static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
{
D
David Weinehall 已提交
1140
	struct pci_dev *pdev = dev_priv->drm.pdev;
1141

D
David Weinehall 已提交
1142 1143
	if (pdev->msi_enabled)
		pci_disable_msi(pdev);
1144 1145

	pm_qos_remove_request(&dev_priv->pm_qos);
1146
	i915_ggtt_cleanup_hw(dev_priv);
1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157
}

/**
 * i915_driver_register - register the driver with the rest of the system
 * @dev_priv: device private
 *
 * Perform any steps necessary to make the driver available via kernel
 * internal or userspace interfaces.
 */
static void i915_driver_register(struct drm_i915_private *dev_priv)
{
1158
	struct drm_device *dev = &dev_priv->drm;
1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171

	i915_gem_shrinker_init(dev_priv);

	/*
	 * Notify a valid surface after modesetting,
	 * when running inside a VM.
	 */
	if (intel_vgpu_active(dev_priv))
		I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);

	/* Reveal our presence to userspace */
	if (drm_dev_register(dev, 0) == 0) {
		i915_debugfs_register(dev_priv);
1172
		i915_guc_log_register(dev_priv);
D
David Weinehall 已提交
1173
		i915_setup_sysfs(dev_priv);
1174 1175 1176

		/* Depends on sysfs having been initialized */
		i915_perf_register(dev_priv);
1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188
	} else
		DRM_ERROR("Failed to register driver for userspace access!\n");

	if (INTEL_INFO(dev_priv)->num_pipes) {
		/* Must be done after probing outputs */
		intel_opregion_register(dev_priv);
		acpi_video_register();
	}

	if (IS_GEN5(dev_priv))
		intel_gpu_ips_init(dev_priv);

1189
	intel_audio_init(dev_priv);
1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206

	/*
	 * Some ports require correctly set-up hpd registers for detection to
	 * work properly (leading to ghost connected connector status), e.g. VGA
	 * on gm45.  Hence we can only set up the initial fbdev config after hpd
	 * irqs are fully enabled. We do it last so that the async config
	 * cannot run before the connectors are registered.
	 */
	intel_fbdev_initial_config_async(dev);
}

/**
 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 * @dev_priv: device private
 */
static void i915_driver_unregister(struct drm_i915_private *dev_priv)
{
1207
	intel_audio_deinit(dev_priv);
1208 1209 1210 1211 1212

	intel_gpu_ips_teardown();
	acpi_video_unregister();
	intel_opregion_unregister(dev_priv);

1213 1214
	i915_perf_unregister(dev_priv);

D
David Weinehall 已提交
1215
	i915_teardown_sysfs(dev_priv);
1216
	i915_guc_log_unregister(dev_priv);
1217
	drm_dev_unregister(&dev_priv->drm);
1218 1219 1220 1221 1222 1223

	i915_gem_shrinker_cleanup(dev_priv);
}

/**
 * i915_driver_load - setup chip and create an initial config
1224 1225
 * @pdev: PCI device
 * @ent: matching PCI ID entry
1226 1227 1228 1229 1230 1231 1232
 *
 * The driver load routine has to do several things:
 *   - drive output discovery via intel_modeset_init()
 *   - initialize the memory manager
 *   - allocate initial config memory
 *   - setup the DRM framebuffer with the allocated memory
 */
1233
int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1234
{
1235 1236
	const struct intel_device_info *match_info =
		(struct intel_device_info *)ent->driver_data;
1237 1238
	struct drm_i915_private *dev_priv;
	int ret;
1239

1240 1241
	/* Enable nuclear pageflip on ILK+ */
	if (!i915.nuclear_pageflip && match_info->gen < 5)
1242
		driver.driver_features &= ~DRIVER_ATOMIC;
1243

1244 1245 1246 1247 1248
	ret = -ENOMEM;
	dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
	if (dev_priv)
		ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
	if (ret) {
1249
		DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1250
		goto out_free;
1251
	}
1252

1253 1254
	dev_priv->drm.pdev = pdev;
	dev_priv->drm.dev_private = dev_priv;
1255

1256 1257
	ret = pci_enable_device(pdev);
	if (ret)
1258
		goto out_fini;
D
Damien Lespiau 已提交
1259

1260
	pci_set_drvdata(pdev, &dev_priv->drm);
1261 1262 1263 1264 1265 1266 1267 1268 1269
	/*
	 * Disable the system suspend direct complete optimization, which can
	 * leave the device suspended skipping the driver's suspend handlers
	 * if the device was already runtime suspended. This is needed due to
	 * the difference in our runtime and system suspend sequence and
	 * becaue the HDA driver may require us to enable the audio power
	 * domain during system suspend.
	 */
	pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;
1270

1271 1272 1273
	ret = i915_driver_init_early(dev_priv, ent);
	if (ret < 0)
		goto out_pci_disable;
1274

1275
	intel_runtime_pm_get(dev_priv);
L
Linus Torvalds 已提交
1276

1277 1278 1279
	ret = i915_driver_init_mmio(dev_priv);
	if (ret < 0)
		goto out_runtime_pm_put;
J
Jesse Barnes 已提交
1280

1281 1282 1283
	ret = i915_driver_init_hw(dev_priv);
	if (ret < 0)
		goto out_cleanup_mmio;
1284 1285

	/*
1286 1287 1288
	 * TODO: move the vblank init and parts of modeset init steps into one
	 * of the i915_driver_init_/i915_driver_register functions according
	 * to the role/effect of the given init step.
1289
	 */
1290
	if (INTEL_INFO(dev_priv)->num_pipes) {
1291
		ret = drm_vblank_init(&dev_priv->drm,
1292 1293 1294
				      INTEL_INFO(dev_priv)->num_pipes);
		if (ret)
			goto out_cleanup_hw;
1295 1296
	}

1297
	ret = i915_load_modeset_init(&dev_priv->drm);
1298 1299 1300 1301 1302 1303 1304
	if (ret < 0)
		goto out_cleanup_vblank;

	i915_driver_register(dev_priv);

	intel_runtime_pm_enable(dev_priv);

M
Mahesh Kumar 已提交
1305 1306
	dev_priv->ipc_enabled = false;

1307 1308 1309 1310
	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
		DRM_INFO("DRM_I915_DEBUG enabled\n");
	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
		DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1311

1312 1313 1314 1315 1316
	intel_runtime_pm_put(dev_priv);

	return 0;

out_cleanup_vblank:
1317
	drm_vblank_cleanup(&dev_priv->drm);
1318 1319 1320 1321 1322 1323 1324 1325 1326
out_cleanup_hw:
	i915_driver_cleanup_hw(dev_priv);
out_cleanup_mmio:
	i915_driver_cleanup_mmio(dev_priv);
out_runtime_pm_put:
	intel_runtime_pm_put(dev_priv);
	i915_driver_cleanup_early(dev_priv);
out_pci_disable:
	pci_disable_device(pdev);
1327
out_fini:
1328
	i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1329 1330 1331
	drm_dev_fini(&dev_priv->drm);
out_free:
	kfree(dev_priv);
1332 1333 1334
	return ret;
}

1335
void i915_driver_unload(struct drm_device *dev)
1336
{
1337
	struct drm_i915_private *dev_priv = to_i915(dev);
D
David Weinehall 已提交
1338
	struct pci_dev *pdev = dev_priv->drm.pdev;
1339

1340 1341
	intel_fbdev_fini(dev);

1342
	if (i915_gem_suspend(dev_priv))
1343
		DRM_ERROR("failed to idle hardware; continuing to unload!\n");
B
Ben Widawsky 已提交
1344

1345 1346
	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);

1347
	drm_atomic_helper_shutdown(dev);
1348

1349 1350
	intel_gvt_cleanup(dev_priv);

1351 1352 1353 1354 1355 1356
	i915_driver_unregister(dev_priv);

	drm_vblank_cleanup(dev);

	intel_modeset_cleanup(dev);

1357
	/*
1358 1359
	 * free the memory space allocated for the child device
	 * config parsed from VBT
1360
	 */
1361 1362 1363 1364 1365 1366 1367 1368 1369
	if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
		kfree(dev_priv->vbt.child_dev);
		dev_priv->vbt.child_dev = NULL;
		dev_priv->vbt.child_dev_num = 0;
	}
	kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
	dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
	kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
	dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1370

D
David Weinehall 已提交
1371 1372
	vga_switcheroo_unregister_client(pdev);
	vga_client_register(pdev, NULL, NULL, NULL);
1373

1374
	intel_csr_ucode_fini(dev_priv);
1375

1376 1377
	/* Free error state after interrupts are fully disabled. */
	cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1378
	i915_reset_error_state(dev_priv);
1379 1380

	/* Flush any outstanding unpin_work. */
1381
	drain_workqueue(dev_priv->wq);
1382

1383
	i915_gem_fini(dev_priv);
1384
	intel_uc_fini_fw(dev_priv);
1385 1386 1387 1388 1389 1390 1391 1392
	intel_fbc_cleanup_cfb(dev_priv);

	intel_power_domains_fini(dev_priv);

	i915_driver_cleanup_hw(dev_priv);
	i915_driver_cleanup_mmio(dev_priv);

	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1393 1394 1395 1396 1397
}

static void i915_driver_release(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
1398 1399

	i915_driver_cleanup_early(dev_priv);
1400 1401 1402
	drm_dev_fini(&dev_priv->drm);

	kfree(dev_priv);
1403 1404
}

1405
static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1406
{
1407
	int ret;
1408

1409 1410 1411
	ret = i915_gem_open(dev, file);
	if (ret)
		return ret;
1412

1413 1414
	return 0;
}
1415

1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432
/**
 * i915_driver_lastclose - clean up after all DRM clients have exited
 * @dev: DRM device
 *
 * Take care of cleaning up after all DRM clients have exited.  In the
 * mode setting case, we want to restore the kernel's initial mode (just
 * in case the last client left us in a bad state).
 *
 * Additionally, in the non-mode setting case, we'll tear down the GTT
 * and DMA structures, since the kernel won't be using them, and clea
 * up any GEM state.
 */
static void i915_driver_lastclose(struct drm_device *dev)
{
	intel_fbdev_restore_mode(dev);
	vga_switcheroo_process_delayed_switch();
}
1433

1434
static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1435
{
1436 1437
	struct drm_i915_file_private *file_priv = file->driver_priv;

1438 1439 1440 1441 1442 1443
	mutex_lock(&dev->struct_mutex);
	i915_gem_context_close(dev, file);
	i915_gem_release(dev, file);
	mutex_unlock(&dev->struct_mutex);

	kfree(file_priv);
1444 1445
}

1446 1447
static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
{
1448
	struct drm_device *dev = &dev_priv->drm;
1449
	struct intel_encoder *encoder;
1450 1451

	drm_modeset_lock_all(dev);
1452 1453 1454
	for_each_intel_encoder(dev, encoder)
		if (encoder->suspend)
			encoder->suspend(encoder);
1455 1456 1457
	drm_modeset_unlock_all(dev);
}

1458 1459
static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
			      bool rpm_resume);
1460
static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1461

1462 1463 1464 1465 1466 1467 1468 1469
static bool suspend_to_idle(struct drm_i915_private *dev_priv)
{
#if IS_ENABLED(CONFIG_ACPI_SLEEP)
	if (acpi_target_system_state() < ACPI_STATE_S3)
		return true;
#endif
	return false;
}
1470

1471
static int i915_drm_suspend(struct drm_device *dev)
J
Jesse Barnes 已提交
1472
{
1473
	struct drm_i915_private *dev_priv = to_i915(dev);
D
David Weinehall 已提交
1474
	struct pci_dev *pdev = dev_priv->drm.pdev;
1475
	pci_power_t opregion_target_state;
1476
	int error;
1477

1478 1479 1480 1481 1482
	/* ignore lid events during suspend */
	mutex_lock(&dev_priv->modeset_restore_lock);
	dev_priv->modeset_restore = MODESET_SUSPENDED;
	mutex_unlock(&dev_priv->modeset_restore_lock);

1483 1484
	disable_rpm_wakeref_asserts(dev_priv);

1485 1486
	/* We do a lot of poking in a lot of registers, make sure they work
	 * properly. */
1487
	intel_display_set_init_power(dev_priv, true);
1488

1489 1490
	drm_kms_helper_poll_disable(dev);

D
David Weinehall 已提交
1491
	pci_save_state(pdev);
J
Jesse Barnes 已提交
1492

1493
	error = i915_gem_suspend(dev_priv);
1494
	if (error) {
D
David Weinehall 已提交
1495
		dev_err(&pdev->dev,
1496
			"GEM idle failed, resume might fail\n");
1497
		goto out;
1498
	}
1499

1500
	intel_display_suspend(dev);
1501

1502
	intel_dp_mst_suspend(dev);
1503

1504 1505
	intel_runtime_pm_disable_interrupts(dev_priv);
	intel_hpd_cancel_work(dev_priv);
1506

1507
	intel_suspend_encoders(dev_priv);
1508

1509
	intel_suspend_hw(dev_priv);
1510

1511
	i915_gem_suspend_gtt_mappings(dev_priv);
1512

1513
	i915_save_state(dev_priv);
1514

1515
	opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1516
	intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1517

1518
	intel_uncore_suspend(dev_priv);
1519
	intel_opregion_unregister(dev_priv);
1520

1521
	intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1522

1523 1524
	dev_priv->suspend_count++;

1525
	intel_csr_ucode_suspend(dev_priv);
1526

1527 1528 1529 1530
out:
	enable_rpm_wakeref_asserts(dev_priv);

	return error;
1531 1532
}

1533
static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1534
{
1535
	struct drm_i915_private *dev_priv = to_i915(dev);
D
David Weinehall 已提交
1536
	struct pci_dev *pdev = dev_priv->drm.pdev;
1537
	bool fw_csr;
1538 1539
	int ret;

1540 1541
	disable_rpm_wakeref_asserts(dev_priv);

1542 1543
	intel_display_set_init_power(dev_priv, false);

1544
	fw_csr = !IS_GEN9_LP(dev_priv) &&
1545
		suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1546 1547 1548 1549 1550 1551 1552 1553 1554
	/*
	 * In case of firmware assisted context save/restore don't manually
	 * deinit the power domains. This also means the CSR/DMC firmware will
	 * stay active, it will power down any HW resources as required and
	 * also enable deeper system power states that would be blocked if the
	 * firmware was inactive.
	 */
	if (!fw_csr)
		intel_power_domains_suspend(dev_priv);
1555

1556
	ret = 0;
1557
	if (IS_GEN9_LP(dev_priv))
1558
		bxt_enable_dc9(dev_priv);
1559
	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1560 1561 1562
		hsw_enable_pc8(dev_priv);
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
		ret = vlv_suspend_complete(dev_priv);
1563 1564 1565

	if (ret) {
		DRM_ERROR("Suspend complete failed: %d\n", ret);
1566 1567
		if (!fw_csr)
			intel_power_domains_init_hw(dev_priv, true);
1568

1569
		goto out;
1570 1571
	}

D
David Weinehall 已提交
1572
	pci_disable_device(pdev);
1573
	/*
1574
	 * During hibernation on some platforms the BIOS may try to access
1575 1576
	 * the device even though it's already in D3 and hang the machine. So
	 * leave the device in D0 on those platforms and hope the BIOS will
1577 1578 1579 1580 1581 1582 1583
	 * power down the device properly. The issue was seen on multiple old
	 * GENs with different BIOS vendors, so having an explicit blacklist
	 * is inpractical; apply the workaround on everything pre GEN6. The
	 * platforms where the issue was seen:
	 * Lenovo Thinkpad X301, X61s, X60, T60, X41
	 * Fujitsu FSC S7110
	 * Acer Aspire 1830T
1584
	 */
1585
	if (!(hibernation && INTEL_GEN(dev_priv) < 6))
D
David Weinehall 已提交
1586
		pci_set_power_state(pdev, PCI_D3hot);
1587

1588 1589
	dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);

1590 1591 1592 1593
out:
	enable_rpm_wakeref_asserts(dev_priv);

	return ret;
1594 1595
}

1596
static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1597 1598 1599
{
	int error;

1600
	if (!dev) {
1601 1602 1603 1604 1605
		DRM_ERROR("dev: %p\n", dev);
		DRM_ERROR("DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}

1606 1607 1608
	if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
			 state.event != PM_EVENT_FREEZE))
		return -EINVAL;
1609 1610 1611

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
1612

1613
	error = i915_drm_suspend(dev);
1614 1615 1616
	if (error)
		return error;

1617
	return i915_drm_suspend_late(dev, false);
J
Jesse Barnes 已提交
1618 1619
}

1620
static int i915_drm_resume(struct drm_device *dev)
1621
{
1622
	struct drm_i915_private *dev_priv = to_i915(dev);
1623
	int ret;
1624

1625
	disable_rpm_wakeref_asserts(dev_priv);
1626
	intel_sanitize_gt_powersave(dev_priv);
1627

1628
	ret = i915_ggtt_enable_hw(dev_priv);
1629 1630 1631
	if (ret)
		DRM_ERROR("failed to re-enable GGTT\n");

1632 1633
	intel_csr_ucode_resume(dev_priv);

1634
	i915_gem_resume(dev_priv);
1635

1636
	i915_restore_state(dev_priv);
1637
	intel_pps_unlock_regs_wa(dev_priv);
1638
	intel_opregion_setup(dev_priv);
1639

1640
	intel_init_pch_refclk(dev_priv);
1641

1642 1643 1644 1645 1646
	/*
	 * Interrupts have to be enabled before any batches are run. If not the
	 * GPU will hang. i915_gem_init_hw() will initiate batches to
	 * update/restore the context.
	 *
1647 1648
	 * drm_mode_config_reset() needs AUX interrupts.
	 *
1649 1650 1651 1652 1653
	 * Modeset enabling in intel_modeset_init_hw() also needs working
	 * interrupts.
	 */
	intel_runtime_pm_enable_interrupts(dev_priv);

1654 1655
	drm_mode_config_reset(dev);

1656
	mutex_lock(&dev->struct_mutex);
1657
	if (i915_gem_init_hw(dev_priv)) {
1658
		DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1659
		i915_gem_set_wedged(dev_priv);
1660 1661
	}
	mutex_unlock(&dev->struct_mutex);
1662

1663
	intel_guc_resume(dev_priv);
1664

1665
	intel_modeset_init_hw(dev);
1666

1667 1668
	spin_lock_irq(&dev_priv->irq_lock);
	if (dev_priv->display.hpd_irq_setup)
1669
		dev_priv->display.hpd_irq_setup(dev_priv);
1670
	spin_unlock_irq(&dev_priv->irq_lock);
1671

1672
	intel_dp_mst_resume(dev);
1673

1674 1675
	intel_display_resume(dev);

1676 1677
	drm_kms_helper_poll_enable(dev);

1678 1679 1680 1681 1682 1683 1684
	/*
	 * ... but also need to make sure that hotplug processing
	 * doesn't cause havoc. Like in the driver load code we don't
	 * bother with the tiny race here where we might loose hotplug
	 * notifications.
	 * */
	intel_hpd_init(dev_priv);
1685

1686
	intel_opregion_register(dev_priv);
1687

1688
	intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1689

1690 1691 1692
	mutex_lock(&dev_priv->modeset_restore_lock);
	dev_priv->modeset_restore = MODESET_DONE;
	mutex_unlock(&dev_priv->modeset_restore_lock);
1693

1694
	intel_opregion_notify_adapter(dev_priv, PCI_D0);
1695

1696
	intel_autoenable_gt_powersave(dev_priv);
1697

1698 1699
	enable_rpm_wakeref_asserts(dev_priv);

1700
	return 0;
1701 1702
}

1703
static int i915_drm_resume_early(struct drm_device *dev)
1704
{
1705
	struct drm_i915_private *dev_priv = to_i915(dev);
D
David Weinehall 已提交
1706
	struct pci_dev *pdev = dev_priv->drm.pdev;
1707
	int ret;
1708

1709 1710 1711 1712 1713 1714 1715 1716 1717
	/*
	 * We have a resume ordering issue with the snd-hda driver also
	 * requiring our device to be power up. Due to the lack of a
	 * parent/child relationship we currently solve this with an early
	 * resume hook.
	 *
	 * FIXME: This should be solved with a special hdmi sink device or
	 * similar so that power domains can be employed.
	 */
1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728

	/*
	 * Note that we need to set the power state explicitly, since we
	 * powered off the device during freeze and the PCI core won't power
	 * it back up for us during thaw. Powering off the device during
	 * freeze is not a hard requirement though, and during the
	 * suspend/resume phases the PCI core makes sure we get here with the
	 * device powered on. So in case we change our freeze logic and keep
	 * the device powered we can also remove the following set power state
	 * call.
	 */
D
David Weinehall 已提交
1729
	ret = pci_set_power_state(pdev, PCI_D0);
1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747
	if (ret) {
		DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
		goto out;
	}

	/*
	 * Note that pci_enable_device() first enables any parent bridge
	 * device and only then sets the power state for this device. The
	 * bridge enabling is a nop though, since bridge devices are resumed
	 * first. The order of enabling power and enabling the device is
	 * imposed by the PCI core as described above, so here we preserve the
	 * same order for the freeze/thaw phases.
	 *
	 * TODO: eventually we should remove pci_disable_device() /
	 * pci_enable_enable_device() from suspend/resume. Due to how they
	 * depend on the device enable refcount we can't anyway depend on them
	 * disabling/enabling the device.
	 */
D
David Weinehall 已提交
1748
	if (pci_enable_device(pdev)) {
1749 1750 1751
		ret = -EIO;
		goto out;
	}
1752

D
David Weinehall 已提交
1753
	pci_set_master(pdev);
1754

1755 1756
	disable_rpm_wakeref_asserts(dev_priv);

1757
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1758
		ret = vlv_resume_prepare(dev_priv, false);
1759
	if (ret)
1760 1761
		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
			  ret);
1762

1763
	intel_uncore_resume_early(dev_priv);
1764

1765
	if (IS_GEN9_LP(dev_priv)) {
1766 1767
		if (!dev_priv->suspended_to_idle)
			gen9_sanitize_dc_state(dev_priv);
1768
		bxt_disable_dc9(dev_priv);
1769
	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1770
		hsw_disable_pc8(dev_priv);
1771
	}
1772

1773
	intel_uncore_sanitize(dev_priv);
1774

1775
	if (IS_GEN9_LP(dev_priv) ||
1776
	    !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1777 1778
		intel_power_domains_init_hw(dev_priv, true);

1779 1780
	i915_gem_sanitize(dev_priv);

1781 1782
	enable_rpm_wakeref_asserts(dev_priv);

1783 1784
out:
	dev_priv->suspended_to_idle = false;
1785 1786

	return ret;
1787 1788
}

1789
static int i915_resume_switcheroo(struct drm_device *dev)
1790
{
1791
	int ret;
1792

1793 1794 1795
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

1796
	ret = i915_drm_resume_early(dev);
1797 1798 1799
	if (ret)
		return ret;

1800 1801 1802
	return i915_drm_resume(dev);
}

1803
/**
1804
 * i915_reset - reset chip after a hang
1805
 * @dev_priv: device private to reset
1806
 *
1807 1808
 * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
 * on failure.
1809
 *
1810 1811
 * Caller must hold the struct_mutex.
 *
1812 1813 1814 1815 1816 1817 1818 1819
 * Procedure is fairly simple:
 *   - reset the chip using the reset reg
 *   - re-init context state
 *   - re-init hardware status page
 *   - re-init ring buffer
 *   - re-init interrupt state
 *   - re-init display
 */
1820
void i915_reset(struct drm_i915_private *dev_priv)
1821
{
1822
	struct i915_gpu_error *error = &dev_priv->gpu_error;
1823
	int ret;
1824

1825
	lockdep_assert_held(&dev_priv->drm.struct_mutex);
1826
	GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1827

1828
	if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1829
		return;
1830

1831
	/* Clear any previous failed attempts at recovery. Time to try again. */
1832 1833 1834
	if (!i915_gem_unset_wedged(dev_priv))
		goto wakeup;

1835
	error->reset_count++;
1836

1837
	pr_notice("drm/i915: Resetting chip after gpu hang\n");
1838
	disable_irq(dev_priv->drm.irq);
1839 1840 1841 1842 1843 1844
	ret = i915_gem_reset_prepare(dev_priv);
	if (ret) {
		DRM_ERROR("GPU recovery failed\n");
		intel_gpu_reset(dev_priv, ALL_ENGINES);
		goto error;
	}
1845

1846
	ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1847
	if (ret) {
1848 1849 1850 1851
		if (ret != -ENODEV)
			DRM_ERROR("Failed to reset chip: %i\n", ret);
		else
			DRM_DEBUG_DRIVER("GPU reset disabled\n");
1852
		goto error;
1853 1854
	}

1855
	i915_gem_reset(dev_priv);
1856 1857
	intel_overlay_reset(dev_priv);

1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871
	/* Ok, now get things going again... */

	/*
	 * Everything depends on having the GTT running, so we need to start
	 * there.  Fortunately we don't need to do this unless we reset the
	 * chip at a PCI level.
	 *
	 * Next we need to restore the context, but we don't use those
	 * yet either...
	 *
	 * Ring buffer needs to be re-initialized in the KMS case, or if X
	 * was running at the time of the reset (i.e. we weren't VT
	 * switched away).
	 */
1872
	ret = i915_gem_init_hw(dev_priv);
1873 1874
	if (ret) {
		DRM_ERROR("Failed hw init on reset %d\n", ret);
1875
		goto error;
1876 1877
	}

1878 1879
	i915_queue_hangcheck(dev_priv);

1880
finish:
1881
	i915_gem_reset_finish(dev_priv);
1882
	enable_irq(dev_priv->drm.irq);
1883

1884
wakeup:
1885 1886
	clear_bit(I915_RESET_HANDOFF, &error->flags);
	wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1887
	return;
1888 1889

error:
1890
	i915_gem_set_wedged(dev_priv);
1891
	goto finish;
1892 1893
}

1894
static int i915_pm_suspend(struct device *kdev)
1895
{
1896 1897
	struct pci_dev *pdev = to_pci_dev(kdev);
	struct drm_device *dev = pci_get_drvdata(pdev);
1898

1899 1900
	if (!dev) {
		dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1901 1902
		return -ENODEV;
	}
1903

1904
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1905 1906
		return 0;

1907
	return i915_drm_suspend(dev);
1908 1909
}

1910
static int i915_pm_suspend_late(struct device *kdev)
1911
{
1912
	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1913 1914

	/*
D
Damien Lespiau 已提交
1915
	 * We have a suspend ordering issue with the snd-hda driver also
1916 1917 1918 1919 1920 1921 1922
	 * requiring our device to be power up. Due to the lack of a
	 * parent/child relationship we currently solve this with an late
	 * suspend hook.
	 *
	 * FIXME: This should be solved with a special hdmi sink device or
	 * similar so that power domains can be employed.
	 */
1923
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1924
		return 0;
1925

1926
	return i915_drm_suspend_late(dev, false);
1927 1928
}

1929
static int i915_pm_poweroff_late(struct device *kdev)
1930
{
1931
	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1932

1933
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1934 1935
		return 0;

1936
	return i915_drm_suspend_late(dev, true);
1937 1938
}

1939
static int i915_pm_resume_early(struct device *kdev)
1940
{
1941
	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1942

1943
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1944 1945
		return 0;

1946
	return i915_drm_resume_early(dev);
1947 1948
}

1949
static int i915_pm_resume(struct device *kdev)
1950
{
1951
	struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1952

1953
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1954 1955
		return 0;

1956
	return i915_drm_resume(dev);
1957 1958
}

1959
/* freeze: before creating the hibernation_image */
1960
static int i915_pm_freeze(struct device *kdev)
1961
{
1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972
	int ret;

	ret = i915_pm_suspend(kdev);
	if (ret)
		return ret;

	ret = i915_gem_freeze(kdev_to_i915(kdev));
	if (ret)
		return ret;

	return 0;
1973 1974
}

1975
static int i915_pm_freeze_late(struct device *kdev)
1976
{
1977 1978
	int ret;

1979
	ret = i915_pm_suspend_late(kdev);
1980 1981 1982
	if (ret)
		return ret;

1983
	ret = i915_gem_freeze_late(kdev_to_i915(kdev));
1984 1985 1986 1987
	if (ret)
		return ret;

	return 0;
1988 1989 1990
}

/* thaw: called after creating the hibernation image, but before turning off. */
1991
static int i915_pm_thaw_early(struct device *kdev)
1992
{
1993
	return i915_pm_resume_early(kdev);
1994 1995
}

1996
static int i915_pm_thaw(struct device *kdev)
1997
{
1998
	return i915_pm_resume(kdev);
1999 2000 2001
}

/* restore: called after loading the hibernation image. */
2002
static int i915_pm_restore_early(struct device *kdev)
2003
{
2004
	return i915_pm_resume_early(kdev);
2005 2006
}

2007
static int i915_pm_restore(struct device *kdev)
2008
{
2009
	return i915_pm_resume(kdev);
2010 2011
}

2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050
/*
 * Save all Gunit registers that may be lost after a D3 and a subsequent
 * S0i[R123] transition. The list of registers needing a save/restore is
 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
 * registers in the following way:
 * - Driver: saved/restored by the driver
 * - Punit : saved/restored by the Punit firmware
 * - No, w/o marking: no need to save/restore, since the register is R/O or
 *                    used internally by the HW in a way that doesn't depend
 *                    keeping the content across a suspend/resume.
 * - Debug : used for debugging
 *
 * We save/restore all registers marked with 'Driver', with the following
 * exceptions:
 * - Registers out of use, including also registers marked with 'Debug'.
 *   These have no effect on the driver's operation, so we don't save/restore
 *   them to reduce the overhead.
 * - Registers that are fully setup by an initialization function called from
 *   the resume path. For example many clock gating and RPS/RC6 registers.
 * - Registers that provide the right functionality with their reset defaults.
 *
 * TODO: Except for registers that based on the above 3 criteria can be safely
 * ignored, we save/restore all others, practically treating the HW context as
 * a black-box for the driver. Further investigation is needed to reduce the
 * saved/restored registers even further, by following the same 3 criteria.
 */
static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
{
	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
	int i;

	/* GAM 0x4000-0x4770 */
	s->wr_watermark		= I915_READ(GEN7_WR_WATERMARK);
	s->gfx_prio_ctrl	= I915_READ(GEN7_GFX_PRIO_CTRL);
	s->arb_mode		= I915_READ(ARB_MODE);
	s->gfx_pend_tlb0	= I915_READ(GEN7_GFX_PEND_TLB0);
	s->gfx_pend_tlb1	= I915_READ(GEN7_GFX_PEND_TLB1);

	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2051
		s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2052 2053

	s->media_max_req_count	= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2054
	s->gfx_max_req_count	= I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094

	s->render_hwsp		= I915_READ(RENDER_HWS_PGA_GEN7);
	s->ecochk		= I915_READ(GAM_ECOCHK);
	s->bsd_hwsp		= I915_READ(BSD_HWS_PGA_GEN7);
	s->blt_hwsp		= I915_READ(BLT_HWS_PGA_GEN7);

	s->tlb_rd_addr		= I915_READ(GEN7_TLB_RD_ADDR);

	/* MBC 0x9024-0x91D0, 0x8500 */
	s->g3dctl		= I915_READ(VLV_G3DCTL);
	s->gsckgctl		= I915_READ(VLV_GSCKGCTL);
	s->mbctl		= I915_READ(GEN6_MBCTL);

	/* GCP 0x9400-0x9424, 0x8100-0x810C */
	s->ucgctl1		= I915_READ(GEN6_UCGCTL1);
	s->ucgctl3		= I915_READ(GEN6_UCGCTL3);
	s->rcgctl1		= I915_READ(GEN6_RCGCTL1);
	s->rcgctl2		= I915_READ(GEN6_RCGCTL2);
	s->rstctl		= I915_READ(GEN6_RSTCTL);
	s->misccpctl		= I915_READ(GEN7_MISCCPCTL);

	/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
	s->gfxpause		= I915_READ(GEN6_GFXPAUSE);
	s->rpdeuhwtc		= I915_READ(GEN6_RPDEUHWTC);
	s->rpdeuc		= I915_READ(GEN6_RPDEUC);
	s->ecobus		= I915_READ(ECOBUS);
	s->pwrdwnupctl		= I915_READ(VLV_PWRDWNUPCTL);
	s->rp_down_timeout	= I915_READ(GEN6_RP_DOWN_TIMEOUT);
	s->rp_deucsw		= I915_READ(GEN6_RPDEUCSW);
	s->rcubmabdtmr		= I915_READ(GEN6_RCUBMABDTMR);
	s->rcedata		= I915_READ(VLV_RCEDATA);
	s->spare2gh		= I915_READ(VLV_SPAREG2H);

	/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
	s->gt_imr		= I915_READ(GTIMR);
	s->gt_ier		= I915_READ(GTIER);
	s->pm_imr		= I915_READ(GEN6_PMIMR);
	s->pm_ier		= I915_READ(GEN6_PMIER);

	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2095
		s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106

	/* GT SA CZ domain, 0x100000-0x138124 */
	s->tilectl		= I915_READ(TILECTL);
	s->gt_fifoctl		= I915_READ(GTFIFOCTL);
	s->gtlc_wake_ctrl	= I915_READ(VLV_GTLC_WAKE_CTRL);
	s->gtlc_survive		= I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	s->pmwgicz		= I915_READ(VLV_PMWGICZ);

	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
	s->gu_ctl0		= I915_READ(VLV_GU_CTL0);
	s->gu_ctl1		= I915_READ(VLV_GU_CTL1);
2107
	s->pcbr			= I915_READ(VLV_PCBR);
2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132
	s->clock_gate_dis2	= I915_READ(VLV_GUNIT_CLOCK_GATE2);

	/*
	 * Not saving any of:
	 * DFT,		0x9800-0x9EC0
	 * SARB,	0xB000-0xB1FC
	 * GAC,		0x5208-0x524C, 0x14000-0x14C000
	 * PCI CFG
	 */
}

static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
{
	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
	u32 val;
	int i;

	/* GAM 0x4000-0x4770 */
	I915_WRITE(GEN7_WR_WATERMARK,	s->wr_watermark);
	I915_WRITE(GEN7_GFX_PRIO_CTRL,	s->gfx_prio_ctrl);
	I915_WRITE(ARB_MODE,		s->arb_mode | (0xffff << 16));
	I915_WRITE(GEN7_GFX_PEND_TLB0,	s->gfx_pend_tlb0);
	I915_WRITE(GEN7_GFX_PEND_TLB1,	s->gfx_pend_tlb1);

	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2133
		I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2134 2135

	I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2136
	I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176

	I915_WRITE(RENDER_HWS_PGA_GEN7,	s->render_hwsp);
	I915_WRITE(GAM_ECOCHK,		s->ecochk);
	I915_WRITE(BSD_HWS_PGA_GEN7,	s->bsd_hwsp);
	I915_WRITE(BLT_HWS_PGA_GEN7,	s->blt_hwsp);

	I915_WRITE(GEN7_TLB_RD_ADDR,	s->tlb_rd_addr);

	/* MBC 0x9024-0x91D0, 0x8500 */
	I915_WRITE(VLV_G3DCTL,		s->g3dctl);
	I915_WRITE(VLV_GSCKGCTL,	s->gsckgctl);
	I915_WRITE(GEN6_MBCTL,		s->mbctl);

	/* GCP 0x9400-0x9424, 0x8100-0x810C */
	I915_WRITE(GEN6_UCGCTL1,	s->ucgctl1);
	I915_WRITE(GEN6_UCGCTL3,	s->ucgctl3);
	I915_WRITE(GEN6_RCGCTL1,	s->rcgctl1);
	I915_WRITE(GEN6_RCGCTL2,	s->rcgctl2);
	I915_WRITE(GEN6_RSTCTL,		s->rstctl);
	I915_WRITE(GEN7_MISCCPCTL,	s->misccpctl);

	/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
	I915_WRITE(GEN6_GFXPAUSE,	s->gfxpause);
	I915_WRITE(GEN6_RPDEUHWTC,	s->rpdeuhwtc);
	I915_WRITE(GEN6_RPDEUC,		s->rpdeuc);
	I915_WRITE(ECOBUS,		s->ecobus);
	I915_WRITE(VLV_PWRDWNUPCTL,	s->pwrdwnupctl);
	I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
	I915_WRITE(GEN6_RPDEUCSW,	s->rp_deucsw);
	I915_WRITE(GEN6_RCUBMABDTMR,	s->rcubmabdtmr);
	I915_WRITE(VLV_RCEDATA,		s->rcedata);
	I915_WRITE(VLV_SPAREG2H,	s->spare2gh);

	/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
	I915_WRITE(GTIMR,		s->gt_imr);
	I915_WRITE(GTIER,		s->gt_ier);
	I915_WRITE(GEN6_PMIMR,		s->pm_imr);
	I915_WRITE(GEN6_PMIER,		s->pm_ier);

	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2177
		I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201

	/* GT SA CZ domain, 0x100000-0x138124 */
	I915_WRITE(TILECTL,			s->tilectl);
	I915_WRITE(GTFIFOCTL,			s->gt_fifoctl);
	/*
	 * Preserve the GT allow wake and GFX force clock bit, they are not
	 * be restored, as they are used to control the s0ix suspend/resume
	 * sequence by the caller.
	 */
	val = I915_READ(VLV_GTLC_WAKE_CTRL);
	val &= VLV_GTLC_ALLOWWAKEREQ;
	val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
	I915_WRITE(VLV_GTLC_WAKE_CTRL, val);

	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	val &= VLV_GFX_CLK_FORCE_ON_BIT;
	val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);

	I915_WRITE(VLV_PMWGICZ,			s->pmwgicz);

	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
	I915_WRITE(VLV_GU_CTL0,			s->gu_ctl0);
	I915_WRITE(VLV_GU_CTL1,			s->gu_ctl1);
2202
	I915_WRITE(VLV_PCBR,			s->pcbr);
2203 2204 2205
	I915_WRITE(VLV_GUNIT_CLOCK_GATE2,	s->clock_gate_dis2);
}

2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219
static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
				  u32 mask, u32 val)
{
	/* The HW does not like us polling for PW_STATUS frequently, so
	 * use the sleeping loop rather than risk the busy spin within
	 * intel_wait_for_register().
	 *
	 * Transitioning between RC6 states should be at most 2ms (see
	 * valleyview_enable_rps) so use a 3ms timeout.
	 */
	return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
			3);
}

2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
{
	u32 val;
	int err;

	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
	if (force_on)
		val |= VLV_GFX_CLK_FORCE_ON_BIT;
	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);

	if (!force_on)
		return 0;

2234 2235 2236 2237 2238
	err = intel_wait_for_register(dev_priv,
				      VLV_GTLC_SURVIVABILITY_REG,
				      VLV_GFX_CLK_STATUS_BIT,
				      VLV_GFX_CLK_STATUS_BIT,
				      20);
2239 2240 2241 2242 2243 2244 2245
	if (err)
		DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
			  I915_READ(VLV_GTLC_SURVIVABILITY_REG));

	return err;
}

2246 2247
static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
{
2248
	u32 mask;
2249
	u32 val;
2250
	int err;
2251 2252 2253 2254 2255 2256 2257 2258

	val = I915_READ(VLV_GTLC_WAKE_CTRL);
	val &= ~VLV_GTLC_ALLOWWAKEREQ;
	if (allow)
		val |= VLV_GTLC_ALLOWWAKEREQ;
	I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
	POSTING_READ(VLV_GTLC_WAKE_CTRL);

2259 2260 2261 2262
	mask = VLV_GTLC_ALLOWWAKEACK;
	val = allow ? mask : 0;

	err = vlv_wait_for_pw_status(dev_priv, mask, val);
2263 2264
	if (err)
		DRM_ERROR("timeout disabling GT waking\n");
2265

2266 2267 2268
	return err;
}

2269 2270
static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
				  bool wait_for_on)
2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281
{
	u32 mask;
	u32 val;

	mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
	val = wait_for_on ? mask : 0;

	/*
	 * RC6 transitioning can be delayed up to 2 msec (see
	 * valleyview_enable_rps), use 3 msec for safety.
	 */
2282
	if (vlv_wait_for_pw_status(dev_priv, mask, val))
2283
		DRM_ERROR("timeout waiting for GT wells to go %s\n",
2284
			  onoff(wait_for_on));
2285 2286 2287 2288 2289 2290 2291
}

static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
{
	if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
		return;

2292
	DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2293 2294 2295
	I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
}

2296
static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2297 2298 2299 2300 2301 2302 2303 2304
{
	u32 mask;
	int err;

	/*
	 * Bspec defines the following GT well on flags as debug only, so
	 * don't treat them as hard failures.
	 */
2305
	vlv_wait_for_gt_wells(dev_priv, false);
2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318

	mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
	WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);

	vlv_check_no_gt_access(dev_priv);

	err = vlv_force_gfx_clock(dev_priv, true);
	if (err)
		goto err1;

	err = vlv_allow_gt_wake(dev_priv, false);
	if (err)
		goto err2;
2319

2320
	if (!IS_CHERRYVIEW(dev_priv))
2321
		vlv_save_gunit_s0ix_state(dev_priv);
2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337

	err = vlv_force_gfx_clock(dev_priv, false);
	if (err)
		goto err2;

	return 0;

err2:
	/* For safety always re-enable waking and disable gfx clock forcing */
	vlv_allow_gt_wake(dev_priv, true);
err1:
	vlv_force_gfx_clock(dev_priv, false);

	return err;
}

2338 2339
static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
				bool rpm_resume)
2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350
{
	int err;
	int ret;

	/*
	 * If any of the steps fail just try to continue, that's the best we
	 * can do at this point. Return the first error code (which will also
	 * leave RPM permanently disabled).
	 */
	ret = vlv_force_gfx_clock(dev_priv, true);

2351
	if (!IS_CHERRYVIEW(dev_priv))
2352
		vlv_restore_gunit_s0ix_state(dev_priv);
2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363

	err = vlv_allow_gt_wake(dev_priv, true);
	if (!ret)
		ret = err;

	err = vlv_force_gfx_clock(dev_priv, false);
	if (!ret)
		ret = err;

	vlv_check_no_gt_access(dev_priv);

2364
	if (rpm_resume)
2365
		intel_init_clock_gating(dev_priv);
2366 2367 2368 2369

	return ret;
}

2370
static int intel_runtime_suspend(struct device *kdev)
2371
{
2372
	struct pci_dev *pdev = to_pci_dev(kdev);
2373
	struct drm_device *dev = pci_get_drvdata(pdev);
2374
	struct drm_i915_private *dev_priv = to_i915(dev);
2375
	int ret;
2376

2377
	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2378 2379
		return -ENODEV;

2380
	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2381 2382
		return -ENODEV;

2383 2384
	DRM_DEBUG_KMS("Suspending device\n");

2385 2386
	disable_rpm_wakeref_asserts(dev_priv);

2387 2388 2389 2390
	/*
	 * We are safe here against re-faults, since the fault handler takes
	 * an RPM reference.
	 */
2391
	i915_gem_runtime_suspend(dev_priv);
2392

2393
	intel_guc_suspend(dev_priv);
2394

2395
	intel_runtime_pm_disable_interrupts(dev_priv);
2396

2397
	ret = 0;
2398
	if (IS_GEN9_LP(dev_priv)) {
2399 2400 2401 2402 2403 2404 2405 2406
		bxt_display_core_uninit(dev_priv);
		bxt_enable_dc9(dev_priv);
	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
		hsw_enable_pc8(dev_priv);
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
		ret = vlv_suspend_complete(dev_priv);
	}

2407 2408
	if (ret) {
		DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2409
		intel_runtime_pm_enable_interrupts(dev_priv);
2410

2411 2412
		enable_rpm_wakeref_asserts(dev_priv);

2413 2414
		return ret;
	}
2415

2416
	intel_uncore_suspend(dev_priv);
2417 2418 2419

	enable_rpm_wakeref_asserts(dev_priv);
	WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2420

2421
	if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2422 2423
		DRM_ERROR("Unclaimed access detected prior to suspending\n");

2424
	dev_priv->pm.suspended = true;
2425 2426

	/*
2427 2428
	 * FIXME: We really should find a document that references the arguments
	 * used below!
2429
	 */
2430
	if (IS_BROADWELL(dev_priv)) {
2431 2432 2433 2434 2435 2436
		/*
		 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
		 * being detected, and the call we do at intel_runtime_resume()
		 * won't be able to restore them. Since PCI_D3hot matches the
		 * actual specification and appears to be working, use it.
		 */
2437
		intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2438
	} else {
2439 2440 2441 2442 2443 2444 2445
		/*
		 * current versions of firmware which depend on this opregion
		 * notification have repurposed the D1 definition to mean
		 * "runtime suspended" vs. what you would normally expect (D3)
		 * to distinguish it from notifications that might be sent via
		 * the suspend path.
		 */
2446
		intel_opregion_notify_adapter(dev_priv, PCI_D1);
2447
	}
2448

2449
	assert_forcewakes_inactive(dev_priv);
2450

2451
	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2452 2453
		intel_hpd_poll_init(dev_priv);

2454
	DRM_DEBUG_KMS("Device suspended\n");
2455 2456 2457
	return 0;
}

2458
static int intel_runtime_resume(struct device *kdev)
2459
{
2460
	struct pci_dev *pdev = to_pci_dev(kdev);
2461
	struct drm_device *dev = pci_get_drvdata(pdev);
2462
	struct drm_i915_private *dev_priv = to_i915(dev);
2463
	int ret = 0;
2464

2465
	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2466
		return -ENODEV;
2467 2468 2469

	DRM_DEBUG_KMS("Resuming device\n");

2470 2471 2472
	WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
	disable_rpm_wakeref_asserts(dev_priv);

2473
	intel_opregion_notify_adapter(dev_priv, PCI_D0);
2474
	dev_priv->pm.suspended = false;
2475 2476
	if (intel_uncore_unclaimed_mmio(dev_priv))
		DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2477

2478
	intel_guc_resume(dev_priv);
2479

2480
	if (IS_GEN9_LP(dev_priv)) {
2481 2482
		bxt_disable_dc9(dev_priv);
		bxt_display_core_init(dev_priv, true);
2483 2484 2485
		if (dev_priv->csr.dmc_payload &&
		    (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
			gen9_enable_dc5(dev_priv);
2486
	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2487
		hsw_disable_pc8(dev_priv);
2488
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2489
		ret = vlv_resume_prepare(dev_priv, true);
2490
	}
2491

2492 2493 2494 2495
	/*
	 * No point of rolling back things in case of an error, as the best
	 * we can do is to hope that things will still work (and disable RPM).
	 */
2496
	i915_gem_init_swizzling(dev_priv);
2497
	i915_gem_restore_fences(dev_priv);
2498

2499
	intel_runtime_pm_enable_interrupts(dev_priv);
2500 2501 2502 2503 2504 2505

	/*
	 * On VLV/CHV display interrupts are part of the display
	 * power well, so hpd is reinitialized from there. For
	 * everyone else do it here.
	 */
2506
	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2507 2508
		intel_hpd_init(dev_priv);

2509 2510
	enable_rpm_wakeref_asserts(dev_priv);

2511 2512 2513 2514 2515 2516
	if (ret)
		DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
	else
		DRM_DEBUG_KMS("Device resumed\n");

	return ret;
2517 2518
}

2519
const struct dev_pm_ops i915_pm_ops = {
2520 2521 2522 2523
	/*
	 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
	 * PMSG_RESUME]
	 */
2524
	.suspend = i915_pm_suspend,
2525 2526
	.suspend_late = i915_pm_suspend_late,
	.resume_early = i915_pm_resume_early,
2527
	.resume = i915_pm_resume,
2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543

	/*
	 * S4 event handlers
	 * @freeze, @freeze_late    : called (1) before creating the
	 *                            hibernation image [PMSG_FREEZE] and
	 *                            (2) after rebooting, before restoring
	 *                            the image [PMSG_QUIESCE]
	 * @thaw, @thaw_early       : called (1) after creating the hibernation
	 *                            image, before writing it [PMSG_THAW]
	 *                            and (2) after failing to create or
	 *                            restore the image [PMSG_RECOVER]
	 * @poweroff, @poweroff_late: called after writing the hibernation
	 *                            image, before rebooting [PMSG_HIBERNATE]
	 * @restore, @restore_early : called after rebooting and restoring the
	 *                            hibernation image [PMSG_RESTORE]
	 */
2544 2545 2546 2547
	.freeze = i915_pm_freeze,
	.freeze_late = i915_pm_freeze_late,
	.thaw_early = i915_pm_thaw_early,
	.thaw = i915_pm_thaw,
2548
	.poweroff = i915_pm_suspend,
2549
	.poweroff_late = i915_pm_poweroff_late,
2550 2551
	.restore_early = i915_pm_restore_early,
	.restore = i915_pm_restore,
2552 2553

	/* S0ix (via runtime suspend) event handlers */
2554 2555
	.runtime_suspend = intel_runtime_suspend,
	.runtime_resume = intel_runtime_resume,
2556 2557
};

2558
static const struct vm_operations_struct i915_gem_vm_ops = {
2559
	.fault = i915_gem_fault,
2560 2561
	.open = drm_gem_vm_open,
	.close = drm_gem_vm_close,
2562 2563
};

2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575
static const struct file_operations i915_driver_fops = {
	.owner = THIS_MODULE,
	.open = drm_open,
	.release = drm_release,
	.unlocked_ioctl = drm_ioctl,
	.mmap = drm_gem_mmap,
	.poll = drm_poll,
	.read = drm_read,
	.compat_ioctl = i915_compat_ioctl,
	.llseek = noop_llseek,
};

2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602
static int
i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file)
{
	return -ENODEV;
}

static const struct drm_ioctl_desc i915_ioctls[] = {
	DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2603
	DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618
	DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2619 2620
	DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635
	DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
	DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2636
	DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2637 2638
};

L
Linus Torvalds 已提交
2639
static struct drm_driver driver = {
2640 2641
	/* Don't use MTRRs here; the Xserver or userspace app should
	 * deal with them for Intel hardware.
D
Dave Airlie 已提交
2642
	 */
2643
	.driver_features =
2644
	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2645
	    DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC,
2646
	.release = i915_driver_release,
2647
	.open = i915_driver_open,
2648
	.lastclose = i915_driver_lastclose,
2649
	.postclose = i915_driver_postclose,
2650
	.set_busid = drm_pci_set_busid,
2651

2652
	.gem_close_object = i915_gem_close_object,
C
Chris Wilson 已提交
2653
	.gem_free_object_unlocked = i915_gem_free_object,
2654
	.gem_vm_ops = &i915_gem_vm_ops,
2655 2656 2657 2658 2659 2660

	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
	.gem_prime_export = i915_gem_prime_export,
	.gem_prime_import = i915_gem_prime_import,

2661
	.dumb_create = i915_gem_dumb_create,
2662
	.dumb_map_offset = i915_gem_mmap_gtt,
2663
	.dumb_destroy = drm_gem_dumb_destroy,
L
Linus Torvalds 已提交
2664
	.ioctls = i915_ioctls,
2665
	.num_ioctls = ARRAY_SIZE(i915_ioctls),
2666
	.fops = &i915_driver_fops,
2667 2668 2669 2670 2671 2672
	.name = DRIVER_NAME,
	.desc = DRIVER_DESC,
	.date = DRIVER_DATE,
	.major = DRIVER_MAJOR,
	.minor = DRIVER_MINOR,
	.patchlevel = DRIVER_PATCHLEVEL,
L
Linus Torvalds 已提交
2673
};
2674 2675 2676 2677

#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/mock_drm.c"
#endif