amd64_edac.c 75.2 KB
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#include "amd64_edac.h"
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#include <asm/amd_nb.h>
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static struct edac_pci_ctl_info *pci_ctl;
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static int report_gart_errors;
module_param(report_gart_errors, int, 0644);

/*
 * Set by command line parameter. If BIOS has enabled the ECC, this override is
 * cleared to prevent re-enabling the hardware by this driver.
 */
static int ecc_enable_override;
module_param(ecc_enable_override, int, 0644);

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static struct msr __percpu *msrs;
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/*
 * count successfully initialized driver instances for setup_pci_device()
 */
static atomic_t drv_instances = ATOMIC_INIT(0);

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/* Per-node driver instances */
static struct mem_ctl_info **mcis;
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static struct ecc_settings **ecc_stngs;
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/*
 * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing
 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
 * or higher value'.
 *
 *FIXME: Produce a better mapping/linearisation.
 */
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static const struct scrubrate {
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       u32 scrubval;           /* bit pattern for scrub rate */
       u32 bandwidth;          /* bandwidth consumed (bytes/sec) */
} scrubrates[] = {
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	{ 0x01, 1600000000UL},
	{ 0x02, 800000000UL},
	{ 0x03, 400000000UL},
	{ 0x04, 200000000UL},
	{ 0x05, 100000000UL},
	{ 0x06, 50000000UL},
	{ 0x07, 25000000UL},
	{ 0x08, 12284069UL},
	{ 0x09, 6274509UL},
	{ 0x0A, 3121951UL},
	{ 0x0B, 1560975UL},
	{ 0x0C, 781440UL},
	{ 0x0D, 390720UL},
	{ 0x0E, 195300UL},
	{ 0x0F, 97650UL},
	{ 0x10, 48854UL},
	{ 0x11, 24427UL},
	{ 0x12, 12213UL},
	{ 0x13, 6101UL},
	{ 0x14, 3051UL},
	{ 0x15, 1523UL},
	{ 0x16, 761UL},
	{ 0x00, 0UL},        /* scrubbing off */
};

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int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
			       u32 *val, const char *func)
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{
	int err = 0;

	err = pci_read_config_dword(pdev, offset, val);
	if (err)
		amd64_warn("%s: error reading F%dx%03x.\n",
			   func, PCI_FUNC(pdev->devfn), offset);

	return err;
}

int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
				u32 val, const char *func)
{
	int err = 0;

	err = pci_write_config_dword(pdev, offset, val);
	if (err)
		amd64_warn("%s: error writing to F%dx%03x.\n",
			   func, PCI_FUNC(pdev->devfn), offset);

	return err;
}

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/*
 * Select DCT to which PCI cfg accesses are routed
 */
static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct)
{
	u32 reg = 0;

	amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, &reg);
	reg &= (pvt->model == 0x30) ? ~3 : ~1;
	reg |= dct;
	amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);
}

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/*
 *
 * Depending on the family, F2 DCT reads need special handling:
 *
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 * K8: has a single DCT only and no address offsets >= 0x100
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 *
 * F10h: each DCT has its own set of regs
 *	DCT0 -> F2x040..
 *	DCT1 -> F2x140..
 *
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 * F16h: has only 1 DCT
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 *
 * F15h: we select which DCT we access using F1x10C[DctCfgSel]
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 */
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static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct,
					 int offset, u32 *val)
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{
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	switch (pvt->fam) {
	case 0xf:
		if (dct || offset >= 0x100)
			return -EINVAL;
		break;
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	case 0x10:
		if (dct) {
			/*
			 * Note: If ganging is enabled, barring the regs
			 * F2x[1,0]98 and F2x[1,0]9C; reads reads to F2x1xx
			 * return 0. (cf. Section 2.8.1 F10h BKDG)
			 */
			if (dct_ganging_enabled(pvt))
				return 0;
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			offset += 0x100;
		}
		break;
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	case 0x15:
		/*
		 * F15h: F2x1xx addresses do not map explicitly to DCT1.
		 * We should select which DCT we access using F1x10C[DctCfgSel]
		 */
		dct = (dct && pvt->model == 0x30) ? 3 : dct;
		f15h_select_dct(pvt, dct);
		break;
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	case 0x16:
		if (dct)
			return -EINVAL;
		break;
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	default:
		break;
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	}
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	return amd64_read_pci_cfg(pvt->F2, offset, val);
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}

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/*
 * Memory scrubber control interface. For K8, memory scrubbing is handled by
 * hardware and can involve L2 cache, dcache as well as the main memory. With
 * F10, this is extended to L3 cache scrubbing on CPU models sporting that
 * functionality.
 *
 * This causes the "units" for the scrubbing speed to vary from 64 byte blocks
 * (dram) over to cache lines. This is nasty, so we will use bandwidth in
 * bytes/sec for the setting.
 *
 * Currently, we only do dram scrubbing. If the scrubbing is done in software on
 * other archs, we might not have access to the caches directly.
 */

/*
 * scan the scrub rate mapping table for a close or matching bandwidth value to
 * issue. If requested is too big, then use last maximum value found.
 */
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static int __set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate)
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{
	u32 scrubval;
	int i;

	/*
	 * map the configured rate (new_bw) to a value specific to the AMD64
	 * memory controller and apply to register. Search for the first
	 * bandwidth entry that is greater or equal than the setting requested
	 * and program that. If at last entry, turn off DRAM scrubbing.
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	 *
	 * If no suitable bandwidth is found, turn off DRAM scrubbing entirely
	 * by falling back to the last element in scrubrates[].
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	 */
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	for (i = 0; i < ARRAY_SIZE(scrubrates) - 1; i++) {
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		/*
		 * skip scrub rates which aren't recommended
		 * (see F10 BKDG, F3x58)
		 */
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		if (scrubrates[i].scrubval < min_rate)
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			continue;

		if (scrubrates[i].bandwidth <= new_bw)
			break;
	}

	scrubval = scrubrates[i].scrubval;

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	pci_write_bits32(ctl, SCRCTRL, scrubval, 0x001F);
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	if (scrubval)
		return scrubrates[i].bandwidth;

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	return 0;
}

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static int set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
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{
	struct amd64_pvt *pvt = mci->pvt_info;
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	u32 min_scrubrate = 0x5;
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	if (pvt->fam == 0xf)
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		min_scrubrate = 0x0;

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	/* Erratum #505 */
	if (pvt->fam == 0x15 && pvt->model < 0x10)
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		f15h_select_dct(pvt, 0);

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	return __set_scrub_rate(pvt->F3, bw, min_scrubrate);
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}

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static int get_scrub_rate(struct mem_ctl_info *mci)
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{
	struct amd64_pvt *pvt = mci->pvt_info;
	u32 scrubval = 0;
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	int i, retval = -EINVAL;
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	/* Erratum #505 */
	if (pvt->fam == 0x15 && pvt->model < 0x10)
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		f15h_select_dct(pvt, 0);

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	amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
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	scrubval = scrubval & 0x001F;

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	for (i = 0; i < ARRAY_SIZE(scrubrates); i++) {
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		if (scrubrates[i].scrubval == scrubval) {
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			retval = scrubrates[i].bandwidth;
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			break;
		}
	}
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	return retval;
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}

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/*
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 * returns true if the SysAddr given by sys_addr matches the
 * DRAM base/limit associated with node_id
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 */
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static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid)
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{
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	u64 addr;
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	/* The K8 treats this as a 40-bit value.  However, bits 63-40 will be
	 * all ones if the most significant implemented address bit is 1.
	 * Here we discard bits 63-40.  See section 3.4.2 of AMD publication
	 * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1
	 * Application Programming.
	 */
	addr = sys_addr & 0x000000ffffffffffull;

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	return ((addr >= get_dram_base(pvt, nid)) &&
		(addr <= get_dram_limit(pvt, nid)));
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}

/*
 * Attempt to map a SysAddr to a node. On success, return a pointer to the
 * mem_ctl_info structure for the node that the SysAddr maps to.
 *
 * On failure, return NULL.
 */
static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
						u64 sys_addr)
{
	struct amd64_pvt *pvt;
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	u8 node_id;
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	u32 intlv_en, bits;

	/*
	 * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section
	 * 3.4.4.2) registers to map the SysAddr to a node ID.
	 */
	pvt = mci->pvt_info;

	/*
	 * The value of this field should be the same for all DRAM Base
	 * registers.  Therefore we arbitrarily choose to read it from the
	 * register for node 0.
	 */
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	intlv_en = dram_intlv_en(pvt, 0);
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	if (intlv_en == 0) {
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		for (node_id = 0; node_id < DRAM_RANGES; node_id++) {
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			if (base_limit_match(pvt, sys_addr, node_id))
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				goto found;
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		}
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		goto err_no_match;
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	}

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	if (unlikely((intlv_en != 0x01) &&
		     (intlv_en != 0x03) &&
		     (intlv_en != 0x07))) {
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		amd64_warn("DRAM Base[IntlvEn] junk value: 0x%x, BIOS bug?\n", intlv_en);
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		return NULL;
	}

	bits = (((u32) sys_addr) >> 12) & intlv_en;

	for (node_id = 0; ; ) {
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		if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits)
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			break;	/* intlv_sel field matches */

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		if (++node_id >= DRAM_RANGES)
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			goto err_no_match;
	}

	/* sanity test for sys_addr */
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	if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) {
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		amd64_warn("%s: sys_addr 0x%llx falls outside base/limit address"
			   "range for node %d with node interleaving enabled.\n",
			   __func__, sys_addr, node_id);
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		return NULL;
	}

found:
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	return edac_mc_find((int)node_id);
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err_no_match:
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	edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n",
		 (unsigned long)sys_addr);
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	return NULL;
}
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/*
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 * compute the CS base address of the @csrow on the DRAM controller @dct.
 * For details see F2x[5C:40] in the processor's BKDG
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 */
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static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct,
				 u64 *base, u64 *mask)
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{
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	u64 csbase, csmask, base_bits, mask_bits;
	u8 addr_shift;
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	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {
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		csbase		= pvt->csels[dct].csbases[csrow];
		csmask		= pvt->csels[dct].csmasks[csrow];
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		base_bits	= GENMASK_ULL(31, 21) | GENMASK_ULL(15, 9);
		mask_bits	= GENMASK_ULL(29, 21) | GENMASK_ULL(15, 9);
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		addr_shift	= 4;
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	/*
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	 * F16h and F15h, models 30h and later need two addr_shift values:
	 * 8 for high and 6 for low (cf. F16h BKDG).
	 */
	} else if (pvt->fam == 0x16 ||
		  (pvt->fam == 0x15 && pvt->model >= 0x30)) {
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		csbase          = pvt->csels[dct].csbases[csrow];
		csmask          = pvt->csels[dct].csmasks[csrow >> 1];

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		*base  = (csbase & GENMASK_ULL(15,  5)) << 6;
		*base |= (csbase & GENMASK_ULL(30, 19)) << 8;
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		*mask = ~0ULL;
		/* poke holes for the csmask */
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		*mask &= ~((GENMASK_ULL(15, 5)  << 6) |
			   (GENMASK_ULL(30, 19) << 8));
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		*mask |= (csmask & GENMASK_ULL(15, 5))  << 6;
		*mask |= (csmask & GENMASK_ULL(30, 19)) << 8;
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		return;
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	} else {
		csbase		= pvt->csels[dct].csbases[csrow];
		csmask		= pvt->csels[dct].csmasks[csrow >> 1];
		addr_shift	= 8;
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		if (pvt->fam == 0x15)
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			base_bits = mask_bits =
				GENMASK_ULL(30,19) | GENMASK_ULL(13,5);
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		else
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			base_bits = mask_bits =
				GENMASK_ULL(28,19) | GENMASK_ULL(13,5);
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	}
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	*base  = (csbase & base_bits) << addr_shift;
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	*mask  = ~0ULL;
	/* poke holes for the csmask */
	*mask &= ~(mask_bits << addr_shift);
	/* OR them in */
	*mask |= (csmask & mask_bits) << addr_shift;
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}

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#define for_each_chip_select(i, dct, pvt) \
	for (i = 0; i < pvt->csels[dct].b_cnt; i++)

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#define chip_select_base(i, dct, pvt) \
	pvt->csels[dct].csbases[i]

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#define for_each_chip_select_mask(i, dct, pvt) \
	for (i = 0; i < pvt->csels[dct].m_cnt; i++)

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/*
 * @input_addr is an InputAddr associated with the node given by mci. Return the
 * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
 */
static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
{
	struct amd64_pvt *pvt;
	int csrow;
	u64 base, mask;

	pvt = mci->pvt_info;

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	for_each_chip_select(csrow, 0, pvt) {
		if (!csrow_enabled(csrow, 0, pvt))
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			continue;

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		get_cs_base_and_mask(pvt, csrow, 0, &base, &mask);

		mask = ~mask;
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		if ((input_addr & mask) == (base & mask)) {
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			edac_dbg(2, "InputAddr 0x%lx matches csrow %d (node %d)\n",
				 (unsigned long)input_addr, csrow,
				 pvt->mc_node_id);
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			return csrow;
		}
	}
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	edac_dbg(2, "no matching csrow for InputAddr 0x%lx (MC node %d)\n",
		 (unsigned long)input_addr, pvt->mc_node_id);
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	return -1;
}

/*
 * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094)
 * for the node represented by mci. Info is passed back in *hole_base,
 * *hole_offset, and *hole_size.  Function returns 0 if info is valid or 1 if
 * info is invalid. Info may be invalid for either of the following reasons:
 *
 * - The revision of the node is not E or greater.  In this case, the DRAM Hole
 *   Address Register does not exist.
 *
 * - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
 *   indicating that its contents are not valid.
 *
 * The values passed back in *hole_base, *hole_offset, and *hole_size are
 * complete 32-bit values despite the fact that the bitfields in the DHAR
 * only represent bits 31-24 of the base and offset values.
 */
int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
			     u64 *hole_offset, u64 *hole_size)
{
	struct amd64_pvt *pvt = mci->pvt_info;

	/* only revE and later have the DRAM Hole Address Register */
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	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) {
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		edac_dbg(1, "  revision %d for node %d does not support DHAR\n",
			 pvt->ext_model, pvt->mc_node_id);
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		return 1;
	}

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	/* valid for Fam10h and above */
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	if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) {
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		edac_dbg(1, "  Dram Memory Hoisting is DISABLED on this system\n");
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		return 1;
	}

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	if (!dhar_valid(pvt)) {
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		edac_dbg(1, "  Dram Memory Hoisting is DISABLED on this node %d\n",
			 pvt->mc_node_id);
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		return 1;
	}

	/* This node has Memory Hoisting */

	/* +------------------+--------------------+--------------------+-----
	 * | memory           | DRAM hole          | relocated          |
	 * | [0, (x - 1)]     | [x, 0xffffffff]    | addresses from     |
	 * |                  |                    | DRAM hole          |
	 * |                  |                    | [0x100000000,      |
	 * |                  |                    |  (0x100000000+     |
	 * |                  |                    |   (0xffffffff-x))] |
	 * +------------------+--------------------+--------------------+-----
	 *
	 * Above is a diagram of physical memory showing the DRAM hole and the
	 * relocated addresses from the DRAM hole.  As shown, the DRAM hole
	 * starts at address x (the base address) and extends through address
	 * 0xffffffff.  The DRAM Hole Address Register (DHAR) relocates the
	 * addresses in the hole so that they start at 0x100000000.
	 */

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	*hole_base = dhar_base(pvt);
	*hole_size = (1ULL << 32) - *hole_base;
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	*hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt)
					: k8_dhar_offset(pvt);
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	edac_dbg(1, "  DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
		 pvt->mc_node_id, (unsigned long)*hole_base,
		 (unsigned long)*hole_offset, (unsigned long)*hole_size);
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	return 0;
}
EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info);

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/*
 * Return the DramAddr that the SysAddr given by @sys_addr maps to.  It is
 * assumed that sys_addr maps to the node given by mci.
 *
 * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section
 * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a
 * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled,
 * then it is also involved in translating a SysAddr to a DramAddr. Sections
 * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting.
 * These parts of the documentation are unclear. I interpret them as follows:
 *
 * When node n receives a SysAddr, it processes the SysAddr as follows:
 *
 * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM
 *    Limit registers for node n. If the SysAddr is not within the range
 *    specified by the base and limit values, then node n ignores the Sysaddr
 *    (since it does not map to node n). Otherwise continue to step 2 below.
 *
 * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is
 *    disabled so skip to step 3 below. Otherwise see if the SysAddr is within
 *    the range of relocated addresses (starting at 0x100000000) from the DRAM
 *    hole. If not, skip to step 3 below. Else get the value of the
 *    DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the
 *    offset defined by this value from the SysAddr.
 *
 * 3. Obtain the base address for node n from the DRAMBase field of the DRAM
 *    Base register for node n. To obtain the DramAddr, subtract the base
 *    address from the SysAddr, as shown near the start of section 3.4.4 (p.70).
 */
static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
{
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	struct amd64_pvt *pvt = mci->pvt_info;
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	u64 dram_base, hole_base, hole_offset, hole_size, dram_addr;
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	int ret;
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	dram_base = get_dram_base(pvt, pvt->mc_node_id);
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	ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset,
				      &hole_size);
	if (!ret) {
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		if ((sys_addr >= (1ULL << 32)) &&
		    (sys_addr < ((1ULL << 32) + hole_size))) {
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			/* use DHAR to translate SysAddr to DramAddr */
			dram_addr = sys_addr - hole_offset;

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			edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
				 (unsigned long)sys_addr,
				 (unsigned long)dram_addr);
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			return dram_addr;
		}
	}

	/*
	 * Translate the SysAddr to a DramAddr as shown near the start of
	 * section 3.4.4 (p. 70).  Although sys_addr is a 64-bit value, the k8
	 * only deals with 40-bit values.  Therefore we discard bits 63-40 of
	 * sys_addr below.  If bit 39 of sys_addr is 1 then the bits we
	 * discard are all 1s.  Otherwise the bits we discard are all 0s.  See
	 * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture
	 * Programmer's Manual Volume 1 Application Programming.
	 */
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	dram_addr = (sys_addr & GENMASK_ULL(39, 0)) - dram_base;
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	edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
		 (unsigned long)sys_addr, (unsigned long)dram_addr);
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	return dram_addr;
}

/*
 * @intlv_en is the value of the IntlvEn field from a DRAM Base register
 * (section 3.4.4.1).  Return the number of bits from a SysAddr that are used
 * for node interleaving.
 */
static int num_node_interleave_bits(unsigned intlv_en)
{
	static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 };
	int n;

	BUG_ON(intlv_en > 7);
	n = intlv_shift_table[intlv_en];
	return n;
}

/* Translate the DramAddr given by @dram_addr to an InputAddr. */
static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr)
{
	struct amd64_pvt *pvt;
	int intlv_shift;
	u64 input_addr;

	pvt = mci->pvt_info;

	/*
	 * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
	 * concerning translating a DramAddr to an InputAddr.
	 */
612
	intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
613
	input_addr = ((dram_addr >> intlv_shift) & GENMASK_ULL(35, 12)) +
614
		      (dram_addr & 0xfff);
615

616 617 618
	edac_dbg(2, "  Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",
		 intlv_shift, (unsigned long)dram_addr,
		 (unsigned long)input_addr);
619 620 621 622 623 624 625 626 627 628 629 630 631 632 633

	return input_addr;
}

/*
 * Translate the SysAddr represented by @sys_addr to an InputAddr.  It is
 * assumed that @sys_addr maps to the node given by mci.
 */
static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr)
{
	u64 input_addr;

	input_addr =
	    dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr));

634 635
	edac_dbg(2, "SysAdddr 0x%lx translates to InputAddr 0x%lx\n",
		 (unsigned long)sys_addr, (unsigned long)input_addr);
636 637 638 639 640 641

	return input_addr;
}

/* Map the Error address to a PAGE and PAGE OFFSET. */
static inline void error_address_to_page_and_offset(u64 error_address,
642
						    struct err_info *err)
643
{
644 645
	err->page = (u32) (error_address >> PAGE_SHIFT);
	err->offset = ((u32) error_address) & ~PAGE_MASK;
646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662
}

/*
 * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address
 * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers
 * of a node that detected an ECC memory error.  mci represents the node that
 * the error address maps to (possibly different from the node that detected
 * the error).  Return the number of the csrow that sys_addr maps to, or -1 on
 * error.
 */
static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr)
{
	int csrow;

	csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr));

	if (csrow == -1)
663 664
		amd64_mc_err(mci, "Failed to translate InputAddr to csrow for "
				  "address 0x%lx\n", (unsigned long)sys_addr);
665 666
	return csrow;
}
667

668
static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
669 670 671 672 673

/*
 * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
 * are ECC capable.
 */
674
static unsigned long determine_edac_cap(struct amd64_pvt *pvt)
675
{
676
	u8 bit;
677
	unsigned long edac_cap = EDAC_FLAG_NONE;
678

679
	bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F)
680 681 682
		? 19
		: 17;

683
	if (pvt->dclr0 & BIT(bit))
684 685 686 687 688
		edac_cap = EDAC_FLAG_SECDED;

	return edac_cap;
}

689
static void debug_display_dimm_sizes(struct amd64_pvt *, u8);
690

691
static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan)
692
{
693
	edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);
694

695 696 697
	edac_dbg(1, "  DIMM type: %sbuffered; all DIMMs support ECC: %s\n",
		 (dclr & BIT(16)) ?  "un" : "",
		 (dclr & BIT(19)) ? "yes" : "no");
698

699 700
	edac_dbg(1, "  PAR/ERR parity: %s\n",
		 (dclr & BIT(8)) ?  "enabled" : "disabled");
701

702
	if (pvt->fam == 0x10)
703 704
		edac_dbg(1, "  DCT 128bit mode width: %s\n",
			 (dclr & BIT(11)) ?  "128b" : "64b");
705

706 707 708 709 710
	edac_dbg(1, "  x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",
		 (dclr & BIT(12)) ?  "yes" : "no",
		 (dclr & BIT(13)) ?  "yes" : "no",
		 (dclr & BIT(14)) ?  "yes" : "no",
		 (dclr & BIT(15)) ?  "yes" : "no");
711 712
}

713
/* Display and decode various NB registers for debug purposes. */
714
static void dump_misc_regs(struct amd64_pvt *pvt)
715
{
716
	edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
717

718 719
	edac_dbg(1, "  NB two channel DRAM capable: %s\n",
		 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no");
720

721 722 723
	edac_dbg(1, "  ECC capable: %s, ChipKill ECC capable: %s\n",
		 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no",
		 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no");
724

725
	debug_dump_dramcfg_low(pvt, pvt->dclr0, 0);
726

727
	edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);
728

729 730
	edac_dbg(1, "F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, offset: 0x%08x\n",
		 pvt->dhar, dhar_base(pvt),
731 732
		 (pvt->fam == 0xf) ? k8_dhar_offset(pvt)
				   : f10_dhar_offset(pvt));
733

734
	edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
735

736
	debug_display_dimm_sizes(pvt, 0);
737

738
	/* everything below this point is Fam10h and above */
739
	if (pvt->fam == 0xf)
740
		return;
741

742
	debug_display_dimm_sizes(pvt, 1);
743

744
	amd64_info("using %s syndromes.\n", ((pvt->ecc_sym_sz == 8) ? "x8" : "x4"));
745

746
	/* Only if NOT ganged does dclr1 have valid info */
747
	if (!dct_ganging_enabled(pvt))
748
		debug_dump_dramcfg_low(pvt, pvt->dclr1, 1);
749 750
}

751
/*
752
 * See BKDG, F2x[1,0][5C:40], F2[1,0][6C:60]
753
 */
754
static void prep_chip_selects(struct amd64_pvt *pvt)
755
{
756
	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {
757 758
		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8;
759 760 761
	} else if (pvt->fam == 0x15 && pvt->model >= 0x30) {
		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4;
		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2;
762
	} else {
763 764
		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4;
765 766 767 768
	}
}

/*
769
 * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers
770
 */
771
static void read_dct_base_mask(struct amd64_pvt *pvt)
772
{
773
	int cs;
774

775
	prep_chip_selects(pvt);
776

777
	for_each_chip_select(cs, 0, pvt) {
778 779
		int reg0   = DCSB0 + (cs * 4);
		int reg1   = DCSB1 + (cs * 4);
780 781
		u32 *base0 = &pvt->csels[0].csbases[cs];
		u32 *base1 = &pvt->csels[1].csbases[cs];
782

783
		if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0))
784 785
			edac_dbg(0, "  DCSB0[%d]=0x%08x reg: F2x%x\n",
				 cs, *base0, reg0);
786

787
		if (pvt->fam == 0xf)
788
			continue;
789

790
		if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, base1))
791
			edac_dbg(0, "  DCSB1[%d]=0x%08x reg: F2x%x\n",
792 793
				 cs, *base1, (pvt->fam == 0x10) ? reg1
								: reg0);
794 795
	}

796
	for_each_chip_select_mask(cs, 0, pvt) {
797 798
		int reg0   = DCSM0 + (cs * 4);
		int reg1   = DCSM1 + (cs * 4);
799 800
		u32 *mask0 = &pvt->csels[0].csmasks[cs];
		u32 *mask1 = &pvt->csels[1].csmasks[cs];
801

802
		if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0))
803 804
			edac_dbg(0, "    DCSM0[%d]=0x%08x reg: F2x%x\n",
				 cs, *mask0, reg0);
805

806
		if (pvt->fam == 0xf)
807
			continue;
808

809
		if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1))
810
			edac_dbg(0, "    DCSM1[%d]=0x%08x reg: F2x%x\n",
811 812
				 cs, *mask1, (pvt->fam == 0x10) ? reg1
								: reg0);
813 814 815
	}
}

816
static enum mem_type determine_memory_type(struct amd64_pvt *pvt, int cs)
817 818 819
{
	enum mem_type type;

820
	/* F15h supports only DDR3 */
821
	if (pvt->fam >= 0x15)
822
		type = (pvt->dclr0 & BIT(16)) ?	MEM_DDR3 : MEM_RDDR3;
823
	else if (pvt->fam == 0x10 || pvt->ext_model >= K8_REV_F) {
824 825 826 827
		if (pvt->dchr0 & DDR3_MODE)
			type = (pvt->dclr0 & BIT(16)) ?	MEM_DDR3 : MEM_RDDR3;
		else
			type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2;
828 829 830 831
	} else {
		type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR;
	}

832
	amd64_info("CS%d: %s\n", cs, edac_mem_types[type]);
833 834 835 836

	return type;
}

837
/* Get the number of DCT channels the memory controller is using. */
838 839
static int k8_early_channel_count(struct amd64_pvt *pvt)
{
840
	int flag;
841

842
	if (pvt->ext_model >= K8_REV_F)
843
		/* RevF (NPT) and later */
844
		flag = pvt->dclr0 & WIDTH_128;
845
	else
846 847 848 849 850 851 852 853 854
		/* RevE and earlier */
		flag = pvt->dclr0 & REVE_WIDTH_128;

	/* not used */
	pvt->dclr1 = 0;

	return (flag) ? 2 : 1;
}

855
/* On F10h and later ErrAddr is MC4_ADDR[47:1] */
856
static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m)
857
{
858
	u64 addr;
859 860 861
	u8 start_bit = 1;
	u8 end_bit   = 47;

862
	if (pvt->fam == 0xf) {
863 864 865 866
		start_bit = 3;
		end_bit   = 39;
	}

867
	addr = m->addr & GENMASK_ULL(end_bit, start_bit);
868 869 870 871

	/*
	 * Erratum 637 workaround
	 */
872
	if (pvt->fam == 0x15) {
873 874 875
		struct amd64_pvt *pvt;
		u64 cc6_base, tmp_addr;
		u32 tmp;
876 877
		u16 mce_nid;
		u8 intlv_en;
878

879
		if ((addr & GENMASK_ULL(47, 24)) >> 24 != 0x00fdf7)
880 881 882 883 884 885 886 887 888
			return addr;

		mce_nid	= amd_get_nb_id(m->extcpu);
		pvt	= mcis[mce_nid]->pvt_info;

		amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp);
		intlv_en = tmp >> 21 & 0x7;

		/* add [47:27] + 3 trailing bits */
889
		cc6_base  = (tmp & GENMASK_ULL(20, 0)) << 3;
890 891 892 893 894 895 896 897

		/* reverse and add DramIntlvEn */
		cc6_base |= intlv_en ^ 0x7;

		/* pin at [47:24] */
		cc6_base <<= 24;

		if (!intlv_en)
898
			return cc6_base | (addr & GENMASK_ULL(23, 0));
899 900 901 902

		amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp);

							/* faster log2 */
903
		tmp_addr  = (addr & GENMASK_ULL(23, 12)) << __fls(intlv_en + 1);
904 905

		/* OR DramIntlvSel into bits [14:12] */
906
		tmp_addr |= (tmp & GENMASK_ULL(23, 21)) >> 9;
907 908

		/* add remaining [11:0] bits from original MC4_ADDR */
909
		tmp_addr |= addr & GENMASK_ULL(11, 0);
910 911 912 913 914

		return cc6_base | tmp_addr;
	}

	return addr;
915 916
}

917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932
static struct pci_dev *pci_get_related_function(unsigned int vendor,
						unsigned int device,
						struct pci_dev *related)
{
	struct pci_dev *dev = NULL;

	while ((dev = pci_get_device(vendor, device, dev))) {
		if (pci_domain_nr(dev->bus) == pci_domain_nr(related->bus) &&
		    (dev->bus->number == related->bus->number) &&
		    (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn)))
			break;
	}

	return dev;
}

933
static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
934
{
935
	struct amd_northbridge *nb;
936 937
	struct pci_dev *f1 = NULL;
	unsigned int pci_func;
938
	int off = range << 3;
939
	u32 llim;
940

941 942
	amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off,  &pvt->ranges[range].base.lo);
	amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo);
943

944
	if (pvt->fam == 0xf)
945
		return;
946

947 948
	if (!dram_rw(pvt, range))
		return;
949

950 951
	amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off,  &pvt->ranges[range].base.hi);
	amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi);
952

953
	/* F15h: factor in CC6 save area by reading dst node's limit reg */
954
	if (pvt->fam != 0x15)
955
		return;
956

957 958 959
	nb = node_to_amd_nb(dram_dst_node(pvt, range));
	if (WARN_ON(!nb))
		return;
960

961 962 963 964
	pci_func = (pvt->model == 0x30) ? PCI_DEVICE_ID_AMD_15H_M30H_NB_F1
					: PCI_DEVICE_ID_AMD_15H_NB_F1;

	f1 = pci_get_related_function(nb->misc->vendor, pci_func, nb->misc);
965 966
	if (WARN_ON(!f1))
		return;
967

968
	amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim);
969

970
	pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0);
971

972 973
				    /* {[39:27],111b} */
	pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16;
974

975
	pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0);
976

977 978 979 980
				    /* [47:40] */
	pvt->ranges[range].lim.hi |= llim >> 13;

	pci_dev_put(f1);
981 982
}

983
static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
984
				    struct err_info *err)
985
{
986
	struct amd64_pvt *pvt = mci->pvt_info;
987

988
	error_address_to_page_and_offset(sys_addr, err);
989 990 991 992 993

	/*
	 * Find out which node the error address belongs to. This may be
	 * different from the node that detected the error.
	 */
994 995
	err->src_mci = find_mc_by_sys_addr(mci, sys_addr);
	if (!err->src_mci) {
996 997
		amd64_mc_err(mci, "failed to map error addr 0x%lx to a node\n",
			     (unsigned long)sys_addr);
998
		err->err_code = ERR_NODE;
999 1000 1001 1002
		return;
	}

	/* Now map the sys_addr to a CSROW */
1003 1004 1005
	err->csrow = sys_addr_to_csrow(err->src_mci, sys_addr);
	if (err->csrow < 0) {
		err->err_code = ERR_CSROW;
1006 1007 1008
		return;
	}

1009
	/* CHIPKILL enabled */
1010
	if (pvt->nbcfg & NBCFG_CHIPKILL) {
1011 1012
		err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome);
		if (err->channel < 0) {
1013 1014 1015 1016 1017
			/*
			 * Syndrome didn't map, so we don't know which of the
			 * 2 DIMMs is in error. So we need to ID 'both' of them
			 * as suspect.
			 */
1018
			amd64_mc_warn(err->src_mci, "unknown syndrome 0x%04x - "
1019
				      "possible error reporting race\n",
1020 1021
				      err->syndrome);
			err->err_code = ERR_CHANNEL;
1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032
			return;
		}
	} else {
		/*
		 * non-chipkill ecc mode
		 *
		 * The k8 documentation is unclear about how to determine the
		 * channel number when using non-chipkill memory.  This method
		 * was obtained from email communication with someone at AMD.
		 * (Wish the email was placed in this comment - norsk)
		 */
1033
		err->channel = ((sys_addr & BIT(3)) != 0);
1034 1035 1036
	}
}

1037
static int ddr2_cs_size(unsigned i, bool dct_width)
1038
{
1039
	unsigned shift = 0;
1040

1041 1042 1043 1044
	if (i <= 2)
		shift = i;
	else if (!(i & 0x1))
		shift = i >> 1;
1045
	else
1046
		shift = (i + 1) >> 1;
1047

1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060
	return 128 << (shift + !!dct_width);
}

static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
				  unsigned cs_mode)
{
	u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;

	if (pvt->ext_model >= K8_REV_F) {
		WARN_ON(cs_mode > 11);
		return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
	}
	else if (pvt->ext_model >= K8_REV_D) {
1061
		unsigned diff;
1062 1063
		WARN_ON(cs_mode > 10);

1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090
		/*
		 * the below calculation, besides trying to win an obfuscated C
		 * contest, maps cs_mode values to DIMM chip select sizes. The
		 * mappings are:
		 *
		 * cs_mode	CS size (mb)
		 * =======	============
		 * 0		32
		 * 1		64
		 * 2		128
		 * 3		128
		 * 4		256
		 * 5		512
		 * 6		256
		 * 7		512
		 * 8		1024
		 * 9		1024
		 * 10		2048
		 *
		 * Basically, it calculates a value with which to shift the
		 * smallest CS size of 32MB.
		 *
		 * ddr[23]_cs_size have a similar purpose.
		 */
		diff = cs_mode/3 + (unsigned)(cs_mode > 5);

		return 32 << (cs_mode - diff);
1091 1092 1093 1094 1095
	}
	else {
		WARN_ON(cs_mode > 6);
		return 32 << cs_mode;
	}
1096 1097
}

1098 1099 1100 1101 1102 1103 1104 1105
/*
 * Get the number of DCT channels in use.
 *
 * Return:
 *	number of Memory Channels in operation
 * Pass back:
 *	contents of the DCL0_LOW register
 */
1106
static int f1x_early_channel_count(struct amd64_pvt *pvt)
1107
{
1108
	int i, j, channels = 0;
1109

1110
	/* On F10h, if we are in 128 bit mode, then we are using 2 channels */
1111
	if (pvt->fam == 0x10 && (pvt->dclr0 & WIDTH_128))
1112
		return 2;
1113 1114

	/*
1115 1116 1117
	 * Need to check if in unganged mode: In such, there are 2 channels,
	 * but they are not in 128 bit mode and thus the above 'dclr0' status
	 * bit will be OFF.
1118 1119 1120 1121
	 *
	 * Need to check DCT0[0] and DCT1[0] to see if only one of them has
	 * their CSEnable bit on. If so, then SINGLE DIMM case.
	 */
1122
	edac_dbg(0, "Data width is not 128 bits - need more decoding\n");
1123

1124 1125 1126 1127 1128
	/*
	 * Check DRAM Bank Address Mapping values for each DIMM to see if there
	 * is more than just one DIMM present in unganged mode. Need to check
	 * both controllers since DIMMs can be placed in either one.
	 */
1129 1130
	for (i = 0; i < 2; i++) {
		u32 dbam = (i ? pvt->dbam1 : pvt->dbam0);
1131

1132 1133 1134 1135 1136 1137
		for (j = 0; j < 4; j++) {
			if (DBAM_DIMM(j, dbam) > 0) {
				channels++;
				break;
			}
		}
1138 1139
	}

1140 1141 1142
	if (channels > 2)
		channels = 2;

1143
	amd64_info("MCT channel count: %d\n", channels);
1144 1145 1146 1147

	return channels;
}

1148
static int ddr3_cs_size(unsigned i, bool dct_width)
1149
{
1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175
	unsigned shift = 0;
	int cs_size = 0;

	if (i == 0 || i == 3 || i == 4)
		cs_size = -1;
	else if (i <= 2)
		shift = i;
	else if (i == 12)
		shift = 7;
	else if (!(i & 0x1))
		shift = i >> 1;
	else
		shift = (i + 1) >> 1;

	if (cs_size != -1)
		cs_size = (128 * (1 << !!dct_width)) << shift;

	return cs_size;
}

static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
				   unsigned cs_mode)
{
	u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;

	WARN_ON(cs_mode > 11);
1176 1177

	if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE)
1178
		return ddr3_cs_size(cs_mode, dclr & WIDTH_128);
1179
	else
1180 1181 1182 1183 1184 1185 1186 1187 1188 1189
		return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
}

/*
 * F15h supports only 64bit DCT interfaces
 */
static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
				   unsigned cs_mode)
{
	WARN_ON(cs_mode > 12);
1190

1191
	return ddr3_cs_size(cs_mode, false);
1192 1193
}

1194
/*
1195
 * F16h and F15h model 30h have only limited cs_modes.
1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208
 */
static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
				unsigned cs_mode)
{
	WARN_ON(cs_mode > 12);

	if (cs_mode == 6 || cs_mode == 8 ||
	    cs_mode == 9 || cs_mode == 12)
		return -1;
	else
		return ddr3_cs_size(cs_mode, false);
}

1209
static void read_dram_ctl_register(struct amd64_pvt *pvt)
1210 1211
{

1212
	if (pvt->fam == 0xf)
1213 1214
		return;

1215
	if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) {
1216 1217
		edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",
			 pvt->dct_sel_lo, dct_sel_baseaddr(pvt));
1218

1219 1220
		edac_dbg(0, "  DCTs operate in %s mode\n",
			 (dct_ganging_enabled(pvt) ? "ganged" : "unganged"));
1221 1222

		if (!dct_ganging_enabled(pvt))
1223 1224
			edac_dbg(0, "  Address range split per DCT: %s\n",
				 (dct_high_range_enabled(pvt) ? "yes" : "no"));
1225

1226 1227 1228
		edac_dbg(0, "  data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n",
			 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),
			 (dct_memory_cleared(pvt) ? "yes" : "no"));
1229

1230 1231 1232 1233
		edac_dbg(0, "  channel interleave: %s, "
			 "interleave bits selector: 0x%x\n",
			 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"),
			 dct_sel_interleave_addr(pvt));
1234 1235
	}

1236
	amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi);
1237 1238
}

1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255
/*
 * Determine channel (DCT) based on the interleaving mode (see F15h M30h BKDG,
 * 2.10.12 Memory Interleaving Modes).
 */
static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
				     u8 intlv_en, int num_dcts_intlv,
				     u32 dct_sel)
{
	u8 channel = 0;
	u8 select;

	if (!(intlv_en))
		return (u8)(dct_sel);

	if (num_dcts_intlv == 2) {
		select = (sys_addr >> 8) & 0x3;
		channel = select ? 0x3 : 0;
1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266
	} else if (num_dcts_intlv == 4) {
		u8 intlv_addr = dct_sel_interleave_addr(pvt);
		switch (intlv_addr) {
		case 0x4:
			channel = (sys_addr >> 8) & 0x3;
			break;
		case 0x5:
			channel = (sys_addr >> 9) & 0x3;
			break;
		}
	}
1267 1268 1269
	return channel;
}

1270
/*
1271
 * Determine channel (DCT) based on the interleaving mode: F10h BKDG, 2.8.9 Memory
1272 1273
 * Interleaving Modes.
 */
1274
static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
1275
				bool hi_range_sel, u8 intlv_en)
1276
{
1277
	u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1;
1278 1279

	if (dct_ganging_enabled(pvt))
1280
		return 0;
1281

1282 1283
	if (hi_range_sel)
		return dct_sel_high;
1284

1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306
	/*
	 * see F2x110[DctSelIntLvAddr] - channel interleave mode
	 */
	if (dct_interleave_enabled(pvt)) {
		u8 intlv_addr = dct_sel_interleave_addr(pvt);

		/* return DCT select function: 0=DCT0, 1=DCT1 */
		if (!intlv_addr)
			return sys_addr >> 6 & 1;

		if (intlv_addr & 0x2) {
			u8 shift = intlv_addr & 0x1 ? 9 : 6;
			u32 temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2;

			return ((sys_addr >> shift) & 1) ^ temp;
		}

		return (sys_addr >> (12 + hweight8(intlv_en))) & 1;
	}

	if (dct_high_range_enabled(pvt))
		return ~dct_sel_high & 1;
1307 1308 1309 1310

	return 0;
}

1311
/* Convert the sys_addr to the normalized DCT address */
1312
static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range,
1313 1314
				 u64 sys_addr, bool hi_rng,
				 u32 dct_sel_base_addr)
1315 1316
{
	u64 chan_off;
1317 1318 1319
	u64 dram_base		= get_dram_base(pvt, range);
	u64 hole_off		= f10_dhar_offset(pvt);
	u64 dct_sel_base_off	= (pvt->dct_sel_hi & 0xFFFFFC00) << 16;
1320

1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334
	if (hi_rng) {
		/*
		 * if
		 * base address of high range is below 4Gb
		 * (bits [47:27] at [31:11])
		 * DRAM address space on this DCT is hoisted above 4Gb	&&
		 * sys_addr > 4Gb
		 *
		 *	remove hole offset from sys_addr
		 * else
		 *	remove high range offset from sys_addr
		 */
		if ((!(dct_sel_base_addr >> 16) ||
		     dct_sel_base_addr < dhar_base(pvt)) &&
1335
		    dhar_valid(pvt) &&
1336
		    (sys_addr >= BIT_64(32)))
1337
			chan_off = hole_off;
1338 1339 1340
		else
			chan_off = dct_sel_base_off;
	} else {
1341 1342 1343 1344 1345 1346 1347 1348 1349
		/*
		 * if
		 * we have a valid hole		&&
		 * sys_addr > 4Gb
		 *
		 *	remove hole
		 * else
		 *	remove dram base to normalize to DCT address
		 */
1350
		if (dhar_valid(pvt) && (sys_addr >= BIT_64(32)))
1351
			chan_off = hole_off;
1352
		else
1353
			chan_off = dram_base;
1354 1355
	}

1356
	return (sys_addr & GENMASK_ULL(47,6)) - (chan_off & GENMASK_ULL(47,23));
1357 1358 1359 1360 1361 1362
}

/*
 * checks if the csrow passed in is marked as SPARED, if so returns the new
 * spare row
 */
1363
static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow)
1364
{
1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375
	int tmp_cs;

	if (online_spare_swap_done(pvt, dct) &&
	    csrow == online_spare_bad_dramcs(pvt, dct)) {

		for_each_chip_select(tmp_cs, dct, pvt) {
			if (chip_select_base(tmp_cs, dct, pvt) & 0x2) {
				csrow = tmp_cs;
				break;
			}
		}
1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387
	}
	return csrow;
}

/*
 * Iterate over the DRAM DCT "base" and "mask" registers looking for a
 * SystemAddr match on the specified 'ChannelSelect' and 'NodeID'
 *
 * Return:
 *	-EINVAL:  NOT FOUND
 *	0..csrow = Chip-Select Row
 */
1388
static int f1x_lookup_addr_in_dct(u64 in_addr, u8 nid, u8 dct)
1389 1390 1391
{
	struct mem_ctl_info *mci;
	struct amd64_pvt *pvt;
1392
	u64 cs_base, cs_mask;
1393 1394 1395
	int cs_found = -EINVAL;
	int csrow;

1396
	mci = mcis[nid];
1397 1398 1399 1400 1401
	if (!mci)
		return cs_found;

	pvt = mci->pvt_info;

1402
	edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct);
1403

1404 1405
	for_each_chip_select(csrow, dct, pvt) {
		if (!csrow_enabled(csrow, dct, pvt))
1406 1407
			continue;

1408
		get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask);
1409

1410 1411
		edac_dbg(1, "    CSROW=%d CSBase=0x%llx CSMask=0x%llx\n",
			 csrow, cs_base, cs_mask);
1412

1413
		cs_mask = ~cs_mask;
1414

1415 1416
		edac_dbg(1, "    (InputAddr & ~CSMask)=0x%llx (CSBase & ~CSMask)=0x%llx\n",
			 (in_addr & cs_mask), (cs_base & cs_mask));
1417

1418
		if ((in_addr & cs_mask) == (cs_base & cs_mask)) {
1419 1420 1421 1422
			if (pvt->fam == 0x15 && pvt->model >= 0x30) {
				cs_found =  csrow;
				break;
			}
1423
			cs_found = f10_process_possible_spare(pvt, dct, csrow);
1424

1425
			edac_dbg(1, " MATCH csrow=%d\n", cs_found);
1426 1427 1428 1429 1430 1431
			break;
		}
	}
	return cs_found;
}

1432 1433 1434 1435 1436
/*
 * See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is
 * swapped with a region located at the bottom of memory so that the GPU can use
 * the interleaved region and thus two channels.
 */
1437
static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr)
1438 1439 1440
{
	u32 swap_reg, swap_base, swap_limit, rgn_size, tmp_addr;

1441
	if (pvt->fam == 0x10) {
1442
		/* only revC3 and revE have that feature */
1443
		if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3))
1444 1445 1446
			return sys_addr;
	}

1447
	amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg);
1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465

	if (!(swap_reg & 0x1))
		return sys_addr;

	swap_base	= (swap_reg >> 3) & 0x7f;
	swap_limit	= (swap_reg >> 11) & 0x7f;
	rgn_size	= (swap_reg >> 20) & 0x7f;
	tmp_addr	= sys_addr >> 27;

	if (!(sys_addr >> 34) &&
	    (((tmp_addr >= swap_base) &&
	     (tmp_addr <= swap_limit)) ||
	     (tmp_addr < rgn_size)))
		return sys_addr ^ (u64)swap_base << 27;

	return sys_addr;
}

1466
/* For a given @dram_range, check if @sys_addr falls within it. */
1467
static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
1468
				  u64 sys_addr, int *chan_sel)
1469
{
1470
	int cs_found = -EINVAL;
1471
	u64 chan_addr;
1472
	u32 dct_sel_base;
1473
	u8 channel;
1474
	bool high_range = false;
1475

1476
	u8 node_id    = dram_dst_node(pvt, range);
1477
	u8 intlv_en   = dram_intlv_en(pvt, range);
1478
	u32 intlv_sel = dram_intlv_sel(pvt, range);
1479

1480 1481
	edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
		 range, sys_addr, get_dram_limit(pvt, range));
1482

1483 1484 1485 1486 1487 1488 1489 1490
	if (dhar_valid(pvt) &&
	    dhar_base(pvt) <= sys_addr &&
	    sys_addr < BIT_64(32)) {
		amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n",
			    sys_addr);
		return -EINVAL;
	}

1491
	if (intlv_en && (intlv_sel != ((sys_addr >> 12) & intlv_en)))
1492 1493
		return -EINVAL;

1494
	sys_addr = f1x_swap_interleaved_region(pvt, sys_addr);
1495

1496 1497 1498 1499 1500 1501 1502 1503 1504
	dct_sel_base = dct_sel_baseaddr(pvt);

	/*
	 * check whether addresses >= DctSelBaseAddr[47:27] are to be used to
	 * select between DCT0 and DCT1.
	 */
	if (dct_high_range_enabled(pvt) &&
	   !dct_ganging_enabled(pvt) &&
	   ((sys_addr >> 27) >= (dct_sel_base >> 11)))
1505
		high_range = true;
1506

1507
	channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en);
1508

1509
	chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr,
1510
					  high_range, dct_sel_base);
1511

1512 1513 1514 1515
	/* Remove node interleaving, see F1x120 */
	if (intlv_en)
		chan_addr = ((chan_addr >> (12 + hweight8(intlv_en))) << 12) |
			    (chan_addr & 0xfff);
1516

1517
	/* remove channel interleave */
1518 1519 1520
	if (dct_interleave_enabled(pvt) &&
	   !dct_high_range_enabled(pvt) &&
	   !dct_ganging_enabled(pvt)) {
1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534

		if (dct_sel_interleave_addr(pvt) != 1) {
			if (dct_sel_interleave_addr(pvt) == 0x3)
				/* hash 9 */
				chan_addr = ((chan_addr >> 10) << 9) |
					     (chan_addr & 0x1ff);
			else
				/* A[6] or hash 6 */
				chan_addr = ((chan_addr >> 7) << 6) |
					     (chan_addr & 0x3f);
		} else
			/* A[12] */
			chan_addr = ((chan_addr >> 13) << 12) |
				     (chan_addr & 0xfff);
1535 1536
	}

1537
	edac_dbg(1, "   Normalized DCT addr: 0x%llx\n", chan_addr);
1538

1539
	cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, channel);
1540

1541
	if (cs_found >= 0)
1542
		*chan_sel = channel;
1543

1544 1545 1546
	return cs_found;
}

1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583
static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
					u64 sys_addr, int *chan_sel)
{
	int cs_found = -EINVAL;
	int num_dcts_intlv = 0;
	u64 chan_addr, chan_offset;
	u64 dct_base, dct_limit;
	u32 dct_cont_base_reg, dct_cont_limit_reg, tmp;
	u8 channel, alias_channel, leg_mmio_hole, dct_sel, dct_offset_en;

	u64 dhar_offset		= f10_dhar_offset(pvt);
	u8 intlv_addr		= dct_sel_interleave_addr(pvt);
	u8 node_id		= dram_dst_node(pvt, range);
	u8 intlv_en		= dram_intlv_en(pvt, range);

	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg);
	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg);

	dct_offset_en		= (u8) ((dct_cont_base_reg >> 3) & BIT(0));
	dct_sel			= (u8) ((dct_cont_base_reg >> 4) & 0x7);

	edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
		 range, sys_addr, get_dram_limit(pvt, range));

	if (!(get_dram_base(pvt, range)  <= sys_addr) &&
	    !(get_dram_limit(pvt, range) >= sys_addr))
		return -EINVAL;

	if (dhar_valid(pvt) &&
	    dhar_base(pvt) <= sys_addr &&
	    sys_addr < BIT_64(32)) {
		amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n",
			    sys_addr);
		return -EINVAL;
	}

	/* Verify sys_addr is within DCT Range. */
1584 1585
	dct_base = (u64) dct_sel_baseaddr(pvt);
	dct_limit = (dct_cont_limit_reg >> 11) & 0x1FFF;
1586 1587

	if (!(dct_cont_base_reg & BIT(0)) &&
1588 1589
	    !(dct_base <= (sys_addr >> 27) &&
	      dct_limit >= (sys_addr >> 27)))
1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601
		return -EINVAL;

	/* Verify number of dct's that participate in channel interleaving. */
	num_dcts_intlv = (int) hweight8(intlv_en);

	if (!(num_dcts_intlv % 2 == 0) || (num_dcts_intlv > 4))
		return -EINVAL;

	channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en,
					     num_dcts_intlv, dct_sel);

	/* Verify we stay within the MAX number of channels allowed */
1602
	if (channel > 3)
1603 1604 1605 1606 1607 1608 1609 1610
		return -EINVAL;

	leg_mmio_hole = (u8) (dct_cont_base_reg >> 1 & BIT(0));

	/* Get normalized DCT addr */
	if (leg_mmio_hole && (sys_addr >= BIT_64(32)))
		chan_offset = dhar_offset;
	else
1611
		chan_offset = dct_base << 27;
1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640

	chan_addr = sys_addr - chan_offset;

	/* remove channel interleave */
	if (num_dcts_intlv == 2) {
		if (intlv_addr == 0x4)
			chan_addr = ((chan_addr >> 9) << 8) |
						(chan_addr & 0xff);
		else if (intlv_addr == 0x5)
			chan_addr = ((chan_addr >> 10) << 9) |
						(chan_addr & 0x1ff);
		else
			return -EINVAL;

	} else if (num_dcts_intlv == 4) {
		if (intlv_addr == 0x4)
			chan_addr = ((chan_addr >> 10) << 8) |
							(chan_addr & 0xff);
		else if (intlv_addr == 0x5)
			chan_addr = ((chan_addr >> 11) << 9) |
							(chan_addr & 0x1ff);
		else
			return -EINVAL;
	}

	if (dct_offset_en) {
		amd64_read_pci_cfg(pvt->F1,
				   DRAM_CONT_HIGH_OFF + (int) channel * 4,
				   &tmp);
1641
		chan_addr +=  (u64) ((tmp >> 11) & 0xfff) << 27;
1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668
	}

	f15h_select_dct(pvt, channel);

	edac_dbg(1, "   Normalized DCT addr: 0x%llx\n", chan_addr);

	/*
	 * Find Chip select:
	 * if channel = 3, then alias it to 1. This is because, in F15 M30h,
	 * there is support for 4 DCT's, but only 2 are currently functional.
	 * They are DCT0 and DCT3. But we have read all registers of DCT3 into
	 * pvt->csels[1]. So we need to use '1' here to get correct info.
	 * Refer F15 M30h BKDG Section 2.10 and 2.10.3 for clarifications.
	 */
	alias_channel =  (channel == 3) ? 1 : channel;

	cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, alias_channel);

	if (cs_found >= 0)
		*chan_sel = alias_channel;

	return cs_found;
}

static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt,
					u64 sys_addr,
					int *chan_sel)
1669
{
1670 1671
	int cs_found = -EINVAL;
	unsigned range;
1672

1673 1674
	for (range = 0; range < DRAM_RANGES; range++) {
		if (!dram_rw(pvt, range))
1675 1676
			continue;

1677 1678 1679 1680
		if (pvt->fam == 0x15 && pvt->model >= 0x30)
			cs_found = f15_m30h_match_to_this_node(pvt, range,
							       sys_addr,
							       chan_sel);
1681

1682 1683
		else if ((get_dram_base(pvt, range)  <= sys_addr) &&
			 (get_dram_limit(pvt, range) >= sys_addr)) {
1684
			cs_found = f1x_match_to_this_node(pvt, range,
1685
							  sys_addr, chan_sel);
1686 1687 1688 1689 1690 1691 1692 1693
			if (cs_found >= 0)
				break;
		}
	}
	return cs_found;
}

/*
1694 1695
 * For reference see "2.8.5 Routing DRAM Requests" in F10 BKDG. This code maps
 * a @sys_addr to NodeID, DCT (channel) and chip select (CSROW).
1696
 *
1697 1698
 * The @sys_addr is usually an error address received from the hardware
 * (MCX_ADDR).
1699
 */
1700
static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
1701
				     struct err_info *err)
1702 1703 1704
{
	struct amd64_pvt *pvt = mci->pvt_info;

1705
	error_address_to_page_and_offset(sys_addr, err);
1706

1707 1708 1709
	err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel);
	if (err->csrow < 0) {
		err->err_code = ERR_CSROW;
1710 1711 1712 1713 1714 1715 1716 1717
		return;
	}

	/*
	 * We need the syndromes for channel detection only when we're
	 * ganged. Otherwise @chan should already contain the channel at
	 * this point.
	 */
1718
	if (dct_ganging_enabled(pvt))
1719
		err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome);
1720 1721 1722
}

/*
1723
 * debug routine to display the memory sizes of all logical DIMMs and its
1724
 * CSROWs
1725
 */
1726
static void debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
1727
{
1728
	int dimm, size0, size1;
1729 1730
	u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;
	u32 dbam  = ctrl ? pvt->dbam1 : pvt->dbam0;
1731

1732
	if (pvt->fam == 0xf) {
1733
		/* K8 families < revF not supported yet */
1734
	       if (pvt->ext_model < K8_REV_F)
1735 1736 1737 1738 1739
			return;
	       else
		       WARN_ON(ctrl != 0);
	}

1740 1741 1742 1743 1744 1745 1746 1747 1748 1749
	if (pvt->fam == 0x10) {
		dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1
							   : pvt->dbam0;
		dcsb = (ctrl && !dct_ganging_enabled(pvt)) ?
				 pvt->csels[1].csbases :
				 pvt->csels[0].csbases;
	} else if (ctrl) {
		dbam = pvt->dbam0;
		dcsb = pvt->csels[1].csbases;
	}
1750 1751
	edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",
		 ctrl, dbam);
1752

1753 1754
	edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);

1755 1756 1757 1758
	/* Dump memory sizes for DIMM and its CSROWs */
	for (dimm = 0; dimm < 4; dimm++) {

		size0 = 0;
1759
		if (dcsb[dimm*2] & DCSB_CS_ENABLE)
1760 1761
			size0 = pvt->ops->dbam_to_cs(pvt, ctrl,
						     DBAM_DIMM(dimm, dbam));
1762 1763

		size1 = 0;
1764
		if (dcsb[dimm*2 + 1] & DCSB_CS_ENABLE)
1765 1766
			size1 = pvt->ops->dbam_to_cs(pvt, ctrl,
						     DBAM_DIMM(dimm, dbam));
1767

1768
		amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n",
1769 1770
				dimm * 2,     size0,
				dimm * 2 + 1, size1);
1771 1772 1773
	}
}

1774
static struct amd64_family_type family_types[] = {
1775
	[K8_CPUS] = {
1776
		.ctl_name = "K8",
1777 1778
		.f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP,
		.f3_id = PCI_DEVICE_ID_AMD_K8_NB_MISC,
1779
		.ops = {
1780 1781 1782
			.early_channel_count	= k8_early_channel_count,
			.map_sysaddr_to_csrow	= k8_map_sysaddr_to_csrow,
			.dbam_to_cs		= k8_dbam_to_chip_select,
1783 1784 1785
		}
	},
	[F10_CPUS] = {
1786
		.ctl_name = "F10h",
1787 1788
		.f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP,
		.f3_id = PCI_DEVICE_ID_AMD_10H_NB_MISC,
1789
		.ops = {
1790
			.early_channel_count	= f1x_early_channel_count,
1791
			.map_sysaddr_to_csrow	= f1x_map_sysaddr_to_csrow,
1792
			.dbam_to_cs		= f10_dbam_to_chip_select,
1793 1794 1795 1796
		}
	},
	[F15_CPUS] = {
		.ctl_name = "F15h",
1797 1798
		.f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1,
		.f3_id = PCI_DEVICE_ID_AMD_15H_NB_F3,
1799
		.ops = {
1800
			.early_channel_count	= f1x_early_channel_count,
1801
			.map_sysaddr_to_csrow	= f1x_map_sysaddr_to_csrow,
1802
			.dbam_to_cs		= f15_dbam_to_chip_select,
1803 1804
		}
	},
1805 1806 1807 1808 1809 1810 1811 1812 1813 1814
	[F15_M30H_CPUS] = {
		.ctl_name = "F15h_M30h",
		.f1_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1,
		.f3_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F3,
		.ops = {
			.early_channel_count	= f1x_early_channel_count,
			.map_sysaddr_to_csrow	= f1x_map_sysaddr_to_csrow,
			.dbam_to_cs		= f16_dbam_to_chip_select,
		}
	},
1815 1816 1817 1818 1819 1820 1821 1822 1823 1824
	[F16_CPUS] = {
		.ctl_name = "F16h",
		.f1_id = PCI_DEVICE_ID_AMD_16H_NB_F1,
		.f3_id = PCI_DEVICE_ID_AMD_16H_NB_F3,
		.ops = {
			.early_channel_count	= f1x_early_channel_count,
			.map_sysaddr_to_csrow	= f1x_map_sysaddr_to_csrow,
			.dbam_to_cs		= f16_dbam_to_chip_select,
		}
	},
1825 1826 1827 1828 1829 1830 1831 1832 1833 1834
	[F16_M30H_CPUS] = {
		.ctl_name = "F16h_M30h",
		.f1_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F1,
		.f3_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F3,
		.ops = {
			.early_channel_count	= f1x_early_channel_count,
			.map_sysaddr_to_csrow	= f1x_map_sysaddr_to_csrow,
			.dbam_to_cs		= f16_dbam_to_chip_select,
		}
	},
1835 1836
};

1837
/*
1838 1839 1840
 * These are tables of eigenvectors (one per line) which can be used for the
 * construction of the syndrome tables. The modified syndrome search algorithm
 * uses those to find the symbol in error and thus the DIMM.
1841
 *
1842
 * Algorithm courtesy of Ross LaFetra from AMD.
1843
 */
1844
static const u16 x4_vectors[] = {
1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880
	0x2f57, 0x1afe, 0x66cc, 0xdd88,
	0x11eb, 0x3396, 0x7f4c, 0xeac8,
	0x0001, 0x0002, 0x0004, 0x0008,
	0x1013, 0x3032, 0x4044, 0x8088,
	0x106b, 0x30d6, 0x70fc, 0xe0a8,
	0x4857, 0xc4fe, 0x13cc, 0x3288,
	0x1ac5, 0x2f4a, 0x5394, 0xa1e8,
	0x1f39, 0x251e, 0xbd6c, 0x6bd8,
	0x15c1, 0x2a42, 0x89ac, 0x4758,
	0x2b03, 0x1602, 0x4f0c, 0xca08,
	0x1f07, 0x3a0e, 0x6b04, 0xbd08,
	0x8ba7, 0x465e, 0x244c, 0x1cc8,
	0x2b87, 0x164e, 0x642c, 0xdc18,
	0x40b9, 0x80de, 0x1094, 0x20e8,
	0x27db, 0x1eb6, 0x9dac, 0x7b58,
	0x11c1, 0x2242, 0x84ac, 0x4c58,
	0x1be5, 0x2d7a, 0x5e34, 0xa718,
	0x4b39, 0x8d1e, 0x14b4, 0x28d8,
	0x4c97, 0xc87e, 0x11fc, 0x33a8,
	0x8e97, 0x497e, 0x2ffc, 0x1aa8,
	0x16b3, 0x3d62, 0x4f34, 0x8518,
	0x1e2f, 0x391a, 0x5cac, 0xf858,
	0x1d9f, 0x3b7a, 0x572c, 0xfe18,
	0x15f5, 0x2a5a, 0x5264, 0xa3b8,
	0x1dbb, 0x3b66, 0x715c, 0xe3f8,
	0x4397, 0xc27e, 0x17fc, 0x3ea8,
	0x1617, 0x3d3e, 0x6464, 0xb8b8,
	0x23ff, 0x12aa, 0xab6c, 0x56d8,
	0x2dfb, 0x1ba6, 0x913c, 0x7328,
	0x185d, 0x2ca6, 0x7914, 0x9e28,
	0x171b, 0x3e36, 0x7d7c, 0xebe8,
	0x4199, 0x82ee, 0x19f4, 0x2e58,
	0x4807, 0xc40e, 0x130c, 0x3208,
	0x1905, 0x2e0a, 0x5804, 0xac08,
	0x213f, 0x132a, 0xadfc, 0x5ba8,
	0x19a9, 0x2efe, 0xb5cc, 0x6f88,
1881 1882
};

1883
static const u16 x8_vectors[] = {
1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904
	0x0145, 0x028a, 0x2374, 0x43c8, 0xa1f0, 0x0520, 0x0a40, 0x1480,
	0x0211, 0x0422, 0x0844, 0x1088, 0x01b0, 0x44e0, 0x23c0, 0xed80,
	0x1011, 0x0116, 0x022c, 0x0458, 0x08b0, 0x8c60, 0x2740, 0x4e80,
	0x0411, 0x0822, 0x1044, 0x0158, 0x02b0, 0x2360, 0x46c0, 0xab80,
	0x0811, 0x1022, 0x012c, 0x0258, 0x04b0, 0x4660, 0x8cc0, 0x2780,
	0x2071, 0x40e2, 0xa0c4, 0x0108, 0x0210, 0x0420, 0x0840, 0x1080,
	0x4071, 0x80e2, 0x0104, 0x0208, 0x0410, 0x0820, 0x1040, 0x2080,
	0x8071, 0x0102, 0x0204, 0x0408, 0x0810, 0x1020, 0x2040, 0x4080,
	0x019d, 0x03d6, 0x136c, 0x2198, 0x50b0, 0xb2e0, 0x0740, 0x0e80,
	0x0189, 0x03ea, 0x072c, 0x0e58, 0x1cb0, 0x56e0, 0x37c0, 0xf580,
	0x01fd, 0x0376, 0x06ec, 0x0bb8, 0x1110, 0x2220, 0x4440, 0x8880,
	0x0163, 0x02c6, 0x1104, 0x0758, 0x0eb0, 0x2be0, 0x6140, 0xc280,
	0x02fd, 0x01c6, 0x0b5c, 0x1108, 0x07b0, 0x25a0, 0x8840, 0x6180,
	0x0801, 0x012e, 0x025c, 0x04b8, 0x1370, 0x26e0, 0x57c0, 0xb580,
	0x0401, 0x0802, 0x015c, 0x02b8, 0x22b0, 0x13e0, 0x7140, 0xe280,
	0x0201, 0x0402, 0x0804, 0x01b8, 0x11b0, 0x31a0, 0x8040, 0x7180,
	0x0101, 0x0202, 0x0404, 0x0808, 0x1010, 0x2020, 0x4040, 0x8080,
	0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
	0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000,
};

1905
static int decode_syndrome(u16 syndrome, const u16 *vectors, unsigned num_vecs,
1906
			   unsigned v_dim)
1907
{
1908 1909 1910 1911
	unsigned int i, err_sym;

	for (err_sym = 0; err_sym < num_vecs / v_dim; err_sym++) {
		u16 s = syndrome;
1912 1913
		unsigned v_idx =  err_sym * v_dim;
		unsigned v_end = (err_sym + 1) * v_dim;
1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925

		/* walk over all 16 bits of the syndrome */
		for (i = 1; i < (1U << 16); i <<= 1) {

			/* if bit is set in that eigenvector... */
			if (v_idx < v_end && vectors[v_idx] & i) {
				u16 ev_comp = vectors[v_idx++];

				/* ... and bit set in the modified syndrome, */
				if (s & i) {
					/* remove it. */
					s ^= ev_comp;
1926

1927 1928 1929
					if (!s)
						return err_sym;
				}
1930

1931 1932 1933 1934
			} else if (s & i)
				/* can't get to zero, move to next symbol */
				break;
		}
1935 1936
	}

1937
	edac_dbg(0, "syndrome(%x) not found\n", syndrome);
1938 1939
	return -1;
}
1940

1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982
static int map_err_sym_to_channel(int err_sym, int sym_size)
{
	if (sym_size == 4)
		switch (err_sym) {
		case 0x20:
		case 0x21:
			return 0;
			break;
		case 0x22:
		case 0x23:
			return 1;
			break;
		default:
			return err_sym >> 4;
			break;
		}
	/* x8 symbols */
	else
		switch (err_sym) {
		/* imaginary bits not in a DIMM */
		case 0x10:
			WARN(1, KERN_ERR "Invalid error symbol: 0x%x\n",
					  err_sym);
			return -1;
			break;

		case 0x11:
			return 0;
			break;
		case 0x12:
			return 1;
			break;
		default:
			return err_sym >> 3;
			break;
		}
	return -1;
}

static int get_channel_from_ecc_syndrome(struct mem_ctl_info *mci, u16 syndrome)
{
	struct amd64_pvt *pvt = mci->pvt_info;
1983 1984
	int err_sym = -1;

1985
	if (pvt->ecc_sym_sz == 8)
1986 1987
		err_sym = decode_syndrome(syndrome, x8_vectors,
					  ARRAY_SIZE(x8_vectors),
1988 1989
					  pvt->ecc_sym_sz);
	else if (pvt->ecc_sym_sz == 4)
1990 1991
		err_sym = decode_syndrome(syndrome, x4_vectors,
					  ARRAY_SIZE(x4_vectors),
1992
					  pvt->ecc_sym_sz);
1993
	else {
1994
		amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz);
1995
		return err_sym;
1996
	}
1997

1998
	return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz);
1999 2000
}

2001 2002
static void __log_bus_error(struct mem_ctl_info *mci, struct err_info *err,
			    u8 ecc_type)
2003
{
2004 2005
	enum hw_event_mc_err_type err_type;
	const char *string;
2006

2007 2008 2009 2010 2011 2012
	if (ecc_type == 2)
		err_type = HW_EVENT_ERR_CORRECTED;
	else if (ecc_type == 1)
		err_type = HW_EVENT_ERR_UNCORRECTED;
	else {
		WARN(1, "Something is rotten in the state of Denmark.\n");
2013 2014 2015
		return;
	}

2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031
	switch (err->err_code) {
	case DECODE_OK:
		string = "";
		break;
	case ERR_NODE:
		string = "Failed to map error addr to a node";
		break;
	case ERR_CSROW:
		string = "Failed to map error addr to a csrow";
		break;
	case ERR_CHANNEL:
		string = "unknown syndrome - possible error reporting race";
		break;
	default:
		string = "WTF error";
		break;
2032
	}
2033 2034 2035 2036 2037

	edac_mc_handle_error(err_type, mci, 1,
			     err->page, err->offset, err->syndrome,
			     err->csrow, err->channel, -1,
			     string, "");
2038 2039
}

2040
static inline void decode_bus_error(int node_id, struct mce *m)
2041
{
2042
	struct mem_ctl_info *mci = mcis[node_id];
2043
	struct amd64_pvt *pvt = mci->pvt_info;
2044
	u8 ecc_type = (m->status >> 45) & 0x3;
2045 2046
	u8 xec = XEC(m->status, 0x1f);
	u16 ec = EC(m->status);
2047 2048
	u64 sys_addr;
	struct err_info err;
2049

2050
	/* Bail out early if this was an 'observed' error */
2051
	if (PP(ec) == NBSL_PP_OBS)
2052
		return;
2053

2054 2055
	/* Do only ECC errors */
	if (xec && xec != F10_NBSL_EXT_ERR_ECC)
2056 2057
		return;

2058 2059
	memset(&err, 0, sizeof(err));

2060
	sys_addr = get_error_address(pvt, m);
2061

2062
	if (ecc_type == 2)
2063 2064 2065 2066 2067
		err.syndrome = extract_syndrome(m->status);

	pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err);

	__log_bus_error(mci, &err, ecc_type);
2068 2069
}

2070
/*
2071
 * Use pvt->F2 which contains the F2 CPU PCI device to get the related
2072
 * F1 (AddrMap) and F3 (Misc) devices. Return negative value on error.
2073
 */
2074
static int reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 f1_id, u16 f3_id)
2075 2076
{
	/* Reserve the ADDRESS MAP Device */
2077 2078
	pvt->F1 = pci_get_related_function(pvt->F2->vendor, f1_id, pvt->F2);
	if (!pvt->F1) {
2079 2080 2081
		amd64_err("error address map device not found: "
			  "vendor %x device 0x%x (broken BIOS?)\n",
			  PCI_VENDOR_ID_AMD, f1_id);
2082
		return -ENODEV;
2083 2084 2085
	}

	/* Reserve the MISC Device */
2086 2087 2088 2089
	pvt->F3 = pci_get_related_function(pvt->F2->vendor, f3_id, pvt->F2);
	if (!pvt->F3) {
		pci_dev_put(pvt->F1);
		pvt->F1 = NULL;
2090

2091 2092 2093
		amd64_err("error F3 device not found: "
			  "vendor %x device 0x%x (broken BIOS?)\n",
			  PCI_VENDOR_ID_AMD, f3_id);
2094

2095
		return -ENODEV;
2096
	}
2097 2098 2099
	edac_dbg(1, "F1: %s\n", pci_name(pvt->F1));
	edac_dbg(1, "F2: %s\n", pci_name(pvt->F2));
	edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
2100 2101 2102 2103

	return 0;
}

2104
static void free_mc_sibling_devs(struct amd64_pvt *pvt)
2105
{
2106 2107
	pci_dev_put(pvt->F1);
	pci_dev_put(pvt->F3);
2108 2109 2110 2111 2112 2113
}

/*
 * Retrieve the hardware registers of the memory controller (this includes the
 * 'Address Map' and 'Misc' device regs)
 */
2114
static void read_mc_regs(struct amd64_pvt *pvt)
2115
{
2116
	unsigned range;
2117
	u64 msr_val;
2118
	u32 tmp;
2119 2120 2121 2122 2123

	/*
	 * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since
	 * those are Read-As-Zero
	 */
2124
	rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem);
2125
	edac_dbg(0, "  TOP_MEM:  0x%016llx\n", pvt->top_mem);
2126 2127 2128 2129

	/* check first whether TOP_MEM2 is enabled */
	rdmsrl(MSR_K8_SYSCFG, msr_val);
	if (msr_val & (1U << 21)) {
2130
		rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2);
2131
		edac_dbg(0, "  TOP_MEM2: 0x%016llx\n", pvt->top_mem2);
2132
	} else
2133
		edac_dbg(0, "  TOP_MEM2 disabled\n");
2134

2135
	amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap);
2136

2137
	read_dram_ctl_register(pvt);
2138

2139 2140
	for (range = 0; range < DRAM_RANGES; range++) {
		u8 rw;
2141

2142 2143 2144 2145 2146 2147 2148
		/* read settings for this DRAM range */
		read_dram_base_limit_regs(pvt, range);

		rw = dram_rw(pvt, range);
		if (!rw)
			continue;

2149 2150 2151 2152
		edac_dbg(1, "  DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n",
			 range,
			 get_dram_base(pvt, range),
			 get_dram_limit(pvt, range));
2153

2154 2155 2156 2157 2158 2159
		edac_dbg(1, "   IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n",
			 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled",
			 (rw & 0x1) ? "R" : "-",
			 (rw & 0x2) ? "W" : "-",
			 dram_intlv_sel(pvt, range),
			 dram_dst_node(pvt, range));
2160 2161
	}

2162
	read_dct_base_mask(pvt);
2163

2164
	amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar);
2165
	amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0);
2166

2167
	amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare);
2168

2169 2170
	amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0);
	amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0);
2171

2172
	if (!dct_ganging_enabled(pvt)) {
2173 2174
		amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1);
		amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1);
2175
	}
2176

2177 2178
	pvt->ecc_sym_sz = 4;

2179
	if (pvt->fam >= 0x10) {
2180
		amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
2181
		/* F16h has only DCT0, so no need to read dbam1 */
2182
		if (pvt->fam != 0x16)
2183
			amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1);
2184

2185
		/* F10h, revD and later can do x8 ECC too */
2186
		if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25))
2187 2188
			pvt->ecc_sym_sz = 8;
	}
2189
	dump_misc_regs(pvt);
2190 2191 2192 2193 2194 2195
}

/*
 * NOTE: CPU Revision Dependent code
 *
 * Input:
2196
 *	@csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1)
2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225
 *	k8 private pointer to -->
 *			DRAM Bank Address mapping register
 *			node_id
 *			DCL register where dual_channel_active is
 *
 * The DBAM register consists of 4 sets of 4 bits each definitions:
 *
 * Bits:	CSROWs
 * 0-3		CSROWs 0 and 1
 * 4-7		CSROWs 2 and 3
 * 8-11		CSROWs 4 and 5
 * 12-15	CSROWs 6 and 7
 *
 * Values range from: 0 to 15
 * The meaning of the values depends on CPU revision and dual-channel state,
 * see relevant BKDG more info.
 *
 * The memory controller provides for total of only 8 CSROWs in its current
 * architecture. Each "pair" of CSROWs normally represents just one DIMM in
 * single channel or two (2) DIMMs in dual channel mode.
 *
 * The following code logic collapses the various tables for CSROW based on CPU
 * revision.
 *
 * Returns:
 *	The number of PAGE_SIZE pages on the specified CSROW number it
 *	encompasses
 *
 */
2226
static u32 get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
2227
{
2228
	u32 cs_mode, nr_pages;
2229
	u32 dbam = dct ? pvt->dbam1 : pvt->dbam0;
2230

2231

2232 2233 2234 2235 2236 2237 2238
	/*
	 * The math on this doesn't look right on the surface because x/2*4 can
	 * be simplified to x*2 but this expression makes use of the fact that
	 * it is integral math where 1/2=0. This intermediate value becomes the
	 * number of bits to shift the DBAM register to extract the proper CSROW
	 * field.
	 */
B
Borislav Petkov 已提交
2239
	cs_mode = DBAM_DIMM(csrow_nr / 2, dbam);
2240

2241
	nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode) << (20 - PAGE_SHIFT);
2242

2243 2244 2245
	edac_dbg(0, "csrow: %d, channel: %d, DBAM idx: %d\n",
		    csrow_nr, dct,  cs_mode);
	edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);
2246 2247 2248 2249 2250 2251 2252 2253

	return nr_pages;
}

/*
 * Initialize the array of csrow attribute instances, based on the values
 * from pci config hardware registers.
 */
2254
static int init_csrows(struct mem_ctl_info *mci)
2255
{
2256
	struct amd64_pvt *pvt = mci->pvt_info;
2257
	struct csrow_info *csrow;
2258
	struct dimm_info *dimm;
2259
	enum edac_type edac_mode;
2260 2261
	enum mem_type mtype;
	int i, j, empty = 1;
2262
	int nr_pages = 0;
2263
	u32 val;
2264

2265
	amd64_read_pci_cfg(pvt->F3, NBCFG, &val);
2266

2267
	pvt->nbcfg = val;
2268

2269 2270 2271
	edac_dbg(0, "node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",
		 pvt->mc_node_id, val,
		 !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE));
2272

2273 2274 2275
	/*
	 * We iterate over DCT0 here but we look at DCT1 in parallel, if needed.
	 */
2276
	for_each_chip_select(i, 0, pvt) {
2277 2278
		bool row_dct0 = !!csrow_enabled(i, 0, pvt);
		bool row_dct1 = false;
2279

2280
		if (pvt->fam != 0xf)
2281 2282 2283
			row_dct1 = !!csrow_enabled(i, 1, pvt);

		if (!row_dct0 && !row_dct1)
2284 2285
			continue;

2286
		csrow = mci->csrows[i];
2287
		empty = 0;
2288 2289 2290 2291

		edac_dbg(1, "MC node: %d, csrow: %d\n",
			    pvt->mc_node_id, i);

2292
		if (row_dct0) {
2293
			nr_pages = get_csrow_nr_pages(pvt, 0, i);
2294 2295
			csrow->channels[0]->dimm->nr_pages = nr_pages;
		}
2296

2297
		/* K8 has only one DCT */
2298
		if (pvt->fam != 0xf && row_dct1) {
2299
			int row_dct1_pages = get_csrow_nr_pages(pvt, 1, i);
2300 2301 2302 2303

			csrow->channels[1]->dimm->nr_pages = row_dct1_pages;
			nr_pages += row_dct1_pages;
		}
2304

2305
		mtype = determine_memory_type(pvt, i);
2306

2307
		edac_dbg(1, "Total csrow%d pages: %u\n", i, nr_pages);
2308 2309 2310 2311

		/*
		 * determine whether CHIPKILL or JUST ECC or NO ECC is operating
		 */
2312
		if (pvt->nbcfg & NBCFG_ECC_ENABLE)
2313 2314
			edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL) ?
				    EDAC_S4ECD4ED : EDAC_SECDED;
2315
		else
2316 2317 2318
			edac_mode = EDAC_NONE;

		for (j = 0; j < pvt->channel_count; j++) {
2319 2320 2321
			dimm = csrow->channels[j]->dimm;
			dimm->mtype = mtype;
			dimm->edac_mode = edac_mode;
2322
		}
2323 2324 2325 2326
	}

	return empty;
}
2327

2328
/* get all cores on this DCT */
2329
static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, u16 nid)
2330 2331 2332 2333 2334 2335 2336 2337 2338
{
	int cpu;

	for_each_online_cpu(cpu)
		if (amd_get_nb_id(cpu) == nid)
			cpumask_set_cpu(cpu, mask);
}

/* check MCG_CTL on all the cpus on this node */
2339
static bool nb_mce_bank_enabled_on_node(u16 nid)
2340 2341
{
	cpumask_var_t mask;
2342
	int cpu, nbe;
2343 2344 2345
	bool ret = false;

	if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) {
2346
		amd64_warn("%s: Error allocating mask\n", __func__);
2347 2348 2349 2350 2351 2352 2353 2354
		return false;
	}

	get_cpus_on_this_dct_cpumask(mask, nid);

	rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs);

	for_each_cpu(cpu, mask) {
2355
		struct msr *reg = per_cpu_ptr(msrs, cpu);
2356
		nbe = reg->l & MSR_MCGCTL_NBE;
2357

2358 2359 2360
		edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
			 cpu, reg->q,
			 (nbe ? "enabled" : "disabled"));
2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371

		if (!nbe)
			goto out;
	}
	ret = true;

out:
	free_cpumask_var(mask);
	return ret;
}

2372
static int toggle_ecc_err_reporting(struct ecc_settings *s, u16 nid, bool on)
2373 2374
{
	cpumask_var_t cmask;
2375
	int cpu;
2376 2377

	if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) {
2378
		amd64_warn("%s: error allocating mask\n", __func__);
2379 2380 2381
		return false;
	}

2382
	get_cpus_on_this_dct_cpumask(cmask, nid);
2383 2384 2385 2386 2387

	rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);

	for_each_cpu(cpu, cmask) {

2388 2389
		struct msr *reg = per_cpu_ptr(msrs, cpu);

2390
		if (on) {
2391
			if (reg->l & MSR_MCGCTL_NBE)
2392
				s->flags.nb_mce_enable = 1;
2393

2394
			reg->l |= MSR_MCGCTL_NBE;
2395 2396
		} else {
			/*
2397
			 * Turn off NB MCE reporting only when it was off before
2398
			 */
2399
			if (!s->flags.nb_mce_enable)
2400
				reg->l &= ~MSR_MCGCTL_NBE;
2401 2402 2403 2404 2405 2406 2407 2408 2409
		}
	}
	wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);

	free_cpumask_var(cmask);

	return 0;
}

2410
static bool enable_ecc_error_reporting(struct ecc_settings *s, u16 nid,
2411
				       struct pci_dev *F3)
2412
{
2413
	bool ret = true;
B
Borislav Petkov 已提交
2414
	u32 value, mask = 0x3;		/* UECC/CECC enable */
2415

2416 2417 2418 2419 2420
	if (toggle_ecc_err_reporting(s, nid, ON)) {
		amd64_warn("Error enabling ECC reporting over MCGCTL!\n");
		return false;
	}

B
Borislav Petkov 已提交
2421
	amd64_read_pci_cfg(F3, NBCTL, &value);
2422

2423 2424
	s->old_nbctl   = value & mask;
	s->nbctl_valid = true;
2425 2426

	value |= mask;
B
Borislav Petkov 已提交
2427
	amd64_write_pci_cfg(F3, NBCTL, value);
2428

2429
	amd64_read_pci_cfg(F3, NBCFG, &value);
2430

2431 2432
	edac_dbg(0, "1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
		 nid, value, !!(value & NBCFG_ECC_ENABLE));
2433

2434
	if (!(value & NBCFG_ECC_ENABLE)) {
2435
		amd64_warn("DRAM ECC disabled on this node, enabling...\n");
2436

2437
		s->flags.nb_ecc_prev = 0;
2438

2439
		/* Attempt to turn on DRAM ECC Enable */
2440 2441
		value |= NBCFG_ECC_ENABLE;
		amd64_write_pci_cfg(F3, NBCFG, value);
2442

2443
		amd64_read_pci_cfg(F3, NBCFG, &value);
2444

2445
		if (!(value & NBCFG_ECC_ENABLE)) {
2446 2447
			amd64_warn("Hardware rejected DRAM ECC enable,"
				   "check memory DIMM configuration.\n");
2448
			ret = false;
2449
		} else {
2450
			amd64_info("Hardware accepted DRAM ECC Enable\n");
2451
		}
2452
	} else {
2453
		s->flags.nb_ecc_prev = 1;
2454
	}
2455

2456 2457
	edac_dbg(0, "2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
		 nid, value, !!(value & NBCFG_ECC_ENABLE));
2458

2459
	return ret;
2460 2461
}

2462
static void restore_ecc_error_reporting(struct ecc_settings *s, u16 nid,
2463
					struct pci_dev *F3)
2464
{
B
Borislav Petkov 已提交
2465 2466
	u32 value, mask = 0x3;		/* UECC/CECC enable */

2467

2468
	if (!s->nbctl_valid)
2469 2470
		return;

B
Borislav Petkov 已提交
2471
	amd64_read_pci_cfg(F3, NBCTL, &value);
2472
	value &= ~mask;
2473
	value |= s->old_nbctl;
2474

B
Borislav Petkov 已提交
2475
	amd64_write_pci_cfg(F3, NBCTL, value);
2476

2477 2478
	/* restore previous BIOS DRAM ECC "off" setting we force-enabled */
	if (!s->flags.nb_ecc_prev) {
2479 2480 2481
		amd64_read_pci_cfg(F3, NBCFG, &value);
		value &= ~NBCFG_ECC_ENABLE;
		amd64_write_pci_cfg(F3, NBCFG, value);
2482 2483 2484
	}

	/* restore the NB Enable MCGCTL bit */
2485
	if (toggle_ecc_err_reporting(s, nid, OFF))
2486
		amd64_warn("Error restoring NB MCGCTL settings!\n");
2487 2488 2489
}

/*
2490 2491 2492 2493
 * EDAC requires that the BIOS have ECC enabled before
 * taking over the processing of ECC errors. A command line
 * option allows to force-enable hardware ECC later in
 * enable_ecc_error_reporting().
2494
 */
2495 2496 2497 2498 2499
static const char *ecc_msg =
	"ECC disabled in the BIOS or no ECC capability, module will not load.\n"
	" Either enable ECC checking or force module loading by setting "
	"'ecc_enable_override'.\n"
	" (Note that use of the override may cause unknown side effects.)\n";
2500

2501
static bool ecc_enabled(struct pci_dev *F3, u16 nid)
2502 2503
{
	u32 value;
2504
	u8 ecc_en = 0;
2505
	bool nb_mce_en = false;
2506

2507
	amd64_read_pci_cfg(F3, NBCFG, &value);
2508

2509
	ecc_en = !!(value & NBCFG_ECC_ENABLE);
2510
	amd64_info("DRAM ECC %s.\n", (ecc_en ? "enabled" : "disabled"));
2511

2512
	nb_mce_en = nb_mce_bank_enabled_on_node(nid);
2513
	if (!nb_mce_en)
2514 2515 2516
		amd64_notice("NB MCE bank disabled, set MSR "
			     "0x%08x[4] on node %d to enable.\n",
			     MSR_IA32_MCG_CTL, nid);
2517

2518 2519 2520 2521 2522
	if (!ecc_en || !nb_mce_en) {
		amd64_notice("%s", ecc_msg);
		return false;
	}
	return true;
2523 2524
}

2525
static int set_mc_sysfs_attrs(struct mem_ctl_info *mci)
2526
{
2527
	struct amd64_pvt *pvt = mci->pvt_info;
2528
	int rc;
2529

2530 2531 2532
	rc = amd64_create_sysfs_dbg_files(mci);
	if (rc < 0)
		return rc;
2533

2534
	if (pvt->fam >= 0x10) {
2535 2536 2537 2538 2539 2540 2541
		rc = amd64_create_sysfs_inject_files(mci);
		if (rc < 0)
			return rc;
	}

	return 0;
}
2542

2543 2544
static void del_mc_sysfs_attrs(struct mem_ctl_info *mci)
{
2545 2546
	struct amd64_pvt *pvt = mci->pvt_info;

2547
	amd64_remove_sysfs_dbg_files(mci);
2548

2549
	if (pvt->fam >= 0x10)
2550
		amd64_remove_sysfs_inject_files(mci);
2551 2552
}

2553 2554
static void setup_mci_misc_attrs(struct mem_ctl_info *mci,
				 struct amd64_family_type *fam)
2555 2556 2557 2558 2559 2560
{
	struct amd64_pvt *pvt = mci->pvt_info;

	mci->mtype_cap		= MEM_FLAG_DDR2 | MEM_FLAG_RDDR2;
	mci->edac_ctl_cap	= EDAC_FLAG_NONE;

2561
	if (pvt->nbcap & NBCAP_SECDED)
2562 2563
		mci->edac_ctl_cap |= EDAC_FLAG_SECDED;

2564
	if (pvt->nbcap & NBCAP_CHIPKILL)
2565 2566
		mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;

2567
	mci->edac_cap		= determine_edac_cap(pvt);
2568 2569
	mci->mod_name		= EDAC_MOD_STR;
	mci->mod_ver		= EDAC_AMD64_VERSION;
2570
	mci->ctl_name		= fam->ctl_name;
2571
	mci->dev_name		= pci_name(pvt->F2);
2572 2573 2574
	mci->ctl_page_to_phys	= NULL;

	/* memory scrubber interface */
2575 2576
	mci->set_sdram_scrub_rate = set_scrub_rate;
	mci->get_sdram_scrub_rate = get_scrub_rate;
2577 2578
}

2579 2580 2581
/*
 * returns a pointer to the family descriptor on success, NULL otherwise.
 */
2582
static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
2583
{
2584 2585
	struct amd64_family_type *fam_type = NULL;

2586
	pvt->ext_model  = boot_cpu_data.x86_model >> 4;
2587
	pvt->stepping	= boot_cpu_data.x86_mask;
2588 2589 2590 2591
	pvt->model	= boot_cpu_data.x86_model;
	pvt->fam	= boot_cpu_data.x86;

	switch (pvt->fam) {
2592
	case 0xf:
2593 2594
		fam_type	= &family_types[K8_CPUS];
		pvt->ops	= &family_types[K8_CPUS].ops;
2595
		break;
2596

2597
	case 0x10:
2598 2599
		fam_type	= &family_types[F10_CPUS];
		pvt->ops	= &family_types[F10_CPUS].ops;
2600 2601 2602
		break;

	case 0x15:
2603
		if (pvt->model == 0x30) {
2604 2605
			fam_type = &family_types[F15_M30H_CPUS];
			pvt->ops = &family_types[F15_M30H_CPUS].ops;
2606 2607 2608
			break;
		}

2609 2610
		fam_type	= &family_types[F15_CPUS];
		pvt->ops	= &family_types[F15_CPUS].ops;
2611 2612
		break;

2613
	case 0x16:
2614 2615 2616 2617 2618
		if (pvt->model == 0x30) {
			fam_type = &family_types[F16_M30H_CPUS];
			pvt->ops = &family_types[F16_M30H_CPUS].ops;
			break;
		}
2619 2620
		fam_type	= &family_types[F16_CPUS];
		pvt->ops	= &family_types[F16_CPUS].ops;
2621 2622
		break;

2623
	default:
2624
		amd64_err("Unsupported family!\n");
2625
		return NULL;
2626
	}
2627

2628
	amd64_info("%s %sdetected (node %d).\n", fam_type->ctl_name,
2629
		     (pvt->fam == 0xf ?
2630 2631 2632
				(pvt->ext_model >= K8_REV_F  ? "revF or later "
							     : "revE or earlier ")
				 : ""), pvt->mc_node_id);
2633
	return fam_type;
2634 2635
}

2636
static int init_one_instance(struct pci_dev *F2)
2637 2638
{
	struct amd64_pvt *pvt = NULL;
2639
	struct amd64_family_type *fam_type = NULL;
2640
	struct mem_ctl_info *mci = NULL;
2641
	struct edac_mc_layer layers[2];
2642
	int err = 0, ret;
2643
	u16 nid = amd_get_node_id(F2);
2644 2645 2646 2647

	ret = -ENOMEM;
	pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL);
	if (!pvt)
2648
		goto err_ret;
2649

2650
	pvt->mc_node_id	= nid;
2651
	pvt->F2 = F2;
2652

2653
	ret = -EINVAL;
2654
	fam_type = per_family_init(pvt);
2655
	if (!fam_type)
2656 2657
		goto err_free;

2658
	ret = -ENODEV;
2659
	err = reserve_mc_sibling_devs(pvt, fam_type->f1_id, fam_type->f3_id);
2660 2661 2662
	if (err)
		goto err_free;

2663
	read_mc_regs(pvt);
2664 2665 2666 2667

	/*
	 * We need to determine how many memory channels there are. Then use
	 * that information for calculating the size of the dynamic instance
2668
	 * tables in the 'mci' structure.
2669
	 */
2670
	ret = -EINVAL;
2671 2672
	pvt->channel_count = pvt->ops->early_channel_count(pvt);
	if (pvt->channel_count < 0)
2673
		goto err_siblings;
2674 2675

	ret = -ENOMEM;
2676 2677 2678 2679
	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = pvt->csels[0].b_cnt;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
2680 2681 2682 2683 2684 2685 2686

	/*
	 * Always allocate two channels since we can have setups with DIMMs on
	 * only one channel. Also, this simplifies handling later for the price
	 * of a couple of KBs tops.
	 */
	layers[1].size = 2;
2687
	layers[1].is_virt_csrow = false;
2688

2689
	mci = edac_mc_alloc(nid, ARRAY_SIZE(layers), layers, 0);
2690
	if (!mci)
2691
		goto err_siblings;
2692 2693

	mci->pvt_info = pvt;
2694
	mci->pdev = &pvt->F2->dev;
2695

2696
	setup_mci_misc_attrs(mci, fam_type);
2697 2698

	if (init_csrows(mci))
2699 2700 2701 2702
		mci->edac_cap = EDAC_FLAG_NONE;

	ret = -ENODEV;
	if (edac_mc_add_mc(mci)) {
2703
		edac_dbg(1, "failed edac_mc_add_mc()\n");
2704 2705
		goto err_add_mc;
	}
2706
	if (set_mc_sysfs_attrs(mci)) {
2707
		edac_dbg(1, "failed edac_mc_add_mc()\n");
2708 2709
		goto err_add_sysfs;
	}
2710

2711 2712 2713 2714
	/* register stuff with EDAC MCE */
	if (report_gart_errors)
		amd_report_gart_errors(true);

2715
	amd_register_ecc_decoder(decode_bus_error);
2716

2717 2718 2719 2720
	mcis[nid] = mci;

	atomic_inc(&drv_instances);

2721 2722
	return 0;

2723 2724
err_add_sysfs:
	edac_mc_del_mc(mci->pdev);
2725 2726 2727
err_add_mc:
	edac_mc_free(mci);

2728 2729
err_siblings:
	free_mc_sibling_devs(pvt);
2730

2731 2732
err_free:
	kfree(pvt);
2733

2734
err_ret:
2735 2736 2737
	return ret;
}

2738 2739
static int probe_one_instance(struct pci_dev *pdev,
			      const struct pci_device_id *mc_type)
2740
{
2741
	u16 nid = amd_get_node_id(pdev);
2742
	struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
2743
	struct ecc_settings *s;
2744
	int ret = 0;
2745 2746

	ret = pci_enable_device(pdev);
2747
	if (ret < 0) {
2748
		edac_dbg(0, "ret=%d\n", ret);
2749 2750
		return -EIO;
	}
2751

2752 2753 2754
	ret = -ENOMEM;
	s = kzalloc(sizeof(struct ecc_settings), GFP_KERNEL);
	if (!s)
2755
		goto err_out;
2756 2757 2758

	ecc_stngs[nid] = s;

2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770
	if (!ecc_enabled(F3, nid)) {
		ret = -ENODEV;

		if (!ecc_enable_override)
			goto err_enable;

		amd64_warn("Forcing ECC on!\n");

		if (!enable_ecc_error_reporting(s, nid, F3))
			goto err_enable;
	}

2771
	ret = init_one_instance(pdev);
2772
	if (ret < 0) {
2773
		amd64_err("Error probing instance: %d\n", nid);
2774 2775
		restore_ecc_error_reporting(s, nid, F3);
	}
2776 2777

	return ret;
2778 2779 2780 2781 2782 2783 2784

err_enable:
	kfree(s);
	ecc_stngs[nid] = NULL;

err_out:
	return ret;
2785 2786
}

2787
static void remove_one_instance(struct pci_dev *pdev)
2788 2789 2790
{
	struct mem_ctl_info *mci;
	struct amd64_pvt *pvt;
2791
	u16 nid = amd_get_node_id(pdev);
2792 2793
	struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
	struct ecc_settings *s = ecc_stngs[nid];
2794

2795
	mci = find_mci_by_dev(&pdev->dev);
2796 2797
	WARN_ON(!mci);

2798
	del_mc_sysfs_attrs(mci);
2799 2800 2801 2802 2803 2804 2805
	/* Remove from EDAC CORE tracking list */
	mci = edac_mc_del_mc(&pdev->dev);
	if (!mci)
		return;

	pvt = mci->pvt_info;

2806
	restore_ecc_error_reporting(s, nid, F3);
2807

2808
	free_mc_sibling_devs(pvt);
2809

2810 2811
	/* unregister from EDAC MCE */
	amd_report_gart_errors(false);
2812
	amd_unregister_ecc_decoder(decode_bus_error);
2813

2814 2815
	kfree(ecc_stngs[nid]);
	ecc_stngs[nid] = NULL;
2816

2817
	/* Free the EDAC CORE resources */
2818
	mci->pvt_info = NULL;
2819
	mcis[nid] = NULL;
2820 2821

	kfree(pvt);
2822 2823 2824 2825 2826 2827 2828 2829
	edac_mc_free(mci);
}

/*
 * This table is part of the interface for loading drivers for PCI devices. The
 * PCI core identifies what devices are on a system during boot, and then
 * inquiry this table to see if this driver is for a given device found.
 */
2830
static const struct pci_device_id amd64_pci_table[] = {
2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846
	{
		.vendor		= PCI_VENDOR_ID_AMD,
		.device		= PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,
		.subvendor	= PCI_ANY_ID,
		.subdevice	= PCI_ANY_ID,
		.class		= 0,
		.class_mask	= 0,
	},
	{
		.vendor		= PCI_VENDOR_ID_AMD,
		.device		= PCI_DEVICE_ID_AMD_10H_NB_DRAM,
		.subvendor	= PCI_ANY_ID,
		.subdevice	= PCI_ANY_ID,
		.class		= 0,
		.class_mask	= 0,
	},
2847 2848 2849 2850 2851 2852 2853 2854
	{
		.vendor		= PCI_VENDOR_ID_AMD,
		.device		= PCI_DEVICE_ID_AMD_15H_NB_F2,
		.subvendor	= PCI_ANY_ID,
		.subdevice	= PCI_ANY_ID,
		.class		= 0,
		.class_mask	= 0,
	},
2855 2856 2857 2858 2859 2860 2861 2862
	{
		.vendor		= PCI_VENDOR_ID_AMD,
		.device		= PCI_DEVICE_ID_AMD_15H_M30H_NB_F2,
		.subvendor	= PCI_ANY_ID,
		.subdevice	= PCI_ANY_ID,
		.class		= 0,
		.class_mask	= 0,
	},
2863 2864 2865 2866 2867 2868 2869 2870
	{
		.vendor		= PCI_VENDOR_ID_AMD,
		.device		= PCI_DEVICE_ID_AMD_16H_NB_F2,
		.subvendor	= PCI_ANY_ID,
		.subdevice	= PCI_ANY_ID,
		.class		= 0,
		.class_mask	= 0,
	},
2871 2872 2873 2874 2875 2876 2877 2878
	{
		.vendor		= PCI_VENDOR_ID_AMD,
		.device		= PCI_DEVICE_ID_AMD_16H_M30H_NB_F2,
		.subvendor	= PCI_ANY_ID,
		.subdevice	= PCI_ANY_ID,
		.class		= 0,
		.class_mask	= 0,
	},
2879

2880 2881 2882 2883 2884 2885
	{0, }
};
MODULE_DEVICE_TABLE(pci, amd64_pci_table);

static struct pci_driver amd64_pci_driver = {
	.name		= EDAC_MOD_STR,
2886 2887
	.probe		= probe_one_instance,
	.remove		= remove_one_instance,
2888 2889 2890
	.id_table	= amd64_pci_table,
};

2891
static void setup_pci_device(void)
2892 2893 2894 2895
{
	struct mem_ctl_info *mci;
	struct amd64_pvt *pvt;

2896
	if (pci_ctl)
2897 2898
		return;

2899
	mci = mcis[0];
2900 2901
	if (!mci)
		return;
2902

2903 2904 2905 2906 2907
	pvt = mci->pvt_info;
	pci_ctl = edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR);
	if (!pci_ctl) {
		pr_warn("%s(): Unable to create PCI control\n", __func__);
		pr_warn("%s(): PCI error report via EDAC not set\n", __func__);
2908 2909 2910 2911 2912
	}
}

static int __init amd64_edac_init(void)
{
2913
	int err = -ENODEV;
2914

2915
	printk(KERN_INFO "AMD64 EDAC driver v%s\n", EDAC_AMD64_VERSION);
2916 2917 2918

	opstate_init();

2919
	if (amd_cache_northbridges() < 0)
2920
		goto err_ret;
2921

2922
	err = -ENOMEM;
2923 2924
	mcis	  = kzalloc(amd_nb_num() * sizeof(mcis[0]), GFP_KERNEL);
	ecc_stngs = kzalloc(amd_nb_num() * sizeof(ecc_stngs[0]), GFP_KERNEL);
2925
	if (!(mcis && ecc_stngs))
2926
		goto err_free;
2927

2928
	msrs = msrs_alloc();
2929
	if (!msrs)
2930
		goto err_free;
2931

2932 2933
	err = pci_register_driver(&amd64_pci_driver);
	if (err)
2934
		goto err_pci;
2935

2936
	err = -ENODEV;
2937 2938
	if (!atomic_read(&drv_instances))
		goto err_no_instances;
2939

2940 2941
	setup_pci_device();
	return 0;
2942

2943
err_no_instances:
2944
	pci_unregister_driver(&amd64_pci_driver);
2945

2946 2947 2948
err_pci:
	msrs_free(msrs);
	msrs = NULL;
2949

2950 2951 2952 2953 2954 2955 2956
err_free:
	kfree(mcis);
	mcis = NULL;

	kfree(ecc_stngs);
	ecc_stngs = NULL;

2957
err_ret:
2958 2959 2960 2961 2962
	return err;
}

static void __exit amd64_edac_exit(void)
{
2963 2964
	if (pci_ctl)
		edac_pci_release_generic_ctl(pci_ctl);
2965 2966

	pci_unregister_driver(&amd64_pci_driver);
2967

2968 2969 2970
	kfree(ecc_stngs);
	ecc_stngs = NULL;

2971 2972 2973
	kfree(mcis);
	mcis = NULL;

2974 2975
	msrs_free(msrs);
	msrs = NULL;
2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988
}

module_init(amd64_edac_init);
module_exit(amd64_edac_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, "
		"Dave Peterson, Thayne Harbaugh");
MODULE_DESCRIPTION("MC support for AMD64 memory controllers - "
		EDAC_AMD64_VERSION);

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");