trans.c 74.4 KB
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/******************************************************************************
 *
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * GPL LICENSE SUMMARY
 *
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 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 * USA
 *
 * The full GNU General Public License is included in this distribution
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 * in the file called COPYING.
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 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 * BSD LICENSE
 *
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 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name Intel Corporation nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/
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#include <linux/pci.h>
#include <linux/pci-aspm.h>
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#include <linux/interrupt.h>
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#include <linux/debugfs.h>
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#include <linux/sched.h>
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#include <linux/bitops.h>
#include <linux/gfp.h>
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#include <linux/vmalloc.h>
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#include "iwl-drv.h"
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#include "iwl-trans.h"
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#include "iwl-csr.h"
#include "iwl-prph.h"
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#include "iwl-scd.h"
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#include "iwl-agn-hw.h"
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#include "iwl-fw-error-dump.h"
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#include "internal.h"
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#include "iwl-fh.h"
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/* extended range in FW SRAM */
#define IWL_FW_MEM_EXTENDED_START	0x40000
#define IWL_FW_MEM_EXTENDED_END		0x57FFF

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static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	if (!trans_pcie->fw_mon_page)
		return;

	dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
		       trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
	__free_pages(trans_pcie->fw_mon_page,
		     get_order(trans_pcie->fw_mon_size));
	trans_pcie->fw_mon_page = NULL;
	trans_pcie->fw_mon_phys = 0;
	trans_pcie->fw_mon_size = 0;
}

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static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
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{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	struct page *page = NULL;
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	dma_addr_t phys;
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	u32 size = 0;
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	u8 power;

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	if (!max_power) {
		/* default max_power is maximum */
		max_power = 26;
	} else {
		max_power += 11;
	}

	if (WARN(max_power > 26,
		 "External buffer size for monitor is too big %d, check the FW TLV\n",
		 max_power))
		return;

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	if (trans_pcie->fw_mon_page) {
		dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
					   trans_pcie->fw_mon_size,
					   DMA_FROM_DEVICE);
		return;
	}

	phys = 0;
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	for (power = max_power; power >= 11; power--) {
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		int order;

		size = BIT(power);
		order = get_order(size);
		page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
				   order);
		if (!page)
			continue;

		phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
				    DMA_FROM_DEVICE);
		if (dma_mapping_error(trans->dev, phys)) {
			__free_pages(page, order);
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			page = NULL;
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			continue;
		}
		IWL_INFO(trans,
			 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
			 size, order);
		break;
	}

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	if (WARN_ON_ONCE(!page))
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		return;

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	if (power != max_power)
		IWL_ERR(trans,
			"Sorry - debug buffer is only %luK while you requested %luK\n",
			(unsigned long)BIT(power - 10),
			(unsigned long)BIT(max_power - 10));

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	trans_pcie->fw_mon_page = page;
	trans_pcie->fw_mon_phys = phys;
	trans_pcie->fw_mon_size = size;
}

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static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
{
	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
		    ((reg & 0x0000ffff) | (2 << 28)));
	return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
}

static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
{
	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
		    ((reg & 0x0000ffff) | (3 << 28)));
}

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static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
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{
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	if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
		iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
				       APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
				       ~APMG_PS_CTRL_MSK_PWR_SRC);
	else
		iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
				       APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
				       ~APMG_PS_CTRL_MSK_PWR_SRC);
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}

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/* PCI registers */
#define PCI_CFG_RETRY_TIMEOUT	0x041

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static void iwl_pcie_apm_config(struct iwl_trans *trans)
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{
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	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	u16 lctl;
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	u16 cap;
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	/*
	 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
	 * Check if BIOS (or OS) enabled L1-ASPM on this device.
	 * If so (likely), disable L0S, so device moves directly L0->L1;
	 *    costs negligible amount of power savings.
	 * If not (unlikely), enable L0S, so there is at least some
	 *    power savings, even without L1.
	 */
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	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
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	if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
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		iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
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	else
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		iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
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	trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
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	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
	trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
	dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
		 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
		 trans->ltr_enabled ? "En" : "Dis");
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}

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/*
 * Start up NIC's basic functionality after it has been reset
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 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
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 * NOTE:  This does not load uCode nor start the embedded processor
 */
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static int iwl_pcie_apm_init(struct iwl_trans *trans)
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{
	int ret = 0;
	IWL_DEBUG_INFO(trans, "Init card's basic functions\n");

	/*
	 * Use "set_bit" below rather than "write", to preserve any hardware
	 * bits already set by default after reset.
	 */

	/* Disable L0S exit timer (platform NMI Work/Around) */
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	if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
		iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
			    CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
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	/*
	 * Disable L0s without affecting L1;
	 *  don't wait for ICH L0s (ICH bug W/A)
	 */
	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
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		    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
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	/* Set FH wait threshold to maximum (HW error during stress W/A) */
	iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);

	/*
	 * Enable HAP INTA (interrupt from management bus) to
	 * wake device's PCI Express link L1a -> L0s
	 */
	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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		    CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
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	iwl_pcie_apm_config(trans);
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	/* Configure analog phase-lock-loop before activating to D0A */
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	if (trans->cfg->base_params->pll_cfg_val)
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		iwl_set_bit(trans, CSR_ANA_PLL_CFG,
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			    trans->cfg->base_params->pll_cfg_val);
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	/*
	 * Set "initialization complete" bit to move adapter from
	 * D0U* --> D0A* (powered-up active) state.
	 */
	iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

	/*
	 * Wait for clock stabilization; once stabilized, access to
	 * device-internal resources is supported, e.g. iwl_write_prph()
	 * and accesses to uCode SRAM.
	 */
	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
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	if (ret < 0) {
		IWL_DEBUG_INFO(trans, "Failed to init the card\n");
		goto out;
	}

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	if (trans->cfg->host_interrupt_operation_mode) {
		/*
		 * This is a bit of an abuse - This is needed for 7260 / 3160
		 * only check host_interrupt_operation_mode even if this is
		 * not related to host_interrupt_operation_mode.
		 *
		 * Enable the oscillator to count wake up time for L1 exit. This
		 * consumes slightly more power (100uA) - but allows to be sure
		 * that we wake up from L1 on time.
		 *
		 * This looks weird: read twice the same register, discard the
		 * value, set a bit, and yet again, read that same register
		 * just to discard the value. But that's the way the hardware
		 * seems to like it.
		 */
		iwl_read_prph(trans, OSC_CLK);
		iwl_read_prph(trans, OSC_CLK);
		iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
		iwl_read_prph(trans, OSC_CLK);
		iwl_read_prph(trans, OSC_CLK);
	}

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	/*
	 * Enable DMA clock and wait for it to stabilize.
	 *
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	 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
	 * bits do not disable clocks.  This preserves any hardware
	 * bits already set by default in "CLK_CTRL_REG" after reset.
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	 */
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	if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
		iwl_write_prph(trans, APMG_CLK_EN_REG,
			       APMG_CLK_VAL_DMA_CLK_RQT);
		udelay(20);

		/* Disable L1-Active */
		iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
				  APMG_PCIDEV_STT_VAL_L1_ACT_DIS);

		/* Clear the interrupt in APMG if the NIC is in RFKILL */
		iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
			       APMG_RTC_INT_STT_RFKILL);
	}
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	set_bit(STATUS_DEVICE_ENABLED, &trans->status);
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out:
	return ret;
}

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/*
 * Enable LP XTAL to avoid HW bug where device may consume much power if
 * FW is not loaded after device reset. LP XTAL is disabled by default
 * after device HW reset. Do it only if XTAL is fed by internal source.
 * Configure device's "persistence" mode to avoid resetting XTAL again when
 * SHRD_HW_RST occurs in S3.
 */
static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
{
	int ret;
	u32 apmg_gp1_reg;
	u32 apmg_xtal_cfg_reg;
	u32 dl_cfg_reg;

	/* Force XTAL ON */
	__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
				 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);

	/* Reset entire device - do controller reset (results in SHRD_HW_RST) */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);

	udelay(10);

	/*
	 * Set "initialization complete" bit to move adapter from
	 * D0U* --> D0A* (powered-up active) state.
	 */
	iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

	/*
	 * Wait for clock stabilization; once stabilized, access to
	 * device-internal resources is possible.
	 */
	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   25000);
	if (WARN_ON(ret < 0)) {
		IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
		/* Release XTAL ON request */
		__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
					   CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
		return;
	}

	/*
	 * Clear "disable persistence" to avoid LP XTAL resetting when
	 * SHRD_HW_RST is applied in S3.
	 */
	iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
				    APMG_PCIDEV_STT_VAL_PERSIST_DIS);

	/*
	 * Force APMG XTAL to be active to prevent its disabling by HW
	 * caused by APMG idle state.
	 */
	apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
						    SHR_APMG_XTAL_CFG_REG);
	iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
				 apmg_xtal_cfg_reg |
				 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);

	/*
	 * Reset entire device again - do controller reset (results in
	 * SHRD_HW_RST). Turn MAC off before proceeding.
	 */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);

	udelay(10);

	/* Enable LP XTAL by indirect access through CSR */
	apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
	iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
				 SHR_APMG_GP1_WF_XTAL_LP_EN |
				 SHR_APMG_GP1_CHICKEN_BIT_SELECT);

	/* Clear delay line clock power up */
	dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
	iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
				 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);

	/*
	 * Enable persistence mode to avoid LP XTAL resetting when
	 * SHRD_HW_RST is applied in S3.
	 */
	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
		    CSR_HW_IF_CONFIG_REG_PERSIST_MODE);

	/*
	 * Clear "initialization complete" bit to move adapter from
	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
	 */
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

	/* Activates XTAL resources monitor */
	__iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
				 CSR_MONITOR_XTAL_RESOURCES);

	/* Release XTAL ON request */
	__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
				   CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
	udelay(10);

	/* Release APMG XTAL */
	iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
				 apmg_xtal_cfg_reg &
				 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
}

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static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
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{
	int ret = 0;

	/* stop device's busmaster DMA activity */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);

	ret = iwl_poll_bit(trans, CSR_RESET,
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			   CSR_RESET_REG_FLAG_MASTER_DISABLED,
			   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
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	if (ret < 0)
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		IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");

	IWL_DEBUG_INFO(trans, "stop master\n");

	return ret;
}

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static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
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{
	IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");

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	if (op_mode_leave) {
		if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
			iwl_pcie_apm_init(trans);

		/* inform ME that we are leaving */
		if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
			iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
					  APMG_PCIDEV_STT_VAL_WAKE_ME);
		else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
			iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
				    CSR_HW_IF_CONFIG_REG_PREPARE |
				    CSR_HW_IF_CONFIG_REG_ENABLE_PME);
		mdelay(5);
	}

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	clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
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	/* Stop device's DMA activity */
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	iwl_pcie_apm_stop_master(trans);
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	if (trans->cfg->lp_xtal_workaround) {
		iwl_pcie_apm_lp_xtal_enable(trans);
		return;
	}

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	/* Reset the entire device */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);

	udelay(10);

	/*
	 * Clear "initialization complete" bit to move adapter from
	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
	 */
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
}

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static int iwl_pcie_nic_init(struct iwl_trans *trans)
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{
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	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	/* nic_init */
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	spin_lock(&trans_pcie->irq_lock);
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	iwl_pcie_apm_init(trans);
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	spin_unlock(&trans_pcie->irq_lock);
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	if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
		iwl_pcie_set_pwr(trans, false);
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	iwl_op_mode_nic_config(trans->op_mode);
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	/* Allocate the RX queue, or reset if it is already allocated */
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	iwl_pcie_rx_init(trans);
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	/* Allocate or reset and init all Tx and Command queues */
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	if (iwl_pcie_tx_init(trans))
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		return -ENOMEM;

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	if (trans->cfg->base_params->shadow_reg_enable) {
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		/* enable shadow regs in HW */
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		iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
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		IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
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	}

	return 0;
}

#define HW_READY_TIMEOUT (50)

/* Note: returns poll_bit return value, which is >= 0 if success */
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static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
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{
	int ret;

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	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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		    CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
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	/* See if we got it */
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	ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
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			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
			   HW_READY_TIMEOUT);
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555 556 557
	if (ret >= 0)
		iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);

558
	IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
559 560 561 562
	return ret;
}

/* Note: returns standard 0/-ERROR code */
563
static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
564 565
{
	int ret;
566
	int t = 0;
567
	int iter;
568

569
	IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
570

571
	ret = iwl_pcie_set_hw_ready(trans);
572
	/* If the card is ready, exit 0 */
573 574 575
	if (ret >= 0)
		return 0;

576 577 578 579 580 581 582 583 584
	for (iter = 0; iter < 10; iter++) {
		/* If HW is not ready, prepare the conditions to check again */
		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
			    CSR_HW_IF_CONFIG_REG_PREPARE);

		do {
			ret = iwl_pcie_set_hw_ready(trans);
			if (ret >= 0)
				return 0;
585

586 587 588 589 590
			usleep_range(200, 1000);
			t += 200;
		} while (t < 150000);
		msleep(25);
	}
591

592
	IWL_ERR(trans, "Couldn't prepare the card\n");
593 594 595 596

	return ret;
}

597 598 599
/*
 * ucode
 */
600
static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
J
Johannes Berg 已提交
601
				   dma_addr_t phy_addr, u32 byte_cnt)
602
{
603
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
604 605
	int ret;

606
	trans_pcie->ucode_write_complete = false;
607 608

	iwl_write_direct32(trans,
609 610
			   FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
			   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
611 612

	iwl_write_direct32(trans,
613 614
			   FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
			   dst_addr);
615 616

	iwl_write_direct32(trans,
J
Johannes Berg 已提交
617 618
			   FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
			   phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
619 620

	iwl_write_direct32(trans,
621 622 623
			   FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
			   (iwl_get_dma_hi_addr(phy_addr)
				<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
624 625

	iwl_write_direct32(trans,
626 627 628 629
			   FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
			   1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
			   1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
			   FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
630 631

	iwl_write_direct32(trans,
632 633 634 635
			   FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
			   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE	|
			   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE	|
			   FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
636

637 638
	ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
				 trans_pcie->ucode_write_complete, 5 * HZ);
639
	if (!ret) {
J
Johannes Berg 已提交
640
		IWL_ERR(trans, "Failed to load firmware chunk!\n");
641 642 643 644 645 646
		return -ETIMEDOUT;
	}

	return 0;
}

647
static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
J
Johannes Berg 已提交
648
			    const struct fw_desc *section)
649
{
J
Johannes Berg 已提交
650 651
	u8 *v_addr;
	dma_addr_t p_addr;
652
	u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
653 654
	int ret = 0;

J
Johannes Berg 已提交
655 656 657
	IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
		     section_num);

658 659 660 661 662 663 664 665 666 667
	v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
				    GFP_KERNEL | __GFP_NOWARN);
	if (!v_addr) {
		IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
		chunk_sz = PAGE_SIZE;
		v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
					    &p_addr, GFP_KERNEL);
		if (!v_addr)
			return -ENOMEM;
	}
J
Johannes Berg 已提交
668

669
	for (offset = 0; offset < section->len; offset += chunk_sz) {
670 671
		u32 copy_size, dst_addr;
		bool extended_addr = false;
J
Johannes Berg 已提交
672

673
		copy_size = min_t(u32, chunk_sz, section->len - offset);
674 675 676 677 678 679 680 681 682
		dst_addr = section->offset + offset;

		if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
		    dst_addr <= IWL_FW_MEM_EXTENDED_END)
			extended_addr = true;

		if (extended_addr)
			iwl_set_bits_prph(trans, LMPM_CHICK,
					  LMPM_CHICK_EXTENDED_ADDR_SPACE);
683

J
Johannes Berg 已提交
684
		memcpy(v_addr, (u8 *)section->data + offset, copy_size);
685 686 687 688 689 690 691
		ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
						   copy_size);

		if (extended_addr)
			iwl_clear_bits_prph(trans, LMPM_CHICK,
					    LMPM_CHICK_EXTENDED_ADDR_SPACE);

J
Johannes Berg 已提交
692 693 694 695 696
		if (ret) {
			IWL_ERR(trans,
				"Could not load the [%d] uCode section\n",
				section_num);
			break;
D
David Spinadel 已提交
697
		}
J
Johannes Berg 已提交
698 699
	}

700
	dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
J
Johannes Berg 已提交
701 702 703
	return ret;
}

704 705 706 707 708 709 710 711 712
/*
 * Driver Takes the ownership on secure machine before FW load
 * and prevent race with the BT load.
 * W/A for ROM bug. (should be remove in the next Si step)
 */
static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
{
	u32 val, loop = 1000;

713 714 715 716 717
	/*
	 * Check the RSA semaphore is accessible.
	 * If the HW isn't locked and the rsa semaphore isn't accessible,
	 * we are in trouble.
	 */
718 719
	val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
	if (val & (BIT(1) | BIT(17))) {
720 721
		IWL_INFO(trans,
			 "can't access the RSA semaphore it is write protected\n");
722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744
		return 0;
	}

	/* take ownership on the AUX IF */
	iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
	iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);

	do {
		iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
		val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
		if (val == 0x1) {
			iwl_write_prph(trans, RSA_ENABLE, 0);
			return 0;
		}

		udelay(10);
		loop--;
	} while (loop > 0);

	IWL_ERR(trans, "Failed to take ownership on secure machine\n");
	return -EIO;
}

745 746 747 748
static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
					   const struct fw_img *image,
					   int cpu,
					   int *first_ucode_section)
749 750
{
	int shift_param;
751 752
	int i, ret = 0, sec_num = 0x1;
	u32 val, last_read_idx = 0;
753 754 755

	if (cpu == 1) {
		shift_param = 0;
756
		*first_ucode_section = 0;
757 758
	} else {
		shift_param = 16;
759
		(*first_ucode_section)++;
760 761
	}

762 763 764 765 766 767 768 769
	for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
		last_read_idx = i;

		if (!image->sec[i].data ||
		    image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
			IWL_DEBUG_FW(trans,
				     "Break since Data not valid or Empty section, sec = %d\n",
				     i);
770
			break;
771 772
		}

773 774 775
		ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
		if (ret)
			return ret;
776 777 778 779 780 781

		/* Notify the ucode of the loaded section number and status */
		val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
		val = val | (sec_num << shift_param);
		iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
		sec_num = (sec_num << 1) | 0x1;
782 783
	}

784 785
	*first_ucode_section = last_read_idx;

786 787 788 789 790
	if (cpu == 1)
		iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
	else
		iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);

791 792
	return 0;
}
793

794 795
static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
				      const struct fw_img *image,
796 797
				      int cpu,
				      int *first_ucode_section)
798 799 800
{
	int shift_param;
	int i, ret = 0;
801
	u32 last_read_idx = 0;
802 803 804

	if (cpu == 1) {
		shift_param = 0;
805
		*first_ucode_section = 0;
806 807
	} else {
		shift_param = 16;
808
		(*first_ucode_section)++;
809 810
	}

811 812 813 814 815 816 817 818
	for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
		last_read_idx = i;

		if (!image->sec[i].data ||
		    image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
			IWL_DEBUG_FW(trans,
				     "Break since Data not valid or Empty section, sec = %d\n",
				     i);
819
			break;
820 821
		}

822 823 824
		ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
		if (ret)
			return ret;
825 826
	}

827 828 829 830 831 832 833 834
	if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
		iwl_set_bits_prph(trans,
				  CSR_UCODE_LOAD_STATUS_ADDR,
				  (LMPM_CPU_UCODE_LOADING_COMPLETED |
				   LMPM_CPU_HDRS_LOADING_COMPLETED |
				   LMPM_CPU_UCODE_LOADING_STARTED) <<
					shift_param);

835 836
	*first_ucode_section = last_read_idx;

837 838 839
	return 0;
}

840 841 842 843 844 845 846 847 848 849 850 851 852 853 854
static void iwl_pcie_apply_destination(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
	int i;

	if (dest->version)
		IWL_ERR(trans,
			"DBG DEST version is %d - expect issues\n",
			dest->version);

	IWL_INFO(trans, "Applying debug destination %s\n",
		 get_fw_dbg_mode_string(dest->monitor_mode));

	if (dest->monitor_mode == EXTERNAL_MODE)
855
		iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897
	else
		IWL_WARN(trans, "PCI should have external buffer debug\n");

	for (i = 0; i < trans->dbg_dest_reg_num; i++) {
		u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
		u32 val = le32_to_cpu(dest->reg_ops[i].val);

		switch (dest->reg_ops[i].op) {
		case CSR_ASSIGN:
			iwl_write32(trans, addr, val);
			break;
		case CSR_SETBIT:
			iwl_set_bit(trans, addr, BIT(val));
			break;
		case CSR_CLEARBIT:
			iwl_clear_bit(trans, addr, BIT(val));
			break;
		case PRPH_ASSIGN:
			iwl_write_prph(trans, addr, val);
			break;
		case PRPH_SETBIT:
			iwl_set_bits_prph(trans, addr, BIT(val));
			break;
		case PRPH_CLEARBIT:
			iwl_clear_bits_prph(trans, addr, BIT(val));
			break;
		default:
			IWL_ERR(trans, "FW debug - unknown OP %d\n",
				dest->reg_ops[i].op);
			break;
		}
	}

	if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
		iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
			       trans_pcie->fw_mon_phys >> dest->base_shift);
		iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
			       (trans_pcie->fw_mon_phys +
				trans_pcie->fw_mon_size) >> dest->end_shift);
	}
}

898
static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
899
				const struct fw_img *image)
900
{
901
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
902
	int ret = 0;
903
	int first_ucode_section;
904

905
	IWL_DEBUG_FW(trans, "working with %s CPU\n",
906 907
		     image->is_dual_cpus ? "Dual" : "Single");

908 909 910 911
	/* load to FW the binary non secured sections of CPU1 */
	ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
	if (ret)
		return ret;
912 913

	if (image->is_dual_cpus) {
914 915 916 917
		/* set CPU2 header address */
		iwl_write_prph(trans,
			       LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
			       LMPM_SECURE_CPU2_HDR_MEM_SPACE);
918

919
		/* load to FW the binary sections of CPU2 */
920 921
		ret = iwl_pcie_load_cpu_sections(trans, image, 2,
						 &first_ucode_section);
922 923
		if (ret)
			return ret;
924
	}
925

926 927 928
	/* supported for 7000 only for the moment */
	if (iwlwifi_mod_params.fw_monitor &&
	    trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
929
		iwl_pcie_alloc_fw_monitor(trans, 0);
930 931 932 933 934 935 936 937

		if (trans_pcie->fw_mon_size) {
			iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
				       trans_pcie->fw_mon_phys >> 4);
			iwl_write_prph(trans, MON_BUFF_END_ADDR,
				       (trans_pcie->fw_mon_phys +
					trans_pcie->fw_mon_size) >> 4);
		}
938 939
	} else if (trans->dbg_dest_tlv) {
		iwl_pcie_apply_destination(trans);
940 941
	}

942
	/* release CPU reset */
943
	iwl_write32(trans, CSR_RESET, 0);
944

945 946
	return 0;
}
947

948 949
static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
					  const struct fw_img *image)
950 951 952 953 954 955 956
{
	int ret = 0;
	int first_ucode_section;

	IWL_DEBUG_FW(trans, "working with %s CPU\n",
		     image->is_dual_cpus ? "Dual" : "Single");

957 958 959
	if (trans->dbg_dest_tlv)
		iwl_pcie_apply_destination(trans);

960 961 962 963 964
	/* TODO: remove in the next Si step */
	ret = iwl_pcie_rsa_race_bug_wa(trans);
	if (ret)
		return ret;

965 966 967 968 969
	/* configure the ucode to be ready to get the secured image */
	/* release CPU reset */
	iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);

	/* load to FW the binary Secured sections of CPU1 */
970 971
	ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
					      &first_ucode_section);
972 973 974 975
	if (ret)
		return ret;

	/* load to FW the binary sections of CPU2 */
976 977
	return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
					       &first_ucode_section);
978 979
}

980
static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
981
				   const struct fw_img *fw, bool run_in_rfkill)
982 983
{
	int ret;
984
	bool hw_rfkill;
985

986
	/* This may fail if AMT took ownership of the device */
987
	if (iwl_pcie_prepare_card_hw(trans)) {
988
		IWL_WARN(trans, "Exit HW not ready\n");
989 990 991
		return -EIO;
	}

992 993
	iwl_enable_rfkill_int(trans);

994
	/* If platform's RF_KILL switch is NOT set to KILL */
995
	hw_rfkill = iwl_is_rfkill_set(trans);
996
	if (hw_rfkill)
997
		set_bit(STATUS_RFKILL, &trans->status);
998
	else
999
		clear_bit(STATUS_RFKILL, &trans->status);
1000
	iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1001
	if (hw_rfkill && !run_in_rfkill)
1002 1003
		return -ERFKILL;

1004
	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1005

1006
	ret = iwl_pcie_nic_init(trans);
1007
	if (ret) {
1008
		IWL_ERR(trans, "Unable to init nic\n");
1009 1010 1011 1012
		return ret;
	}

	/* make sure rfkill handshake bits are cleared */
1013 1014
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1015 1016 1017
		    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);

	/* clear (again), then enable host interrupts */
1018
	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1019
	iwl_enable_interrupts(trans);
1020 1021

	/* really make sure rfkill handshake bits are cleared */
1022 1023
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1024

1025
	/* Load the given image to the HW */
1026 1027
	if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
		return iwl_pcie_load_given_ucode_8000(trans, fw);
1028 1029
	else
		return iwl_pcie_load_given_ucode(trans, fw);
1030 1031
}

1032
static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1033
{
1034
	iwl_pcie_reset_ict(trans);
1035
	iwl_pcie_tx_start(trans, scd_addr);
1036 1037
}

1038
static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1039
{
1040
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1041 1042 1043
	bool hw_rfkill, was_hw_rfkill;

	was_hw_rfkill = iwl_is_rfkill_set(trans);
1044

1045
	/* tell the device to stop sending interrupts */
1046
	spin_lock(&trans_pcie->irq_lock);
1047
	iwl_disable_interrupts(trans);
1048
	spin_unlock(&trans_pcie->irq_lock);
1049

1050
	/* device going down, Stop using ICT table */
1051
	iwl_pcie_disable_ict(trans);
1052 1053 1054 1055 1056 1057 1058 1059

	/*
	 * If a HW restart happens during firmware loading,
	 * then the firmware loading might call this function
	 * and later it might be called again due to the
	 * restart. So don't process again if the device is
	 * already dead.
	 */
1060 1061
	if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
		IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
1062
		iwl_pcie_tx_stop(trans);
1063
		iwl_pcie_rx_stop(trans);
1064

1065
		/* Power-down device's busmaster DMA clocks */
1066 1067 1068 1069 1070
		if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
			iwl_write_prph(trans, APMG_CLK_DIS_REG,
				       APMG_CLK_VAL_DMA_CLK_RQT);
			udelay(5);
		}
1071 1072 1073
	}

	/* Make sure (redundant) we've released our request to stay awake */
1074
	iwl_clear_bit(trans, CSR_GP_CNTRL,
1075
		      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1076 1077

	/* Stop the device, and put it in low power state */
1078
	iwl_pcie_apm_stop(trans, false);
1079

1080 1081 1082 1083 1084 1085 1086 1087 1088 1089
	/* stop and reset the on-board processor */
	iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
	udelay(20);

	/*
	 * Upon stop, the APM issues an interrupt if HW RF kill is set.
	 * This is a bug in certain verions of the hardware.
	 * Certain devices also keep sending HW RF kill interrupt all
	 * the time, unless the interrupt is ACKed even if the interrupt
	 * should be masked. Re-ACK all the interrupts here.
1090
	 */
1091
	spin_lock(&trans_pcie->irq_lock);
1092
	iwl_disable_interrupts(trans);
1093
	spin_unlock(&trans_pcie->irq_lock);
1094

D
Don Fry 已提交
1095 1096

	/* clear all status bits */
1097 1098 1099 1100
	clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
	clear_bit(STATUS_INT_ENABLED, &trans->status);
	clear_bit(STATUS_TPOWER_PMI, &trans->status);
	clear_bit(STATUS_RFKILL, &trans->status);
1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112

	/*
	 * Even if we stop the HW, we still want the RF kill
	 * interrupt
	 */
	iwl_enable_rfkill_int(trans);

	/*
	 * Check again since the RF kill state may have changed while
	 * all the interrupts were disabled, in this case we couldn't
	 * receive the RF kill interrupt and update the state in the
	 * op_mode.
1113 1114 1115 1116 1117 1118
	 * Don't call the op_mode if the rkfill state hasn't changed.
	 * This allows the op_mode to call stop_device from the rfkill
	 * notification without endless recursion. Under very rare
	 * circumstances, we might have a small recursion if the rfkill
	 * state changed exactly now while we were called from stop_device.
	 * This is very unlikely but can happen and is supported.
1119 1120 1121
	 */
	hw_rfkill = iwl_is_rfkill_set(trans);
	if (hw_rfkill)
1122
		set_bit(STATUS_RFKILL, &trans->status);
1123
	else
1124
		clear_bit(STATUS_RFKILL, &trans->status);
1125
	if (hw_rfkill != was_hw_rfkill)
1126
		iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1127 1128 1129

	/* re-take ownership to prevent other users from stealing the deivce */
	iwl_pcie_prepare_card_hw(trans);
1130 1131 1132 1133 1134
}

void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
{
	if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1135
		iwl_trans_pcie_stop_device(trans, true);
1136 1137
}

1138
static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
1139 1140
{
	iwl_disable_interrupts(trans);
1141 1142 1143 1144 1145 1146 1147 1148

	/*
	 * in testing mode, the host stays awake and the
	 * hardware won't be reset (not even partially)
	 */
	if (test)
		return;

1149 1150
	iwl_pcie_disable_ict(trans);

1151 1152
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1153 1154 1155 1156 1157 1158 1159 1160 1161 1162
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

	/*
	 * reset TX queues -- some of their registers reset during S3
	 * so if we don't reset everything here the D3 image would try
	 * to execute some invalid memory upon resume
	 */
	iwl_trans_pcie_tx_reset(trans);

1163 1164
	if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
		iwl_pcie_set_pwr(trans, true);
1165 1166 1167
}

static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1168 1169
				    enum iwl_d3_status *status,
				    bool test)
1170 1171 1172 1173
{
	u32 val;
	int ret;

1174 1175 1176 1177 1178 1179
	if (test) {
		iwl_enable_interrupts(trans);
		*status = IWL_D3_STATUS_ALIVE;
		return 0;
	}

1180 1181 1182 1183 1184 1185 1186 1187 1188 1189
	/*
	 * Also enables interrupts - none will happen as the device doesn't
	 * know we're waking it up, only when the opmode actually tells it
	 * after this call.
	 */
	iwl_pcie_reset_ict(trans);

	iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
	iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

1190 1191 1192
	if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
		udelay(2);

1193 1194 1195 1196
	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   25000);
1197
	if (ret < 0) {
1198 1199 1200 1201
		IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
		return ret;
	}

1202 1203
	if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
		iwl_pcie_set_pwr(trans, false);
1204

1205 1206 1207 1208 1209 1210 1211 1212
	iwl_trans_pcie_tx_reset(trans);

	ret = iwl_pcie_rx_init(trans);
	if (ret) {
		IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
		return ret;
	}

1213 1214 1215 1216 1217 1218
	val = iwl_read32(trans, CSR_RESET);
	if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
		*status = IWL_D3_STATUS_RESET;
	else
		*status = IWL_D3_STATUS_ALIVE;

1219
	return 0;
1220 1221
}

1222
static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1223
{
1224
	bool hw_rfkill;
J
Johannes Berg 已提交
1225
	int err;
1226

1227
	err = iwl_pcie_prepare_card_hw(trans);
1228
	if (err) {
1229
		IWL_ERR(trans, "Error while preparing HW: %d\n", err);
J
Johannes Berg 已提交
1230
		return err;
1231
	}
1232

1233
	/* Reset the entire device */
1234
	iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1235 1236 1237

	usleep_range(10, 15);

1238
	iwl_pcie_apm_init(trans);
1239

1240 1241 1242
	/* From now on, the op_mode will be kept updated about RF kill state */
	iwl_enable_rfkill_int(trans);

1243
	hw_rfkill = iwl_is_rfkill_set(trans);
1244
	if (hw_rfkill)
1245
		set_bit(STATUS_RFKILL, &trans->status);
1246
	else
1247
		clear_bit(STATUS_RFKILL, &trans->status);
1248
	iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1249

J
Johannes Berg 已提交
1250
	return 0;
1251 1252
}

1253
static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1254
{
1255
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1256

1257
	/* disable interrupts - don't enable HW RF kill interrupt */
1258
	spin_lock(&trans_pcie->irq_lock);
1259
	iwl_disable_interrupts(trans);
1260
	spin_unlock(&trans_pcie->irq_lock);
1261

1262
	iwl_pcie_apm_stop(trans, true);
1263

1264
	spin_lock(&trans_pcie->irq_lock);
1265
	iwl_disable_interrupts(trans);
1266
	spin_unlock(&trans_pcie->irq_lock);
1267

E
Emmanuel Grumbach 已提交
1268
	iwl_pcie_disable_ict(trans);
1269 1270
}

1271 1272
static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
{
1273
	writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1274 1275 1276 1277
}

static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
{
1278
	writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1279 1280 1281 1282
}

static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
{
1283
	return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1284 1285
}

1286 1287
static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
{
A
Amnon Paz 已提交
1288 1289
	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
			       ((reg & 0x000FFFFF) | (3 << 24)));
1290 1291 1292 1293 1294 1295 1296
	return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
}

static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
				      u32 val)
{
	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
A
Amnon Paz 已提交
1297
			       ((addr & 0x000FFFFF) | (3 << 24)));
1298 1299 1300
	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
}

1301 1302 1303 1304 1305 1306
static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
{
	WARN_ON(1);
	return 0;
}

1307
static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1308
				     const struct iwl_trans_config *trans_cfg)
1309 1310 1311 1312
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1313
	trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1314
	trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1315 1316 1317 1318 1319 1320 1321
	if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
		trans_pcie->n_no_reclaim_cmds = 0;
	else
		trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
	if (trans_pcie->n_no_reclaim_cmds)
		memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
		       trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1322

1323 1324 1325 1326 1327
	trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
	if (trans_pcie->rx_buf_size_8k)
		trans_pcie->rx_page_order = get_order(8 * 1024);
	else
		trans_pcie->rx_page_order = get_order(4 * 1024);
1328

J
Johannes Berg 已提交
1329
	trans_pcie->command_names = trans_cfg->command_names;
1330
	trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1331
	trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1332

1333 1334 1335
	/* init ref_count to 1 (should be cleared when ucode is loaded) */
	trans_pcie->ref_count = 1;

1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346
	/* Initialize NAPI here - it should be before registering to mac80211
	 * in the opmode but after the HW struct is allocated.
	 * As this function may be called again in some corner cases don't
	 * do anything if NAPI was already initialized.
	 */
	if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
		init_dummy_netdev(&trans_pcie->napi_dev);
		iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
				     &trans_pcie->napi_dev,
				     iwl_pcie_dummy_napi_poll, 64);
	}
1347 1348
}

1349
void iwl_trans_pcie_free(struct iwl_trans *trans)
1350
{
1351
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1352

1353 1354
	synchronize_irq(trans_pcie->pci_dev->irq);

1355
	iwl_pcie_tx_free(trans);
1356
	iwl_pcie_rx_free(trans);
1357

J
Johannes Berg 已提交
1358 1359
	free_irq(trans_pcie->pci_dev->irq, trans);
	iwl_pcie_free_ict(trans);
1360 1361

	pci_disable_msi(trans_pcie->pci_dev);
1362
	iounmap(trans_pcie->hw_base);
1363 1364 1365
	pci_release_regions(trans_pcie->pci_dev);
	pci_disable_device(trans_pcie->pci_dev);

1366 1367 1368
	if (trans_pcie->napi.poll)
		netif_napi_del(&trans_pcie->napi);

1369 1370
	iwl_pcie_free_fw_monitor(trans);

1371
	iwl_trans_free(trans);
1372 1373
}

D
Don Fry 已提交
1374 1375 1376
static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
{
	if (state)
1377
		set_bit(STATUS_TPOWER_PMI, &trans->status);
D
Don Fry 已提交
1378
	else
1379
		clear_bit(STATUS_TPOWER_PMI, &trans->status);
D
Don Fry 已提交
1380 1381
}

1382 1383
static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
						unsigned long *flags)
1384 1385
{
	int ret;
1386 1387 1388
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1389

1390 1391 1392
	if (trans_pcie->cmd_in_flight)
		goto out;

1393
	/* this bit wakes up the NIC */
1394 1395
	__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
				 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1396 1397
	if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
		udelay(2);
1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428

	/*
	 * These bits say the device is running, and should keep running for
	 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
	 * but they do not indicate that embedded SRAM is restored yet;
	 * 3945 and 4965 have volatile SRAM, and must save/restore contents
	 * to/from host DRAM when sleeping/waking for power-saving.
	 * Each direction takes approximately 1/4 millisecond; with this
	 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
	 * series of register accesses are expected (e.g. reading Event Log),
	 * to keep device from sleeping.
	 *
	 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
	 * SRAM is okay/restored.  We don't check that here because this call
	 * is just for hardware register access; but GP1 MAC_SLEEP check is a
	 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
	 *
	 * 5000 series and later (including 1000 series) have non-volatile SRAM,
	 * and do not save/restore SRAM when power cycling.
	 */
	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
			   CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
			   (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
			    CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
	if (unlikely(ret < 0)) {
		iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
		if (!silent) {
			u32 val = iwl_read32(trans, CSR_GP_CNTRL);
			WARN_ONCE(1,
				  "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
				  val);
1429
			spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1430 1431 1432 1433
			return false;
		}
	}

1434
out:
1435 1436 1437 1438
	/*
	 * Fool sparse by faking we release the lock - sparse will
	 * track nic_access anyway.
	 */
1439
	__release(&trans_pcie->reg_lock);
1440 1441 1442
	return true;
}

1443 1444
static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
					      unsigned long *flags)
1445
{
1446
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1447

1448
	lockdep_assert_held(&trans_pcie->reg_lock);
1449 1450 1451 1452 1453

	/*
	 * Fool sparse by faking we acquiring the lock - sparse will
	 * track nic_access anyway.
	 */
1454
	__acquire(&trans_pcie->reg_lock);
1455

1456 1457 1458
	if (trans_pcie->cmd_in_flight)
		goto out;

1459 1460
	__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
				   CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1461 1462 1463 1464 1465 1466 1467
	/*
	 * Above we read the CSR_GP_CNTRL register, which will flush
	 * any previous writes, but we need the write that clears the
	 * MAC_ACCESS_REQ bit to be performed before any other writes
	 * scheduled on different CPUs (after we drop reg_lock).
	 */
	mmiowb();
1468
out:
1469
	spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1470 1471
}

1472 1473 1474 1475 1476 1477 1478
static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
				   void *buf, int dwords)
{
	unsigned long flags;
	int offs, ret = 0;
	u32 *vals = buf;

1479
	if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1480 1481 1482
		iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
		for (offs = 0; offs < dwords; offs++)
			vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1483
		iwl_trans_release_nic_access(trans, &flags);
1484 1485 1486 1487 1488 1489 1490
	} else {
		ret = -EBUSY;
	}
	return ret;
}

static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1491
				    const void *buf, int dwords)
1492 1493 1494
{
	unsigned long flags;
	int offs, ret = 0;
1495
	const u32 *vals = buf;
1496

1497
	if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1498 1499
		iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
		for (offs = 0; offs < dwords; offs++)
E
Emmanuel Grumbach 已提交
1500 1501
			iwl_write32(trans, HBUS_TARG_MEM_WDAT,
				    vals ? vals[offs] : 0);
1502
		iwl_trans_release_nic_access(trans, &flags);
1503 1504 1505 1506 1507
	} else {
		ret = -EBUSY;
	}
	return ret;
}
1508

1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562
static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
					    unsigned long txqs,
					    bool freeze)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	int queue;

	for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
		struct iwl_txq *txq = &trans_pcie->txq[queue];
		unsigned long now;

		spin_lock_bh(&txq->lock);

		now = jiffies;

		if (txq->frozen == freeze)
			goto next_queue;

		IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
				    freeze ? "Freezing" : "Waking", queue);

		txq->frozen = freeze;

		if (txq->q.read_ptr == txq->q.write_ptr)
			goto next_queue;

		if (freeze) {
			if (unlikely(time_after(now,
						txq->stuck_timer.expires))) {
				/*
				 * The timer should have fired, maybe it is
				 * spinning right now on the lock.
				 */
				goto next_queue;
			}
			/* remember how long until the timer fires */
			txq->frozen_expiry_remainder =
				txq->stuck_timer.expires - now;
			del_timer(&txq->stuck_timer);
			goto next_queue;
		}

		/*
		 * Wake a non-empty queue -> arm timer with the
		 * remainder before it froze
		 */
		mod_timer(&txq->stuck_timer,
			  now + txq->frozen_expiry_remainder);

next_queue:
		spin_unlock_bh(&txq->lock);
	}
}

1563 1564
#define IWL_FLUSH_WAIT_MS	2000

1565
static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1566
{
1567
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1568
	struct iwl_txq *txq;
1569 1570 1571
	struct iwl_queue *q;
	int cnt;
	unsigned long now = jiffies;
1572 1573
	u32 scd_sram_addr;
	u8 buf[16];
1574 1575 1576
	int ret = 0;

	/* waiting for all the tx frames complete might take a while */
1577
	for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1578 1579
		u8 wr_ptr;

W
Wey-Yi Guy 已提交
1580
		if (cnt == trans_pcie->cmd_queue)
1581
			continue;
1582 1583 1584 1585
		if (!test_bit(cnt, trans_pcie->queue_used))
			continue;
		if (!(BIT(cnt) & txq_bm))
			continue;
1586 1587

		IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1588
		txq = &trans_pcie->txq[cnt];
1589
		q = &txq->q;
1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600
		wr_ptr = ACCESS_ONCE(q->write_ptr);

		while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
		       !time_after(jiffies,
				   now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
			u8 write_ptr = ACCESS_ONCE(q->write_ptr);

			if (WARN_ONCE(wr_ptr != write_ptr,
				      "WR pointer moved while flushing %d -> %d\n",
				      wr_ptr, write_ptr))
				return -ETIMEDOUT;
1601
			msleep(1);
1602
		}
1603 1604

		if (q->read_ptr != q->write_ptr) {
1605 1606
			IWL_ERR(trans,
				"fail to flush all tx fifo queues Q %d\n", cnt);
1607 1608 1609
			ret = -ETIMEDOUT;
			break;
		}
1610
		IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1611
	}
1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644

	if (!ret)
		return 0;

	IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
		txq->q.read_ptr, txq->q.write_ptr);

	scd_sram_addr = trans_pcie->scd_base_addr +
			SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
	iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));

	iwl_print_hex_error(trans, buf, sizeof(buf));

	for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
		IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
			iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));

	for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
		u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
		u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
		bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
		u32 tbl_dw =
			iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
					     SCD_TRANS_TBL_OFFSET_QUEUE(cnt));

		if (cnt & 0x1)
			tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
		else
			tbl_dw = tbl_dw & 0x0000FFFF;

		IWL_ERR(trans,
			"Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
			cnt, active ? "" : "in", fifo, tbl_dw,
1645 1646
			iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
				(TFD_QUEUE_SIZE_MAX - 1),
1647 1648 1649
			iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
	}

1650 1651 1652
	return ret;
}

1653 1654 1655
static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
					 u32 mask, u32 value)
{
1656
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1657 1658
	unsigned long flags;

1659
	spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1660
	__iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1661
	spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1662 1663
}

1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695
void iwl_trans_pcie_ref(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	unsigned long flags;

	if (iwlwifi_mod_params.d0i3_disable)
		return;

	spin_lock_irqsave(&trans_pcie->ref_lock, flags);
	IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
	trans_pcie->ref_count++;
	spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
}

void iwl_trans_pcie_unref(struct iwl_trans *trans)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	unsigned long flags;

	if (iwlwifi_mod_params.d0i3_disable)
		return;

	spin_lock_irqsave(&trans_pcie->ref_lock, flags);
	IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
	if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
		spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
		return;
	}
	trans_pcie->ref_count--;
	spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
}

1696 1697
static const char *get_csr_string(int cmd)
{
J
Johannes Berg 已提交
1698
#define IWL_CMD(x) case x: return #x
1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721
	switch (cmd) {
	IWL_CMD(CSR_HW_IF_CONFIG_REG);
	IWL_CMD(CSR_INT_COALESCING);
	IWL_CMD(CSR_INT);
	IWL_CMD(CSR_INT_MASK);
	IWL_CMD(CSR_FH_INT_STATUS);
	IWL_CMD(CSR_GPIO_IN);
	IWL_CMD(CSR_RESET);
	IWL_CMD(CSR_GP_CNTRL);
	IWL_CMD(CSR_HW_REV);
	IWL_CMD(CSR_EEPROM_REG);
	IWL_CMD(CSR_EEPROM_GP);
	IWL_CMD(CSR_OTP_GP_REG);
	IWL_CMD(CSR_GIO_REG);
	IWL_CMD(CSR_GP_UCODE_REG);
	IWL_CMD(CSR_GP_DRIVER_REG);
	IWL_CMD(CSR_UCODE_DRV_GP1);
	IWL_CMD(CSR_UCODE_DRV_GP2);
	IWL_CMD(CSR_LED_REG);
	IWL_CMD(CSR_DRAM_INT_TBL_REG);
	IWL_CMD(CSR_GIO_CHICKEN_BITS);
	IWL_CMD(CSR_ANA_PLL_CFG);
	IWL_CMD(CSR_HW_REV_WA_REG);
1722
	IWL_CMD(CSR_MONITOR_STATUS_REG);
1723 1724 1725 1726
	IWL_CMD(CSR_DBG_HPET_MEM_REG);
	default:
		return "UNKNOWN";
	}
J
Johannes Berg 已提交
1727
#undef IWL_CMD
1728 1729
}

1730
void iwl_pcie_dump_csr(struct iwl_trans *trans)
1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754
{
	int i;
	static const u32 csr_tbl[] = {
		CSR_HW_IF_CONFIG_REG,
		CSR_INT_COALESCING,
		CSR_INT,
		CSR_INT_MASK,
		CSR_FH_INT_STATUS,
		CSR_GPIO_IN,
		CSR_RESET,
		CSR_GP_CNTRL,
		CSR_HW_REV,
		CSR_EEPROM_REG,
		CSR_EEPROM_GP,
		CSR_OTP_GP_REG,
		CSR_GIO_REG,
		CSR_GP_UCODE_REG,
		CSR_GP_DRIVER_REG,
		CSR_UCODE_DRV_GP1,
		CSR_UCODE_DRV_GP2,
		CSR_LED_REG,
		CSR_DRAM_INT_TBL_REG,
		CSR_GIO_CHICKEN_BITS,
		CSR_ANA_PLL_CFG,
1755
		CSR_MONITOR_STATUS_REG,
1756 1757 1758 1759 1760 1761 1762 1763 1764
		CSR_HW_REV_WA_REG,
		CSR_DBG_HPET_MEM_REG
	};
	IWL_ERR(trans, "CSR values:\n");
	IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
		"CSR_INT_PERIODIC_REG)\n");
	for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
		IWL_ERR(trans, "  %25s: 0X%08x\n",
			get_csr_string(csr_tbl[i]),
1765
			iwl_read32(trans, csr_tbl[i]));
1766 1767 1768
	}
}

1769 1770 1771
#ifdef CONFIG_IWLWIFI_DEBUGFS
/* create and remove of files */
#define DEBUGFS_ADD_FILE(name, parent, mode) do {			\
1772
	if (!debugfs_create_file(#name, mode, parent, trans,		\
1773
				 &iwl_dbgfs_##name##_ops))		\
1774
		goto err;						\
1775 1776 1777 1778 1779 1780
} while (0)

/* file operation */
#define DEBUGFS_READ_FILE_OPS(name)					\
static const struct file_operations iwl_dbgfs_##name##_ops = {		\
	.read = iwl_dbgfs_##name##_read,				\
1781
	.open = simple_open,						\
1782 1783 1784
	.llseek = generic_file_llseek,					\
};

1785 1786 1787
#define DEBUGFS_WRITE_FILE_OPS(name)                                    \
static const struct file_operations iwl_dbgfs_##name##_ops = {          \
	.write = iwl_dbgfs_##name##_write,                              \
1788
	.open = simple_open,						\
1789 1790 1791
	.llseek = generic_file_llseek,					\
};

1792 1793 1794 1795
#define DEBUGFS_READ_WRITE_FILE_OPS(name)				\
static const struct file_operations iwl_dbgfs_##name##_ops = {		\
	.write = iwl_dbgfs_##name##_write,				\
	.read = iwl_dbgfs_##name##_read,				\
1796
	.open = simple_open,						\
1797 1798 1799 1800
	.llseek = generic_file_llseek,					\
};

static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1801 1802
				       char __user *user_buf,
				       size_t count, loff_t *ppos)
1803
{
1804
	struct iwl_trans *trans = file->private_data;
1805
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1806
	struct iwl_txq *txq;
1807 1808 1809 1810 1811
	struct iwl_queue *q;
	char *buf;
	int pos = 0;
	int cnt;
	int ret;
1812 1813
	size_t bufsz;

1814
	bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
1815

J
Johannes Berg 已提交
1816
	if (!trans_pcie->txq)
1817
		return -EAGAIN;
J
Johannes Berg 已提交
1818

1819 1820 1821 1822
	buf = kzalloc(bufsz, GFP_KERNEL);
	if (!buf)
		return -ENOMEM;

1823
	for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1824
		txq = &trans_pcie->txq[cnt];
1825 1826
		q = &txq->q;
		pos += scnprintf(buf + pos, bufsz - pos,
1827
				"hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
1828
				cnt, q->read_ptr, q->write_ptr,
1829
				!!test_bit(cnt, trans_pcie->queue_used),
1830
				 !!test_bit(cnt, trans_pcie->queue_stopped),
1831
				 txq->need_update, txq->frozen,
1832
				 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1833 1834 1835 1836 1837 1838 1839
	}
	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
	kfree(buf);
	return ret;
}

static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1840 1841 1842
				       char __user *user_buf,
				       size_t count, loff_t *ppos)
{
1843
	struct iwl_trans *trans = file->private_data;
1844
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1845
	struct iwl_rxq *rxq = &trans_pcie->rxq;
1846 1847 1848 1849 1850 1851 1852 1853
	char buf[256];
	int pos = 0;
	const size_t bufsz = sizeof(buf);

	pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
						rxq->read);
	pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
						rxq->write);
1854 1855 1856 1857
	pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
						rxq->write_actual);
	pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
						rxq->need_update);
1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869
	pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
						rxq->free_count);
	if (rxq->rb_stts) {
		pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
			 le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
	} else {
		pos += scnprintf(buf + pos, bufsz - pos,
					"closed_rb_num: Not Allocated\n");
	}
	return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
}

1870 1871
static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
					char __user *user_buf,
1872 1873
					size_t count, loff_t *ppos)
{
1874
	struct iwl_trans *trans = file->private_data;
1875
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1876 1877 1878 1879 1880 1881 1882 1883
	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;

	int pos = 0;
	char *buf;
	int bufsz = 24 * 64; /* 24 items * 64 char per item */
	ssize_t ret;

	buf = kzalloc(bufsz, GFP_KERNEL);
J
Johannes Berg 已提交
1884
	if (!buf)
1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932
		return -ENOMEM;

	pos += scnprintf(buf + pos, bufsz - pos,
			"Interrupt Statistics Report:\n");

	pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
		isr_stats->hw);
	pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
		isr_stats->sw);
	if (isr_stats->sw || isr_stats->hw) {
		pos += scnprintf(buf + pos, bufsz - pos,
			"\tLast Restarting Code:  0x%X\n",
			isr_stats->err_code);
	}
#ifdef CONFIG_IWLWIFI_DEBUG
	pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
		isr_stats->sch);
	pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
		isr_stats->alive);
#endif
	pos += scnprintf(buf + pos, bufsz - pos,
		"HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);

	pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
		isr_stats->ctkill);

	pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
		isr_stats->wakeup);

	pos += scnprintf(buf + pos, bufsz - pos,
		"Rx command responses:\t\t %u\n", isr_stats->rx);

	pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
		isr_stats->tx);

	pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
		isr_stats->unhandled);

	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
	kfree(buf);
	return ret;
}

static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
					 const char __user *user_buf,
					 size_t count, loff_t *ppos)
{
	struct iwl_trans *trans = file->private_data;
1933
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951
	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;

	char buf[8];
	int buf_size;
	u32 reset_flag;

	memset(buf, 0, sizeof(buf));
	buf_size = min(count, sizeof(buf) -  1);
	if (copy_from_user(buf, user_buf, buf_size))
		return -EFAULT;
	if (sscanf(buf, "%x", &reset_flag) != 1)
		return -EFAULT;
	if (reset_flag == 0)
		memset(isr_stats, 0, sizeof(*isr_stats));

	return count;
}

1952
static ssize_t iwl_dbgfs_csr_write(struct file *file,
1953 1954
				   const char __user *user_buf,
				   size_t count, loff_t *ppos)
1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967
{
	struct iwl_trans *trans = file->private_data;
	char buf[8];
	int buf_size;
	int csr;

	memset(buf, 0, sizeof(buf));
	buf_size = min(count, sizeof(buf) -  1);
	if (copy_from_user(buf, user_buf, buf_size))
		return -EFAULT;
	if (sscanf(buf, "%d", &csr) != 1)
		return -EFAULT;

1968
	iwl_pcie_dump_csr(trans);
1969 1970 1971 1972 1973

	return count;
}

static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1974 1975
				     char __user *user_buf,
				     size_t count, loff_t *ppos)
1976 1977
{
	struct iwl_trans *trans = file->private_data;
1978
	char *buf = NULL;
1979
	ssize_t ret;
1980

1981 1982 1983 1984 1985 1986 1987
	ret = iwl_dump_fh(trans, &buf);
	if (ret < 0)
		return ret;
	if (!buf)
		return -EINVAL;
	ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
	kfree(buf);
1988 1989 1990
	return ret;
}

1991
DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1992
DEBUGFS_READ_FILE_OPS(fh_reg);
1993 1994
DEBUGFS_READ_FILE_OPS(rx_queue);
DEBUGFS_READ_FILE_OPS(tx_queue);
1995
DEBUGFS_WRITE_FILE_OPS(csr);
1996 1997 1998 1999 2000 2001

/*
 * Create the debugfs files and directories
 *
 */
static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2002
					 struct dentry *dir)
2003 2004 2005
{
	DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
	DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2006
	DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2007 2008
	DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
	DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2009
	return 0;
2010 2011 2012 2013

err:
	IWL_ERR(trans, "failed to create the trans debugfs entry\n");
	return -ENOMEM;
2014
}
2015 2016 2017 2018 2019 2020 2021
#else
static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
					 struct dentry *dir)
{
	return 0;
}
#endif /*CONFIG_IWLWIFI_DEBUGFS */
2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033

static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
{
	u32 cmdlen = 0;
	int i;

	for (i = 0; i < IWL_NUM_OF_TBS; i++)
		cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);

	return cmdlen;
}

2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061
static const struct {
	u32 start, end;
} iwl_prph_dump_addr[] = {
	{ .start = 0x00a00000, .end = 0x00a00000 },
	{ .start = 0x00a0000c, .end = 0x00a00024 },
	{ .start = 0x00a0002c, .end = 0x00a0003c },
	{ .start = 0x00a00410, .end = 0x00a00418 },
	{ .start = 0x00a00420, .end = 0x00a00420 },
	{ .start = 0x00a00428, .end = 0x00a00428 },
	{ .start = 0x00a00430, .end = 0x00a0043c },
	{ .start = 0x00a00444, .end = 0x00a00444 },
	{ .start = 0x00a004c0, .end = 0x00a004cc },
	{ .start = 0x00a004d8, .end = 0x00a004d8 },
	{ .start = 0x00a004e0, .end = 0x00a004f0 },
	{ .start = 0x00a00840, .end = 0x00a00840 },
	{ .start = 0x00a00850, .end = 0x00a00858 },
	{ .start = 0x00a01004, .end = 0x00a01008 },
	{ .start = 0x00a01010, .end = 0x00a01010 },
	{ .start = 0x00a01018, .end = 0x00a01018 },
	{ .start = 0x00a01024, .end = 0x00a01024 },
	{ .start = 0x00a0102c, .end = 0x00a01034 },
	{ .start = 0x00a0103c, .end = 0x00a01040 },
	{ .start = 0x00a01048, .end = 0x00a01094 },
	{ .start = 0x00a01c00, .end = 0x00a01c20 },
	{ .start = 0x00a01c58, .end = 0x00a01c58 },
	{ .start = 0x00a01c7c, .end = 0x00a01c7c },
	{ .start = 0x00a01c28, .end = 0x00a01c54 },
	{ .start = 0x00a01c5c, .end = 0x00a01c5c },
2062
	{ .start = 0x00a01c60, .end = 0x00a01cdc },
2063 2064 2065 2066 2067
	{ .start = 0x00a01ce0, .end = 0x00a01d0c },
	{ .start = 0x00a01d18, .end = 0x00a01d20 },
	{ .start = 0x00a01d2c, .end = 0x00a01d30 },
	{ .start = 0x00a01d40, .end = 0x00a01d5c },
	{ .start = 0x00a01d80, .end = 0x00a01d80 },
2068 2069 2070
	{ .start = 0x00a01d98, .end = 0x00a01d9c },
	{ .start = 0x00a01da8, .end = 0x00a01da8 },
	{ .start = 0x00a01db8, .end = 0x00a01df4 },
2071 2072 2073
	{ .start = 0x00a01dc0, .end = 0x00a01dfc },
	{ .start = 0x00a01e00, .end = 0x00a01e2c },
	{ .start = 0x00a01e40, .end = 0x00a01e60 },
2074 2075
	{ .start = 0x00a01e68, .end = 0x00a01e6c },
	{ .start = 0x00a01e74, .end = 0x00a01e74 },
2076 2077
	{ .start = 0x00a01e84, .end = 0x00a01e90 },
	{ .start = 0x00a01e9c, .end = 0x00a01ec4 },
2078 2079 2080
	{ .start = 0x00a01ed0, .end = 0x00a01ee0 },
	{ .start = 0x00a01f00, .end = 0x00a01f1c },
	{ .start = 0x00a01f44, .end = 0x00a01ffc },
2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149
	{ .start = 0x00a02000, .end = 0x00a02048 },
	{ .start = 0x00a02068, .end = 0x00a020f0 },
	{ .start = 0x00a02100, .end = 0x00a02118 },
	{ .start = 0x00a02140, .end = 0x00a0214c },
	{ .start = 0x00a02168, .end = 0x00a0218c },
	{ .start = 0x00a021c0, .end = 0x00a021c0 },
	{ .start = 0x00a02400, .end = 0x00a02410 },
	{ .start = 0x00a02418, .end = 0x00a02420 },
	{ .start = 0x00a02428, .end = 0x00a0242c },
	{ .start = 0x00a02434, .end = 0x00a02434 },
	{ .start = 0x00a02440, .end = 0x00a02460 },
	{ .start = 0x00a02468, .end = 0x00a024b0 },
	{ .start = 0x00a024c8, .end = 0x00a024cc },
	{ .start = 0x00a02500, .end = 0x00a02504 },
	{ .start = 0x00a0250c, .end = 0x00a02510 },
	{ .start = 0x00a02540, .end = 0x00a02554 },
	{ .start = 0x00a02580, .end = 0x00a025f4 },
	{ .start = 0x00a02600, .end = 0x00a0260c },
	{ .start = 0x00a02648, .end = 0x00a02650 },
	{ .start = 0x00a02680, .end = 0x00a02680 },
	{ .start = 0x00a026c0, .end = 0x00a026d0 },
	{ .start = 0x00a02700, .end = 0x00a0270c },
	{ .start = 0x00a02804, .end = 0x00a02804 },
	{ .start = 0x00a02818, .end = 0x00a0281c },
	{ .start = 0x00a02c00, .end = 0x00a02db4 },
	{ .start = 0x00a02df4, .end = 0x00a02fb0 },
	{ .start = 0x00a03000, .end = 0x00a03014 },
	{ .start = 0x00a0301c, .end = 0x00a0302c },
	{ .start = 0x00a03034, .end = 0x00a03038 },
	{ .start = 0x00a03040, .end = 0x00a03048 },
	{ .start = 0x00a03060, .end = 0x00a03068 },
	{ .start = 0x00a03070, .end = 0x00a03074 },
	{ .start = 0x00a0307c, .end = 0x00a0307c },
	{ .start = 0x00a03080, .end = 0x00a03084 },
	{ .start = 0x00a0308c, .end = 0x00a03090 },
	{ .start = 0x00a03098, .end = 0x00a03098 },
	{ .start = 0x00a030a0, .end = 0x00a030a0 },
	{ .start = 0x00a030a8, .end = 0x00a030b4 },
	{ .start = 0x00a030bc, .end = 0x00a030bc },
	{ .start = 0x00a030c0, .end = 0x00a0312c },
	{ .start = 0x00a03c00, .end = 0x00a03c5c },
	{ .start = 0x00a04400, .end = 0x00a04454 },
	{ .start = 0x00a04460, .end = 0x00a04474 },
	{ .start = 0x00a044c0, .end = 0x00a044ec },
	{ .start = 0x00a04500, .end = 0x00a04504 },
	{ .start = 0x00a04510, .end = 0x00a04538 },
	{ .start = 0x00a04540, .end = 0x00a04548 },
	{ .start = 0x00a04560, .end = 0x00a0457c },
	{ .start = 0x00a04590, .end = 0x00a04598 },
	{ .start = 0x00a045c0, .end = 0x00a045f4 },
};

static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
				    struct iwl_fw_error_dump_data **data)
{
	struct iwl_fw_error_dump_prph *prph;
	unsigned long flags;
	u32 prph_len = 0, i;

	if (!iwl_trans_grab_nic_access(trans, false, &flags))
		return 0;

	for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
		/* The range includes both boundaries */
		int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
			 iwl_prph_dump_addr[i].start + 4;
		int reg;
		__le32 *val;

L
Liad Kaufman 已提交
2150
		prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171

		(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
		(*data)->len = cpu_to_le32(sizeof(*prph) +
					num_bytes_in_chunk);
		prph = (void *)(*data)->data;
		prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
		val = (void *)prph->data;

		for (reg = iwl_prph_dump_addr[i].start;
		     reg <= iwl_prph_dump_addr[i].end;
		     reg += 4)
			*val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
								      reg));
		*data = iwl_fw_error_next_data(*data);
	}

	iwl_trans_release_nic_access(trans, &flags);

	return prph_len;
}

2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192
#define IWL_CSR_TO_DUMP (0x250)

static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
				   struct iwl_fw_error_dump_data **data)
{
	u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
	__le32 *val;
	int i;

	(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
	(*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
	val = (void *)(*data)->data;

	for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
		*val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));

	*data = iwl_fw_error_next_data(*data);

	return csr_len;
}

2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217
static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
				       struct iwl_fw_error_dump_data **data)
{
	u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
	unsigned long flags;
	__le32 *val;
	int i;

	if (!iwl_trans_grab_nic_access(trans, false, &flags))
		return 0;

	(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
	(*data)->len = cpu_to_le32(fh_regs_len);
	val = (void *)(*data)->data;

	for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
		*val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));

	iwl_trans_release_nic_access(trans, &flags);

	*data = iwl_fw_error_next_data(*data);

	return sizeof(**data) + fh_regs_len;
}

2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240
static u32
iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
				 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
				 u32 monitor_len)
{
	u32 buf_size_in_dwords = (monitor_len >> 2);
	u32 *buffer = (u32 *)fw_mon_data->data;
	unsigned long flags;
	u32 i;

	if (!iwl_trans_grab_nic_access(trans, false, &flags))
		return 0;

	__iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
	for (i = 0; i < buf_size_in_dwords; i++)
		buffer[i] = __iwl_read_prph(trans, MON_DMARB_RD_DATA_ADDR);
	__iwl_write_prph(trans, MON_DMARB_RD_CTL_ADDR, 0x0);

	iwl_trans_release_nic_access(trans, &flags);

	return monitor_len;
}

2241 2242
static
struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
2243 2244 2245 2246 2247
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	struct iwl_fw_error_dump_data *data;
	struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
	struct iwl_fw_error_dump_txcmd *txcmd;
2248
	struct iwl_trans_dump_data *dump_data;
2249
	u32 len;
2250
	u32 monitor_len;
2251 2252
	int i, ptr;

2253 2254 2255 2256 2257
	/* transport dump header */
	len = sizeof(*dump_data);

	/* host commands */
	len += sizeof(*data) +
2258 2259
		cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);

2260 2261 2262 2263
	/* CSR registers */
	len += sizeof(*data) + IWL_CSR_TO_DUMP;

	/* PRPH registers */
2264 2265 2266 2267 2268 2269 2270 2271 2272
	for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
		/* The range includes both boundaries */
		int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
			iwl_prph_dump_addr[i].start + 4;

		len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
			num_bytes_in_chunk;
	}

2273 2274 2275
	/* FH registers */
	len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);

2276
	/* FW monitor */
2277
	if (trans_pcie->fw_mon_page) {
2278
		len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292
		       trans_pcie->fw_mon_size;
		monitor_len = trans_pcie->fw_mon_size;
	} else if (trans->dbg_dest_tlv) {
		u32 base, end;

		base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
		end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);

		base = iwl_read_prph(trans, base) <<
		       trans->dbg_dest_tlv->base_shift;
		end = iwl_read_prph(trans, end) <<
		      trans->dbg_dest_tlv->end_shift;

		/* Make "end" point to the actual end */
2293 2294
		if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
		    trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2295 2296 2297 2298 2299 2300 2301
			end += (1 << trans->dbg_dest_tlv->end_shift);
		monitor_len = end - base;
		len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
		       monitor_len;
	} else {
		monitor_len = 0;
	}
2302

2303 2304 2305
	dump_data = vzalloc(len);
	if (!dump_data)
		return NULL;
2306 2307

	len = 0;
2308
	data = (void *)dump_data->data;
2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332
	data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
	txcmd = (void *)data->data;
	spin_lock_bh(&cmdq->lock);
	ptr = cmdq->q.write_ptr;
	for (i = 0; i < cmdq->q.n_window; i++) {
		u8 idx = get_cmd_index(&cmdq->q, ptr);
		u32 caplen, cmdlen;

		cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
		caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);

		if (cmdlen) {
			len += sizeof(*txcmd) + caplen;
			txcmd->cmdlen = cpu_to_le32(cmdlen);
			txcmd->caplen = cpu_to_le32(caplen);
			memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
			txcmd = (void *)((u8 *)txcmd->data + caplen);
		}

		ptr = iwl_queue_dec_wrap(ptr);
	}
	spin_unlock_bh(&cmdq->lock);

	data->len = cpu_to_le32(len);
2333
	len += sizeof(*data);
2334 2335 2336
	data = iwl_fw_error_next_data(data);

	len += iwl_trans_pcie_dump_prph(trans, &data);
2337
	len += iwl_trans_pcie_dump_csr(trans, &data);
2338
	len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2339
	/* data is already pointing to the next section */
2340

2341 2342 2343
	if ((trans_pcie->fw_mon_page &&
	     trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
	    trans->dbg_dest_tlv) {
2344
		struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357
		u32 base, write_ptr, wrap_cnt;

		/* If there was a dest TLV - use the values from there */
		if (trans->dbg_dest_tlv) {
			write_ptr =
				le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
			wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
			base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
		} else {
			base = MON_BUFF_BASE_ADDR;
			write_ptr = MON_BUFF_WRPTR;
			wrap_cnt = MON_BUFF_CYCLE_CNT;
		}
2358 2359 2360 2361

		data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
		fw_mon_data = (void *)data->data;
		fw_mon_data->fw_mon_wr_ptr =
2362
			cpu_to_le32(iwl_read_prph(trans, write_ptr));
2363
		fw_mon_data->fw_mon_cycle_cnt =
2364
			cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2365
		fw_mon_data->fw_mon_base_ptr =
2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383
			cpu_to_le32(iwl_read_prph(trans, base));

		len += sizeof(*data) + sizeof(*fw_mon_data);
		if (trans_pcie->fw_mon_page) {
			/*
			 * The firmware is now asserted, it won't write anything
			 * to the buffer. CPU can take ownership to fetch the
			 * data. The buffer will be handed back to the device
			 * before the firmware will be restarted.
			 */
			dma_sync_single_for_cpu(trans->dev,
						trans_pcie->fw_mon_phys,
						trans_pcie->fw_mon_size,
						DMA_FROM_DEVICE);
			memcpy(fw_mon_data->data,
			       page_address(trans_pcie->fw_mon_page),
			       trans_pcie->fw_mon_size);

2384 2385
			monitor_len = trans_pcie->fw_mon_size;
		} else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2386 2387 2388 2389 2390 2391 2392 2393
			/*
			 * Update pointers to reflect actual values after
			 * shifting
			 */
			base = iwl_read_prph(trans, base) <<
			       trans->dbg_dest_tlv->base_shift;
			iwl_trans_read_mem(trans, base, fw_mon_data->data,
					   monitor_len / sizeof(u32));
2394 2395 2396 2397 2398 2399 2400 2401
		} else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
			monitor_len =
				iwl_trans_pci_dump_marbh_monitor(trans,
								 fw_mon_data,
								 monitor_len);
		} else {
			/* Didn't match anything - output no monitor data */
			monitor_len = 0;
2402
		}
2403 2404 2405

		len += monitor_len;
		data->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2406 2407
	}

2408 2409 2410
	dump_data->len = len;

	return dump_data;
2411
}
2412

2413
static const struct iwl_trans_ops trans_ops_pcie = {
2414
	.start_hw = iwl_trans_pcie_start_hw,
2415
	.op_mode_leave = iwl_trans_pcie_op_mode_leave,
2416
	.fw_alive = iwl_trans_pcie_fw_alive,
2417
	.start_fw = iwl_trans_pcie_start_fw,
2418
	.stop_device = iwl_trans_pcie_stop_device,
2419

2420 2421
	.d3_suspend = iwl_trans_pcie_d3_suspend,
	.d3_resume = iwl_trans_pcie_d3_resume,
2422

2423
	.send_cmd = iwl_trans_pcie_send_hcmd,
2424

2425
	.tx = iwl_trans_pcie_tx,
2426
	.reclaim = iwl_trans_pcie_reclaim,
2427

2428
	.txq_disable = iwl_trans_pcie_txq_disable,
2429
	.txq_enable = iwl_trans_pcie_txq_enable,
2430

2431
	.dbgfs_register = iwl_trans_pcie_dbgfs_register,
2432

2433
	.wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2434
	.freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2435

2436 2437 2438
	.write8 = iwl_trans_pcie_write8,
	.write32 = iwl_trans_pcie_write32,
	.read32 = iwl_trans_pcie_read32,
2439 2440
	.read_prph = iwl_trans_pcie_read_prph,
	.write_prph = iwl_trans_pcie_write_prph,
2441 2442
	.read_mem = iwl_trans_pcie_read_mem,
	.write_mem = iwl_trans_pcie_write_mem,
2443
	.configure = iwl_trans_pcie_configure,
D
Don Fry 已提交
2444
	.set_pmi = iwl_trans_pcie_set_pmi,
2445
	.grab_nic_access = iwl_trans_pcie_grab_nic_access,
2446 2447
	.release_nic_access = iwl_trans_pcie_release_nic_access,
	.set_bits_mask = iwl_trans_pcie_set_bits_mask,
2448

2449 2450 2451
	.ref = iwl_trans_pcie_ref,
	.unref = iwl_trans_pcie_unref,

2452
	.dump_data = iwl_trans_pcie_dump_data,
2453
};
2454

2455
struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2456 2457
				       const struct pci_device_id *ent,
				       const struct iwl_cfg *cfg)
2458 2459 2460 2461 2462 2463
{
	struct iwl_trans_pcie *trans_pcie;
	struct iwl_trans *trans;
	u16 pci_cmd;
	int err;

2464 2465 2466 2467
	trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
				&pdev->dev, cfg, &trans_ops_pcie, 0);
	if (!trans)
		return ERR_PTR(-ENOMEM);
2468 2469 2470 2471

	trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	trans_pcie->trans = trans;
J
Johannes Berg 已提交
2472
	spin_lock_init(&trans_pcie->irq_lock);
2473
	spin_lock_init(&trans_pcie->reg_lock);
J
Johannes Berg 已提交
2474
	spin_lock_init(&trans_pcie->ref_lock);
2475
	init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2476

J
Johannes Berg 已提交
2477 2478 2479 2480
	err = pci_enable_device(pdev);
	if (err)
		goto out_no_pci;

2481 2482 2483 2484 2485 2486 2487 2488 2489 2490
	if (!cfg->base_params->pcie_l1_allowed) {
		/*
		 * W/A - seems to solve weird behavior. We need to remove this
		 * if we don't want to stay in L1 all the time. This wastes a
		 * lot of power.
		 */
		pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
				       PCIE_LINK_STATE_L1 |
				       PCIE_LINK_STATE_CLKPM);
	}
2491 2492 2493 2494 2495 2496 2497 2498 2499 2500

	pci_set_master(pdev);

	err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
	if (!err)
		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
	if (err) {
		err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
		if (!err)
			err = pci_set_consistent_dma_mask(pdev,
2501
							  DMA_BIT_MASK(32));
2502 2503
		/* both attempts failed: */
		if (err) {
2504
			dev_err(&pdev->dev, "No suitable DMA available\n");
2505 2506 2507 2508 2509 2510
			goto out_pci_disable_device;
		}
	}

	err = pci_request_regions(pdev, DRV_NAME);
	if (err) {
2511
		dev_err(&pdev->dev, "pci_request_regions failed\n");
2512 2513 2514
		goto out_pci_disable_device;
	}

2515
	trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2516
	if (!trans_pcie->hw_base) {
2517
		dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2518 2519 2520 2521 2522 2523 2524 2525
		err = -ENODEV;
		goto out_pci_release_regions;
	}

	/* We disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state */
	pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);

2526 2527 2528 2529
	trans->dev = &pdev->dev;
	trans_pcie->pci_dev = pdev;
	iwl_disable_interrupts(trans);

2530
	err = pci_enable_msi(pdev);
2531
	if (err) {
2532
		dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
2533 2534 2535 2536 2537 2538 2539
		/* enable rfkill interrupt: hw bug w/a */
		pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
		if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
			pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
			pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
		}
	}
2540

2541
	trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2542 2543 2544 2545 2546 2547
	/*
	 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
	 * changed, and now the revision step also includes bit 0-1 (no more
	 * "dash" value). To keep hw_rev backwards compatible - we'll store it
	 * in the old format.
	 */
2548 2549 2550 2551
	if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
		unsigned long flags;
		int ret;

2552
		trans->hw_rev = (trans->hw_rev & 0xfff0) |
2553
				(CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2554

2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586
		/*
		 * in-order to recognize C step driver should read chip version
		 * id located at the AUX bus MISC address space.
		 */
		iwl_set_bit(trans, CSR_GP_CNTRL,
			    CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
		udelay(2);

		ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
				   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
				   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
				   25000);
		if (ret < 0) {
			IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
			goto out_pci_disable_msi;
		}

		if (iwl_trans_grab_nic_access(trans, false, &flags)) {
			u32 hw_step;

			hw_step = __iwl_read_prph(trans, WFPM_CTRL_REG);
			hw_step |= ENABLE_WFPM;
			__iwl_write_prph(trans, WFPM_CTRL_REG, hw_step);
			hw_step = __iwl_read_prph(trans, AUX_MISC_REG);
			hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
			if (hw_step == 0x3)
				trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
						(SILICON_C_STEP << 2);
			iwl_trans_release_nic_access(trans, &flags);
		}
	}

E
Emmanuel Grumbach 已提交
2587
	trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2588 2589
	snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
		 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2590

2591
	/* Initialize the wait queue for commands */
2592
	init_waitqueue_head(&trans_pcie->wait_command_queue);
2593

J
Johannes Berg 已提交
2594
	if (iwl_pcie_alloc_ict(trans))
2595
		goto out_pci_disable_msi;
J
Johannes Berg 已提交
2596

2597
	err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2598 2599 2600
				   iwl_pcie_irq_handler,
				   IRQF_SHARED, DRV_NAME, trans);
	if (err) {
J
Johannes Berg 已提交
2601 2602 2603 2604
		IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
		goto out_free_ict;
	}

2605
	trans_pcie->inta_mask = CSR_INI_SET_MASK;
2606
	trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
2607

2608 2609
	return trans;

J
Johannes Berg 已提交
2610 2611
out_free_ict:
	iwl_pcie_free_ict(trans);
2612 2613
out_pci_disable_msi:
	pci_disable_msi(pdev);
2614 2615 2616 2617 2618
out_pci_release_regions:
	pci_release_regions(pdev);
out_pci_disable_device:
	pci_disable_device(pdev);
out_no_pci:
2619
	iwl_trans_free(trans);
2620
	return ERR_PTR(err);
2621
}