trans.c 40.2 KB
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/******************************************************************************
 *
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * GPL LICENSE SUMMARY
 *
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 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 * USA
 *
 * The full GNU General Public License is included in this distribution
 * in the file called LICENSE.GPL.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 * BSD LICENSE
 *
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 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
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 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name Intel Corporation nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/
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#include <linux/pci.h>
#include <linux/pci-aspm.h>
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#include <linux/interrupt.h>
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#include <linux/debugfs.h>
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#include <linux/sched.h>
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#include <linux/bitops.h>
#include <linux/gfp.h>
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#include "iwl-drv.h"
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#include "iwl-trans.h"
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#include "iwl-csr.h"
#include "iwl-prph.h"
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#include "iwl-agn-hw.h"
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#include "internal.h"
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static void iwl_pcie_set_pwr_vmain(struct iwl_trans *trans)
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{
/*
 * (for documentation purposes)
 * to set power to V_AUX, do:

		if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
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			iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
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					       APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
					       ~APMG_PS_CTRL_MSK_PWR_SRC);
 */

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	iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
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			       APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
			       ~APMG_PS_CTRL_MSK_PWR_SRC);
}

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/* PCI registers */
#define PCI_CFG_RETRY_TIMEOUT	0x041

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static void iwl_pcie_apm_config(struct iwl_trans *trans)
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{
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	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	u16 lctl;
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	/*
	 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
	 * Check if BIOS (or OS) enabled L1-ASPM on this device.
	 * If so (likely), disable L0S, so device moves directly L0->L1;
	 *    costs negligible amount of power savings.
	 * If not (unlikely), enable L0S, so there is at least some
	 *    power savings, even without L1.
	 */
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	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
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	if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
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		/* L1-ASPM enabled; disable(!) L0S */
		iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
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		dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
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	} else {
		/* L1-ASPM disabled; enable(!) L0S */
		iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
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		dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
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	}
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	trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
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}

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/*
 * Start up NIC's basic functionality after it has been reset
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 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
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 * NOTE:  This does not load uCode nor start the embedded processor
 */
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static int iwl_pcie_apm_init(struct iwl_trans *trans)
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{
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	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	int ret = 0;
	IWL_DEBUG_INFO(trans, "Init card's basic functions\n");

	/*
	 * Use "set_bit" below rather than "write", to preserve any hardware
	 * bits already set by default after reset.
	 */

	/* Disable L0S exit timer (platform NMI Work/Around) */
	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
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		    CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
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	/*
	 * Disable L0s without affecting L1;
	 *  don't wait for ICH L0s (ICH bug W/A)
	 */
	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
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		    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
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	/* Set FH wait threshold to maximum (HW error during stress W/A) */
	iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);

	/*
	 * Enable HAP INTA (interrupt from management bus) to
	 * wake device's PCI Express link L1a -> L0s
	 */
	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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		    CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
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	iwl_pcie_apm_config(trans);
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	/* Configure analog phase-lock-loop before activating to D0A */
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	if (trans->cfg->base_params->pll_cfg_val)
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		iwl_set_bit(trans, CSR_ANA_PLL_CFG,
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			    trans->cfg->base_params->pll_cfg_val);
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	/*
	 * Set "initialization complete" bit to move adapter from
	 * D0U* --> D0A* (powered-up active) state.
	 */
	iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

	/*
	 * Wait for clock stabilization; once stabilized, access to
	 * device-internal resources is supported, e.g. iwl_write_prph()
	 * and accesses to uCode SRAM.
	 */
	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
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	if (ret < 0) {
		IWL_DEBUG_INFO(trans, "Failed to init the card\n");
		goto out;
	}

	/*
	 * Enable DMA clock and wait for it to stabilize.
	 *
	 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
	 * do not disable clocks.  This preserves any hardware bits already
	 * set by default in "CLK_CTRL_REG" after reset.
	 */
	iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
	udelay(20);

	/* Disable L1-Active */
	iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
			  APMG_PCIDEV_STT_VAL_L1_ACT_DIS);

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	set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
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out:
	return ret;
}

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static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
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{
	int ret = 0;

	/* stop device's busmaster DMA activity */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);

	ret = iwl_poll_bit(trans, CSR_RESET,
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			   CSR_RESET_REG_FLAG_MASTER_DISABLED,
			   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
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	if (ret)
		IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");

	IWL_DEBUG_INFO(trans, "stop master\n");

	return ret;
}

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static void iwl_pcie_apm_stop(struct iwl_trans *trans)
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{
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	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");

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	clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
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	/* Stop device's DMA activity */
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	iwl_pcie_apm_stop_master(trans);
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	/* Reset the entire device */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);

	udelay(10);

	/*
	 * Clear "initialization complete" bit to move adapter from
	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
	 */
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
}

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static int iwl_pcie_nic_init(struct iwl_trans *trans)
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{
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	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	unsigned long flags;

	/* nic_init */
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	spin_lock_irqsave(&trans_pcie->irq_lock, flags);
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	iwl_pcie_apm_init(trans);
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	/* Set interrupt coalescing calibration timer to default (512 usecs) */
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	iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
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	spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
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	iwl_pcie_set_pwr_vmain(trans);
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	iwl_op_mode_nic_config(trans->op_mode);
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	/* Allocate the RX queue, or reset if it is already allocated */
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	iwl_pcie_rx_init(trans);
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	/* Allocate or reset and init all Tx and Command queues */
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	if (iwl_pcie_tx_init(trans))
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		return -ENOMEM;

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	if (trans->cfg->base_params->shadow_reg_enable) {
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		/* enable shadow regs in HW */
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		iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
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		IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
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	}

	return 0;
}

#define HW_READY_TIMEOUT (50)

/* Note: returns poll_bit return value, which is >= 0 if success */
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static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
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{
	int ret;

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	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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		    CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
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	/* See if we got it */
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	ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
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			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
			   HW_READY_TIMEOUT);
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	IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
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	return ret;
}

/* Note: returns standard 0/-ERROR code */
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static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
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{
	int ret;
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	int t = 0;
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	IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
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	ret = iwl_pcie_set_hw_ready(trans);
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	/* If the card is ready, exit 0 */
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	if (ret >= 0)
		return 0;

	/* If HW is not ready, prepare the conditions to check again */
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	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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		    CSR_HW_IF_CONFIG_REG_PREPARE);
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	do {
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		ret = iwl_pcie_set_hw_ready(trans);
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		if (ret >= 0)
			return 0;
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		usleep_range(200, 1000);
		t += 200;
	} while (t < 150000);
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	return ret;
}

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/*
 * ucode
 */
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static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
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				   dma_addr_t phy_addr, u32 byte_cnt)
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{
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	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	int ret;

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	trans_pcie->ucode_write_complete = false;
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	iwl_write_direct32(trans,
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			   FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
			   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
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	iwl_write_direct32(trans,
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			   FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
			   dst_addr);
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	iwl_write_direct32(trans,
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			   FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
			   phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
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	iwl_write_direct32(trans,
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			   FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
			   (iwl_get_dma_hi_addr(phy_addr)
				<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
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	iwl_write_direct32(trans,
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			   FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
			   1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
			   1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
			   FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
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	iwl_write_direct32(trans,
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			   FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
			   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE	|
			   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE	|
			   FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
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	ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
				 trans_pcie->ucode_write_complete, 5 * HZ);
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	if (!ret) {
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		IWL_ERR(trans, "Failed to load firmware chunk!\n");
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		return -ETIMEDOUT;
	}

	return 0;
}

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static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
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			    const struct fw_desc *section)
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{
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	u8 *v_addr;
	dma_addr_t p_addr;
	u32 offset;
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	int ret = 0;

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	IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
		     section_num);

	v_addr = dma_alloc_coherent(trans->dev, PAGE_SIZE, &p_addr, GFP_KERNEL);
	if (!v_addr)
		return -ENOMEM;

	for (offset = 0; offset < section->len; offset += PAGE_SIZE) {
		u32 copy_size;

		copy_size = min_t(u32, PAGE_SIZE, section->len - offset);
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		memcpy(v_addr, (u8 *)section->data + offset, copy_size);
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		ret = iwl_pcie_load_firmware_chunk(trans,
						   section->offset + offset,
						   p_addr, copy_size);
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		if (ret) {
			IWL_ERR(trans,
				"Could not load the [%d] uCode section\n",
				section_num);
			break;
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		}
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	}

	dma_free_coherent(trans->dev, PAGE_SIZE, v_addr, p_addr);
	return ret;
}

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static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
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				const struct fw_img *image)
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{
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	int i, ret = 0;
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	for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
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		if (!image->sec[i].data)
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			break;
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		ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
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		if (ret)
			return ret;
	}
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	/* Remove all resets to allow NIC to operate */
	iwl_write32(trans, CSR_RESET, 0);

	return 0;
}

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static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
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				   const struct fw_img *fw, bool run_in_rfkill)
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{
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	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	int ret;
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	bool hw_rfkill;
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	/* This may fail if AMT took ownership of the device */
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	if (iwl_pcie_prepare_card_hw(trans)) {
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		IWL_WARN(trans, "Exit HW not ready\n");
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		return -EIO;
	}

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	clear_bit(STATUS_FW_ERROR, &trans_pcie->status);

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	iwl_enable_rfkill_int(trans);

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	/* If platform's RF_KILL switch is NOT set to KILL */
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	hw_rfkill = iwl_is_rfkill_set(trans);
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	iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
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	if (hw_rfkill && !run_in_rfkill)
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		return -ERFKILL;

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	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
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	ret = iwl_pcie_nic_init(trans);
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	if (ret) {
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		IWL_ERR(trans, "Unable to init nic\n");
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		return ret;
	}

	/* make sure rfkill handshake bits are cleared */
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	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
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		    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);

	/* clear (again), then enable host interrupts */
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	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
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	iwl_enable_interrupts(trans);
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	/* really make sure rfkill handshake bits are cleared */
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	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
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	/* Load the given image to the HW */
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	return iwl_pcie_load_given_ucode(trans, fw);
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}

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static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
486
{
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	iwl_pcie_reset_ict(trans);
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	iwl_pcie_tx_start(trans, scd_addr);
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}

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static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
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{
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	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	unsigned long flags;
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	/* tell the device to stop sending interrupts */
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	spin_lock_irqsave(&trans_pcie->irq_lock, flags);
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	iwl_disable_interrupts(trans);
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	spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
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	/* device going down, Stop using ICT table */
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	iwl_pcie_disable_ict(trans);
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	/*
	 * If a HW restart happens during firmware loading,
	 * then the firmware loading might call this function
	 * and later it might be called again due to the
	 * restart. So don't process again if the device is
	 * already dead.
	 */
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	if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
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		iwl_pcie_tx_stop(trans);
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		iwl_pcie_rx_stop(trans);
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		/* Power-down device's busmaster DMA clocks */
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		iwl_write_prph(trans, APMG_CLK_DIS_REG,
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			       APMG_CLK_VAL_DMA_CLK_RQT);
		udelay(5);
	}

	/* Make sure (redundant) we've released our request to stay awake */
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	iwl_clear_bit(trans, CSR_GP_CNTRL,
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		      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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	/* Stop the device, and put it in low power state */
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	iwl_pcie_apm_stop(trans);
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	/* Upon stop, the APM issues an interrupt if HW RF kill is set.
	 * Clean again the interrupt here
	 */
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	spin_lock_irqsave(&trans_pcie->irq_lock, flags);
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	iwl_disable_interrupts(trans);
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	spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
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	iwl_enable_rfkill_int(trans);

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	/* stop and reset the on-board processor */
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	iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
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	/* clear all status bits */
	clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
	clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
	clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
544
	clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
545
	clear_bit(STATUS_RFKILL, &trans_pcie->status);
546 547
}

548 549 550 551 552 553 554 555 556 557 558
static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
{
	/* let the ucode operate on its own */
	iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
		    CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);

	iwl_disable_interrupts(trans);
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
}

559
static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
560
{
561
	bool hw_rfkill;
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Johannes Berg 已提交
562
	int err;
563

564
	err = iwl_pcie_prepare_card_hw(trans);
565
	if (err) {
566
		IWL_ERR(trans, "Error while preparing HW: %d\n", err);
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567
		return err;
568
	}
569

570
	iwl_pcie_apm_init(trans);
571

572 573 574
	/* From now on, the op_mode will be kept updated about RF kill state */
	iwl_enable_rfkill_int(trans);

575
	hw_rfkill = iwl_is_rfkill_set(trans);
576
	iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
577

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Johannes Berg 已提交
578
	return 0;
579 580
}

581 582
static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
				   bool op_mode_leaving)
583
{
584
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
585
	bool hw_rfkill;
586
	unsigned long flags;
587

588 589 590 591
	spin_lock_irqsave(&trans_pcie->irq_lock, flags);
	iwl_disable_interrupts(trans);
	spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);

592
	iwl_pcie_apm_stop(trans);
593

594 595 596
	spin_lock_irqsave(&trans_pcie->irq_lock, flags);
	iwl_disable_interrupts(trans);
	spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
597

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Emmanuel Grumbach 已提交
598 599
	iwl_pcie_disable_ict(trans);

600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615
	if (!op_mode_leaving) {
		/*
		 * Even if we stop the HW, we still want the RF kill
		 * interrupt
		 */
		iwl_enable_rfkill_int(trans);

		/*
		 * Check again since the RF kill state may have changed while
		 * all the interrupts were disabled, in this case we couldn't
		 * receive the RF kill interrupt and update the state in the
		 * op_mode.
		 */
		hw_rfkill = iwl_is_rfkill_set(trans);
		iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
	}
616 617
}

618 619
static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
{
620
	writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
621 622 623 624
}

static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
{
625
	writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
626 627 628 629
}

static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
{
630
	return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
631 632
}

633 634 635 636 637 638 639 640 641 642 643 644 645 646
static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
{
	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
	return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
}

static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
				      u32 val)
{
	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
			       ((addr & 0x0000FFFF) | (3 << 24)));
	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
}

647
static void iwl_trans_pcie_configure(struct iwl_trans *trans,
648
				     const struct iwl_trans_config *trans_cfg)
649 650 651 652
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	trans_pcie->cmd_queue = trans_cfg->cmd_queue;
653
	trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
654 655 656 657 658 659 660
	if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
		trans_pcie->n_no_reclaim_cmds = 0;
	else
		trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
	if (trans_pcie->n_no_reclaim_cmds)
		memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
		       trans_pcie->n_no_reclaim_cmds * sizeof(u8));
661

662 663 664 665 666
	trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
	if (trans_pcie->rx_buf_size_8k)
		trans_pcie->rx_page_order = get_order(8 * 1024);
	else
		trans_pcie->rx_page_order = get_order(4 * 1024);
667 668 669

	trans_pcie->wd_timeout =
		msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
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Johannes Berg 已提交
670 671

	trans_pcie->command_names = trans_cfg->command_names;
672
	trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
673 674
}

675
void iwl_trans_pcie_free(struct iwl_trans *trans)
676
{
677
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
678

679 680 681
	synchronize_irq(trans_pcie->pci_dev->irq);
	tasklet_kill(&trans_pcie->irq_tasklet);

682
	iwl_pcie_tx_free(trans);
683
	iwl_pcie_rx_free(trans);
684

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Johannes Berg 已提交
685 686
	free_irq(trans_pcie->pci_dev->irq, trans);
	iwl_pcie_free_ict(trans);
687 688

	pci_disable_msi(trans_pcie->pci_dev);
689
	iounmap(trans_pcie->hw_base);
690 691
	pci_release_regions(trans_pcie->pci_dev);
	pci_disable_device(trans_pcie->pci_dev);
692
	kmem_cache_destroy(trans->dev_cmd_pool);
693

694
	kfree(trans);
695 696
}

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697 698 699 700 701
static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	if (state)
702
		set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
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Don Fry 已提交
703
	else
704
		clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
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705 706
}

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707
#ifdef CONFIG_PM_SLEEP
708 709 710 711 712 713 714
static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
{
	return 0;
}

static int iwl_trans_pcie_resume(struct iwl_trans *trans)
{
715
	bool hw_rfkill;
716

717 718
	iwl_enable_rfkill_int(trans);

719
	hw_rfkill = iwl_is_rfkill_set(trans);
720
	iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
721

722 723
	return 0;
}
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Johannes Berg 已提交
724
#endif /* CONFIG_PM_SLEEP */
725

726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786
static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent)
{
	int ret;

	lockdep_assert_held(&trans->reg_lock);

	/* this bit wakes up the NIC */
	__iwl_set_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);

	/*
	 * These bits say the device is running, and should keep running for
	 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
	 * but they do not indicate that embedded SRAM is restored yet;
	 * 3945 and 4965 have volatile SRAM, and must save/restore contents
	 * to/from host DRAM when sleeping/waking for power-saving.
	 * Each direction takes approximately 1/4 millisecond; with this
	 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
	 * series of register accesses are expected (e.g. reading Event Log),
	 * to keep device from sleeping.
	 *
	 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
	 * SRAM is okay/restored.  We don't check that here because this call
	 * is just for hardware register access; but GP1 MAC_SLEEP check is a
	 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
	 *
	 * 5000 series and later (including 1000 series) have non-volatile SRAM,
	 * and do not save/restore SRAM when power cycling.
	 */
	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
			   CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
			   (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
			    CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
	if (unlikely(ret < 0)) {
		iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
		if (!silent) {
			u32 val = iwl_read32(trans, CSR_GP_CNTRL);
			WARN_ONCE(1,
				  "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
				  val);
			return false;
		}
	}

	return true;
}

static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)
{
	lockdep_assert_held(&trans->reg_lock);
	__iwl_clear_bit(trans, CSR_GP_CNTRL,
			CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
	/*
	 * Above we read the CSR_GP_CNTRL register, which will flush
	 * any previous writes, but we need the write that clears the
	 * MAC_ACCESS_REQ bit to be performed before any other writes
	 * scheduled on different CPUs (after we drop reg_lock).
	 */
	mmiowb();
}

787 788 789 790 791 792 793 794
static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
				   void *buf, int dwords)
{
	unsigned long flags;
	int offs, ret = 0;
	u32 *vals = buf;

	spin_lock_irqsave(&trans->reg_lock, flags);
795
	if (iwl_trans_grab_nic_access(trans, false)) {
796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814
		iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
		for (offs = 0; offs < dwords; offs++)
			vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
		iwl_trans_release_nic_access(trans);
	} else {
		ret = -EBUSY;
	}
	spin_unlock_irqrestore(&trans->reg_lock, flags);
	return ret;
}

static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
				    void *buf, int dwords)
{
	unsigned long flags;
	int offs, ret = 0;
	u32 *vals = buf;

	spin_lock_irqsave(&trans->reg_lock, flags);
815
	if (iwl_trans_grab_nic_access(trans, false)) {
816 817 818 819 820 821 822 823 824 825
		iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
		for (offs = 0; offs < dwords; offs++)
			iwl_write32(trans, HBUS_TARG_MEM_WDAT, vals[offs]);
		iwl_trans_release_nic_access(trans);
	} else {
		ret = -EBUSY;
	}
	spin_unlock_irqrestore(&trans->reg_lock, flags);
	return ret;
}
826

827 828
#define IWL_FLUSH_WAIT_MS	2000

829
static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
830
{
831
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
832
	struct iwl_txq *txq;
833 834 835 836 837 838
	struct iwl_queue *q;
	int cnt;
	unsigned long now = jiffies;
	int ret = 0;

	/* waiting for all the tx frames complete might take a while */
839
	for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
W
Wey-Yi Guy 已提交
840
		if (cnt == trans_pcie->cmd_queue)
841
			continue;
842
		txq = &trans_pcie->txq[cnt];
843 844 845 846 847 848 849 850 851 852 853 854 855 856
		q = &txq->q;
		while (q->read_ptr != q->write_ptr && !time_after(jiffies,
		       now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
			msleep(1);

		if (q->read_ptr != q->write_ptr) {
			IWL_ERR(trans, "fail to flush all tx fifo queues\n");
			ret = -ETIMEDOUT;
			break;
		}
	}
	return ret;
}

857 858
static const char *get_fh_string(int cmd)
{
J
Johannes Berg 已提交
859
#define IWL_CMD(x) case x: return #x
860 861 862 863 864 865 866 867 868 869 870 871 872
	switch (cmd) {
	IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
	IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
	IWL_CMD(FH_RSCSR_CHNL0_WPTR);
	IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
	IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
	IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
	IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
	IWL_CMD(FH_TSSR_TX_STATUS_REG);
	IWL_CMD(FH_TSSR_TX_ERROR_REG);
	default:
		return "UNKNOWN";
	}
J
Johannes Berg 已提交
873
#undef IWL_CMD
874 875
}

876
int iwl_pcie_dump_fh(struct iwl_trans *trans, char **buf)
877 878 879 880 881 882 883 884 885 886 887 888 889
{
	int i;
	static const u32 fh_tbl[] = {
		FH_RSCSR_CHNL0_STTS_WPTR_REG,
		FH_RSCSR_CHNL0_RBDCB_BASE_REG,
		FH_RSCSR_CHNL0_WPTR,
		FH_MEM_RCSR_CHNL0_CONFIG_REG,
		FH_MEM_RSSR_SHARED_CTRL_REG,
		FH_MEM_RSSR_RX_STATUS_REG,
		FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
		FH_TSSR_TX_STATUS_REG,
		FH_TSSR_TX_ERROR_REG
	};
890 891 892 893 894 895

#ifdef CONFIG_IWLWIFI_DEBUGFS
	if (buf) {
		int pos = 0;
		size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;

896 897 898
		*buf = kmalloc(bufsz, GFP_KERNEL);
		if (!*buf)
			return -ENOMEM;
899

900 901
		pos += scnprintf(*buf + pos, bufsz - pos,
				"FH register values:\n");
902 903

		for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
904 905 906
			pos += scnprintf(*buf + pos, bufsz - pos,
				"  %34s: 0X%08x\n",
				get_fh_string(fh_tbl[i]),
907
				iwl_read_direct32(trans, fh_tbl[i]));
908

909 910 911
		return pos;
	}
#endif
912

913
	IWL_ERR(trans, "FH register values:\n");
914
	for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++)
915 916
		IWL_ERR(trans, "  %34s: 0X%08x\n",
			get_fh_string(fh_tbl[i]),
917
			iwl_read_direct32(trans, fh_tbl[i]));
918

919 920 921 922 923
	return 0;
}

static const char *get_csr_string(int cmd)
{
J
Johannes Berg 已提交
924
#define IWL_CMD(x) case x: return #x
925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951
	switch (cmd) {
	IWL_CMD(CSR_HW_IF_CONFIG_REG);
	IWL_CMD(CSR_INT_COALESCING);
	IWL_CMD(CSR_INT);
	IWL_CMD(CSR_INT_MASK);
	IWL_CMD(CSR_FH_INT_STATUS);
	IWL_CMD(CSR_GPIO_IN);
	IWL_CMD(CSR_RESET);
	IWL_CMD(CSR_GP_CNTRL);
	IWL_CMD(CSR_HW_REV);
	IWL_CMD(CSR_EEPROM_REG);
	IWL_CMD(CSR_EEPROM_GP);
	IWL_CMD(CSR_OTP_GP_REG);
	IWL_CMD(CSR_GIO_REG);
	IWL_CMD(CSR_GP_UCODE_REG);
	IWL_CMD(CSR_GP_DRIVER_REG);
	IWL_CMD(CSR_UCODE_DRV_GP1);
	IWL_CMD(CSR_UCODE_DRV_GP2);
	IWL_CMD(CSR_LED_REG);
	IWL_CMD(CSR_DRAM_INT_TBL_REG);
	IWL_CMD(CSR_GIO_CHICKEN_BITS);
	IWL_CMD(CSR_ANA_PLL_CFG);
	IWL_CMD(CSR_HW_REV_WA_REG);
	IWL_CMD(CSR_DBG_HPET_MEM_REG);
	default:
		return "UNKNOWN";
	}
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Johannes Berg 已提交
952
#undef IWL_CMD
953 954
}

955
void iwl_pcie_dump_csr(struct iwl_trans *trans)
956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988
{
	int i;
	static const u32 csr_tbl[] = {
		CSR_HW_IF_CONFIG_REG,
		CSR_INT_COALESCING,
		CSR_INT,
		CSR_INT_MASK,
		CSR_FH_INT_STATUS,
		CSR_GPIO_IN,
		CSR_RESET,
		CSR_GP_CNTRL,
		CSR_HW_REV,
		CSR_EEPROM_REG,
		CSR_EEPROM_GP,
		CSR_OTP_GP_REG,
		CSR_GIO_REG,
		CSR_GP_UCODE_REG,
		CSR_GP_DRIVER_REG,
		CSR_UCODE_DRV_GP1,
		CSR_UCODE_DRV_GP2,
		CSR_LED_REG,
		CSR_DRAM_INT_TBL_REG,
		CSR_GIO_CHICKEN_BITS,
		CSR_ANA_PLL_CFG,
		CSR_HW_REV_WA_REG,
		CSR_DBG_HPET_MEM_REG
	};
	IWL_ERR(trans, "CSR values:\n");
	IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
		"CSR_INT_PERIODIC_REG)\n");
	for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
		IWL_ERR(trans, "  %25s: 0X%08x\n",
			get_csr_string(csr_tbl[i]),
989
			iwl_read32(trans, csr_tbl[i]));
990 991 992
	}
}

993 994 995
#ifdef CONFIG_IWLWIFI_DEBUGFS
/* create and remove of files */
#define DEBUGFS_ADD_FILE(name, parent, mode) do {			\
996
	if (!debugfs_create_file(#name, mode, parent, trans,		\
997
				 &iwl_dbgfs_##name##_ops))		\
998
		goto err;						\
999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015
} while (0)

/* file operation */
#define DEBUGFS_READ_FUNC(name)                                         \
static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
					char __user *user_buf,          \
					size_t count, loff_t *ppos);

#define DEBUGFS_WRITE_FUNC(name)                                        \
static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
					const char __user *user_buf,    \
					size_t count, loff_t *ppos);

#define DEBUGFS_READ_FILE_OPS(name)					\
	DEBUGFS_READ_FUNC(name);					\
static const struct file_operations iwl_dbgfs_##name##_ops = {		\
	.read = iwl_dbgfs_##name##_read,				\
1016
	.open = simple_open,						\
1017 1018 1019
	.llseek = generic_file_llseek,					\
};

1020 1021 1022 1023
#define DEBUGFS_WRITE_FILE_OPS(name)                                    \
	DEBUGFS_WRITE_FUNC(name);                                       \
static const struct file_operations iwl_dbgfs_##name##_ops = {          \
	.write = iwl_dbgfs_##name##_write,                              \
1024
	.open = simple_open,						\
1025 1026 1027
	.llseek = generic_file_llseek,					\
};

1028 1029 1030 1031 1032 1033
#define DEBUGFS_READ_WRITE_FILE_OPS(name)				\
	DEBUGFS_READ_FUNC(name);					\
	DEBUGFS_WRITE_FUNC(name);					\
static const struct file_operations iwl_dbgfs_##name##_ops = {		\
	.write = iwl_dbgfs_##name##_write,				\
	.read = iwl_dbgfs_##name##_read,				\
1034
	.open = simple_open,						\
1035 1036 1037 1038
	.llseek = generic_file_llseek,					\
};

static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1039 1040
				       char __user *user_buf,
				       size_t count, loff_t *ppos)
1041
{
1042
	struct iwl_trans *trans = file->private_data;
1043
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1044
	struct iwl_txq *txq;
1045 1046 1047 1048 1049
	struct iwl_queue *q;
	char *buf;
	int pos = 0;
	int cnt;
	int ret;
1050 1051
	size_t bufsz;

1052
	bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1053

J
Johannes Berg 已提交
1054
	if (!trans_pcie->txq)
1055
		return -EAGAIN;
J
Johannes Berg 已提交
1056

1057 1058 1059 1060
	buf = kzalloc(bufsz, GFP_KERNEL);
	if (!buf)
		return -ENOMEM;

1061
	for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1062
		txq = &trans_pcie->txq[cnt];
1063 1064
		q = &txq->q;
		pos += scnprintf(buf + pos, bufsz - pos,
1065
				"hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1066
				cnt, q->read_ptr, q->write_ptr,
1067 1068
				!!test_bit(cnt, trans_pcie->queue_used),
				!!test_bit(cnt, trans_pcie->queue_stopped));
1069 1070 1071 1072 1073 1074 1075
	}
	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
	kfree(buf);
	return ret;
}

static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1076 1077 1078
				       char __user *user_buf,
				       size_t count, loff_t *ppos)
{
1079
	struct iwl_trans *trans = file->private_data;
1080
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1081
	struct iwl_rxq *rxq = &trans_pcie->rxq;
1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101
	char buf[256];
	int pos = 0;
	const size_t bufsz = sizeof(buf);

	pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
						rxq->read);
	pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
						rxq->write);
	pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
						rxq->free_count);
	if (rxq->rb_stts) {
		pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
			 le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
	} else {
		pos += scnprintf(buf + pos, bufsz - pos,
					"closed_rb_num: Not Allocated\n");
	}
	return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
}

1102 1103
static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
					char __user *user_buf,
1104 1105
					size_t count, loff_t *ppos)
{
1106
	struct iwl_trans *trans = file->private_data;
1107
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1108 1109 1110 1111 1112 1113 1114 1115
	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;

	int pos = 0;
	char *buf;
	int bufsz = 24 * 64; /* 24 items * 64 char per item */
	ssize_t ret;

	buf = kzalloc(bufsz, GFP_KERNEL);
J
Johannes Berg 已提交
1116
	if (!buf)
1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164
		return -ENOMEM;

	pos += scnprintf(buf + pos, bufsz - pos,
			"Interrupt Statistics Report:\n");

	pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
		isr_stats->hw);
	pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
		isr_stats->sw);
	if (isr_stats->sw || isr_stats->hw) {
		pos += scnprintf(buf + pos, bufsz - pos,
			"\tLast Restarting Code:  0x%X\n",
			isr_stats->err_code);
	}
#ifdef CONFIG_IWLWIFI_DEBUG
	pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
		isr_stats->sch);
	pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
		isr_stats->alive);
#endif
	pos += scnprintf(buf + pos, bufsz - pos,
		"HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);

	pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
		isr_stats->ctkill);

	pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
		isr_stats->wakeup);

	pos += scnprintf(buf + pos, bufsz - pos,
		"Rx command responses:\t\t %u\n", isr_stats->rx);

	pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
		isr_stats->tx);

	pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
		isr_stats->unhandled);

	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
	kfree(buf);
	return ret;
}

static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
					 const char __user *user_buf,
					 size_t count, loff_t *ppos)
{
	struct iwl_trans *trans = file->private_data;
1165
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183
	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;

	char buf[8];
	int buf_size;
	u32 reset_flag;

	memset(buf, 0, sizeof(buf));
	buf_size = min(count, sizeof(buf) -  1);
	if (copy_from_user(buf, user_buf, buf_size))
		return -EFAULT;
	if (sscanf(buf, "%x", &reset_flag) != 1)
		return -EFAULT;
	if (reset_flag == 0)
		memset(isr_stats, 0, sizeof(*isr_stats));

	return count;
}

1184
static ssize_t iwl_dbgfs_csr_write(struct file *file,
1185 1186
				   const char __user *user_buf,
				   size_t count, loff_t *ppos)
1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199
{
	struct iwl_trans *trans = file->private_data;
	char buf[8];
	int buf_size;
	int csr;

	memset(buf, 0, sizeof(buf));
	buf_size = min(count, sizeof(buf) -  1);
	if (copy_from_user(buf, user_buf, buf_size))
		return -EFAULT;
	if (sscanf(buf, "%d", &csr) != 1)
		return -EFAULT;

1200
	iwl_pcie_dump_csr(trans);
1201 1202 1203 1204 1205

	return count;
}

static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1206 1207
				     char __user *user_buf,
				     size_t count, loff_t *ppos)
1208 1209
{
	struct iwl_trans *trans = file->private_data;
1210
	char *buf = NULL;
1211 1212 1213
	int pos = 0;
	ssize_t ret = -EFAULT;

1214
	ret = pos = iwl_pcie_dump_fh(trans, &buf);
1215 1216 1217 1218 1219 1220 1221 1222 1223
	if (buf) {
		ret = simple_read_from_buffer(user_buf,
					      count, ppos, buf, pos);
		kfree(buf);
	}

	return ret;
}

1224 1225 1226 1227 1228 1229 1230 1231 1232
static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
					  const char __user *user_buf,
					  size_t count, loff_t *ppos)
{
	struct iwl_trans *trans = file->private_data;

	if (!trans->op_mode)
		return -EAGAIN;

1233
	local_bh_disable();
1234
	iwl_op_mode_nic_error(trans->op_mode);
1235
	local_bh_enable();
1236 1237 1238 1239

	return count;
}

1240
DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1241
DEBUGFS_READ_FILE_OPS(fh_reg);
1242 1243
DEBUGFS_READ_FILE_OPS(rx_queue);
DEBUGFS_READ_FILE_OPS(tx_queue);
1244
DEBUGFS_WRITE_FILE_OPS(csr);
1245
DEBUGFS_WRITE_FILE_OPS(fw_restart);
1246 1247 1248 1249 1250 1251

/*
 * Create the debugfs files and directories
 *
 */
static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1252
					 struct dentry *dir)
1253 1254 1255
{
	DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
	DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1256
	DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1257 1258
	DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
	DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1259
	DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
1260
	return 0;
1261 1262 1263 1264

err:
	IWL_ERR(trans, "failed to create the trans debugfs entry\n");
	return -ENOMEM;
1265 1266 1267
}
#else
static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1268 1269 1270 1271
					 struct dentry *dir)
{
	return 0;
}
1272 1273
#endif /*CONFIG_IWLWIFI_DEBUGFS */

1274
static const struct iwl_trans_ops trans_ops_pcie = {
1275
	.start_hw = iwl_trans_pcie_start_hw,
1276
	.stop_hw = iwl_trans_pcie_stop_hw,
1277
	.fw_alive = iwl_trans_pcie_fw_alive,
1278
	.start_fw = iwl_trans_pcie_start_fw,
1279
	.stop_device = iwl_trans_pcie_stop_device,
1280

1281 1282
	.wowlan_suspend = iwl_trans_pcie_wowlan_suspend,

1283
	.send_cmd = iwl_trans_pcie_send_hcmd,
1284

1285
	.tx = iwl_trans_pcie_tx,
1286
	.reclaim = iwl_trans_pcie_reclaim,
1287

1288
	.txq_disable = iwl_trans_pcie_txq_disable,
1289
	.txq_enable = iwl_trans_pcie_txq_enable,
1290

1291
	.dbgfs_register = iwl_trans_pcie_dbgfs_register,
1292

1293
	.wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1294

J
Johannes Berg 已提交
1295
#ifdef CONFIG_PM_SLEEP
1296 1297
	.suspend = iwl_trans_pcie_suspend,
	.resume = iwl_trans_pcie_resume,
J
Johannes Berg 已提交
1298
#endif
1299 1300 1301
	.write8 = iwl_trans_pcie_write8,
	.write32 = iwl_trans_pcie_write32,
	.read32 = iwl_trans_pcie_read32,
1302 1303
	.read_prph = iwl_trans_pcie_read_prph,
	.write_prph = iwl_trans_pcie_write_prph,
1304 1305
	.read_mem = iwl_trans_pcie_read_mem,
	.write_mem = iwl_trans_pcie_write_mem,
1306
	.configure = iwl_trans_pcie_configure,
D
Don Fry 已提交
1307
	.set_pmi = iwl_trans_pcie_set_pmi,
1308 1309
	.grab_nic_access = iwl_trans_pcie_grab_nic_access,
	.release_nic_access = iwl_trans_pcie_release_nic_access
1310
};
1311

1312
struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1313 1314
				       const struct pci_device_id *ent,
				       const struct iwl_cfg *cfg)
1315 1316 1317 1318 1319 1320 1321
{
	struct iwl_trans_pcie *trans_pcie;
	struct iwl_trans *trans;
	u16 pci_cmd;
	int err;

	trans = kzalloc(sizeof(struct iwl_trans) +
1322
			sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1323

1324
	if (!trans)
1325 1326 1327 1328 1329
		return NULL;

	trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	trans->ops = &trans_ops_pcie;
1330
	trans->cfg = cfg;
1331
	trans_pcie->trans = trans;
J
Johannes Berg 已提交
1332
	spin_lock_init(&trans_pcie->irq_lock);
1333
	init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1334 1335 1336 1337

	/* W/A - seems to solve weird behavior. We need to remove this if we
	 * don't want to stay in L1 all the time. This wastes a lot of power */
	pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
1338
			       PCIE_LINK_STATE_CLKPM);
1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353

	if (pci_enable_device(pdev)) {
		err = -ENODEV;
		goto out_no_pci;
	}

	pci_set_master(pdev);

	err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
	if (!err)
		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
	if (err) {
		err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
		if (!err)
			err = pci_set_consistent_dma_mask(pdev,
1354
							  DMA_BIT_MASK(32));
1355 1356
		/* both attempts failed: */
		if (err) {
1357
			dev_err(&pdev->dev, "No suitable DMA available\n");
1358 1359 1360 1361 1362 1363
			goto out_pci_disable_device;
		}
	}

	err = pci_request_regions(pdev, DRV_NAME);
	if (err) {
1364
		dev_err(&pdev->dev, "pci_request_regions failed\n");
1365 1366 1367
		goto out_pci_disable_device;
	}

1368
	trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1369
	if (!trans_pcie->hw_base) {
1370
		dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1371 1372 1373 1374 1375 1376 1377 1378 1379
		err = -ENODEV;
		goto out_pci_release_regions;
	}

	/* We disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state */
	pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);

	err = pci_enable_msi(pdev);
1380
	if (err) {
1381
		dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1382 1383 1384 1385 1386 1387 1388
		/* enable rfkill interrupt: hw bug w/a */
		pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
		if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
			pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
			pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
		}
	}
1389 1390 1391

	trans->dev = &pdev->dev;
	trans_pcie->pci_dev = pdev;
1392
	trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
E
Emmanuel Grumbach 已提交
1393
	trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1394 1395
	snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
		 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1396

1397
	/* Initialize the wait queue for commands */
1398
	init_waitqueue_head(&trans_pcie->wait_command_queue);
1399
	spin_lock_init(&trans->reg_lock);
1400

1401 1402
	snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
		 "iwl_cmd_pool:%s", dev_name(trans->dev));
1403 1404 1405

	trans->dev_cmd_headroom = 0;
	trans->dev_cmd_pool =
1406
		kmem_cache_create(trans->dev_cmd_pool_name,
1407 1408 1409 1410 1411 1412 1413 1414 1415
				  sizeof(struct iwl_device_cmd)
				  + trans->dev_cmd_headroom,
				  sizeof(void *),
				  SLAB_HWCACHE_ALIGN,
				  NULL);

	if (!trans->dev_cmd_pool)
		goto out_pci_disable_msi;

J
Johannes Berg 已提交
1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430
	trans_pcie->inta_mask = CSR_INI_SET_MASK;

	tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
		     iwl_pcie_tasklet, (unsigned long)trans);

	if (iwl_pcie_alloc_ict(trans))
		goto out_free_cmd_pool;

	err = request_irq(pdev->irq, iwl_pcie_isr_ict,
			  IRQF_SHARED, DRV_NAME, trans);
	if (err) {
		IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
		goto out_free_ict;
	}

1431 1432
	return trans;

J
Johannes Berg 已提交
1433 1434 1435 1436
out_free_ict:
	iwl_pcie_free_ict(trans);
out_free_cmd_pool:
	kmem_cache_destroy(trans->dev_cmd_pool);
1437 1438
out_pci_disable_msi:
	pci_disable_msi(pdev);
1439 1440 1441 1442 1443 1444 1445 1446
out_pci_release_regions:
	pci_release_regions(pdev);
out_pci_disable_device:
	pci_disable_device(pdev);
out_no_pci:
	kfree(trans);
	return NULL;
}