trans.c 61.5 KB
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/******************************************************************************
 *
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * GPL LICENSE SUMMARY
 *
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Wey-Yi Guy 已提交
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 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 * USA
 *
 * The full GNU General Public License is included in this distribution
 * in the file called LICENSE.GPL.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 * BSD LICENSE
 *
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 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
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 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name Intel Corporation nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/
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#include <linux/pci.h>
#include <linux/pci-aspm.h>
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#include <linux/interrupt.h>
66
#include <linux/debugfs.h>
67
#include <linux/sched.h>
68 69
#include <linux/bitops.h>
#include <linux/gfp.h>
70

71
#include "iwl-drv.h"
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#include "iwl-trans.h"
73 74
#include "iwl-csr.h"
#include "iwl-prph.h"
75
#include "iwl-agn-hw.h"
76
#include "internal.h"
77
/* FIXME: need to abstract out TX command (once we know what it looks like) */
78
#include "dvm/commands.h"
79

80
#define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie)	\
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	(((1<<trans->cfg->base_params->num_of_queues) - 1) &\
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	(~(1<<(trans_pcie)->cmd_queue)))

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static int iwl_trans_rx_alloc(struct iwl_trans *trans)
85
{
86
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
87
	struct iwl_rxq *rxq = &trans_pcie->rxq;
88
	struct device *dev = trans->dev;
89

90
	memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
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	spin_lock_init(&rxq->lock);

	if (WARN_ON(rxq->bd || rxq->rb_stts))
		return -EINVAL;

	/* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
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	rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
				      &rxq->bd_dma, GFP_KERNEL);
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	if (!rxq->bd)
		goto err_bd;

	/*Allocate the driver's pointer to receive buffer status */
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	rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
					   &rxq->rb_stts_dma, GFP_KERNEL);
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	if (!rxq->rb_stts)
		goto err_rb_stts;

	return 0;

err_rb_stts:
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	dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
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			  rxq->bd, rxq->bd_dma);
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	memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
	rxq->bd = NULL;
err_bd:
	return -ENOMEM;
}

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static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
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{
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	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	struct iwl_rxq *rxq = &trans_pcie->rxq;
124
	int i;
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	/* Fill the rx_used queue with _all_ of the Rx buffers */
	for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
		/* In the reset function, these buffers may have been allocated
		 * to an SKB, so we need to unmap and free potential storage */
		if (rxq->pool[i].page != NULL) {
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			dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
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				       PAGE_SIZE << trans_pcie->rx_page_order,
				       DMA_FROM_DEVICE);
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			__free_pages(rxq->pool[i].page,
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				     trans_pcie->rx_page_order);
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			rxq->pool[i].page = NULL;
		}
		list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
	}
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}

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static void iwl_trans_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
143
{
144
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	u32 rb_size;
	const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
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	u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
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149
	if (trans_pcie->rx_buf_size_8k)
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		rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
	else
		rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;

	/* Stop Rx DMA */
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	iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
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	/* Reset driver's Rx queue write index */
158
	iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
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	/* Tell device where to find RBD circular buffer in DRAM */
161
	iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
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			   (u32)(rxq->bd_dma >> 8));

	/* Tell device where in DRAM to update its Rx status */
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	iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
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			   rxq->rb_stts_dma >> 4);

	/* Enable Rx DMA
	 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
	 *      the credit mechanism in 5000 HW RX FIFO
	 * Direct rx interrupts to hosts
	 * Rx buffer size 4 or 8k
	 * RB timeout 0x10
	 * 256 RBDs
	 */
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	iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
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			   FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
			   FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
			   FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
			   rb_size|
			   (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
			   (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));

	/* Set interrupt coalescing timer to default (2048 usecs) */
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	iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
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}

188
static int iwl_rx_init(struct iwl_trans *trans)
189
{
190
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
191
	struct iwl_rxq *rxq = &trans_pcie->rxq;
192

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	int i, err;
	unsigned long flags;

	if (!rxq->bd) {
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		err = iwl_trans_rx_alloc(trans);
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		if (err)
			return err;
	}

	spin_lock_irqsave(&rxq->lock, flags);
	INIT_LIST_HEAD(&rxq->rx_free);
	INIT_LIST_HEAD(&rxq->rx_used);

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	INIT_WORK(&trans_pcie->rx_replenish,
		  iwl_pcie_rx_replenish_work);

209
	iwl_trans_rxq_free_rx_bufs(trans);
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	for (i = 0; i < RX_QUEUE_SIZE; i++)
		rxq->queue[i] = NULL;

	/* Set us so that we have processed and used all buffers, but have
	 * not restocked the Rx queue with fresh buffers */
	rxq->read = rxq->write = 0;
	rxq->write_actual = 0;
	rxq->free_count = 0;
	spin_unlock_irqrestore(&rxq->lock, flags);

221
	iwl_pcie_rx_replenish(trans);
222

223
	iwl_trans_rx_hw_init(trans, rxq);
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	spin_lock_irqsave(&trans_pcie->irq_lock, flags);
226
	rxq->need_update = 1;
227
	iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
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	spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
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	return 0;
}

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static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
234
{
235
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
236
	struct iwl_rxq *rxq = &trans_pcie->rxq;
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	unsigned long flags;

	/*if rxq->bd is NULL, it means that nothing has been allocated,
	 * exit now */
	if (!rxq->bd) {
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		IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
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		return;
	}

	spin_lock_irqsave(&rxq->lock, flags);
247
	iwl_trans_rxq_free_rx_bufs(trans);
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	spin_unlock_irqrestore(&rxq->lock, flags);

250
	dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
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			  rxq->bd, rxq->bd_dma);
	memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
	rxq->bd = NULL;

	if (rxq->rb_stts)
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		dma_free_coherent(trans->dev,
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				  sizeof(struct iwl_rb_status),
				  rxq->rb_stts, rxq->rb_stts_dma);
	else
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		IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
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	memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
	rxq->rb_stts = NULL;
}

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static int iwl_trans_rx_stop(struct iwl_trans *trans)
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{

	/* stop Rx DMA */
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	iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
	return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
271
				   FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
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}

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static int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
				struct iwl_dma_ptr *ptr, size_t size)
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{
	if (WARN_ON(ptr->addr))
		return -EINVAL;

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	ptr->addr = dma_alloc_coherent(trans->dev, size,
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				       &ptr->dma, GFP_KERNEL);
	if (!ptr->addr)
		return -ENOMEM;
	ptr->size = size;
	return 0;
}

288 289
static void iwlagn_free_dma_ptr(struct iwl_trans *trans,
				struct iwl_dma_ptr *ptr)
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{
	if (unlikely(!ptr->addr))
		return;

294
	dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
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	memset(ptr, 0, sizeof(*ptr));
}

298 299
static void iwl_trans_pcie_queue_stuck_timer(unsigned long data)
{
300
	struct iwl_txq *txq = (void *)data;
301
	struct iwl_queue *q = &txq->q;
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	struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
	struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
304
	u32 scd_sram_addr = trans_pcie->scd_base_addr +
305
				SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
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	u8 buf[16];
	int i;
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	spin_lock(&txq->lock);
	/* check if triggered erroneously */
	if (txq->q.read_ptr == txq->q.write_ptr) {
		spin_unlock(&txq->lock);
		return;
	}
	spin_unlock(&txq->lock);

	IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
		jiffies_to_msecs(trans_pcie->wd_timeout));
	IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
		txq->q.read_ptr, txq->q.write_ptr);

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	iwl_read_targ_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));

	iwl_print_hex_error(trans, buf, sizeof(buf));

	for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
		IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
			iwl_read_direct32(trans, FH_TX_TRB_REG(i)));

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	for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
		u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
		u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
		bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
		u32 tbl_dw =
			iwl_read_targ_mem(trans,
					  trans_pcie->scd_base_addr +
					  SCD_TRANS_TBL_OFFSET_QUEUE(i));

		if (i & 0x1)
			tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
		else
			tbl_dw = tbl_dw & 0x0000FFFF;

		IWL_ERR(trans,
			"Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
			i, active ? "" : "in", fifo, tbl_dw,
			iwl_read_prph(trans,
				      SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1),
			iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
	}
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	for (i = q->read_ptr; i != q->write_ptr;
	     i = iwl_queue_inc_wrap(i, q->n_bd)) {
		struct iwl_tx_cmd *tx_cmd =
			(struct iwl_tx_cmd *)txq->entries[i].cmd->payload;
		IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
			get_unaligned_le32(&tx_cmd->scratch));
	}

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	iwl_op_mode_nic_error(trans->op_mode);
}

363
static int iwl_trans_txq_alloc(struct iwl_trans *trans,
364
			       struct iwl_txq *txq, int slots_num,
365
			       u32 txq_id)
366
{
367
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
368
	size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
369 370
	int i;

371
	if (WARN_ON(txq->entries || txq->tfds))
372 373
		return -EINVAL;

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	setup_timer(&txq->stuck_timer, iwl_trans_pcie_queue_stuck_timer,
		    (unsigned long)txq);
	txq->trans_pcie = trans_pcie;

378 379
	txq->q.n_window = slots_num;

380
	txq->entries = kcalloc(slots_num,
381
			       sizeof(struct iwl_pcie_txq_entry),
382
			       GFP_KERNEL);
383

384
	if (!txq->entries)
385 386
		goto error;

387
	if (txq_id == trans_pcie->cmd_queue)
388
		for (i = 0; i < slots_num; i++) {
389 390 391 392
			txq->entries[i].cmd =
				kmalloc(sizeof(struct iwl_device_cmd),
					GFP_KERNEL);
			if (!txq->entries[i].cmd)
393 394
				goto error;
		}
395 396 397

	/* Circular buffer of transmit frame descriptors (TFDs),
	 * shared with device */
398
	txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
399
				       &txq->q.dma_addr, GFP_KERNEL);
400
	if (!txq->tfds) {
401
		IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
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		goto error;
	}
	txq->q.id = txq_id;

	return 0;
error:
408
	if (txq->entries && txq_id == trans_pcie->cmd_queue)
409
		for (i = 0; i < slots_num; i++)
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			kfree(txq->entries[i].cmd);
	kfree(txq->entries);
	txq->entries = NULL;
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	return -ENOMEM;

}

418
static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
419
			      int slots_num, u32 txq_id)
420 421 422 423 424 425 426 427 428 429
{
	int ret;

	txq->need_update = 0;

	/* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
	 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
	BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));

	/* Initialize queue's high/low-water marks, and head/tail indexes */
430
	ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
431 432 433 434
			txq_id);
	if (ret)
		return ret;

435 436
	spin_lock_init(&txq->lock);

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	/*
	 * Tell nic where to find circular buffer of Tx Frame Descriptors for
	 * given Tx queue, and enable the DMA channel used for that queue.
	 * Circular buffer (TFD queue in DRAM) physical base address */
441
	iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
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			     txq->q.dma_addr >> 8);

	return 0;
}

447
/*
448
 * iwl_pcie_txq_unmap -  Unmap any remaining DMA mappings and free skb's
449
 */
450
void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
451
{
452
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
453
	struct iwl_txq *txq = &trans_pcie->txq[txq_id];
454
	struct iwl_queue *q = &txq->q;
455
	enum dma_data_direction dma_dir;
456 457 458 459

	if (!q->n_bd)
		return;

460 461 462
	/* In the command queue, all the TBs are mapped as BIDI
	 * so unmap them as such.
	 */
463
	if (txq_id == trans_pcie->cmd_queue)
464
		dma_dir = DMA_BIDIRECTIONAL;
465
	else
466 467
		dma_dir = DMA_TO_DEVICE;

468
	spin_lock_bh(&txq->lock);
469
	while (q->write_ptr != q->read_ptr) {
470
		iwl_pcie_txq_free_tfd(trans, txq, dma_dir);
471 472
		q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
	}
473
	spin_unlock_bh(&txq->lock);
474 475
}

476 477
/*
 * iwl_txq_free - Deallocate DMA queue.
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 * @txq: Transmit queue to deallocate.
 *
 * Empty queue by removing and destroying all BD's.
 * Free all buffers.
 * 0-fill, but do not free "txq" descriptor structure.
 */
484
static void iwl_txq_free(struct iwl_trans *trans, int txq_id)
485
{
486
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
487
	struct iwl_txq *txq = &trans_pcie->txq[txq_id];
488
	struct device *dev = trans->dev;
489
	int i;
490

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	if (WARN_ON(!txq))
		return;

494
	iwl_pcie_txq_unmap(trans, txq_id);
495 496

	/* De-alloc array of command/tx buffers */
497
	if (txq_id == trans_pcie->cmd_queue)
498
		for (i = 0; i < txq->q.n_window; i++) {
499
			kfree(txq->entries[i].cmd);
500
			kfree(txq->entries[i].copy_cmd);
501
			kfree(txq->entries[i].free_buf);
502
		}
503 504 505

	/* De-alloc circular buffer of TFDs */
	if (txq->q.n_bd) {
506
		dma_free_coherent(dev, sizeof(struct iwl_tfd) *
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				  txq->q.n_bd, txq->tfds, txq->q.dma_addr);
		memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
	}

511 512
	kfree(txq->entries);
	txq->entries = NULL;
513

514 515
	del_timer_sync(&txq->stuck_timer);

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	/* 0-fill queue descriptor structure */
	memset(txq, 0, sizeof(*txq));
}

520
/*
521 522 523 524
 * iwl_trans_tx_free - Free TXQ Context
 *
 * Destroy all TX DMA queues and structures
 */
525
static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
526 527
{
	int txq_id;
528
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
529 530

	/* Tx queues */
531
	if (trans_pcie->txq) {
532
		for (txq_id = 0;
533
		     txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
534
			iwl_txq_free(trans, txq_id);
535 536
	}

537 538
	kfree(trans_pcie->txq);
	trans_pcie->txq = NULL;
539

540
	iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
541

542
	iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
543 544
}

545
/*
546 547 548
 * iwl_trans_tx_alloc - allocate TX context
 * Allocate all Tx DMA structures and initialize them
 */
549
static int iwl_trans_tx_alloc(struct iwl_trans *trans)
550 551 552
{
	int ret;
	int txq_id, slots_num;
553
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
554

555
	u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
556 557
			sizeof(struct iwlagn_scd_bc_tbl);

558 559
	/*It is not allowed to alloc twice, so warn when this happens.
	 * We cannot rely on the previous allocation, so free and fail */
560
	if (WARN_ON(trans_pcie->txq)) {
561 562 563 564
		ret = -EINVAL;
		goto error;
	}

565
	ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
566
				   scd_bc_tbls_size);
567
	if (ret) {
568
		IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
569 570 571 572
		goto error;
	}

	/* Alloc keep-warm buffer */
573
	ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
574
	if (ret) {
575
		IWL_ERR(trans, "Keep Warm allocation failed\n");
576 577 578
		goto error;
	}

579
	trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
580
				  sizeof(struct iwl_txq), GFP_KERNEL);
581
	if (!trans_pcie->txq) {
582
		IWL_ERR(trans, "Not enough memory for txq\n");
583 584 585 586 587
		ret = ENOMEM;
		goto error;
	}

	/* Alloc and init all Tx queues, including the command queue (#4/#9) */
588
	for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
589
	     txq_id++) {
W
Wey-Yi Guy 已提交
590
		slots_num = (txq_id == trans_pcie->cmd_queue) ?
591
					TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
592 593
		ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
					  slots_num, txq_id);
594
		if (ret) {
595
			IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
596 597 598 599 600 601 602
			goto error;
		}
	}

	return 0;

error:
603
	iwl_trans_pcie_tx_free(trans);
604 605 606

	return ret;
}
607
static int iwl_tx_init(struct iwl_trans *trans)
608
{
609
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
610 611 612 613 614
	int ret;
	int txq_id, slots_num;
	unsigned long flags;
	bool alloc = false;

615
	if (!trans_pcie->txq) {
616
		ret = iwl_trans_tx_alloc(trans);
617 618 619 620 621
		if (ret)
			goto error;
		alloc = true;
	}

J
Johannes Berg 已提交
622
	spin_lock_irqsave(&trans_pcie->irq_lock, flags);
623 624

	/* Turn off all Tx DMA fifos */
625
	iwl_write_prph(trans, SCD_TXFACT, 0);
626 627

	/* Tell NIC where to find the "keep warm" buffer */
628
	iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
629
			   trans_pcie->kw.dma >> 4);
630

J
Johannes Berg 已提交
631
	spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
632 633

	/* Alloc and init all Tx queues, including the command queue (#4/#9) */
634
	for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
635
	     txq_id++) {
W
Wey-Yi Guy 已提交
636
		slots_num = (txq_id == trans_pcie->cmd_queue) ?
637
					TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
638 639
		ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
					 slots_num, txq_id);
640
		if (ret) {
641
			IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
642 643 644 645 646 647 648 649
			goto error;
		}
	}

	return 0;
error:
	/*Upon error, free only if we allocated something */
	if (alloc)
650
		iwl_trans_pcie_tx_free(trans);
651 652 653
	return ret;
}

654
static void iwl_set_pwr_vmain(struct iwl_trans *trans)
655 656 657 658 659 660
{
/*
 * (for documentation purposes)
 * to set power to V_AUX, do:

		if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
661
			iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
662 663 664 665
					       APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
					       ~APMG_PS_CTRL_MSK_PWR_SRC);
 */

666
	iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
667 668 669 670
			       APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
			       ~APMG_PS_CTRL_MSK_PWR_SRC);
}

E
Emmanuel Grumbach 已提交
671 672 673 674 675 676 677
/* PCI registers */
#define PCI_CFG_RETRY_TIMEOUT	0x041
#define PCI_CFG_LINK_CTRL_VAL_L0S_EN	0x01
#define PCI_CFG_LINK_CTRL_VAL_L1_EN	0x02

static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
{
678
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
E
Emmanuel Grumbach 已提交
679 680
	u16 pci_lnk_ctl;

681 682
	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL,
				  &pci_lnk_ctl);
E
Emmanuel Grumbach 已提交
683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709
	return pci_lnk_ctl;
}

static void iwl_apm_config(struct iwl_trans *trans)
{
	/*
	 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
	 * Check if BIOS (or OS) enabled L1-ASPM on this device.
	 * If so (likely), disable L0S, so device moves directly L0->L1;
	 *    costs negligible amount of power savings.
	 * If not (unlikely), enable L0S, so there is at least some
	 *    power savings, even without L1.
	 */
	u16 lctl = iwl_pciexp_link_ctrl(trans);

	if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
				PCI_CFG_LINK_CTRL_VAL_L1_EN) {
		/* L1-ASPM enabled; disable(!) L0S */
		iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
		dev_printk(KERN_INFO, trans->dev,
			   "L1 Enabled; Disabling L0S\n");
	} else {
		/* L1-ASPM disabled; enable(!) L0S */
		iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
		dev_printk(KERN_INFO, trans->dev,
			   "L1 Disabled; Enabling L0S\n");
	}
710
	trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
E
Emmanuel Grumbach 已提交
711 712
}

713 714 715 716 717 718 719
/*
 * Start up NIC's basic functionality after it has been reset
 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 * NOTE:  This does not load uCode nor start the embedded processor
 */
static int iwl_apm_init(struct iwl_trans *trans)
{
D
Don Fry 已提交
720
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
721 722 723 724 725 726 727 728 729 730
	int ret = 0;
	IWL_DEBUG_INFO(trans, "Init card's basic functions\n");

	/*
	 * Use "set_bit" below rather than "write", to preserve any hardware
	 * bits already set by default after reset.
	 */

	/* Disable L0S exit timer (platform NMI Work/Around) */
	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
731
		    CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
732 733 734 735 736 737

	/*
	 * Disable L0s without affecting L1;
	 *  don't wait for ICH L0s (ICH bug W/A)
	 */
	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
738
		    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
739 740 741 742 743 744 745 746 747

	/* Set FH wait threshold to maximum (HW error during stress W/A) */
	iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);

	/*
	 * Enable HAP INTA (interrupt from management bus) to
	 * wake device's PCI Express link L1a -> L0s
	 */
	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
748
		    CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
749

E
Emmanuel Grumbach 已提交
750
	iwl_apm_config(trans);
751 752

	/* Configure analog phase-lock-loop before activating to D0A */
753
	if (trans->cfg->base_params->pll_cfg_val)
754
		iwl_set_bit(trans, CSR_ANA_PLL_CFG,
755
			    trans->cfg->base_params->pll_cfg_val);
756 757 758 759 760 761 762 763 764 765 766 767 768

	/*
	 * Set "initialization complete" bit to move adapter from
	 * D0U* --> D0A* (powered-up active) state.
	 */
	iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

	/*
	 * Wait for clock stabilization; once stabilized, access to
	 * device-internal resources is supported, e.g. iwl_write_prph()
	 * and accesses to uCode SRAM.
	 */
	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
769 770
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789
	if (ret < 0) {
		IWL_DEBUG_INFO(trans, "Failed to init the card\n");
		goto out;
	}

	/*
	 * Enable DMA clock and wait for it to stabilize.
	 *
	 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
	 * do not disable clocks.  This preserves any hardware bits already
	 * set by default in "CLK_CTRL_REG" after reset.
	 */
	iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
	udelay(20);

	/* Disable L1-Active */
	iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
			  APMG_PCIDEV_STT_VAL_L1_ACT_DIS);

D
Don Fry 已提交
790
	set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
791 792 793 794 795

out:
	return ret;
}

796 797 798 799 800 801 802 803
static int iwl_apm_stop_master(struct iwl_trans *trans)
{
	int ret = 0;

	/* stop device's busmaster DMA activity */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);

	ret = iwl_poll_bit(trans, CSR_RESET,
804 805
			   CSR_RESET_REG_FLAG_MASTER_DISABLED,
			   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
806 807 808 809 810 811 812 813 814 815
	if (ret)
		IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");

	IWL_DEBUG_INFO(trans, "stop master\n");

	return ret;
}

static void iwl_apm_stop(struct iwl_trans *trans)
{
D
Don Fry 已提交
816
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
817 818
	IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");

D
Don Fry 已提交
819
	clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836

	/* Stop device's DMA activity */
	iwl_apm_stop_master(trans);

	/* Reset the entire device */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);

	udelay(10);

	/*
	 * Clear "initialization complete" bit to move adapter from
	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
	 */
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
}

837
static int iwl_nic_init(struct iwl_trans *trans)
838
{
J
Johannes Berg 已提交
839
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
840 841 842
	unsigned long flags;

	/* nic_init */
J
Johannes Berg 已提交
843
	spin_lock_irqsave(&trans_pcie->irq_lock, flags);
844
	iwl_apm_init(trans);
845 846

	/* Set interrupt coalescing calibration timer to default (512 usecs) */
847
	iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
848

J
Johannes Berg 已提交
849
	spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
850

851
	iwl_set_pwr_vmain(trans);
852

J
Johannes Berg 已提交
853
	iwl_op_mode_nic_config(trans->op_mode);
854 855

	/* Allocate the RX queue, or reset if it is already allocated */
856
	iwl_rx_init(trans);
857 858

	/* Allocate or reset and init all Tx and Command queues */
859
	if (iwl_tx_init(trans))
860 861
		return -ENOMEM;

862
	if (trans->cfg->base_params->shadow_reg_enable) {
863
		/* enable shadow regs in HW */
864
		iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
865
		IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
866 867 868 869 870 871 872 873
	}

	return 0;
}

#define HW_READY_TIMEOUT (50)

/* Note: returns poll_bit return value, which is >= 0 if success */
874
static int iwl_set_hw_ready(struct iwl_trans *trans)
875 876 877
{
	int ret;

878
	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
879
		    CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
880 881

	/* See if we got it */
882
	ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
883 884 885
			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
			   HW_READY_TIMEOUT);
886

887
	IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
888 889 890 891
	return ret;
}

/* Note: returns standard 0/-ERROR code */
892
static int iwl_prepare_card_hw(struct iwl_trans *trans)
893 894
{
	int ret;
895
	int t = 0;
896

897
	IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
898

899
	ret = iwl_set_hw_ready(trans);
900
	/* If the card is ready, exit 0 */
901 902 903 904
	if (ret >= 0)
		return 0;

	/* If HW is not ready, prepare the conditions to check again */
905
	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
906
		    CSR_HW_IF_CONFIG_REG_PREPARE);
907

908 909 910 911
	do {
		ret = iwl_set_hw_ready(trans);
		if (ret >= 0)
			return 0;
912

913 914 915
		usleep_range(200, 1000);
		t += 200;
	} while (t < 150000);
916 917 918 919

	return ret;
}

920 921 922
/*
 * ucode
 */
J
Johannes Berg 已提交
923 924
static int iwl_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
				   dma_addr_t phy_addr, u32 byte_cnt)
925
{
926
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
927 928
	int ret;

929
	trans_pcie->ucode_write_complete = false;
930 931

	iwl_write_direct32(trans,
932 933
			   FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
			   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
934 935

	iwl_write_direct32(trans,
936 937
			   FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
			   dst_addr);
938 939

	iwl_write_direct32(trans,
J
Johannes Berg 已提交
940 941
			   FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
			   phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
942 943

	iwl_write_direct32(trans,
944 945 946
			   FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
			   (iwl_get_dma_hi_addr(phy_addr)
				<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
947 948

	iwl_write_direct32(trans,
949 950 951 952
			   FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
			   1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
			   1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
			   FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
953 954

	iwl_write_direct32(trans,
955 956 957 958
			   FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
			   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE	|
			   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE	|
			   FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
959

960 961
	ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
				 trans_pcie->ucode_write_complete, 5 * HZ);
962
	if (!ret) {
J
Johannes Berg 已提交
963
		IWL_ERR(trans, "Failed to load firmware chunk!\n");
964 965 966 967 968 969
		return -ETIMEDOUT;
	}

	return 0;
}

J
Johannes Berg 已提交
970 971
static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
			    const struct fw_desc *section)
972
{
J
Johannes Berg 已提交
973 974 975
	u8 *v_addr;
	dma_addr_t p_addr;
	u32 offset;
976 977
	int ret = 0;

J
Johannes Berg 已提交
978 979 980 981 982 983 984 985 986 987 988
	IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
		     section_num);

	v_addr = dma_alloc_coherent(trans->dev, PAGE_SIZE, &p_addr, GFP_KERNEL);
	if (!v_addr)
		return -ENOMEM;

	for (offset = 0; offset < section->len; offset += PAGE_SIZE) {
		u32 copy_size;

		copy_size = min_t(u32, PAGE_SIZE, section->len - offset);
989

J
Johannes Berg 已提交
990 991 992 993 994 995 996 997
		memcpy(v_addr, (u8 *)section->data + offset, copy_size);
		ret = iwl_load_firmware_chunk(trans, section->offset + offset,
					      p_addr, copy_size);
		if (ret) {
			IWL_ERR(trans,
				"Could not load the [%d] uCode section\n",
				section_num);
			break;
D
David Spinadel 已提交
998
		}
J
Johannes Berg 已提交
999 1000 1001 1002 1003 1004
	}

	dma_free_coherent(trans->dev, PAGE_SIZE, v_addr, p_addr);
	return ret;
}

1005 1006
static int iwl_load_given_ucode(struct iwl_trans *trans,
				const struct fw_img *image)
1007
{
1008
	int i, ret = 0;
1009

1010
	for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
J
Johannes Berg 已提交
1011
		if (!image->sec[i].data)
1012
			break;
1013

1014 1015 1016 1017
		ret = iwl_load_section(trans, i, &image->sec[i]);
		if (ret)
			return ret;
	}
1018 1019 1020 1021 1022 1023 1024

	/* Remove all resets to allow NIC to operate */
	iwl_write32(trans, CSR_RESET, 0);

	return 0;
}

1025 1026
static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
				   const struct fw_img *fw)
1027
{
1028
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1029
	int ret;
1030
	bool hw_rfkill;
1031

1032 1033
	/* This may fail if AMT took ownership of the device */
	if (iwl_prepare_card_hw(trans)) {
1034
		IWL_WARN(trans, "Exit HW not ready\n");
1035 1036 1037
		return -EIO;
	}

1038 1039
	clear_bit(STATUS_FW_ERROR, &trans_pcie->status);

1040 1041
	iwl_enable_rfkill_int(trans);

1042
	/* If platform's RF_KILL switch is NOT set to KILL */
1043
	hw_rfkill = iwl_is_rfkill_set(trans);
1044
	iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1045
	if (hw_rfkill)
1046 1047
		return -ERFKILL;

1048
	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1049

1050
	ret = iwl_nic_init(trans);
1051
	if (ret) {
1052
		IWL_ERR(trans, "Unable to init nic\n");
1053 1054 1055 1056
		return ret;
	}

	/* make sure rfkill handshake bits are cleared */
1057 1058
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1059 1060 1061
		    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);

	/* clear (again), then enable host interrupts */
1062
	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1063
	iwl_enable_interrupts(trans);
1064 1065

	/* really make sure rfkill handshake bits are cleared */
1066 1067
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1068

1069
	/* Load the given image to the HW */
1070
	return iwl_load_given_ucode(trans, fw);
1071 1072
}

1073 1074 1075
/*
 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
 */
1076
static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1077
{
J
Johannes Berg 已提交
1078 1079 1080
	struct iwl_trans_pcie __maybe_unused *trans_pcie =
		IWL_TRANS_GET_PCIE_TRANS(trans);

1081
	iwl_write_prph(trans, SCD_TXFACT, mask);
1082 1083
}

1084
static void iwl_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
1085
{
1086
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1087
	u32 a;
1088
	int chan;
1089 1090
	u32 reg_val;

1091 1092 1093 1094
	/* make sure all queue are not stopped/used */
	memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
	memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));

1095
	trans_pcie->scd_base_addr =
1096
		iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1097 1098 1099 1100

	WARN_ON(scd_base_addr != 0 &&
		scd_base_addr != trans_pcie->scd_base_addr);

1101
	a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1102
	/* reset conext data memory */
1103
	for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1104
		a += 4)
1105
		iwl_write_targ_mem(trans, a, 0);
1106
	/* reset tx status memory */
1107
	for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1108
		a += 4)
1109
		iwl_write_targ_mem(trans, a, 0);
1110
	for (; a < trans_pcie->scd_base_addr +
1111
	       SCD_TRANS_TBL_OFFSET_QUEUE(
1112
				trans->cfg->base_params->num_of_queues);
1113
	       a += 4)
1114
		iwl_write_targ_mem(trans, a, 0);
1115

1116
	iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1117
		       trans_pcie->scd_bc_tbls.dma >> 10);
1118

1119 1120 1121 1122 1123
	/* The chain extension of the SCD doesn't work well. This feature is
	 * enabled by default by the HW, so we need to disable it manually.
	 */
	iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);

1124 1125
	iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
				trans_pcie->cmd_fifo);
1126

1127 1128 1129
	/* Activate all Tx DMA/FIFO channels */
	iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));

1130 1131
	/* Enable DMA channel */
	for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1132
		iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1133 1134
				   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
				   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1135 1136

	/* Update FH chicken bits */
1137 1138
	reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
	iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1139 1140 1141
			   reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);

	/* Enable L1-Active */
1142
	iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1143
			    APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1144 1145
}

1146
static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1147
{
1148
	iwl_pcie_reset_ict(trans);
1149
	iwl_tx_start(trans, scd_addr);
1150 1151
}

1152
/*
1153 1154
 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
 */
1155
static int iwl_trans_tx_stop(struct iwl_trans *trans)
1156
{
1157
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1158
	int ch, txq_id, ret;
1159 1160 1161
	unsigned long flags;

	/* Turn off all Tx DMA fifos */
J
Johannes Berg 已提交
1162
	spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1163

1164
	iwl_trans_txq_set_sched(trans, 0);
1165 1166

	/* Stop each Tx DMA channel, and wait for it to be idle */
1167
	for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1168
		iwl_write_direct32(trans,
1169
				   FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1170
		ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1171
			FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
1172
		if (ret < 0)
1173
			IWL_ERR(trans,
1174
				"Failing on timeout while stopping DMA channel %d [0x%08x]\n",
1175 1176 1177
				ch,
				iwl_read_direct32(trans,
						  FH_TSSR_TX_STATUS_REG));
1178
	}
J
Johannes Berg 已提交
1179
	spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1180

1181
	if (!trans_pcie->txq) {
1182 1183
		IWL_WARN(trans,
			 "Stopping tx queues that aren't allocated...\n");
1184 1185 1186 1187
		return 0;
	}

	/* Unmap DMA from host system and free skb's */
1188
	for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1189
	     txq_id++)
1190
		iwl_pcie_txq_unmap(trans, txq_id);
1191 1192 1193 1194

	return 0;
}

1195
static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1196
{
1197
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1198
	unsigned long flags;
1199

1200
	/* tell the device to stop sending interrupts */
J
Johannes Berg 已提交
1201
	spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1202
	iwl_disable_interrupts(trans);
J
Johannes Berg 已提交
1203
	spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1204

1205
	/* device going down, Stop using ICT table */
1206
	iwl_pcie_disable_ict(trans);
1207 1208 1209 1210 1211 1212 1213 1214

	/*
	 * If a HW restart happens during firmware loading,
	 * then the firmware loading might call this function
	 * and later it might be called again due to the
	 * restart. So don't process again if the device is
	 * already dead.
	 */
D
Don Fry 已提交
1215
	if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
1216 1217
		iwl_trans_tx_stop(trans);
		iwl_trans_rx_stop(trans);
1218

1219
		/* Power-down device's busmaster DMA clocks */
1220
		iwl_write_prph(trans, APMG_CLK_DIS_REG,
1221 1222 1223 1224 1225
			       APMG_CLK_VAL_DMA_CLK_RQT);
		udelay(5);
	}

	/* Make sure (redundant) we've released our request to stay awake */
1226
	iwl_clear_bit(trans, CSR_GP_CNTRL,
1227
		      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1228 1229

	/* Stop the device, and put it in low power state */
1230
	iwl_apm_stop(trans);
1231 1232 1233 1234

	/* Upon stop, the APM issues an interrupt if HW RF kill is set.
	 * Clean again the interrupt here
	 */
J
Johannes Berg 已提交
1235
	spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1236
	iwl_disable_interrupts(trans);
J
Johannes Berg 已提交
1237
	spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1238

1239 1240
	iwl_enable_rfkill_int(trans);

1241
	/* wait to make sure we flush pending tasklet*/
J
Johannes Berg 已提交
1242
	synchronize_irq(trans_pcie->irq);
1243 1244
	tasklet_kill(&trans_pcie->irq_tasklet);

J
Johannes Berg 已提交
1245 1246
	cancel_work_sync(&trans_pcie->rx_replenish);

1247
	/* stop and reset the on-board processor */
1248
	iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
D
Don Fry 已提交
1249 1250 1251 1252 1253

	/* clear all status bits */
	clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
	clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
	clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
1254
	clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1255
	clear_bit(STATUS_RFKILL, &trans_pcie->status);
1256 1257
}

1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268
static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
{
	/* let the ucode operate on its own */
	iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
		    CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);

	iwl_disable_interrupts(trans);
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
}

1269
static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1270
			     struct iwl_device_cmd *dev_cmd, int txq_id)
1271
{
1272 1273
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1274
	struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1275
	struct iwl_cmd_meta *out_meta;
1276
	struct iwl_txq *txq;
1277
	struct iwl_queue *q;
1278 1279 1280 1281 1282
	dma_addr_t phys_addr = 0;
	dma_addr_t txcmd_phys;
	dma_addr_t scratch_phys;
	u16 len, firstlen, secondlen;
	u8 wait_write_ptr = 0;
1283
	__le16 fc = hdr->frame_control;
1284
	u8 hdr_len = ieee80211_hdrlen(fc);
1285
	u16 __maybe_unused wifi_seq;
1286

1287
	txq = &trans_pcie->txq[txq_id];
1288 1289
	q = &txq->q;

1290 1291 1292 1293
	if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) {
		WARN_ON_ONCE(1);
		return -EINVAL;
	}
1294

1295
	spin_lock(&txq->lock);
1296

1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309
	/* In AGG mode, the index in the ring must correspond to the WiFi
	 * sequence number. This is a HW requirements to help the SCD to parse
	 * the BA.
	 * Check here that the packets are in the right place on the ring.
	 */
#ifdef CONFIG_IWLWIFI_DEBUG
	wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
	WARN_ONCE((iwl_read_prph(trans, SCD_AGGR_SEL) & BIT(txq_id)) &&
		  ((wifi_seq & 0xff) != q->write_ptr),
		  "Q: %d WiFi Seq %d tfdNum %d",
		  txq_id, wifi_seq, q->write_ptr);
#endif

1310
	/* Set up driver data for this TFD */
1311 1312
	txq->entries[q->write_ptr].skb = skb;
	txq->entries[q->write_ptr].cmd = dev_cmd;
1313 1314

	dev_cmd->hdr.cmd = REPLY_TX;
1315 1316 1317
	dev_cmd->hdr.sequence =
		cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
			    INDEX_TO_SEQ(q->write_ptr)));
1318 1319

	/* Set up first empty entry in queue's array of Tx/cmd buffers */
1320
	out_meta = &txq->entries[q->write_ptr].meta;
1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340

	/*
	 * Use the first empty entry in this queue's command buffer array
	 * to contain the Tx command and MAC header concatenated together
	 * (payload data will be in another buffer).
	 * Size of this varies, due to varying MAC header length.
	 * If end is not dword aligned, we'll have 2 extra bytes at the end
	 * of the MAC header (device reads on dword boundaries).
	 * We'll tell device about this padding later.
	 */
	len = sizeof(struct iwl_tx_cmd) +
		sizeof(struct iwl_cmd_header) + hdr_len;
	firstlen = (len + 3) & ~3;

	/* Tell NIC about any 2-byte padding after MAC header */
	if (firstlen != len)
		tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;

	/* Physical address of this Tx command's header (not MAC header!),
	 * within command buffer array. */
1341
	txcmd_phys = dma_map_single(trans->dev,
1342 1343
				    &dev_cmd->hdr, firstlen,
				    DMA_BIDIRECTIONAL);
1344
	if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1345
		goto out_err;
1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359
	dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
	dma_unmap_len_set(out_meta, len, firstlen);

	if (!ieee80211_has_morefrags(fc)) {
		txq->need_update = 1;
	} else {
		wait_write_ptr = 1;
		txq->need_update = 0;
	}

	/* Set up TFD's 2nd entry to point directly to remainder of skb,
	 * if any (802.11 null frames have no payload). */
	secondlen = skb->len - hdr_len;
	if (secondlen > 0) {
1360
		phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1361
					   secondlen, DMA_TO_DEVICE);
1362 1363
		if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
			dma_unmap_single(trans->dev,
1364 1365 1366
					 dma_unmap_addr(out_meta, mapping),
					 dma_unmap_len(out_meta, len),
					 DMA_BIDIRECTIONAL);
1367
			goto out_err;
1368 1369 1370 1371
		}
	}

	/* Attach buffers to TFD */
1372
	iwl_pcie_tx_build_tfd(trans, txq, txcmd_phys, firstlen, 1);
1373
	if (secondlen > 0)
1374
		iwl_pcie_tx_build_tfd(trans, txq, phys_addr, secondlen, 0);
1375 1376 1377 1378 1379

	scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
				offsetof(struct iwl_tx_cmd, scratch);

	/* take back ownership of DMA buffer to enable update */
1380
	dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1381
				DMA_BIDIRECTIONAL);
1382 1383 1384
	tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
	tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);

1385
	IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1386
		     le16_to_cpu(dev_cmd->hdr.sequence));
1387
	IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1388 1389

	/* Set up entry for this TFD in Tx byte-count array */
1390
	iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1391

1392
	dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1393
				   DMA_BIDIRECTIONAL);
1394

1395
	trace_iwlwifi_dev_tx(trans->dev, skb,
1396
			     &txq->tfds[txq->q.write_ptr],
1397 1398 1399
			     sizeof(struct iwl_tfd),
			     &dev_cmd->hdr, firstlen,
			     skb->data + hdr_len, secondlen);
1400 1401
	trace_iwlwifi_dev_tx_data(trans->dev, skb,
				  skb->data + hdr_len, secondlen);
1402

1403
	/* start timer if queue currently empty */
1404 1405
	if (txq->need_update && q->read_ptr == q->write_ptr &&
	    trans_pcie->wd_timeout)
1406 1407
		mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);

1408 1409
	/* Tell device the write index *just past* this latest filled TFD */
	q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1410
	iwl_pcie_txq_inc_wr_ptr(trans, txq);
1411

1412 1413 1414 1415 1416 1417
	/*
	 * At this point the frame is "transmitted" successfully
	 * and we will get a TX status notification eventually,
	 * regardless of the value of ret. "ret" only indicates
	 * whether or not we should update the write pointer.
	 */
1418
	if (iwl_queue_space(q) < q->high_mark) {
1419 1420
		if (wait_write_ptr) {
			txq->need_update = 1;
1421
			iwl_pcie_txq_inc_wr_ptr(trans, txq);
1422
		} else {
1423
			iwl_stop_queue(trans, txq);
1424 1425
		}
	}
1426
	spin_unlock(&txq->lock);
1427
	return 0;
1428 1429 1430
 out_err:
	spin_unlock(&txq->lock);
	return -1;
1431 1432
}

1433
static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1434
{
1435
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1436
	int err;
1437
	bool hw_rfkill;
1438

1439 1440
	trans_pcie->inta_mask = CSR_INI_SET_MASK;

1441 1442
	if (!trans_pcie->irq_requested) {
		tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1443
			iwl_pcie_tasklet, (unsigned long)trans);
1444

1445
		iwl_pcie_alloc_ict(trans);
1446

1447 1448
		err = request_irq(trans_pcie->irq, iwl_pcie_isr_ict,
				  IRQF_SHARED, DRV_NAME, trans);
1449 1450
		if (err) {
			IWL_ERR(trans, "Error allocating IRQ %d\n",
J
Johannes Berg 已提交
1451
				trans_pcie->irq);
1452
			goto error;
1453 1454 1455
		}

		trans_pcie->irq_requested = true;
1456 1457
	}

1458 1459
	err = iwl_prepare_card_hw(trans);
	if (err) {
1460
		IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1461
		goto err_free_irq;
1462
	}
1463 1464 1465

	iwl_apm_init(trans);

1466 1467 1468
	/* From now on, the op_mode will be kept updated about RF kill state */
	iwl_enable_rfkill_int(trans);

1469
	hw_rfkill = iwl_is_rfkill_set(trans);
1470
	iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1471

1472 1473
	return err;

1474
err_free_irq:
1475
	trans_pcie->irq_requested = false;
J
Johannes Berg 已提交
1476
	free_irq(trans_pcie->irq, trans);
1477
error:
1478
	iwl_pcie_free_ict(trans);
1479 1480
	tasklet_kill(&trans_pcie->irq_tasklet);
	return err;
1481 1482
}

1483 1484
static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
				   bool op_mode_leaving)
1485
{
1486
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1487
	bool hw_rfkill;
1488
	unsigned long flags;
1489

1490 1491 1492 1493
	spin_lock_irqsave(&trans_pcie->irq_lock, flags);
	iwl_disable_interrupts(trans);
	spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);

1494 1495
	iwl_apm_stop(trans);

1496 1497 1498
	spin_lock_irqsave(&trans_pcie->irq_lock, flags);
	iwl_disable_interrupts(trans);
	spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1499

1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515
	if (!op_mode_leaving) {
		/*
		 * Even if we stop the HW, we still want the RF kill
		 * interrupt
		 */
		iwl_enable_rfkill_int(trans);

		/*
		 * Check again since the RF kill state may have changed while
		 * all the interrupts were disabled, in this case we couldn't
		 * receive the RF kill interrupt and update the state in the
		 * op_mode.
		 */
		hw_rfkill = iwl_is_rfkill_set(trans);
		iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
	}
1516 1517
}

1518 1519
static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
				   struct sk_buff_head *skbs)
1520
{
1521
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1522
	struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1523 1524 1525
	/* n_bd is usually 256 => n_bd - 1 = 0xff */
	int tfd_num = ssn & (txq->q.n_bd - 1);

1526 1527
	spin_lock(&txq->lock);

1528
	if (txq->q.read_ptr != tfd_num) {
1529 1530
		IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
				   txq_id, txq->q.read_ptr, tfd_num, ssn);
1531
		iwl_pcie_txq_reclaim(trans, txq_id, tfd_num, skbs);
1532
		if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1533
			iwl_wake_queue(trans, txq);
1534
	}
1535 1536

	spin_unlock(&txq->lock);
1537 1538
}

1539 1540
static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
{
1541
	writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1542 1543 1544 1545
}

static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
{
1546
	writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1547 1548 1549 1550
}

static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
{
1551
	return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1552 1553
}

1554
static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1555
				     const struct iwl_trans_config *trans_cfg)
1556 1557 1558 1559
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1560
	trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1561 1562 1563 1564 1565 1566 1567
	if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
		trans_pcie->n_no_reclaim_cmds = 0;
	else
		trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
	if (trans_pcie->n_no_reclaim_cmds)
		memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
		       trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1568

1569 1570 1571 1572 1573
	trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
	if (trans_pcie->rx_buf_size_8k)
		trans_pcie->rx_page_order = get_order(8 * 1024);
	else
		trans_pcie->rx_page_order = get_order(4 * 1024);
1574 1575 1576

	trans_pcie->wd_timeout =
		msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
J
Johannes Berg 已提交
1577 1578

	trans_pcie->command_names = trans_cfg->command_names;
1579 1580
}

1581
void iwl_trans_pcie_free(struct iwl_trans *trans)
1582
{
1583
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1584

1585 1586
	iwl_trans_pcie_tx_free(trans);
	iwl_trans_pcie_rx_free(trans);
1587

1588
	if (trans_pcie->irq_requested == true) {
J
Johannes Berg 已提交
1589
		free_irq(trans_pcie->irq, trans);
1590
		iwl_pcie_free_ict(trans);
1591
	}
1592 1593

	pci_disable_msi(trans_pcie->pci_dev);
1594
	iounmap(trans_pcie->hw_base);
1595 1596
	pci_release_regions(trans_pcie->pci_dev);
	pci_disable_device(trans_pcie->pci_dev);
1597
	kmem_cache_destroy(trans->dev_cmd_pool);
1598

1599
	kfree(trans);
1600 1601
}

D
Don Fry 已提交
1602 1603 1604 1605 1606
static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	if (state)
1607
		set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
D
Don Fry 已提交
1608
	else
1609
		clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
D
Don Fry 已提交
1610 1611
}

J
Johannes Berg 已提交
1612
#ifdef CONFIG_PM_SLEEP
1613 1614 1615 1616 1617 1618 1619
static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
{
	return 0;
}

static int iwl_trans_pcie_resume(struct iwl_trans *trans)
{
1620
	bool hw_rfkill;
1621

1622 1623
	iwl_enable_rfkill_int(trans);

1624
	hw_rfkill = iwl_is_rfkill_set(trans);
1625
	iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1626

1627
	if (!hw_rfkill)
1628 1629
		iwl_enable_interrupts(trans);

1630 1631
	return 0;
}
J
Johannes Berg 已提交
1632
#endif /* CONFIG_PM_SLEEP */
1633

1634 1635
#define IWL_FLUSH_WAIT_MS	2000

1636
static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
1637
{
1638
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1639
	struct iwl_txq *txq;
1640 1641 1642 1643 1644 1645
	struct iwl_queue *q;
	int cnt;
	unsigned long now = jiffies;
	int ret = 0;

	/* waiting for all the tx frames complete might take a while */
1646
	for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
W
Wey-Yi Guy 已提交
1647
		if (cnt == trans_pcie->cmd_queue)
1648
			continue;
1649
		txq = &trans_pcie->txq[cnt];
1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663
		q = &txq->q;
		while (q->read_ptr != q->write_ptr && !time_after(jiffies,
		       now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
			msleep(1);

		if (q->read_ptr != q->write_ptr) {
			IWL_ERR(trans, "fail to flush all tx fifo queues\n");
			ret = -ETIMEDOUT;
			break;
		}
	}
	return ret;
}

1664 1665
static const char *get_fh_string(int cmd)
{
J
Johannes Berg 已提交
1666
#define IWL_CMD(x) case x: return #x
1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679
	switch (cmd) {
	IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
	IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
	IWL_CMD(FH_RSCSR_CHNL0_WPTR);
	IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
	IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
	IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
	IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
	IWL_CMD(FH_TSSR_TX_STATUS_REG);
	IWL_CMD(FH_TSSR_TX_ERROR_REG);
	default:
		return "UNKNOWN";
	}
J
Johannes Berg 已提交
1680
#undef IWL_CMD
1681 1682
}

1683
int iwl_pcie_dump_fh(struct iwl_trans *trans, char **buf)
1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696
{
	int i;
	static const u32 fh_tbl[] = {
		FH_RSCSR_CHNL0_STTS_WPTR_REG,
		FH_RSCSR_CHNL0_RBDCB_BASE_REG,
		FH_RSCSR_CHNL0_WPTR,
		FH_MEM_RCSR_CHNL0_CONFIG_REG,
		FH_MEM_RSSR_SHARED_CTRL_REG,
		FH_MEM_RSSR_RX_STATUS_REG,
		FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
		FH_TSSR_TX_STATUS_REG,
		FH_TSSR_TX_ERROR_REG
	};
1697 1698 1699 1700 1701 1702

#ifdef CONFIG_IWLWIFI_DEBUGFS
	if (buf) {
		int pos = 0;
		size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;

1703 1704 1705
		*buf = kmalloc(bufsz, GFP_KERNEL);
		if (!*buf)
			return -ENOMEM;
1706

1707 1708
		pos += scnprintf(*buf + pos, bufsz - pos,
				"FH register values:\n");
1709 1710

		for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
1711 1712 1713
			pos += scnprintf(*buf + pos, bufsz - pos,
				"  %34s: 0X%08x\n",
				get_fh_string(fh_tbl[i]),
1714
				iwl_read_direct32(trans, fh_tbl[i]));
1715

1716 1717 1718
		return pos;
	}
#endif
1719

1720
	IWL_ERR(trans, "FH register values:\n");
1721
	for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++)
1722 1723
		IWL_ERR(trans, "  %34s: 0X%08x\n",
			get_fh_string(fh_tbl[i]),
1724
			iwl_read_direct32(trans, fh_tbl[i]));
1725

1726 1727 1728 1729 1730
	return 0;
}

static const char *get_csr_string(int cmd)
{
J
Johannes Berg 已提交
1731
#define IWL_CMD(x) case x: return #x
1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758
	switch (cmd) {
	IWL_CMD(CSR_HW_IF_CONFIG_REG);
	IWL_CMD(CSR_INT_COALESCING);
	IWL_CMD(CSR_INT);
	IWL_CMD(CSR_INT_MASK);
	IWL_CMD(CSR_FH_INT_STATUS);
	IWL_CMD(CSR_GPIO_IN);
	IWL_CMD(CSR_RESET);
	IWL_CMD(CSR_GP_CNTRL);
	IWL_CMD(CSR_HW_REV);
	IWL_CMD(CSR_EEPROM_REG);
	IWL_CMD(CSR_EEPROM_GP);
	IWL_CMD(CSR_OTP_GP_REG);
	IWL_CMD(CSR_GIO_REG);
	IWL_CMD(CSR_GP_UCODE_REG);
	IWL_CMD(CSR_GP_DRIVER_REG);
	IWL_CMD(CSR_UCODE_DRV_GP1);
	IWL_CMD(CSR_UCODE_DRV_GP2);
	IWL_CMD(CSR_LED_REG);
	IWL_CMD(CSR_DRAM_INT_TBL_REG);
	IWL_CMD(CSR_GIO_CHICKEN_BITS);
	IWL_CMD(CSR_ANA_PLL_CFG);
	IWL_CMD(CSR_HW_REV_WA_REG);
	IWL_CMD(CSR_DBG_HPET_MEM_REG);
	default:
		return "UNKNOWN";
	}
J
Johannes Berg 已提交
1759
#undef IWL_CMD
1760 1761
}

1762
void iwl_pcie_dump_csr(struct iwl_trans *trans)
1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795
{
	int i;
	static const u32 csr_tbl[] = {
		CSR_HW_IF_CONFIG_REG,
		CSR_INT_COALESCING,
		CSR_INT,
		CSR_INT_MASK,
		CSR_FH_INT_STATUS,
		CSR_GPIO_IN,
		CSR_RESET,
		CSR_GP_CNTRL,
		CSR_HW_REV,
		CSR_EEPROM_REG,
		CSR_EEPROM_GP,
		CSR_OTP_GP_REG,
		CSR_GIO_REG,
		CSR_GP_UCODE_REG,
		CSR_GP_DRIVER_REG,
		CSR_UCODE_DRV_GP1,
		CSR_UCODE_DRV_GP2,
		CSR_LED_REG,
		CSR_DRAM_INT_TBL_REG,
		CSR_GIO_CHICKEN_BITS,
		CSR_ANA_PLL_CFG,
		CSR_HW_REV_WA_REG,
		CSR_DBG_HPET_MEM_REG
	};
	IWL_ERR(trans, "CSR values:\n");
	IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
		"CSR_INT_PERIODIC_REG)\n");
	for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
		IWL_ERR(trans, "  %25s: 0X%08x\n",
			get_csr_string(csr_tbl[i]),
1796
			iwl_read32(trans, csr_tbl[i]));
1797 1798 1799
	}
}

1800 1801 1802
#ifdef CONFIG_IWLWIFI_DEBUGFS
/* create and remove of files */
#define DEBUGFS_ADD_FILE(name, parent, mode) do {			\
1803
	if (!debugfs_create_file(#name, mode, parent, trans,		\
1804
				 &iwl_dbgfs_##name##_ops))		\
1805
		goto err;						\
1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823
} while (0)

/* file operation */
#define DEBUGFS_READ_FUNC(name)                                         \
static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
					char __user *user_buf,          \
					size_t count, loff_t *ppos);

#define DEBUGFS_WRITE_FUNC(name)                                        \
static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
					const char __user *user_buf,    \
					size_t count, loff_t *ppos);


#define DEBUGFS_READ_FILE_OPS(name)					\
	DEBUGFS_READ_FUNC(name);					\
static const struct file_operations iwl_dbgfs_##name##_ops = {		\
	.read = iwl_dbgfs_##name##_read,				\
1824
	.open = simple_open,						\
1825 1826 1827
	.llseek = generic_file_llseek,					\
};

1828 1829 1830 1831
#define DEBUGFS_WRITE_FILE_OPS(name)                                    \
	DEBUGFS_WRITE_FUNC(name);                                       \
static const struct file_operations iwl_dbgfs_##name##_ops = {          \
	.write = iwl_dbgfs_##name##_write,                              \
1832
	.open = simple_open,						\
1833 1834 1835
	.llseek = generic_file_llseek,					\
};

1836 1837 1838 1839 1840 1841
#define DEBUGFS_READ_WRITE_FILE_OPS(name)				\
	DEBUGFS_READ_FUNC(name);					\
	DEBUGFS_WRITE_FUNC(name);					\
static const struct file_operations iwl_dbgfs_##name##_ops = {		\
	.write = iwl_dbgfs_##name##_write,				\
	.read = iwl_dbgfs_##name##_read,				\
1842
	.open = simple_open,						\
1843 1844 1845 1846
	.llseek = generic_file_llseek,					\
};

static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1847 1848
				       char __user *user_buf,
				       size_t count, loff_t *ppos)
1849
{
1850
	struct iwl_trans *trans = file->private_data;
1851
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1852
	struct iwl_txq *txq;
1853 1854 1855 1856 1857
	struct iwl_queue *q;
	char *buf;
	int pos = 0;
	int cnt;
	int ret;
1858 1859
	size_t bufsz;

1860
	bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1861

J
Johannes Berg 已提交
1862
	if (!trans_pcie->txq)
1863
		return -EAGAIN;
J
Johannes Berg 已提交
1864

1865 1866 1867 1868
	buf = kzalloc(bufsz, GFP_KERNEL);
	if (!buf)
		return -ENOMEM;

1869
	for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1870
		txq = &trans_pcie->txq[cnt];
1871 1872
		q = &txq->q;
		pos += scnprintf(buf + pos, bufsz - pos,
1873
				"hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1874
				cnt, q->read_ptr, q->write_ptr,
1875 1876
				!!test_bit(cnt, trans_pcie->queue_used),
				!!test_bit(cnt, trans_pcie->queue_stopped));
1877 1878 1879 1880 1881 1882 1883
	}
	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
	kfree(buf);
	return ret;
}

static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1884 1885 1886
				       char __user *user_buf,
				       size_t count, loff_t *ppos)
{
1887
	struct iwl_trans *trans = file->private_data;
1888
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1889
	struct iwl_rxq *rxq = &trans_pcie->rxq;
1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909
	char buf[256];
	int pos = 0;
	const size_t bufsz = sizeof(buf);

	pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
						rxq->read);
	pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
						rxq->write);
	pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
						rxq->free_count);
	if (rxq->rb_stts) {
		pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
			 le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
	} else {
		pos += scnprintf(buf + pos, bufsz - pos,
					"closed_rb_num: Not Allocated\n");
	}
	return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
}

1910 1911
static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
					char __user *user_buf,
1912 1913
					size_t count, loff_t *ppos)
{
1914
	struct iwl_trans *trans = file->private_data;
1915
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1916 1917 1918 1919 1920 1921 1922 1923
	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;

	int pos = 0;
	char *buf;
	int bufsz = 24 * 64; /* 24 items * 64 char per item */
	ssize_t ret;

	buf = kzalloc(bufsz, GFP_KERNEL);
J
Johannes Berg 已提交
1924
	if (!buf)
1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972
		return -ENOMEM;

	pos += scnprintf(buf + pos, bufsz - pos,
			"Interrupt Statistics Report:\n");

	pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
		isr_stats->hw);
	pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
		isr_stats->sw);
	if (isr_stats->sw || isr_stats->hw) {
		pos += scnprintf(buf + pos, bufsz - pos,
			"\tLast Restarting Code:  0x%X\n",
			isr_stats->err_code);
	}
#ifdef CONFIG_IWLWIFI_DEBUG
	pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
		isr_stats->sch);
	pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
		isr_stats->alive);
#endif
	pos += scnprintf(buf + pos, bufsz - pos,
		"HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);

	pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
		isr_stats->ctkill);

	pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
		isr_stats->wakeup);

	pos += scnprintf(buf + pos, bufsz - pos,
		"Rx command responses:\t\t %u\n", isr_stats->rx);

	pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
		isr_stats->tx);

	pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
		isr_stats->unhandled);

	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
	kfree(buf);
	return ret;
}

static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
					 const char __user *user_buf,
					 size_t count, loff_t *ppos)
{
	struct iwl_trans *trans = file->private_data;
1973
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991
	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;

	char buf[8];
	int buf_size;
	u32 reset_flag;

	memset(buf, 0, sizeof(buf));
	buf_size = min(count, sizeof(buf) -  1);
	if (copy_from_user(buf, user_buf, buf_size))
		return -EFAULT;
	if (sscanf(buf, "%x", &reset_flag) != 1)
		return -EFAULT;
	if (reset_flag == 0)
		memset(isr_stats, 0, sizeof(*isr_stats));

	return count;
}

1992
static ssize_t iwl_dbgfs_csr_write(struct file *file,
1993 1994
				   const char __user *user_buf,
				   size_t count, loff_t *ppos)
1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007
{
	struct iwl_trans *trans = file->private_data;
	char buf[8];
	int buf_size;
	int csr;

	memset(buf, 0, sizeof(buf));
	buf_size = min(count, sizeof(buf) -  1);
	if (copy_from_user(buf, user_buf, buf_size))
		return -EFAULT;
	if (sscanf(buf, "%d", &csr) != 1)
		return -EFAULT;

2008
	iwl_pcie_dump_csr(trans);
2009 2010 2011 2012 2013

	return count;
}

static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2014 2015
				     char __user *user_buf,
				     size_t count, loff_t *ppos)
2016 2017
{
	struct iwl_trans *trans = file->private_data;
2018
	char *buf = NULL;
2019 2020 2021
	int pos = 0;
	ssize_t ret = -EFAULT;

2022
	ret = pos = iwl_pcie_dump_fh(trans, &buf);
2023 2024 2025 2026 2027 2028 2029 2030 2031
	if (buf) {
		ret = simple_read_from_buffer(user_buf,
					      count, ppos, buf, pos);
		kfree(buf);
	}

	return ret;
}

2032 2033 2034 2035 2036 2037 2038 2039 2040
static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
					  const char __user *user_buf,
					  size_t count, loff_t *ppos)
{
	struct iwl_trans *trans = file->private_data;

	if (!trans->op_mode)
		return -EAGAIN;

2041
	local_bh_disable();
2042
	iwl_op_mode_nic_error(trans->op_mode);
2043
	local_bh_enable();
2044 2045 2046 2047

	return count;
}

2048
DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2049
DEBUGFS_READ_FILE_OPS(fh_reg);
2050 2051
DEBUGFS_READ_FILE_OPS(rx_queue);
DEBUGFS_READ_FILE_OPS(tx_queue);
2052
DEBUGFS_WRITE_FILE_OPS(csr);
2053
DEBUGFS_WRITE_FILE_OPS(fw_restart);
2054 2055 2056 2057 2058 2059

/*
 * Create the debugfs files and directories
 *
 */
static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2060
					 struct dentry *dir)
2061 2062 2063
{
	DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
	DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2064
	DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2065 2066
	DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
	DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2067
	DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
2068
	return 0;
2069 2070 2071 2072

err:
	IWL_ERR(trans, "failed to create the trans debugfs entry\n");
	return -ENOMEM;
2073 2074 2075
}
#else
static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2076 2077 2078 2079
					 struct dentry *dir)
{
	return 0;
}
2080 2081
#endif /*CONFIG_IWLWIFI_DEBUGFS */

2082
static const struct iwl_trans_ops trans_ops_pcie = {
2083
	.start_hw = iwl_trans_pcie_start_hw,
2084
	.stop_hw = iwl_trans_pcie_stop_hw,
2085
	.fw_alive = iwl_trans_pcie_fw_alive,
2086
	.start_fw = iwl_trans_pcie_start_fw,
2087
	.stop_device = iwl_trans_pcie_stop_device,
2088

2089 2090
	.wowlan_suspend = iwl_trans_pcie_wowlan_suspend,

2091
	.send_cmd = iwl_pcie_send_cmd,
2092

2093
	.tx = iwl_trans_pcie_tx,
2094
	.reclaim = iwl_trans_pcie_reclaim,
2095

2096 2097
	.txq_disable = iwl_pcie_txq_disable,
	.txq_enable = iwl_pcie_txq_enable,
2098

2099
	.dbgfs_register = iwl_trans_pcie_dbgfs_register,
2100

2101
	.wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2102

J
Johannes Berg 已提交
2103
#ifdef CONFIG_PM_SLEEP
2104 2105
	.suspend = iwl_trans_pcie_suspend,
	.resume = iwl_trans_pcie_resume,
J
Johannes Berg 已提交
2106
#endif
2107 2108 2109
	.write8 = iwl_trans_pcie_write8,
	.write32 = iwl_trans_pcie_write32,
	.read32 = iwl_trans_pcie_read32,
2110
	.configure = iwl_trans_pcie_configure,
D
Don Fry 已提交
2111
	.set_pmi = iwl_trans_pcie_set_pmi,
2112
};
2113

2114
struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2115 2116
				       const struct pci_device_id *ent,
				       const struct iwl_cfg *cfg)
2117 2118 2119 2120 2121 2122 2123
{
	struct iwl_trans_pcie *trans_pcie;
	struct iwl_trans *trans;
	u16 pci_cmd;
	int err;

	trans = kzalloc(sizeof(struct iwl_trans) +
2124
			sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2125

2126
	if (!trans)
2127 2128 2129 2130 2131
		return NULL;

	trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	trans->ops = &trans_ops_pcie;
2132
	trans->cfg = cfg;
2133
	trans_pcie->trans = trans;
J
Johannes Berg 已提交
2134
	spin_lock_init(&trans_pcie->irq_lock);
2135
	init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2136 2137 2138 2139

	/* W/A - seems to solve weird behavior. We need to remove this if we
	 * don't want to stay in L1 all the time. This wastes a lot of power */
	pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2140
			       PCIE_LINK_STATE_CLKPM);
2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155

	if (pci_enable_device(pdev)) {
		err = -ENODEV;
		goto out_no_pci;
	}

	pci_set_master(pdev);

	err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
	if (!err)
		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
	if (err) {
		err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
		if (!err)
			err = pci_set_consistent_dma_mask(pdev,
2156
							  DMA_BIT_MASK(32));
2157 2158 2159 2160 2161 2162 2163 2164 2165 2166
		/* both attempts failed: */
		if (err) {
			dev_printk(KERN_ERR, &pdev->dev,
				   "No suitable DMA available.\n");
			goto out_pci_disable_device;
		}
	}

	err = pci_request_regions(pdev, DRV_NAME);
	if (err) {
2167 2168
		dev_printk(KERN_ERR, &pdev->dev,
			   "pci_request_regions failed\n");
2169 2170 2171
		goto out_pci_disable_device;
	}

2172
	trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2173
	if (!trans_pcie->hw_base) {
2174
		dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed\n");
2175 2176 2177 2178 2179 2180 2181 2182 2183
		err = -ENODEV;
		goto out_pci_release_regions;
	}

	/* We disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state */
	pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);

	err = pci_enable_msi(pdev);
2184
	if (err) {
2185
		dev_printk(KERN_ERR, &pdev->dev,
2186
			   "pci_enable_msi failed(0X%x)\n", err);
2187 2188 2189 2190 2191 2192 2193
		/* enable rfkill interrupt: hw bug w/a */
		pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
		if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
			pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
			pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
		}
	}
2194 2195

	trans->dev = &pdev->dev;
J
Johannes Berg 已提交
2196
	trans_pcie->irq = pdev->irq;
2197
	trans_pcie->pci_dev = pdev;
2198
	trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
E
Emmanuel Grumbach 已提交
2199
	trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2200 2201
	snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
		 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2202

2203
	/* Initialize the wait queue for commands */
2204
	init_waitqueue_head(&trans_pcie->wait_command_queue);
2205
	spin_lock_init(&trans->reg_lock);
2206

2207 2208
	snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
		 "iwl_cmd_pool:%s", dev_name(trans->dev));
2209 2210 2211

	trans->dev_cmd_headroom = 0;
	trans->dev_cmd_pool =
2212
		kmem_cache_create(trans->dev_cmd_pool_name,
2213 2214 2215 2216 2217 2218 2219 2220 2221
				  sizeof(struct iwl_device_cmd)
				  + trans->dev_cmd_headroom,
				  sizeof(void *),
				  SLAB_HWCACHE_ALIGN,
				  NULL);

	if (!trans->dev_cmd_pool)
		goto out_pci_disable_msi;

2222 2223
	return trans;

2224 2225
out_pci_disable_msi:
	pci_disable_msi(pdev);
2226 2227 2228 2229 2230 2231 2232 2233
out_pci_release_regions:
	pci_release_regions(pdev);
out_pci_disable_device:
	pci_disable_device(pdev);
out_no_pci:
	kfree(trans);
	return NULL;
}