trans.c 44.8 KB
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/******************************************************************************
 *
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * GPL LICENSE SUMMARY
 *
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 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 * USA
 *
 * The full GNU General Public License is included in this distribution
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 * in the file called COPYING.
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 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 * BSD LICENSE
 *
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 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
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 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name Intel Corporation nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/
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#include <linux/pci.h>
#include <linux/pci-aspm.h>
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#include <linux/interrupt.h>
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#include <linux/debugfs.h>
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#include <linux/sched.h>
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#include <linux/bitops.h>
#include <linux/gfp.h>
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#include "iwl-drv.h"
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#include "iwl-trans.h"
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#include "iwl-csr.h"
#include "iwl-prph.h"
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#include "iwl-agn-hw.h"
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#include "internal.h"
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static void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
						  u32 reg, u32 mask, u32 value)
{
	u32 v;

#ifdef CONFIG_IWLWIFI_DEBUG
	WARN_ON_ONCE(value & ~mask);
#endif

	v = iwl_read32(trans, reg);
	v &= ~mask;
	v |= value;
	iwl_write32(trans, reg, v);
}

static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
					      u32 reg, u32 mask)
{
	__iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
}

static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
					    u32 reg, u32 mask)
{
	__iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
}

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static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
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{
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	if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
		iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
				       APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
				       ~APMG_PS_CTRL_MSK_PWR_SRC);
	else
		iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
				       APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
				       ~APMG_PS_CTRL_MSK_PWR_SRC);
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}

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/* PCI registers */
#define PCI_CFG_RETRY_TIMEOUT	0x041

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static void iwl_pcie_apm_config(struct iwl_trans *trans)
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{
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	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	u16 lctl;
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	/*
	 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
	 * Check if BIOS (or OS) enabled L1-ASPM on this device.
	 * If so (likely), disable L0S, so device moves directly L0->L1;
	 *    costs negligible amount of power savings.
	 * If not (unlikely), enable L0S, so there is at least some
	 *    power savings, even without L1.
	 */
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	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
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	if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
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		/* L1-ASPM enabled; disable(!) L0S */
		iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
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		dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
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	} else {
		/* L1-ASPM disabled; enable(!) L0S */
		iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
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		dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
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	}
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	trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
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}

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/*
 * Start up NIC's basic functionality after it has been reset
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 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
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 * NOTE:  This does not load uCode nor start the embedded processor
 */
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static int iwl_pcie_apm_init(struct iwl_trans *trans)
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{
	int ret = 0;
	IWL_DEBUG_INFO(trans, "Init card's basic functions\n");

	/*
	 * Use "set_bit" below rather than "write", to preserve any hardware
	 * bits already set by default after reset.
	 */

	/* Disable L0S exit timer (platform NMI Work/Around) */
	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
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		    CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
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	/*
	 * Disable L0s without affecting L1;
	 *  don't wait for ICH L0s (ICH bug W/A)
	 */
	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
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		    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
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	/* Set FH wait threshold to maximum (HW error during stress W/A) */
	iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);

	/*
	 * Enable HAP INTA (interrupt from management bus) to
	 * wake device's PCI Express link L1a -> L0s
	 */
	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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		    CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
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	iwl_pcie_apm_config(trans);
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	/* Configure analog phase-lock-loop before activating to D0A */
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	if (trans->cfg->base_params->pll_cfg_val)
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		iwl_set_bit(trans, CSR_ANA_PLL_CFG,
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			    trans->cfg->base_params->pll_cfg_val);
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	/*
	 * Set "initialization complete" bit to move adapter from
	 * D0U* --> D0A* (powered-up active) state.
	 */
	iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

	/*
	 * Wait for clock stabilization; once stabilized, access to
	 * device-internal resources is supported, e.g. iwl_write_prph()
	 * and accesses to uCode SRAM.
	 */
	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
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	if (ret < 0) {
		IWL_DEBUG_INFO(trans, "Failed to init the card\n");
		goto out;
	}

	/*
	 * Enable DMA clock and wait for it to stabilize.
	 *
	 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
	 * do not disable clocks.  This preserves any hardware bits already
	 * set by default in "CLK_CTRL_REG" after reset.
	 */
	iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
	udelay(20);

	/* Disable L1-Active */
	iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
			  APMG_PCIDEV_STT_VAL_L1_ACT_DIS);

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	/* Clear the interrupt in APMG if the NIC is in RFKILL */
	iwl_write_prph(trans, APMG_RTC_INT_STT_REG, APMG_RTC_INT_STT_RFKILL);

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	set_bit(STATUS_DEVICE_ENABLED, &trans->status);
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out:
	return ret;
}

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static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
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{
	int ret = 0;

	/* stop device's busmaster DMA activity */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);

	ret = iwl_poll_bit(trans, CSR_RESET,
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			   CSR_RESET_REG_FLAG_MASTER_DISABLED,
			   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
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	if (ret)
		IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");

	IWL_DEBUG_INFO(trans, "stop master\n");

	return ret;
}

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static void iwl_pcie_apm_stop(struct iwl_trans *trans)
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{
	IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");

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	clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
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	/* Stop device's DMA activity */
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	iwl_pcie_apm_stop_master(trans);
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	/* Reset the entire device */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);

	udelay(10);

	/*
	 * Clear "initialization complete" bit to move adapter from
	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
	 */
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
}

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static int iwl_pcie_nic_init(struct iwl_trans *trans)
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{
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	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	unsigned long flags;

	/* nic_init */
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	spin_lock_irqsave(&trans_pcie->irq_lock, flags);
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	iwl_pcie_apm_init(trans);
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	spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
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	iwl_pcie_set_pwr(trans, false);
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	iwl_op_mode_nic_config(trans->op_mode);
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	/* Allocate the RX queue, or reset if it is already allocated */
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	iwl_pcie_rx_init(trans);
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	/* Allocate or reset and init all Tx and Command queues */
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	if (iwl_pcie_tx_init(trans))
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		return -ENOMEM;

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	if (trans->cfg->base_params->shadow_reg_enable) {
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		/* enable shadow regs in HW */
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		iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
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		IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
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	}

	return 0;
}

#define HW_READY_TIMEOUT (50)

/* Note: returns poll_bit return value, which is >= 0 if success */
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static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
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{
	int ret;

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	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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		    CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
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	/* See if we got it */
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	ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
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			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
			   HW_READY_TIMEOUT);
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	IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
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	return ret;
}

/* Note: returns standard 0/-ERROR code */
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static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
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{
	int ret;
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	int t = 0;
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	IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
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	ret = iwl_pcie_set_hw_ready(trans);
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	/* If the card is ready, exit 0 */
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	if (ret >= 0)
		return 0;

	/* If HW is not ready, prepare the conditions to check again */
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	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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		    CSR_HW_IF_CONFIG_REG_PREPARE);
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	do {
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		ret = iwl_pcie_set_hw_ready(trans);
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		if (ret >= 0)
			return 0;
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		usleep_range(200, 1000);
		t += 200;
	} while (t < 150000);
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	return ret;
}

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/*
 * ucode
 */
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static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
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				   dma_addr_t phy_addr, u32 byte_cnt)
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{
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	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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	int ret;

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	trans_pcie->ucode_write_complete = false;
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	iwl_write_direct32(trans,
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			   FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
			   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
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	iwl_write_direct32(trans,
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			   FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
			   dst_addr);
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	iwl_write_direct32(trans,
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			   FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
			   phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
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	iwl_write_direct32(trans,
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			   FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
			   (iwl_get_dma_hi_addr(phy_addr)
				<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
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	iwl_write_direct32(trans,
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			   FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
			   1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
			   1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
			   FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
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	iwl_write_direct32(trans,
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			   FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
			   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE	|
			   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE	|
			   FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
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	ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
				 trans_pcie->ucode_write_complete, 5 * HZ);
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	if (!ret) {
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		IWL_ERR(trans, "Failed to load firmware chunk!\n");
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		return -ETIMEDOUT;
	}

	return 0;
}

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static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
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			    const struct fw_desc *section)
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{
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	u8 *v_addr;
	dma_addr_t p_addr;
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	u32 offset, chunk_sz = section->len;
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	int ret = 0;

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	IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
		     section_num);

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	v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
				    GFP_KERNEL | __GFP_NOWARN);
	if (!v_addr) {
		IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
		chunk_sz = PAGE_SIZE;
		v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
					    &p_addr, GFP_KERNEL);
		if (!v_addr)
			return -ENOMEM;
	}
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	for (offset = 0; offset < section->len; offset += chunk_sz) {
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		u32 copy_size;

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		copy_size = min_t(u32, chunk_sz, section->len - offset);
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		memcpy(v_addr, (u8 *)section->data + offset, copy_size);
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		ret = iwl_pcie_load_firmware_chunk(trans,
						   section->offset + offset,
						   p_addr, copy_size);
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		if (ret) {
			IWL_ERR(trans,
				"Could not load the [%d] uCode section\n",
				section_num);
			break;
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		}
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	}

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	dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
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	return ret;
}

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static int iwl_pcie_secure_set(struct iwl_trans *trans, int cpu)
{
	int shift_param;
	u32 address;
	int ret = 0;

	if (cpu == 1) {
		shift_param = 0;
		address = CSR_SECURE_BOOT_CPU1_STATUS_ADDR;
	} else {
		shift_param = 16;
		address = CSR_SECURE_BOOT_CPU2_STATUS_ADDR;
	}

	/* set CPU to started */
	iwl_trans_set_bits_mask(trans,
				CSR_UCODE_LOAD_STATUS_ADDR,
				CSR_CPU_STATUS_LOADING_STARTED << shift_param,
				1);

	/* set last complete descriptor number */
	iwl_trans_set_bits_mask(trans,
				CSR_UCODE_LOAD_STATUS_ADDR,
				CSR_CPU_STATUS_NUM_OF_LAST_COMPLETED
				<< shift_param,
				1);

	/* set last loaded block */
	iwl_trans_set_bits_mask(trans,
				CSR_UCODE_LOAD_STATUS_ADDR,
				CSR_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK
				<< shift_param,
				1);

	/* image loading complete */
	iwl_trans_set_bits_mask(trans,
				CSR_UCODE_LOAD_STATUS_ADDR,
				CSR_CPU_STATUS_LOADING_COMPLETED
				<< shift_param,
				1);

	/* set FH_TCSR_0_REG  */
	iwl_trans_set_bits_mask(trans, FH_TCSR_0_REG0, 0x00400000, 1);

	/* verify image verification started  */
	ret = iwl_poll_bit(trans, address,
			   CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS,
			   CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS,
			   CSR_SECURE_TIME_OUT);
	if (ret < 0) {
		IWL_ERR(trans, "secure boot process didn't start\n");
		return ret;
	}

	/* wait for image verification to complete  */
	ret = iwl_poll_bit(trans, address,
			   CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED,
			   CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED,
			   CSR_SECURE_TIME_OUT);

	if (ret < 0) {
		IWL_ERR(trans, "Time out on secure boot process\n");
		return ret;
	}

	return 0;
}

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static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
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				const struct fw_img *image)
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{
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	int i, ret = 0;
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	IWL_DEBUG_FW(trans,
		     "working with %s image\n",
		     image->is_secure ? "Secured" : "Non Secured");
	IWL_DEBUG_FW(trans,
		     "working with %s CPU\n",
		     image->is_dual_cpus ? "Dual" : "Single");

	/* configure the ucode to be ready to get the secured image */
	if (image->is_secure) {
		/* set secure boot inspector addresses */
		iwl_write32(trans, CSR_SECURE_INSPECTOR_CODE_ADDR, 0);
		iwl_write32(trans, CSR_SECURE_INSPECTOR_DATA_ADDR, 0);

		/* release CPU1 reset if secure inspector image burned in OTP */
		iwl_write32(trans, CSR_RESET, 0);
	}

	/* load to FW the binary sections of CPU1 */
	IWL_DEBUG_INFO(trans, "Loading CPU1\n");
	for (i = 0;
	     i < IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU;
	     i++) {
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		if (!image->sec[i].data)
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			break;
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		ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
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		if (ret)
			return ret;
	}
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	/* configure the ucode to start secure process on CPU1 */
	if (image->is_secure) {
		/* config CPU1 to start secure protocol */
		ret = iwl_pcie_secure_set(trans, 1);
		if (ret)
			return ret;
	} else {
		/* Remove all resets to allow NIC to operate */
		iwl_write32(trans, CSR_RESET, 0);
	}

	if (image->is_dual_cpus) {
		/* load to FW the binary sections of CPU2 */
		IWL_DEBUG_INFO(trans, "working w/ DUAL CPUs - Loading CPU2\n");
		for (i = IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU;
			i < IWL_UCODE_SECTION_MAX; i++) {
			if (!image->sec[i].data)
				break;
			ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
			if (ret)
				return ret;
		}

		if (image->is_secure) {
			/* set CPU2 for secure protocol */
			ret = iwl_pcie_secure_set(trans, 2);
			if (ret)
				return ret;
		}
	}
576 577 578 579

	return 0;
}

580
static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
581
				   const struct fw_img *fw, bool run_in_rfkill)
582 583
{
	int ret;
584
	bool hw_rfkill;
585

586
	/* This may fail if AMT took ownership of the device */
587
	if (iwl_pcie_prepare_card_hw(trans)) {
588
		IWL_WARN(trans, "Exit HW not ready\n");
589 590 591
		return -EIO;
	}

592 593
	iwl_enable_rfkill_int(trans);

594
	/* If platform's RF_KILL switch is NOT set to KILL */
595
	hw_rfkill = iwl_is_rfkill_set(trans);
596
	if (hw_rfkill)
597
		set_bit(STATUS_RFKILL, &trans->status);
598
	else
599
		clear_bit(STATUS_RFKILL, &trans->status);
600
	iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
601
	if (hw_rfkill && !run_in_rfkill)
602 603
		return -ERFKILL;

604
	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
605

606
	ret = iwl_pcie_nic_init(trans);
607
	if (ret) {
608
		IWL_ERR(trans, "Unable to init nic\n");
609 610 611 612
		return ret;
	}

	/* make sure rfkill handshake bits are cleared */
613 614
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
615 616 617
		    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);

	/* clear (again), then enable host interrupts */
618
	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
619
	iwl_enable_interrupts(trans);
620 621

	/* really make sure rfkill handshake bits are cleared */
622 623
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
624

625
	/* Load the given image to the HW */
626
	return iwl_pcie_load_given_ucode(trans, fw);
627 628
}

629
static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
630
{
631
	iwl_pcie_reset_ict(trans);
632
	iwl_pcie_tx_start(trans, scd_addr);
633 634
}

635
static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
636
{
637
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
638
	unsigned long flags;
639
	bool hw_rfkill;
640

641
	/* tell the device to stop sending interrupts */
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Johannes Berg 已提交
642
	spin_lock_irqsave(&trans_pcie->irq_lock, flags);
643
	iwl_disable_interrupts(trans);
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Johannes Berg 已提交
644
	spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
645

646
	/* device going down, Stop using ICT table */
647
	iwl_pcie_disable_ict(trans);
648 649 650 651 652 653 654 655

	/*
	 * If a HW restart happens during firmware loading,
	 * then the firmware loading might call this function
	 * and later it might be called again due to the
	 * restart. So don't process again if the device is
	 * already dead.
	 */
656
	if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
657
		iwl_pcie_tx_stop(trans);
658
		iwl_pcie_rx_stop(trans);
659

660
		/* Power-down device's busmaster DMA clocks */
661
		iwl_write_prph(trans, APMG_CLK_DIS_REG,
662 663 664 665 666
			       APMG_CLK_VAL_DMA_CLK_RQT);
		udelay(5);
	}

	/* Make sure (redundant) we've released our request to stay awake */
667
	iwl_clear_bit(trans, CSR_GP_CNTRL,
668
		      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
669 670

	/* Stop the device, and put it in low power state */
671
	iwl_pcie_apm_stop(trans);
672 673 674 675

	/* Upon stop, the APM issues an interrupt if HW RF kill is set.
	 * Clean again the interrupt here
	 */
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676
	spin_lock_irqsave(&trans_pcie->irq_lock, flags);
677
	iwl_disable_interrupts(trans);
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678
	spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
679 680

	/* stop and reset the on-board processor */
681
	iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
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682 683

	/* clear all status bits */
684 685 686 687 688
	clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
	clear_bit(STATUS_INT_ENABLED, &trans->status);
	clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
	clear_bit(STATUS_TPOWER_PMI, &trans->status);
	clear_bit(STATUS_RFKILL, &trans->status);
689 690 691 692 693 694 695 696 697 698 699 700 701 702 703

	/*
	 * Even if we stop the HW, we still want the RF kill
	 * interrupt
	 */
	iwl_enable_rfkill_int(trans);

	/*
	 * Check again since the RF kill state may have changed while
	 * all the interrupts were disabled, in this case we couldn't
	 * receive the RF kill interrupt and update the state in the
	 * op_mode.
	 */
	hw_rfkill = iwl_is_rfkill_set(trans);
	if (hw_rfkill)
704
		set_bit(STATUS_RFKILL, &trans->status);
705
	else
706
		clear_bit(STATUS_RFKILL, &trans->status);
707
	iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
708 709
}

710
static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
711 712
{
	iwl_disable_interrupts(trans);
713 714 715 716 717 718 719 720

	/*
	 * in testing mode, the host stays awake and the
	 * hardware won't be reset (not even partially)
	 */
	if (test)
		return;

721 722
	iwl_pcie_disable_ict(trans);

723 724
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
725 726 727 728 729 730 731 732 733 734 735 736 737 738
	iwl_clear_bit(trans, CSR_GP_CNTRL,
		      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

	/*
	 * reset TX queues -- some of their registers reset during S3
	 * so if we don't reset everything here the D3 image would try
	 * to execute some invalid memory upon resume
	 */
	iwl_trans_pcie_tx_reset(trans);

	iwl_pcie_set_pwr(trans, true);
}

static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
739 740
				    enum iwl_d3_status *status,
				    bool test)
741 742 743 744
{
	u32 val;
	int ret;

745 746 747 748 749 750
	if (test) {
		iwl_enable_interrupts(trans);
		*status = IWL_D3_STATUS_ALIVE;
		return 0;
	}

751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787
	iwl_pcie_set_pwr(trans, false);

	val = iwl_read32(trans, CSR_RESET);
	if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
		*status = IWL_D3_STATUS_RESET;
		return 0;
	}

	/*
	 * Also enables interrupts - none will happen as the device doesn't
	 * know we're waking it up, only when the opmode actually tells it
	 * after this call.
	 */
	iwl_pcie_reset_ict(trans);

	iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
	iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   25000);
	if (ret) {
		IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
		return ret;
	}

	iwl_trans_pcie_tx_reset(trans);

	ret = iwl_pcie_rx_init(trans);
	if (ret) {
		IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
		return ret;
	}

	*status = IWL_D3_STATUS_ALIVE;
	return 0;
788 789
}

790
static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
791
{
792
	bool hw_rfkill;
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Johannes Berg 已提交
793
	int err;
794

795
	err = iwl_pcie_prepare_card_hw(trans);
796
	if (err) {
797
		IWL_ERR(trans, "Error while preparing HW: %d\n", err);
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Johannes Berg 已提交
798
		return err;
799
	}
800

801 802 803 804 805
	/* Reset the entire device */
	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);

	usleep_range(10, 15);

806
	iwl_pcie_apm_init(trans);
807

808 809 810
	/* From now on, the op_mode will be kept updated about RF kill state */
	iwl_enable_rfkill_int(trans);

811
	hw_rfkill = iwl_is_rfkill_set(trans);
812
	if (hw_rfkill)
813
		set_bit(STATUS_RFKILL, &trans->status);
814
	else
815
		clear_bit(STATUS_RFKILL, &trans->status);
816
	iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
817

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Johannes Berg 已提交
818
	return 0;
819 820
}

821
static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
822
{
823
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
824
	unsigned long flags;
825

826
	/* disable interrupts - don't enable HW RF kill interrupt */
827 828 829 830
	spin_lock_irqsave(&trans_pcie->irq_lock, flags);
	iwl_disable_interrupts(trans);
	spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);

831
	iwl_pcie_apm_stop(trans);
832

833 834 835
	spin_lock_irqsave(&trans_pcie->irq_lock, flags);
	iwl_disable_interrupts(trans);
	spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
836

E
Emmanuel Grumbach 已提交
837
	iwl_pcie_disable_ict(trans);
838 839
}

840 841
static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
{
842
	writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
843 844 845 846
}

static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
{
847
	writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
848 849 850 851
}

static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
{
852
	return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
853 854
}

855 856
static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
{
A
Amnon Paz 已提交
857 858
	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
			       ((reg & 0x000FFFFF) | (3 << 24)));
859 860 861 862 863 864 865
	return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
}

static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
				      u32 val)
{
	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
A
Amnon Paz 已提交
866
			       ((addr & 0x000FFFFF) | (3 << 24)));
867 868 869
	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
}

870
static void iwl_trans_pcie_configure(struct iwl_trans *trans,
871
				     const struct iwl_trans_config *trans_cfg)
872 873 874 875
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	trans_pcie->cmd_queue = trans_cfg->cmd_queue;
876
	trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
877 878 879 880 881 882 883
	if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
		trans_pcie->n_no_reclaim_cmds = 0;
	else
		trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
	if (trans_pcie->n_no_reclaim_cmds)
		memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
		       trans_pcie->n_no_reclaim_cmds * sizeof(u8));
884

885 886 887 888 889
	trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
	if (trans_pcie->rx_buf_size_8k)
		trans_pcie->rx_page_order = get_order(8 * 1024);
	else
		trans_pcie->rx_page_order = get_order(4 * 1024);
890 891 892

	trans_pcie->wd_timeout =
		msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
J
Johannes Berg 已提交
893 894

	trans_pcie->command_names = trans_cfg->command_names;
895
	trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
896 897
}

898
void iwl_trans_pcie_free(struct iwl_trans *trans)
899
{
900
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
901

902 903
	synchronize_irq(trans_pcie->pci_dev->irq);

904
	iwl_pcie_tx_free(trans);
905
	iwl_pcie_rx_free(trans);
906

J
Johannes Berg 已提交
907 908
	free_irq(trans_pcie->pci_dev->irq, trans);
	iwl_pcie_free_ict(trans);
909 910

	pci_disable_msi(trans_pcie->pci_dev);
911
	iounmap(trans_pcie->hw_base);
912 913
	pci_release_regions(trans_pcie->pci_dev);
	pci_disable_device(trans_pcie->pci_dev);
914
	kmem_cache_destroy(trans->dev_cmd_pool);
915

916
	kfree(trans);
917 918
}

D
Don Fry 已提交
919 920 921
static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
{
	if (state)
922
		set_bit(STATUS_TPOWER_PMI, &trans->status);
D
Don Fry 已提交
923
	else
924
		clear_bit(STATUS_TPOWER_PMI, &trans->status);
D
Don Fry 已提交
925 926
}

927 928
static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
						unsigned long *flags)
929 930
{
	int ret;
931 932 933
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
934 935

	/* this bit wakes up the NIC */
936 937
	__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
				 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968

	/*
	 * These bits say the device is running, and should keep running for
	 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
	 * but they do not indicate that embedded SRAM is restored yet;
	 * 3945 and 4965 have volatile SRAM, and must save/restore contents
	 * to/from host DRAM when sleeping/waking for power-saving.
	 * Each direction takes approximately 1/4 millisecond; with this
	 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
	 * series of register accesses are expected (e.g. reading Event Log),
	 * to keep device from sleeping.
	 *
	 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
	 * SRAM is okay/restored.  We don't check that here because this call
	 * is just for hardware register access; but GP1 MAC_SLEEP check is a
	 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
	 *
	 * 5000 series and later (including 1000 series) have non-volatile SRAM,
	 * and do not save/restore SRAM when power cycling.
	 */
	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
			   CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
			   (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
			    CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
	if (unlikely(ret < 0)) {
		iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
		if (!silent) {
			u32 val = iwl_read32(trans, CSR_GP_CNTRL);
			WARN_ONCE(1,
				  "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
				  val);
969
			spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
970 971 972 973
			return false;
		}
	}

974 975 976 977
	/*
	 * Fool sparse by faking we release the lock - sparse will
	 * track nic_access anyway.
	 */
978
	__release(&trans_pcie->reg_lock);
979 980 981
	return true;
}

982 983
static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
					      unsigned long *flags)
984
{
985
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
986

987
	lockdep_assert_held(&trans_pcie->reg_lock);
988 989 990 991 992

	/*
	 * Fool sparse by faking we acquiring the lock - sparse will
	 * track nic_access anyway.
	 */
993
	__acquire(&trans_pcie->reg_lock);
994

995 996
	__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
				   CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
997 998 999 1000 1001 1002 1003
	/*
	 * Above we read the CSR_GP_CNTRL register, which will flush
	 * any previous writes, but we need the write that clears the
	 * MAC_ACCESS_REQ bit to be performed before any other writes
	 * scheduled on different CPUs (after we drop reg_lock).
	 */
	mmiowb();
1004
	spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1005 1006
}

1007 1008 1009 1010 1011 1012 1013
static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
				   void *buf, int dwords)
{
	unsigned long flags;
	int offs, ret = 0;
	u32 *vals = buf;

1014
	if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1015 1016 1017
		iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
		for (offs = 0; offs < dwords; offs++)
			vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1018
		iwl_trans_release_nic_access(trans, &flags);
1019 1020 1021 1022 1023 1024 1025
	} else {
		ret = -EBUSY;
	}
	return ret;
}

static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1026
				    const void *buf, int dwords)
1027 1028 1029
{
	unsigned long flags;
	int offs, ret = 0;
1030
	const u32 *vals = buf;
1031

1032
	if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1033 1034
		iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
		for (offs = 0; offs < dwords; offs++)
E
Emmanuel Grumbach 已提交
1035 1036
			iwl_write32(trans, HBUS_TARG_MEM_WDAT,
				    vals ? vals[offs] : 0);
1037
		iwl_trans_release_nic_access(trans, &flags);
1038 1039 1040 1041 1042
	} else {
		ret = -EBUSY;
	}
	return ret;
}
1043

1044 1045
#define IWL_FLUSH_WAIT_MS	2000

1046
static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
1047
{
1048
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1049
	struct iwl_txq *txq;
1050 1051 1052
	struct iwl_queue *q;
	int cnt;
	unsigned long now = jiffies;
1053 1054
	u32 scd_sram_addr;
	u8 buf[16];
1055 1056 1057
	int ret = 0;

	/* waiting for all the tx frames complete might take a while */
1058
	for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
W
Wey-Yi Guy 已提交
1059
		if (cnt == trans_pcie->cmd_queue)
1060
			continue;
1061
		txq = &trans_pcie->txq[cnt];
1062 1063 1064 1065 1066 1067
		q = &txq->q;
		while (q->read_ptr != q->write_ptr && !time_after(jiffies,
		       now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
			msleep(1);

		if (q->read_ptr != q->write_ptr) {
1068 1069
			IWL_ERR(trans,
				"fail to flush all tx fifo queues Q %d\n", cnt);
1070 1071 1072 1073
			ret = -ETIMEDOUT;
			break;
		}
	}
1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111

	if (!ret)
		return 0;

	IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
		txq->q.read_ptr, txq->q.write_ptr);

	scd_sram_addr = trans_pcie->scd_base_addr +
			SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
	iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));

	iwl_print_hex_error(trans, buf, sizeof(buf));

	for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
		IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
			iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));

	for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
		u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
		u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
		bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
		u32 tbl_dw =
			iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
					     SCD_TRANS_TBL_OFFSET_QUEUE(cnt));

		if (cnt & 0x1)
			tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
		else
			tbl_dw = tbl_dw & 0x0000FFFF;

		IWL_ERR(trans,
			"Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
			cnt, active ? "" : "in", fifo, tbl_dw,
			iwl_read_prph(trans,
				      SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
			iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
	}

1112 1113 1114
	return ret;
}

1115 1116 1117
static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
					 u32 mask, u32 value)
{
1118
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1119 1120
	unsigned long flags;

1121
	spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1122
	__iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1123
	spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1124 1125
}

1126 1127
static const char *get_csr_string(int cmd)
{
J
Johannes Berg 已提交
1128
#define IWL_CMD(x) case x: return #x
1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155
	switch (cmd) {
	IWL_CMD(CSR_HW_IF_CONFIG_REG);
	IWL_CMD(CSR_INT_COALESCING);
	IWL_CMD(CSR_INT);
	IWL_CMD(CSR_INT_MASK);
	IWL_CMD(CSR_FH_INT_STATUS);
	IWL_CMD(CSR_GPIO_IN);
	IWL_CMD(CSR_RESET);
	IWL_CMD(CSR_GP_CNTRL);
	IWL_CMD(CSR_HW_REV);
	IWL_CMD(CSR_EEPROM_REG);
	IWL_CMD(CSR_EEPROM_GP);
	IWL_CMD(CSR_OTP_GP_REG);
	IWL_CMD(CSR_GIO_REG);
	IWL_CMD(CSR_GP_UCODE_REG);
	IWL_CMD(CSR_GP_DRIVER_REG);
	IWL_CMD(CSR_UCODE_DRV_GP1);
	IWL_CMD(CSR_UCODE_DRV_GP2);
	IWL_CMD(CSR_LED_REG);
	IWL_CMD(CSR_DRAM_INT_TBL_REG);
	IWL_CMD(CSR_GIO_CHICKEN_BITS);
	IWL_CMD(CSR_ANA_PLL_CFG);
	IWL_CMD(CSR_HW_REV_WA_REG);
	IWL_CMD(CSR_DBG_HPET_MEM_REG);
	default:
		return "UNKNOWN";
	}
J
Johannes Berg 已提交
1156
#undef IWL_CMD
1157 1158
}

1159
void iwl_pcie_dump_csr(struct iwl_trans *trans)
1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192
{
	int i;
	static const u32 csr_tbl[] = {
		CSR_HW_IF_CONFIG_REG,
		CSR_INT_COALESCING,
		CSR_INT,
		CSR_INT_MASK,
		CSR_FH_INT_STATUS,
		CSR_GPIO_IN,
		CSR_RESET,
		CSR_GP_CNTRL,
		CSR_HW_REV,
		CSR_EEPROM_REG,
		CSR_EEPROM_GP,
		CSR_OTP_GP_REG,
		CSR_GIO_REG,
		CSR_GP_UCODE_REG,
		CSR_GP_DRIVER_REG,
		CSR_UCODE_DRV_GP1,
		CSR_UCODE_DRV_GP2,
		CSR_LED_REG,
		CSR_DRAM_INT_TBL_REG,
		CSR_GIO_CHICKEN_BITS,
		CSR_ANA_PLL_CFG,
		CSR_HW_REV_WA_REG,
		CSR_DBG_HPET_MEM_REG
	};
	IWL_ERR(trans, "CSR values:\n");
	IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
		"CSR_INT_PERIODIC_REG)\n");
	for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
		IWL_ERR(trans, "  %25s: 0X%08x\n",
			get_csr_string(csr_tbl[i]),
1193
			iwl_read32(trans, csr_tbl[i]));
1194 1195 1196
	}
}

1197 1198 1199
#ifdef CONFIG_IWLWIFI_DEBUGFS
/* create and remove of files */
#define DEBUGFS_ADD_FILE(name, parent, mode) do {			\
1200
	if (!debugfs_create_file(#name, mode, parent, trans,		\
1201
				 &iwl_dbgfs_##name##_ops))		\
1202
		goto err;						\
1203 1204 1205 1206 1207 1208
} while (0)

/* file operation */
#define DEBUGFS_READ_FILE_OPS(name)					\
static const struct file_operations iwl_dbgfs_##name##_ops = {		\
	.read = iwl_dbgfs_##name##_read,				\
1209
	.open = simple_open,						\
1210 1211 1212
	.llseek = generic_file_llseek,					\
};

1213 1214 1215
#define DEBUGFS_WRITE_FILE_OPS(name)                                    \
static const struct file_operations iwl_dbgfs_##name##_ops = {          \
	.write = iwl_dbgfs_##name##_write,                              \
1216
	.open = simple_open,						\
1217 1218 1219
	.llseek = generic_file_llseek,					\
};

1220 1221 1222 1223
#define DEBUGFS_READ_WRITE_FILE_OPS(name)				\
static const struct file_operations iwl_dbgfs_##name##_ops = {		\
	.write = iwl_dbgfs_##name##_write,				\
	.read = iwl_dbgfs_##name##_read,				\
1224
	.open = simple_open,						\
1225 1226 1227 1228
	.llseek = generic_file_llseek,					\
};

static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1229 1230
				       char __user *user_buf,
				       size_t count, loff_t *ppos)
1231
{
1232
	struct iwl_trans *trans = file->private_data;
1233
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1234
	struct iwl_txq *txq;
1235 1236 1237 1238 1239
	struct iwl_queue *q;
	char *buf;
	int pos = 0;
	int cnt;
	int ret;
1240 1241
	size_t bufsz;

1242
	bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1243

J
Johannes Berg 已提交
1244
	if (!trans_pcie->txq)
1245
		return -EAGAIN;
J
Johannes Berg 已提交
1246

1247 1248 1249 1250
	buf = kzalloc(bufsz, GFP_KERNEL);
	if (!buf)
		return -ENOMEM;

1251
	for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1252
		txq = &trans_pcie->txq[cnt];
1253 1254
		q = &txq->q;
		pos += scnprintf(buf + pos, bufsz - pos,
1255
				"hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1256
				cnt, q->read_ptr, q->write_ptr,
1257 1258
				!!test_bit(cnt, trans_pcie->queue_used),
				!!test_bit(cnt, trans_pcie->queue_stopped));
1259 1260 1261 1262 1263 1264 1265
	}
	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
	kfree(buf);
	return ret;
}

static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1266 1267 1268
				       char __user *user_buf,
				       size_t count, loff_t *ppos)
{
1269
	struct iwl_trans *trans = file->private_data;
1270
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1271
	struct iwl_rxq *rxq = &trans_pcie->rxq;
1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291
	char buf[256];
	int pos = 0;
	const size_t bufsz = sizeof(buf);

	pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
						rxq->read);
	pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
						rxq->write);
	pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
						rxq->free_count);
	if (rxq->rb_stts) {
		pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
			 le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
	} else {
		pos += scnprintf(buf + pos, bufsz - pos,
					"closed_rb_num: Not Allocated\n");
	}
	return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
}

1292 1293
static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
					char __user *user_buf,
1294 1295
					size_t count, loff_t *ppos)
{
1296
	struct iwl_trans *trans = file->private_data;
1297
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1298 1299 1300 1301 1302 1303 1304 1305
	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;

	int pos = 0;
	char *buf;
	int bufsz = 24 * 64; /* 24 items * 64 char per item */
	ssize_t ret;

	buf = kzalloc(bufsz, GFP_KERNEL);
J
Johannes Berg 已提交
1306
	if (!buf)
1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354
		return -ENOMEM;

	pos += scnprintf(buf + pos, bufsz - pos,
			"Interrupt Statistics Report:\n");

	pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
		isr_stats->hw);
	pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
		isr_stats->sw);
	if (isr_stats->sw || isr_stats->hw) {
		pos += scnprintf(buf + pos, bufsz - pos,
			"\tLast Restarting Code:  0x%X\n",
			isr_stats->err_code);
	}
#ifdef CONFIG_IWLWIFI_DEBUG
	pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
		isr_stats->sch);
	pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
		isr_stats->alive);
#endif
	pos += scnprintf(buf + pos, bufsz - pos,
		"HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);

	pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
		isr_stats->ctkill);

	pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
		isr_stats->wakeup);

	pos += scnprintf(buf + pos, bufsz - pos,
		"Rx command responses:\t\t %u\n", isr_stats->rx);

	pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
		isr_stats->tx);

	pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
		isr_stats->unhandled);

	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
	kfree(buf);
	return ret;
}

static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
					 const char __user *user_buf,
					 size_t count, loff_t *ppos)
{
	struct iwl_trans *trans = file->private_data;
1355
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373
	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;

	char buf[8];
	int buf_size;
	u32 reset_flag;

	memset(buf, 0, sizeof(buf));
	buf_size = min(count, sizeof(buf) -  1);
	if (copy_from_user(buf, user_buf, buf_size))
		return -EFAULT;
	if (sscanf(buf, "%x", &reset_flag) != 1)
		return -EFAULT;
	if (reset_flag == 0)
		memset(isr_stats, 0, sizeof(*isr_stats));

	return count;
}

1374
static ssize_t iwl_dbgfs_csr_write(struct file *file,
1375 1376
				   const char __user *user_buf,
				   size_t count, loff_t *ppos)
1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389
{
	struct iwl_trans *trans = file->private_data;
	char buf[8];
	int buf_size;
	int csr;

	memset(buf, 0, sizeof(buf));
	buf_size = min(count, sizeof(buf) -  1);
	if (copy_from_user(buf, user_buf, buf_size))
		return -EFAULT;
	if (sscanf(buf, "%d", &csr) != 1)
		return -EFAULT;

1390
	iwl_pcie_dump_csr(trans);
1391 1392 1393 1394 1395

	return count;
}

static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1396 1397
				     char __user *user_buf,
				     size_t count, loff_t *ppos)
1398 1399
{
	struct iwl_trans *trans = file->private_data;
1400
	char *buf = NULL;
1401 1402 1403
	int pos = 0;
	ssize_t ret = -EFAULT;

1404
	ret = pos = iwl_dump_fh(trans, &buf);
1405 1406 1407 1408 1409 1410 1411 1412 1413
	if (buf) {
		ret = simple_read_from_buffer(user_buf,
					      count, ppos, buf, pos);
		kfree(buf);
	}

	return ret;
}

1414
DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1415
DEBUGFS_READ_FILE_OPS(fh_reg);
1416 1417
DEBUGFS_READ_FILE_OPS(rx_queue);
DEBUGFS_READ_FILE_OPS(tx_queue);
1418
DEBUGFS_WRITE_FILE_OPS(csr);
1419 1420 1421 1422 1423 1424

/*
 * Create the debugfs files and directories
 *
 */
static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1425
					 struct dentry *dir)
1426 1427 1428
{
	DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
	DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1429
	DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1430 1431
	DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
	DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1432
	return 0;
1433 1434 1435 1436

err:
	IWL_ERR(trans, "failed to create the trans debugfs entry\n");
	return -ENOMEM;
1437 1438 1439
}
#else
static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1440 1441 1442 1443
					 struct dentry *dir)
{
	return 0;
}
1444 1445
#endif /*CONFIG_IWLWIFI_DEBUGFS */

1446
static const struct iwl_trans_ops trans_ops_pcie = {
1447
	.start_hw = iwl_trans_pcie_start_hw,
1448
	.op_mode_leave = iwl_trans_pcie_op_mode_leave,
1449
	.fw_alive = iwl_trans_pcie_fw_alive,
1450
	.start_fw = iwl_trans_pcie_start_fw,
1451
	.stop_device = iwl_trans_pcie_stop_device,
1452

1453 1454
	.d3_suspend = iwl_trans_pcie_d3_suspend,
	.d3_resume = iwl_trans_pcie_d3_resume,
1455

1456
	.send_cmd = iwl_trans_pcie_send_hcmd,
1457

1458
	.tx = iwl_trans_pcie_tx,
1459
	.reclaim = iwl_trans_pcie_reclaim,
1460

1461
	.txq_disable = iwl_trans_pcie_txq_disable,
1462
	.txq_enable = iwl_trans_pcie_txq_enable,
1463

1464
	.dbgfs_register = iwl_trans_pcie_dbgfs_register,
1465

1466
	.wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1467

1468 1469 1470
	.write8 = iwl_trans_pcie_write8,
	.write32 = iwl_trans_pcie_write32,
	.read32 = iwl_trans_pcie_read32,
1471 1472
	.read_prph = iwl_trans_pcie_read_prph,
	.write_prph = iwl_trans_pcie_write_prph,
1473 1474
	.read_mem = iwl_trans_pcie_read_mem,
	.write_mem = iwl_trans_pcie_write_mem,
1475
	.configure = iwl_trans_pcie_configure,
D
Don Fry 已提交
1476
	.set_pmi = iwl_trans_pcie_set_pmi,
1477
	.grab_nic_access = iwl_trans_pcie_grab_nic_access,
1478 1479
	.release_nic_access = iwl_trans_pcie_release_nic_access,
	.set_bits_mask = iwl_trans_pcie_set_bits_mask,
1480
};
1481

1482
struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1483 1484
				       const struct pci_device_id *ent,
				       const struct iwl_cfg *cfg)
1485 1486 1487 1488 1489 1490 1491
{
	struct iwl_trans_pcie *trans_pcie;
	struct iwl_trans *trans;
	u16 pci_cmd;
	int err;

	trans = kzalloc(sizeof(struct iwl_trans) +
1492
			sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1493 1494 1495 1496
	if (!trans) {
		err = -ENOMEM;
		goto out;
	}
1497 1498 1499 1500

	trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

	trans->ops = &trans_ops_pcie;
1501
	trans->cfg = cfg;
1502
	trans_lockdep_init(trans);
1503
	trans_pcie->trans = trans;
J
Johannes Berg 已提交
1504
	spin_lock_init(&trans_pcie->irq_lock);
1505
	spin_lock_init(&trans_pcie->reg_lock);
1506
	init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1507

J
Johannes Berg 已提交
1508 1509 1510 1511
	err = pci_enable_device(pdev);
	if (err)
		goto out_no_pci;

1512 1513 1514 1515 1516 1517 1518 1519 1520 1521
	if (!cfg->base_params->pcie_l1_allowed) {
		/*
		 * W/A - seems to solve weird behavior. We need to remove this
		 * if we don't want to stay in L1 all the time. This wastes a
		 * lot of power.
		 */
		pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
				       PCIE_LINK_STATE_L1 |
				       PCIE_LINK_STATE_CLKPM);
	}
1522 1523 1524 1525 1526 1527 1528 1529 1530 1531

	pci_set_master(pdev);

	err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
	if (!err)
		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
	if (err) {
		err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
		if (!err)
			err = pci_set_consistent_dma_mask(pdev,
1532
							  DMA_BIT_MASK(32));
1533 1534
		/* both attempts failed: */
		if (err) {
1535
			dev_err(&pdev->dev, "No suitable DMA available\n");
1536 1537 1538 1539 1540 1541
			goto out_pci_disable_device;
		}
	}

	err = pci_request_regions(pdev, DRV_NAME);
	if (err) {
1542
		dev_err(&pdev->dev, "pci_request_regions failed\n");
1543 1544 1545
		goto out_pci_disable_device;
	}

1546
	trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1547
	if (!trans_pcie->hw_base) {
1548
		dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1549 1550 1551 1552 1553 1554 1555 1556 1557
		err = -ENODEV;
		goto out_pci_release_regions;
	}

	/* We disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state */
	pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);

	err = pci_enable_msi(pdev);
1558
	if (err) {
1559
		dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1560 1561 1562 1563 1564 1565 1566
		/* enable rfkill interrupt: hw bug w/a */
		pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
		if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
			pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
			pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
		}
	}
1567 1568 1569

	trans->dev = &pdev->dev;
	trans_pcie->pci_dev = pdev;
1570
	trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
E
Emmanuel Grumbach 已提交
1571
	trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1572 1573
	snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
		 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1574

1575
	/* Initialize the wait queue for commands */
1576
	init_waitqueue_head(&trans_pcie->wait_command_queue);
1577

1578 1579
	snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
		 "iwl_cmd_pool:%s", dev_name(trans->dev));
1580 1581 1582

	trans->dev_cmd_headroom = 0;
	trans->dev_cmd_pool =
1583
		kmem_cache_create(trans->dev_cmd_pool_name,
1584 1585 1586 1587 1588 1589
				  sizeof(struct iwl_device_cmd)
				  + trans->dev_cmd_headroom,
				  sizeof(void *),
				  SLAB_HWCACHE_ALIGN,
				  NULL);

1590 1591
	if (!trans->dev_cmd_pool) {
		err = -ENOMEM;
1592
		goto out_pci_disable_msi;
1593
	}
1594

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Johannes Berg 已提交
1595 1596 1597 1598 1599
	trans_pcie->inta_mask = CSR_INI_SET_MASK;

	if (iwl_pcie_alloc_ict(trans))
		goto out_free_cmd_pool;

1600 1601 1602 1603
	err = request_threaded_irq(pdev->irq, iwl_pcie_isr_ict,
				   iwl_pcie_irq_handler,
				   IRQF_SHARED, DRV_NAME, trans);
	if (err) {
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Johannes Berg 已提交
1604 1605 1606 1607
		IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
		goto out_free_ict;
	}

1608 1609
	return trans;

J
Johannes Berg 已提交
1610 1611 1612 1613
out_free_ict:
	iwl_pcie_free_ict(trans);
out_free_cmd_pool:
	kmem_cache_destroy(trans->dev_cmd_pool);
1614 1615
out_pci_disable_msi:
	pci_disable_msi(pdev);
1616 1617 1618 1619 1620 1621
out_pci_release_regions:
	pci_release_regions(pdev);
out_pci_disable_device:
	pci_disable_device(pdev);
out_no_pci:
	kfree(trans);
1622 1623
out:
	return ERR_PTR(err);
1624
}