i915_drv.h 105.9 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include "i915_reg.h"
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#include "intel_bios.h"
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#include "intel_ringbuffer.h"
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#include "intel_lrc.h"
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#include "i915_gem_gtt.h"
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#include "i915_gem_render_state.h"
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <drm/intel-gtt.h>
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#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
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#include <drm/drm_gem.h>
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#include <linux/backlight.h>
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#include <linux/hashtable.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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#include "intel_guc.h"
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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20150928"
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#undef WARN_ON
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/* Many gcc seem to no see through this and fall over :( */
#if 0
#define WARN_ON(x) ({ \
	bool __i915_warn_cond = (x); \
	if (__builtin_constant_p(__i915_warn_cond)) \
		BUILD_BUG_ON(__i915_warn_cond); \
	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
#else
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#define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
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#endif

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#undef WARN_ON_ONCE
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#define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
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#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
			     (long) (x), __func__);
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
	if (unlikely(__ret_warn_on)) {					\
		if (i915.verbose_state_checks)				\
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			WARN(1, format);				\
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		else 							\
			DRM_ERROR(format);				\
	}								\
	unlikely(__ret_warn_on);					\
})

#define I915_STATE_WARN_ON(condition) ({				\
	int __ret_warn_on = !!(condition);				\
	if (unlikely(__ret_warn_on)) {					\
		if (i915.verbose_state_checks)				\
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			WARN(1, "WARN_ON(" #condition ")\n");		\
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		else 							\
			DRM_ERROR("WARN_ON(" #condition ")\n");		\
	}								\
	unlikely(__ret_warn_on);					\
})
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static inline const char *yesno(bool v)
{
	return v ? "yes" : "no";
}

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enum pipe {
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	INVALID_PIPE = -1,
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	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
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	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
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	TRANSCODER_EDP,
	I915_MAX_TRANSCODERS
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};
#define transcoder_name(t) ((t) + 'A')

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/*
 * This is the maximum (across all platforms) number of planes (primary +
 * sprites) that can be active at the same time on one pipe.
 *
 * This value doesn't count the cursor plane.
 */
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#define I915_MAX_PLANES	4
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enum plane {
	PLANE_A = 0,
	PLANE_B,
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	PLANE_C,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
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enum port {
	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

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#define I915_NUM_PHYS_VLV 2
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enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
	DPIO_PHY1
};

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enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
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	POWER_DOMAIN_TRANSCODER_EDP,
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	POWER_DOMAIN_PORT_DDI_A_2_LANES,
	POWER_DOMAIN_PORT_DDI_A_4_LANES,
	POWER_DOMAIN_PORT_DDI_B_2_LANES,
	POWER_DOMAIN_PORT_DDI_B_4_LANES,
	POWER_DOMAIN_PORT_DDI_C_2_LANES,
	POWER_DOMAIN_PORT_DDI_C_4_LANES,
	POWER_DOMAIN_PORT_DDI_D_2_LANES,
	POWER_DOMAIN_PORT_DDI_D_4_LANES,
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	POWER_DOMAIN_PORT_DDI_E_2_LANES,
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	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
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	POWER_DOMAIN_VGA,
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	POWER_DOMAIN_AUDIO,
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	POWER_DOMAIN_PLLS,
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	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
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	POWER_DOMAIN_INIT,
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	POWER_DOMAIN_NUM,
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};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
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	HPD_PORT_E,
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	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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#define for_each_plane(__dev_priv, __pipe, __p)				\
	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)
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#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)
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#define for_each_crtc(dev, crtc) \
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)

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#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
			    &dev->mode_config.plane_list,	\
			    base.head)

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#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
		if ((intel_plane)->pipe == (intel_crtc)->pipe)

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#define for_each_intel_crtc(dev, intel_crtc) \
	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)

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#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

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#define for_each_intel_connector(dev, intel_connector)		\
	list_for_each_entry(intel_connector,			\
			    &dev->mode_config.connector_list,	\
			    base.head)

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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
		if ((intel_encoder)->base.crtc == (__crtc))

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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
		if ((intel_connector)->base.encoder == (__encoder))

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#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
		if ((1 << (domain)) & (mask))

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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
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/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
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	} mm;
	struct idr context_idr;

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	struct intel_rps_client {
		struct list_head link;
		unsigned boosts;
	} rps;
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	struct intel_engine_cs *bsd_ring;
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};

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enum intel_dpll_id {
	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
	/* real shared dpll ids must be >= 0 */
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	DPLL_ID_PCH_PLL_A = 0,
	DPLL_ID_PCH_PLL_B = 1,
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	/* hsw/bdw */
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	DPLL_ID_WRPLL1 = 0,
	DPLL_ID_WRPLL2 = 1,
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	/* skl */
	DPLL_ID_SKL_DPLL1 = 0,
	DPLL_ID_SKL_DPLL2 = 1,
	DPLL_ID_SKL_DPLL3 = 2,
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};
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#define I915_NUM_PLLS 3
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struct intel_dpll_hw_state {
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	/* i9xx, pch plls */
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	uint32_t dpll;
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	uint32_t dpll_md;
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	uint32_t fp0;
	uint32_t fp1;
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	/* hsw, bdw */
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	uint32_t wrpll;
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	/* skl */
	/*
	 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
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	 * lower part of ctrl1 and they get shifted into position when writing
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	 * the register.  This allows us to easily compare the state to share
	 * the DPLL.
	 */
	uint32_t ctrl1;
	/* HDMI only, 0 when used for DP */
	uint32_t cfgcr1, cfgcr2;
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	/* bxt */
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	uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
		 pcsdw12;
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};

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struct intel_shared_dpll_config {
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	unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
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	struct intel_dpll_hw_state hw_state;
};

struct intel_shared_dpll {
	struct intel_shared_dpll_config config;
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	int active; /* count of number of active CRTCs (i.e. DPMS on) */
	bool on; /* is the PLL actually active? Disabled during modeset */
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	const char *name;
	/* should match the index in the dev_priv->shared_dplls array */
	enum intel_dpll_id id;
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	/* The mode_set hook is optional and should be used together with the
	 * intel_prepare_shared_dpll function. */
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	void (*mode_set)(struct drm_i915_private *dev_priv,
			 struct intel_shared_dpll *pll);
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	void (*enable)(struct drm_i915_private *dev_priv,
		       struct intel_shared_dpll *pll);
	void (*disable)(struct drm_i915_private *dev_priv,
			struct intel_shared_dpll *pll);
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	bool (*get_hw_state)(struct drm_i915_private *dev_priv,
			     struct intel_shared_dpll *pll,
			     struct intel_dpll_hw_state *hw_state);
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};

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#define SKL_DPLL0 0
#define SKL_DPLL1 1
#define SKL_DPLL2 2
#define SKL_DPLL3 3

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/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

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/* Interface history:
 *
 * 1.1: Original.
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 * 1.2: Add Power Management
 * 1.3: Add vblank support
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 * 1.4: Fix cmdbuffer path, add heap destroy
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 * 1.5: Add vblank pipe configuration
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 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
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 */
#define DRIVER_MAJOR		1
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#define DRIVER_MINOR		6
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#define DRIVER_PATCHLEVEL	0

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#define WATCH_LISTS	0
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struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

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struct intel_opregion {
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	struct opregion_header __iomem *header;
	struct opregion_acpi __iomem *acpi;
	struct opregion_swsci __iomem *swsci;
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	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
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	struct opregion_asle __iomem *asle;
	void __iomem *vbt;
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	u32 __iomem *lid_state;
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	struct work_struct asle_work;
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};
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#define OPREGION_SIZE            (8*1024)
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struct intel_overlay;
struct intel_overlay_error_state;

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#define I915_FENCE_REG_NONE -1
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#define I915_MAX_NUM_FENCES 32
/* 32 fences + sign bit for FENCE_REG_NONE */
#define I915_MAX_NUM_FENCE_BITS 6
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struct drm_i915_fence_reg {
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	struct list_head lru_list;
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	struct drm_i915_gem_object *obj;
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	int pin_count;
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};
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struct sdvo_device_mapping {
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	u8 initialized;
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	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
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	u8 i2c_pin;
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	u8 ddc_pin;
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};

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struct intel_display_error_state;

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struct drm_i915_error_state {
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	struct kref ref;
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	struct timeval time;

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	char error_msg[128];
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	int iommu;
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	u32 reset_count;
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	u32 suspend_count;
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	/* Generic register state */
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	u32 eir;
	u32 pgtbl_er;
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	u32 ier;
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	u32 gtier[4];
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	u32 ccid;
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	u32 derrmr;
	u32 forcewake;
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	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
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	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
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	u32 done_reg;
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	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
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	u32 extra_instdone[I915_NUM_INSTDONE_REG];
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
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	struct drm_i915_error_object *semaphore_obj;
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	struct drm_i915_error_ring {
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		bool valid;
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		/* Software tracked state */
		bool waiting;
		int hangcheck_score;
		enum intel_ring_hangcheck_action hangcheck_action;
		int num_requests;

		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

		u32 semaphore_seqno[I915_NUM_RINGS - 1];

		/* Register state */
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		u32 start;
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		u32 tail;
		u32 head;
		u32 ctl;
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 instdone;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
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		u64 acthd;
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		u32 fault_reg;
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		u64 faddr;
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		u32 rc_psmi; /* sleep state */
		u32 semaphore_mboxes[I915_NUM_RINGS - 1];

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		struct drm_i915_error_object {
			int page_count;
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			u64 gtt_offset;
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			u32 *pages[0];
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		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
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		struct drm_i915_error_request {
			long jiffies;
			u32 seqno;
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			u32 tail;
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		} *requests;
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		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;
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		pid_t pid;
		char comm[TASK_COMM_LEN];
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	} ring[I915_NUM_RINGS];
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	struct drm_i915_error_buffer {
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		u32 size;
582
		u32 name;
583
		u32 rseqno[I915_NUM_RINGS], wseqno;
584
		u64 gtt_offset;
585 586
		u32 read_domains;
		u32 write_domain;
587
		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
588 589 590 591
		s32 pinned:2;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
592
		u32 userptr:1;
593
		s32 ring:4;
594
		u32 cache_level:3;
595
	} **active_bo, **pinned_bo;
596

597
	u32 *active_bo_count, *pinned_bo_count;
598
	u32 vm_count;
599 600
};

601
struct intel_connector;
602
struct intel_encoder;
603
struct intel_crtc_state;
604
struct intel_initial_plane_config;
605
struct intel_crtc;
606 607
struct intel_limit;
struct dpll;
608

609 610 611
struct drm_i915_display_funcs {
	int (*get_display_clock_speed)(struct drm_device *dev);
	int (*get_fifo_size)(struct drm_device *dev, int plane);
612 613 614 615 616 617 618 619 620 621 622 623 624 625
	/**
	 * find_dpll() - Find the best values for the PLL
	 * @limit: limits for the PLL
	 * @crtc: current CRTC
	 * @target: target frequency in kHz
	 * @refclk: reference clock frequency in kHz
	 * @match_clock: if provided, @best_clock P divider must
	 *               match the P divider from @match_clock
	 *               used for LVDS downclocking
	 * @best_clock: best PLL values found
	 *
	 * Returns true on success, false on failure.
	 */
	bool (*find_dpll)(const struct intel_limit *limit,
626
			  struct intel_crtc_state *crtc_state,
627 628 629
			  int target, int refclk,
			  struct dpll *match_clock,
			  struct dpll *best_clock);
630
	void (*update_wm)(struct drm_crtc *crtc);
631 632
	void (*update_sprite_wm)(struct drm_plane *plane,
				 struct drm_crtc *crtc,
633 634
				 uint32_t sprite_width, uint32_t sprite_height,
				 int pixel_size, bool enable, bool scaled);
635 636
	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
	void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
637 638 639
	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
640
				struct intel_crtc_state *);
641 642
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
643 644
	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
645 646
	void (*crtc_enable)(struct drm_crtc *crtc);
	void (*crtc_disable)(struct drm_crtc *crtc);
647 648
	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
649
				   const struct drm_display_mode *adjusted_mode);
650
	void (*audio_codec_disable)(struct intel_encoder *encoder);
651
	void (*fdi_link_train)(struct drm_crtc *crtc);
652
	void (*init_clock_gating)(struct drm_device *dev);
653 654
	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
655
			  struct drm_i915_gem_object *obj,
656
			  struct drm_i915_gem_request *req,
657
			  uint32_t flags);
658 659 660
	void (*update_primary_plane)(struct drm_crtc *crtc,
				     struct drm_framebuffer *fb,
				     int x, int y);
661
	void (*hpd_irq_setup)(struct drm_device *dev);
662 663 664 665 666
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
667

668
	int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
669 670 671 672 673
	uint32_t (*get_backlight)(struct intel_connector *connector);
	void (*set_backlight)(struct intel_connector *connector,
			      uint32_t level);
	void (*disable_backlight)(struct intel_connector *connector);
	void (*enable_backlight)(struct intel_connector *connector);
674 675
	uint32_t (*backlight_hz_to_pwm)(struct intel_connector *connector,
					uint32_t hz);
676 677
};

678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694
enum forcewake_domain_id {
	FW_DOMAIN_ID_RENDER = 0,
	FW_DOMAIN_ID_BLITTER,
	FW_DOMAIN_ID_MEDIA,

	FW_DOMAIN_ID_COUNT
};

enum forcewake_domains {
	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
	FORCEWAKE_MEDIA	= (1 << FW_DOMAIN_ID_MEDIA),
	FORCEWAKE_ALL = (FORCEWAKE_RENDER |
			 FORCEWAKE_BLITTER |
			 FORCEWAKE_MEDIA)
};

695
struct intel_uncore_funcs {
696
	void (*force_wake_get)(struct drm_i915_private *dev_priv,
697
							enum forcewake_domains domains);
698
	void (*force_wake_put)(struct drm_i915_private *dev_priv,
699
							enum forcewake_domains domains);
700 701 702 703 704 705 706 707 708 709 710 711 712 713

	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);

	void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
				uint8_t val, bool trace);
	void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
				uint16_t val, bool trace);
	void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
				uint32_t val, bool trace);
	void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
				uint64_t val, bool trace);
714 715
};

716 717 718 719 720 721
struct intel_uncore {
	spinlock_t lock; /** lock is also taken in irq contexts. */

	struct intel_uncore_funcs funcs;

	unsigned fifo_count;
722
	enum forcewake_domains fw_domains;
723 724 725

	struct intel_uncore_forcewake_domain {
		struct drm_i915_private *i915;
726
		enum forcewake_domain_id id;
727 728
		unsigned wake_count;
		struct timer_list timer;
729 730 731 732 733 734
		u32 reg_set;
		u32 val_set;
		u32 val_clear;
		u32 reg_ack;
		u32 reg_post;
		u32 val_reset;
735 736 737 738 739 740 741 742 743 744 745 746
	} fw_domain[FW_DOMAIN_ID_COUNT];
};

/* Iterate over initialised fw domains */
#define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
	for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
	     (i__) < FW_DOMAIN_ID_COUNT; \
	     (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
		if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))

#define for_each_fw_domain(domain__, dev_priv__, i__) \
	for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
747

748 749 750 751 752 753
enum csr_state {
	FW_UNINITIALIZED = 0,
	FW_LOADED,
	FW_FAILED
};

754 755
struct intel_csr {
	const char *fw_path;
756
	uint32_t *dmc_payload;
757 758 759 760
	uint32_t dmc_fw_size;
	uint32_t mmio_count;
	uint32_t mmioaddr[8];
	uint32_t mmiodata[8];
761
	enum csr_state state;
762 763
};

764 765 766 767 768 769 770 771 772 773 774 775 776 777
#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
	func(is_mobile) sep \
	func(is_i85x) sep \
	func(is_i915g) sep \
	func(is_i945gm) sep \
	func(is_g33) sep \
	func(need_gfx_hws) sep \
	func(is_g4x) sep \
	func(is_pineview) sep \
	func(is_broadwater) sep \
	func(is_crestline) sep \
	func(is_ivybridge) sep \
	func(is_valleyview) sep \
	func(is_haswell) sep \
778
	func(is_skylake) sep \
779
	func(is_preliminary) sep \
780 781 782 783 784 785 786
	func(has_fbc) sep \
	func(has_pipe_cxsr) sep \
	func(has_hotplug) sep \
	func(cursor_needs_physical) sep \
	func(has_overlay) sep \
	func(overlay_needs_physical) sep \
	func(supports_tv) sep \
787
	func(has_llc) sep \
788 789
	func(has_ddi) sep \
	func(has_fpga_dbg)
D
Daniel Vetter 已提交
790

791 792
#define DEFINE_FLAG(name) u8 name:1
#define SEP_SEMICOLON ;
D
Daniel Vetter 已提交
793

794
struct intel_device_info {
795
	u32 display_mmio_offset;
796
	u16 device_id;
797
	u8 num_pipes:3;
798
	u8 num_sprites[I915_MAX_PIPES];
799
	u8 gen;
800
	u8 ring_mask; /* Rings supported by the HW */
801
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
802 803 804 805
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
806
	int cursor_offsets[I915_MAX_PIPES];
807 808 809 810 811 812 813

	/* Slice/subslice/EU info */
	u8 slice_total;
	u8 subslice_total;
	u8 subslice_per_slice;
	u8 eu_total;
	u8 eu_per_subslice;
814 815
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
816 817 818
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
819 820
};

821 822 823
#undef DEFINE_FLAG
#undef SEP_SEMICOLON

824 825
enum i915_cache_level {
	I915_CACHE_NONE = 0,
826 827 828 829 830
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
831
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
832 833
};

834 835 836 837 838 839
struct i915_ctx_hang_stats {
	/* This context had batch pending when hang was declared */
	unsigned batch_pending;

	/* This context had batch active when hang was declared */
	unsigned batch_active;
840 841 842 843

	/* Time when this context was last blamed for a GPU reset */
	unsigned long guilty_ts;

844 845 846 847 848
	/* If the contexts causes a second GPU hang within this time,
	 * it is permanently banned from submitting any more work.
	 */
	unsigned long ban_period_seconds;

849 850
	/* This context is banned to submit more work */
	bool banned;
851
};
852 853

/* This must match up with the value previously used for execbuf2.rsvd1. */
854
#define DEFAULT_CONTEXT_HANDLE 0
855 856

#define CONTEXT_NO_ZEROMAP (1<<0)
857 858 859 860 861
/**
 * struct intel_context - as the name implies, represents a context.
 * @ref: reference count.
 * @user_handle: userspace tracking identity for this context.
 * @remap_slice: l3 row remapping information.
862 863
 * @flags: context specific flags:
 *         CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
864 865 866 867
 * @file_priv: filp associated with this context (NULL for global default
 *	       context).
 * @hang_stats: information about the role of this context in possible GPU
 *		hangs.
868
 * @ppgtt: virtual memory space used by this context.
869 870 871 872 873 874 875
 * @legacy_hw_ctx: render context backing object and whether it is correctly
 *                initialized (legacy ring submission mechanism only).
 * @link: link in the global list of contexts.
 *
 * Contexts are memory images used by the hardware to store copies of their
 * internal state.
 */
876
struct intel_context {
877
	struct kref ref;
878
	int user_handle;
879
	uint8_t remap_slice;
880
	struct drm_i915_private *i915;
881
	int flags;
882
	struct drm_i915_file_private *file_priv;
883
	struct i915_ctx_hang_stats hang_stats;
884
	struct i915_hw_ppgtt *ppgtt;
885

886
	/* Legacy ring buffer submission */
887 888 889 890 891
	struct {
		struct drm_i915_gem_object *rcs_state;
		bool initialized;
	} legacy_hw_ctx;

892 893 894
	/* Execlists */
	struct {
		struct drm_i915_gem_object *state;
895
		struct intel_ringbuffer *ringbuf;
896
		int pin_count;
897 898
	} engine[I915_NUM_RINGS];

899
	struct list_head link;
900 901
};

902 903 904 905 906
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
907
	ORIGIN_DIRTYFB,
908 909
};

910
struct i915_fbc {
P
Paulo Zanoni 已提交
911 912 913
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
914
	unsigned long uncompressed_size;
B
Ben Widawsky 已提交
915
	unsigned threshold;
916
	unsigned int fb_id;
917 918
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
919
	struct intel_crtc *crtc;
920 921
	int y;

922
	struct drm_mm_node compressed_fb;
923 924
	struct drm_mm_node *compressed_llb;

925 926
	bool false_color;

927 928 929 930
	/* Tracks whether the HW is actually enabled, not whether the feature is
	 * possible. */
	bool enabled;

931 932
	struct intel_fbc_work {
		struct delayed_work work;
933
		struct intel_crtc *crtc;
934 935 936
		struct drm_framebuffer *fb;
	} *fbc_work;

937 938 939
	enum no_fbc_reason {
		FBC_OK, /* FBC is enabled */
		FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
940 941 942 943 944 945 946 947 948
		FBC_NO_OUTPUT, /* no outputs enabled to compress */
		FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
		FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
		FBC_MODE_TOO_LARGE, /* mode too large for compression */
		FBC_BAD_PLANE, /* fbc not supported on plane */
		FBC_NOT_TILED, /* buffer not tiled */
		FBC_MULTIPLE_PIPES, /* more than one pipe active */
		FBC_MODULE_PARAM,
		FBC_CHIP_DEFAULT, /* disabled by default on this chip */
949
		FBC_ROTATION, /* rotation is not supported */
950
		FBC_IN_DBG_MASTER, /* kernel debugger is active */
951
		FBC_BAD_STRIDE, /* stride is not supported */
952
		FBC_PIXEL_RATE, /* pixel rate is too big */
953
		FBC_PIXEL_FORMAT /* pixel format is invalid */
954
	} no_fbc_reason;
955

956
	bool (*fbc_enabled)(struct drm_i915_private *dev_priv);
957
	void (*enable_fbc)(struct intel_crtc *crtc);
958
	void (*disable_fbc)(struct drm_i915_private *dev_priv);
959 960
};

961 962 963 964 965 966 967 968 969 970 971 972 973 974 975
/**
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
976 977
};

978
struct intel_dp;
979 980 981 982 983 984 985 986 987
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
988
struct i915_psr {
989
	struct mutex lock;
R
Rodrigo Vivi 已提交
990 991
	bool sink_support;
	bool source_ok;
992
	struct intel_dp *enabled;
993 994
	bool active;
	struct delayed_work work;
995
	unsigned busy_frontbuffer_bits;
996 997
	bool psr2_support;
	bool aux_frame_sync;
998
};
999

1000
enum intel_pch {
1001
	PCH_NONE = 0,	/* No PCH present */
1002 1003
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
1004
	PCH_LPT,	/* Lynxpoint PCH */
1005
	PCH_SPT,        /* Sunrisepoint PCH */
B
Ben Widawsky 已提交
1006
	PCH_NOP,
1007 1008
};

1009 1010 1011 1012 1013
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

1014
#define QUIRK_PIPEA_FORCE (1<<0)
1015
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1016
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1017
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1018
#define QUIRK_PIPEB_FORCE (1<<4)
1019
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1020

1021
struct intel_fbdev;
1022
struct intel_fbc_work;
1023

1024 1025
struct intel_gmbus {
	struct i2c_adapter adapter;
1026
	u32 force_bit;
1027
	u32 reg0;
1028
	u32 gpio_reg;
1029
	struct i2c_algo_bit_data bit_algo;
1030 1031 1032
	struct drm_i915_private *dev_priv;
};

1033
struct i915_suspend_saved_registers {
1034
	u32 saveDSPARB;
J
Jesse Barnes 已提交
1035
	u32 saveLVDS;
1036 1037
	u32 savePP_ON_DELAYS;
	u32 savePP_OFF_DELAYS;
J
Jesse Barnes 已提交
1038 1039 1040
	u32 savePP_ON;
	u32 savePP_OFF;
	u32 savePP_CONTROL;
1041
	u32 savePP_DIVISOR;
J
Jesse Barnes 已提交
1042
	u32 saveFBC_CONTROL;
1043 1044
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
J
Jesse Barnes 已提交
1045 1046 1047
	u32 saveSWF0[16];
	u32 saveSWF1[16];
	u32 saveSWF2[3];
1048
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1049
	u32 savePCH_PORT_HOTPLUG;
1050
	u16 saveGCDGMBUS;
1051
};
1052

1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
1111
	u32 pcbr;
1112 1113 1114
	u32 clock_gate_dis2;
};

1115 1116 1117 1118
struct intel_rps_ei {
	u32 cz_clock;
	u32 render_c0;
	u32 media_c0;
1119 1120
};

1121
struct intel_gen6_power_mgmt {
I
Imre Deak 已提交
1122 1123 1124 1125
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1126
	struct work_struct work;
I
Imre Deak 已提交
1127
	bool interrupts_enabled;
1128
	u32 pm_iir;
1129

1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
1145
	u8 idle_freq;		/* Frequency to request when we are idle */
1146 1147 1148
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1149
	u32 cz_freq;
1150

1151 1152 1153
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

1154 1155 1156
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1157 1158 1159 1160
	spinlock_t client_lock;
	struct list_head clients;
	bool client_boost;

1161
	bool enabled;
1162
	struct delayed_work delayed_resume_work;
1163
	unsigned boosts;
1164

1165
	struct intel_rps_client semaphores, mmioflips;
1166

1167 1168 1169
	/* manual wa residency calculations */
	struct intel_rps_ei up_ei, down_ei;

1170 1171
	/*
	 * Protects RPS/RC6 register access and PCU communication.
1172 1173 1174
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
1175 1176
	 */
	struct mutex hw_lock;
1177 1178
};

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1179 1180 1181
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1193
	u64 last_time2;
1194 1195 1196 1197 1198 1199 1200
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1231 1232
/* Power well structure for haswell */
struct i915_power_well {
1233
	const char *name;
1234
	bool always_on;
1235 1236
	/* power well enable/disable usage count */
	int count;
1237 1238
	/* cached hw enabled state */
	bool hw_enabled;
1239
	unsigned long domains;
1240
	unsigned long data;
1241
	const struct i915_power_well_ops *ops;
1242 1243
};

1244
struct i915_power_domains {
1245 1246 1247 1248 1249
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1250
	bool initializing;
1251
	int power_well_count;
1252

1253
	struct mutex lock;
1254
	int domain_use_count[POWER_DOMAIN_NUM];
1255
	struct i915_power_well *power_wells;
1256 1257
};

1258
#define MAX_L3_SLICES 2
1259
struct intel_l3_parity {
1260
	u32 *remap_info[MAX_L3_SLICES];
1261
	struct work_struct error_work;
1262
	int which_slice;
1263 1264
};

1265 1266 1267
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1268 1269 1270 1271
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
	 * are idle and not used by the GPU) but still have
	 * (presumably uncached) pages still attached.
	 */
	struct list_head unbound_list;

	/** Usable portion of the GTT for GEM */
	unsigned long stolen_base; /* limited to low memory (32-bit) */

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1288
	struct notifier_block oom_notifier;
1289
	struct shrinker shrinker;
1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303
	bool shrinker_no_lock_stealing;

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

	/**
	 * We leave the user IRQ off as much as possible,
	 * but this means that requests will finish and never
	 * be retired once the system goes idle. Set a timer to
	 * fire periodically while the ring is running. When it
	 * fires, go retire requests.
	 */
	struct delayed_work retire_work;

1304 1305 1306 1307 1308 1309 1310 1311 1312
	/**
	 * When we detect an idle GPU, we want to turn on
	 * powersaving features. So once we see that there
	 * are no more requests outstanding and no more
	 * arrive within a small period of time, we fire
	 * off the idle_work.
	 */
	struct delayed_work idle_work;

1313 1314 1315 1316 1317 1318
	/**
	 * Are we in a non-interruptible section of code like
	 * modesetting?
	 */
	bool interruptible;

1319 1320 1321 1322 1323 1324 1325 1326
	/**
	 * Is the GPU currently considered idle, or busy executing userspace
	 * requests?  Whilst idle, we attempt to power down the hardware and
	 * display clocks. In order to reduce the effect on performance, there
	 * is a slight delay before we do so.
	 */
	bool busy;

1327 1328 1329
	/* the indicator for dispatch video commands on two BSD rings */
	int bsd_ring_dispatch_index;

1330 1331 1332 1333 1334 1335
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1336
	spinlock_t object_stat_lock;
1337 1338 1339 1340
	size_t object_memory;
	u32 object_count;
};

1341
struct drm_i915_error_state_buf {
1342
	struct drm_i915_private *i915;
1343 1344 1345 1346 1347 1348 1349 1350
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1351 1352 1353 1354 1355
struct i915_error_state_file_priv {
	struct drm_device *dev;
	struct drm_i915_error_state *error;
};

1356 1357 1358 1359
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1360 1361 1362
	/* Hang gpu twice in this window and your context gets banned */
#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)

1363 1364
	struct workqueue_struct *hangcheck_wq;
	struct delayed_work hangcheck_work;
1365 1366 1367 1368 1369

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
	struct drm_i915_error_state *first_error;
1370 1371 1372

	unsigned long missed_irq_rings;

1373
	/**
M
Mika Kuoppala 已提交
1374
	 * State variable controlling the reset flow and count
1375
	 *
M
Mika Kuoppala 已提交
1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388
	 * This is a counter which gets incremented when reset is triggered,
	 * and again when reset has been handled. So odd values (lowest bit set)
	 * means that reset is in progress and even values that
	 * (reset_counter >> 1):th reset was successfully completed.
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1389 1390 1391 1392
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1393 1394 1395 1396
	 */
	atomic_t reset_counter;

#define I915_RESET_IN_PROGRESS_FLAG	1
M
Mika Kuoppala 已提交
1397
#define I915_WEDGED			(1 << 31)
1398 1399 1400 1401 1402 1403

	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1404

1405 1406 1407 1408 1409 1410
	/* Userspace knobs for gpu hang simulation;
	 * combines both a ring mask, and extra flags
	 */
	u32 stop_rings;
#define I915_STOP_RING_ALLOW_BAN       (1 << 31)
#define I915_STOP_RING_ALLOW_WARN      (1 << 30)
1411 1412 1413

	/* For missed irq/seqno simulation. */
	unsigned int test_irq_rings;
1414 1415 1416

	/* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset   */
	bool reload_in_reset;
1417 1418
};

1419 1420 1421 1422 1423 1424
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1425 1426 1427 1428 1429
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

X
Xiong Zhang 已提交
1430 1431 1432 1433
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1434
struct ddi_vbt_port_info {
1435 1436 1437 1438 1439 1440
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1441
	uint8_t hdmi_level_shift;
1442 1443 1444 1445

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1446 1447

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1448
	uint8_t alternate_ddc_pin;
1449 1450 1451

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1452 1453
};

R
Rodrigo Vivi 已提交
1454 1455 1456 1457 1458
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1459 1460
};

1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1473
	unsigned int has_mipi:1;
1474 1475 1476
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1477 1478
	enum drrs_support_type drrs_type;

1479 1480 1481 1482 1483 1484 1485 1486 1487 1488
	/* eDP */
	int edp_rate;
	int edp_lanes;
	int edp_preemphasis;
	int edp_vswing;
	bool edp_initialized;
	bool edp_support;
	int edp_bpp;
	struct edp_power_seq edp_pps;

R
Rodrigo Vivi 已提交
1489 1490 1491 1492 1493 1494 1495 1496 1497
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1498 1499
	struct {
		u16 pwm_freq_hz;
1500
		bool present;
1501
		bool active_low_pwm;
1502
		u8 min_brightness;	/* min_brightness/255 of max */
1503 1504
	} backlight;

1505 1506
	/* MIPI DSI */
	struct {
1507
		u16 port;
1508
		u16 panel_id;
1509 1510 1511 1512 1513 1514
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
		u8 *sequence[MIPI_SEQ_MAX];
1515 1516
	} dsi;

1517 1518 1519
	int crt_ddc_pin;

	int child_dev_num;
1520
	union child_device_config *child_dev;
1521 1522

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1523 1524
};

1525 1526 1527 1528 1529
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1530 1531 1532 1533 1534 1535 1536 1537
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1538
struct ilk_wm_values {
1539 1540 1541 1542 1543 1544 1545 1546
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1547 1548 1549 1550 1551
struct vlv_pipe_wm {
	uint16_t primary;
	uint16_t sprite[2];
	uint8_t cursor;
};
1552

1553 1554 1555 1556
struct vlv_sr_wm {
	uint16_t plane;
	uint8_t cursor;
};
1557

1558 1559 1560
struct vlv_wm_values {
	struct vlv_pipe_wm pipe[3];
	struct vlv_sr_wm sr;
1561 1562 1563 1564 1565
	struct {
		uint8_t cursor;
		uint8_t sprite[2];
		uint8_t primary;
	} ddl[3];
1566 1567
	uint8_t level;
	bool cxsr;
1568 1569
};

1570
struct skl_ddb_entry {
1571
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1572 1573 1574 1575
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1576
	return entry->end - entry->start;
1577 1578
}

1579 1580 1581 1582 1583 1584 1585 1586 1587
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1588
struct skl_ddb_allocation {
1589
	struct skl_ddb_entry pipe[I915_MAX_PIPES];
1590 1591
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* y-plane */
1592 1593 1594
	struct skl_ddb_entry cursor[I915_MAX_PIPES];
};

1595 1596
struct skl_wm_values {
	bool dirty[I915_MAX_PIPES];
1597
	struct skl_ddb_allocation ddb;
1598 1599 1600 1601 1602 1603 1604 1605 1606
	uint32_t wm_linetime[I915_MAX_PIPES];
	uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
	uint32_t cursor[I915_MAX_PIPES][8];
	uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
	uint32_t cursor_trans[I915_MAX_PIPES];
};

struct skl_wm_level {
	bool plane_en[I915_MAX_PLANES];
1607
	bool cursor_en;
1608 1609 1610 1611 1612 1613
	uint16_t plane_res_b[I915_MAX_PLANES];
	uint8_t plane_res_l[I915_MAX_PLANES];
	uint16_t cursor_res_b;
	uint8_t cursor_res_l;
};

1614
/*
1615 1616 1617 1618
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1619
 *
1620 1621 1622
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1623
 *
1624 1625
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1626
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1627
 * it can be changed with the standard runtime PM files from sysfs.
1628 1629 1630 1631 1632
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1633
 * case it happens.
1634
 *
1635
 * For more, read the Documentation/power/runtime_pm.txt.
1636
 */
1637 1638
struct i915_runtime_pm {
	bool suspended;
1639
	bool irqs_enabled;
1640 1641
};

1642 1643 1644 1645 1646
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1647
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1648 1649 1650 1651 1652
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1653
	INTEL_PIPE_CRC_SOURCE_AUTO,
1654 1655 1656
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1657
struct intel_pipe_crc_entry {
1658
	uint32_t frame;
1659 1660 1661
	uint32_t crc[5];
};

1662
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1663
struct intel_pipe_crc {
1664 1665
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1666
	struct intel_pipe_crc_entry *entries;
1667
	enum intel_pipe_crc_source source;
1668
	int head, tail;
1669
	wait_queue_head_t wq;
1670 1671
};

1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682
struct i915_frontbuffer_tracking {
	struct mutex lock;

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696
struct i915_wa_reg {
	u32 addr;
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

#define I915_MAX_WA_REGS 16

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
};

1697 1698 1699 1700
struct i915_virtual_gpu {
	bool active;
};

1701 1702 1703 1704 1705
struct i915_execbuffer_params {
	struct drm_device               *dev;
	struct drm_file                 *file;
	uint32_t                        dispatch_flags;
	uint32_t                        args_batch_start_offset;
1706
	uint64_t                        batch_obj_vm_offset;
1707 1708 1709
	struct intel_engine_cs          *ring;
	struct drm_i915_gem_object      *batch_obj;
	struct intel_context            *ctx;
1710
	struct drm_i915_gem_request     *request;
1711 1712
};

1713
struct drm_i915_private {
1714
	struct drm_device *dev;
1715
	struct kmem_cache *objects;
1716
	struct kmem_cache *vmas;
1717
	struct kmem_cache *requests;
1718

1719
	const struct intel_device_info info;
1720 1721 1722 1723 1724

	int relative_constants_mode;

	void __iomem *regs;

1725
	struct intel_uncore uncore;
1726

1727 1728
	struct i915_virtual_gpu vgpu;

1729 1730
	struct intel_guc guc;

1731 1732 1733 1734 1735
	struct intel_csr csr;

	/* Display CSR-related protection */
	struct mutex csr_lock;

1736
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1737

1738 1739 1740 1741 1742 1743 1744 1745 1746
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

1747 1748 1749
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

1750 1751
	wait_queue_head_t gmbus_wait_queue;

1752
	struct pci_dev *bridge_dev;
1753
	struct intel_engine_cs ring[I915_NUM_RINGS];
1754
	struct drm_i915_gem_object *semaphore_obj;
1755
	uint32_t last_seqno, next_seqno;
1756

1757
	struct drm_dma_handle *status_page_dmah;
1758 1759 1760 1761 1762
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

1763 1764 1765
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

1766 1767
	bool display_irqs_enabled;

1768 1769 1770
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
1771 1772
	/* Sideband mailbox protection */
	struct mutex sb_lock;
1773 1774

	/** Cached value of IMR to avoid reads in updating the bitfield */
1775 1776 1777 1778
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
1779
	u32 gt_irq_mask;
1780
	u32 pm_irq_mask;
1781
	u32 pm_rps_events;
1782
	u32 pipestat_irq_mask[I915_MAX_PIPES];
1783

1784
	struct i915_hotplug hotplug;
1785
	struct i915_fbc fbc;
1786
	struct i915_drrs drrs;
1787
	struct intel_opregion opregion;
1788
	struct intel_vbt_data vbt;
1789

1790 1791
	bool preserve_bios_swizzle;

1792 1793 1794
	/* overlay */
	struct intel_overlay *overlay;

1795
	/* backlight registers and fields in struct intel_panel */
1796
	struct mutex backlight_lock;
1797

1798 1799 1800
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
1801 1802 1803
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

1804 1805 1806 1807 1808
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
1809
	unsigned int skl_boot_cdclk;
1810
	unsigned int cdclk_freq, max_cdclk_freq;
M
Mika Kahola 已提交
1811
	unsigned int max_dotclk_freq;
1812
	unsigned int hpll_freq;
1813

1814 1815 1816 1817 1818 1819 1820
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
1821 1822 1823 1824 1825 1826 1827
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
1828
	unsigned short pch_id;
1829 1830 1831

	unsigned long quirks;

1832 1833
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
1834

1835
	struct list_head vm_list; /* Global list of all address spaces */
1836
	struct i915_gtt gtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
1837

1838
	struct i915_gem_mm mm;
1839 1840
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
1841 1842 1843

	/* Kernel Modesetting */

1844
	struct sdvo_device_mapping sdvo_mappings[2];
1845

1846 1847
	struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1848 1849
	wait_queue_head_t pending_flip_queue;

1850 1851 1852 1853
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

D
Daniel Vetter 已提交
1854 1855
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1856
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1857

1858
	struct i915_workarounds workarounds;
1859

1860 1861
	/* Reclocking support */
	bool render_reclock_avail;
1862 1863 1864

	struct i915_frontbuffer_tracking fb_tracking;

1865
	u16 orig_clock;
1866

1867
	bool mchbar_need_disable;
1868

1869 1870
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
1871 1872 1873
	/* Cannot be determined by PCIID. You must always read a register. */
	size_t ellc_size;

1874
	/* gen6+ rps state */
1875
	struct intel_gen6_power_mgmt rps;
1876

1877 1878
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
1879
	struct intel_ilk_power_mgmt ips;
1880

1881
	struct i915_power_domains power_domains;
1882

R
Rodrigo Vivi 已提交
1883
	struct i915_psr psr;
1884

1885
	struct i915_gpu_error gpu_error;
1886

1887 1888
	struct drm_i915_gem_object *vlv_pctx;

1889
#ifdef CONFIG_DRM_FBDEV_EMULATION
1890 1891
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
1892
	struct work_struct fbdev_suspend_work;
1893
#endif
1894 1895

	struct drm_property *broadcast_rgb_property;
1896
	struct drm_property *force_audio_property;
1897

I
Imre Deak 已提交
1898
	/* hda/i915 audio component */
1899
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
1900 1901
	bool audio_component_registered;

1902
	uint32_t hw_context_size;
1903
	struct list_head context_list;
1904

1905
	u32 fdi_rx_config;
1906

1907 1908
	u32 chv_phy_control;

1909
	u32 suspend_count;
1910
	struct i915_suspend_saved_registers regfile;
1911
	struct vlv_s0ix_state vlv_s0ix_state;
1912

1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
1925 1926 1927 1928 1929 1930
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
1931

1932 1933 1934 1935 1936 1937 1938
		/*
		 * The skl_wm_values structure is a bit too big for stack
		 * allocation, so we keep the staging struct where we store
		 * intermediate results here instead.
		 */
		struct skl_wm_values skl_results;

1939
		/* current hardware state */
1940 1941 1942
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
1943
			struct vlv_wm_values vlv;
1944
		};
1945 1946

		uint8_t max_level;
1947 1948
	} wm;

1949 1950
	struct i915_runtime_pm pm;

1951 1952
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
1953
		int (*execbuf_submit)(struct i915_execbuffer_params *params,
1954
				      struct drm_i915_gem_execbuffer2 *args,
1955
				      struct list_head *vmas);
1956 1957 1958 1959 1960
		int (*init_rings)(struct drm_device *dev);
		void (*cleanup_ring)(struct intel_engine_cs *ring);
		void (*stop_ring)(struct intel_engine_cs *ring);
	} gt;

1961 1962
	bool edp_low_vswing;

1963 1964 1965 1966
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
1967
};
L
Linus Torvalds 已提交
1968

1969 1970 1971 1972 1973
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
	return dev->dev_private;
}

I
Imre Deak 已提交
1974 1975 1976 1977 1978
static inline struct drm_i915_private *dev_to_i915(struct device *dev)
{
	return to_i915(dev_get_drvdata(dev));
}

1979 1980 1981 1982 1983
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

1984 1985 1986 1987 1988
/* Iterate over initialised rings */
#define for_each_ring(ring__, dev_priv__, i__) \
	for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
		if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))

1989 1990 1991 1992 1993 1994 1995
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

1996
#define I915_GTT_OFFSET_NONE ((u32)-1)
1997

1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013
struct drm_i915_gem_object_ops {
	/* Interface between the GEM object and its backing storage.
	 * get_pages() is called once prior to the use of the associated set
	 * of pages before to binding them into the GTT, and put_pages() is
	 * called after we no longer need them. As we expect there to be
	 * associated cost with migrating pages between the backing storage
	 * and making them available for the GPU (e.g. clflush), we may hold
	 * onto the pages after they are no longer referenced by the GPU
	 * in case they may be used again shortly (for example migrating the
	 * pages to a different memory domain within the GTT). put_pages()
	 * will therefore most likely be called when the object itself is
	 * being released or under memory pressure (where we attempt to
	 * reap pages for the shrinker).
	 */
	int (*get_pages)(struct drm_i915_gem_object *);
	void (*put_pages)(struct drm_i915_gem_object *);
2014 2015
	int (*dmabuf_export)(struct drm_i915_gem_object *);
	void (*release)(struct drm_i915_gem_object *);
2016 2017
};

2018 2019
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2020
 * considered to be the frontbuffer for the given plane interface-wise. This
2021 2022 2023 2024 2025
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2026 2027
#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2028 2029 2030 2031 2032
#define INTEL_FRONTBUFFER_BITS \
	(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2033 2034 2035
	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2036
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2037
	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2038
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2039
	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2040

2041
struct drm_i915_gem_object {
2042
	struct drm_gem_object base;
2043

2044 2045
	const struct drm_i915_gem_object_ops *ops;

B
Ben Widawsky 已提交
2046 2047 2048
	/** List of VMAs backed by this object */
	struct list_head vma_list;

2049 2050
	/** Stolen memory for this object, instead of being backed by shmem. */
	struct drm_mm_node *stolen;
2051
	struct list_head global_list;
2052

2053
	struct list_head ring_list[I915_NUM_RINGS];
2054 2055
	/** Used in execbuf to temporarily hold a ref */
	struct list_head obj_exec_link;
2056

2057
	struct list_head batch_pool_link;
2058

2059
	/**
2060 2061 2062
	 * This is set if the object is on the active lists (has pending
	 * rendering and so a non-zero seqno), and is not set if it i s on
	 * inactive (ready to be unbound) list.
2063
	 */
2064
	unsigned int active:I915_NUM_RINGS;
2065 2066 2067 2068 2069

	/**
	 * This is set if the object has been written to since last bound
	 * to the GTT
	 */
2070
	unsigned int dirty:1;
2071 2072 2073 2074 2075 2076

	/**
	 * Fence register bits (if any) for this object.  Will be set
	 * as needed when mapped into the GTT.
	 * Protected by dev->struct_mutex.
	 */
2077
	signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2078 2079 2080 2081

	/**
	 * Advice: are the backing pages purgeable?
	 */
2082
	unsigned int madv:2;
2083 2084 2085 2086

	/**
	 * Current tiling mode for the object.
	 */
2087
	unsigned int tiling_mode:2;
2088 2089 2090 2091 2092 2093 2094 2095
	/**
	 * Whether the tiling parameters for the currently associated fence
	 * register have changed. Note that for the purposes of tracking
	 * tiling changes we also treat the unfenced register, the register
	 * slot that the object occupies whilst it executes a fenced
	 * command (such as BLT on gen2/3), as a "fence".
	 */
	unsigned int fence_dirty:1;
2096

2097 2098 2099 2100
	/**
	 * Is the object at the current location in the gtt mappable and
	 * fenceable? Used to avoid costly recalculations.
	 */
2101
	unsigned int map_and_fenceable:1;
2102

2103 2104 2105 2106 2107
	/**
	 * Whether the current gtt mapping needs to be mappable (and isn't just
	 * mappable by accident). Track pin and fault separate for a more
	 * accurate mappable working set.
	 */
2108
	unsigned int fault_mappable:1;
2109

2110 2111 2112 2113 2114
	/*
	 * Is the object to be mapped as read-only to the GPU
	 * Only honoured if hardware has relevant pte bit
	 */
	unsigned long gt_ro:1;
2115
	unsigned int cache_level:3;
2116
	unsigned int cache_dirty:1;
2117

2118 2119
	unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;

2120 2121
	unsigned int pin_display;

2122
	struct sg_table *pages;
2123
	int pages_pin_count;
2124 2125 2126 2127
	struct get_page {
		struct scatterlist *sg;
		int last;
	} get_page;
2128

2129
	/* prime dma-buf support */
2130 2131 2132
	void *dma_buf_vmapping;
	int vmapping_count;

2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143
	/** Breadcrumb of last rendering to the buffer.
	 * There can only be one writer, but we allow for multiple readers.
	 * If there is a writer that necessarily implies that all other
	 * read requests are complete - but we may only be lazily clearing
	 * the read requests. A read request is naturally the most recent
	 * request on a ring, so we may have two different write and read
	 * requests on one ring where the write request is older than the
	 * read request. This allows for the CPU to read from an active
	 * buffer by only waiting for the write to complete.
	 * */
	struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2144
	struct drm_i915_gem_request *last_write_req;
2145
	/** Breadcrumb of last fenced GPU access to the buffer. */
2146
	struct drm_i915_gem_request *last_fenced_req;
2147

2148
	/** Current tiling stride for the object, if it's tiled. */
2149
	uint32_t stride;
2150

2151 2152 2153
	/** References from framebuffers, locks out tiling changes. */
	unsigned long framebuffer_references;

2154
	/** Record of address bit 17 of each page at last unbind. */
2155
	unsigned long *bit_17;
2156

2157
	union {
2158 2159 2160
		/** for phy allocated objects */
		struct drm_dma_handle *phys_handle;

2161 2162 2163 2164 2165 2166
		struct i915_gem_userptr {
			uintptr_t ptr;
			unsigned read_only :1;
			unsigned workers :4;
#define I915_GEM_USERPTR_MAX_WORKERS 15

2167 2168
			struct i915_mm_struct *mm;
			struct i915_mmu_object *mmu_object;
2169 2170 2171 2172
			struct work_struct *work;
		} userptr;
	};
};
2173
#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2174

2175 2176 2177 2178
void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

2179 2180 2181 2182 2183 2184
/**
 * Request queue structure.
 *
 * The request queue allows us to note sequence numbers that have been emitted
 * and may be associated with active buffers to be retired.
 *
2185 2186 2187 2188
 * By keeping this list, we can avoid having to do questionable sequence
 * number comparisons on buffer last_read|write_seqno. It also allows an
 * emission time to be associated with the request for tracking how far ahead
 * of the GPU the submission is.
2189 2190 2191
 *
 * The requests are reference counted, so upon creation they should have an
 * initial reference taken using kref_init
2192 2193
 */
struct drm_i915_gem_request {
2194 2195
	struct kref ref;

2196
	/** On Which ring this request was generated */
2197
	struct drm_i915_private *i915;
2198
	struct intel_engine_cs *ring;
2199

2200 2201 2202
	/** GEM sequence number associated with this request. */
	uint32_t seqno;

2203 2204 2205
	/** Position in the ringbuffer of the start of the request */
	u32 head;

2206 2207 2208 2209 2210 2211 2212 2213
	/**
	 * Position in the ringbuffer of the start of the postfix.
	 * This is required to calculate the maximum available ringbuffer
	 * space without overwriting the postfix.
	 */
	 u32 postfix;

	/** Position in the ringbuffer of the end of the whole request */
2214 2215
	u32 tail;

2216
	/**
D
Dave Airlie 已提交
2217
	 * Context and ring buffer related to this request
2218 2219 2220 2221 2222 2223 2224 2225
	 * Contexts are refcounted, so when this request is associated with a
	 * context, we must increment the context's refcount, to guarantee that
	 * it persists while any request is linked to it. Requests themselves
	 * are also refcounted, so the request will only be freed when the last
	 * reference to it is dismissed, and the code in
	 * i915_gem_request_free() will then decrement the refcount on the
	 * context.
	 */
2226
	struct intel_context *ctx;
2227
	struct intel_ringbuffer *ringbuf;
2228

2229 2230
	/** Batch buffer related to this request if any (used for
	    error state dump only) */
2231 2232
	struct drm_i915_gem_object *batch_obj;

2233 2234 2235
	/** Time at which this request was emitted, in jiffies. */
	unsigned long emitted_jiffies;

2236
	/** global list entry for this request */
2237
	struct list_head list;
2238

2239
	struct drm_i915_file_private *file_priv;
2240 2241
	/** file_priv list entry for this request */
	struct list_head client_list;
2242

2243 2244 2245
	/** process identifier submitting this request */
	struct pid *pid;

2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264
	/**
	 * The ELSP only accepts two elements at a time, so we queue
	 * context/tail pairs on a given queue (ring->execlist_queue) until the
	 * hardware is available. The queue serves a double purpose: we also use
	 * it to keep track of the up to 2 contexts currently in the hardware
	 * (usually one in execution and the other queued up by the GPU): We
	 * only remove elements from the head of the queue when the hardware
	 * informs us that an element has been completed.
	 *
	 * All accesses to the queue are mediated by a spinlock
	 * (ring->execlist_lock).
	 */

	/** Execlist link in the submission queue.*/
	struct list_head execlist_link;

	/** Execlists no. of times this request has been sent to the ELSP */
	int elsp_submitted;

2265 2266
};

2267
int i915_gem_request_alloc(struct intel_engine_cs *ring,
2268 2269
			   struct intel_context *ctx,
			   struct drm_i915_gem_request **req_out);
2270
void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2271
void i915_gem_request_free(struct kref *req_ref);
2272 2273
int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
				   struct drm_file *file);
2274

2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286
static inline uint32_t
i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
{
	return req ? req->seqno : 0;
}

static inline struct intel_engine_cs *
i915_gem_request_get_ring(struct drm_i915_gem_request *req)
{
	return req ? req->ring : NULL;
}

2287
static inline struct drm_i915_gem_request *
2288 2289
i915_gem_request_reference(struct drm_i915_gem_request *req)
{
2290 2291 2292
	if (req)
		kref_get(&req->ref);
	return req;
2293 2294 2295 2296 2297
}

static inline void
i915_gem_request_unreference(struct drm_i915_gem_request *req)
{
2298
	WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2299 2300 2301
	kref_put(&req->ref, i915_gem_request_free);
}

2302 2303 2304
static inline void
i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
{
2305 2306 2307 2308
	struct drm_device *dev;

	if (!req)
		return;
2309

2310 2311
	dev = req->ring->dev;
	if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2312 2313 2314
		mutex_unlock(&dev->struct_mutex);
}

2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326
static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
					   struct drm_i915_gem_request *src)
{
	if (src)
		i915_gem_request_reference(src);

	if (*pdst)
		i915_gem_request_unreference(*pdst);

	*pdst = src;
}

2327 2328 2329 2330 2331 2332
/*
 * XXX: i915_gem_request_completed should be here but currently needs the
 * definition of i915_seqno_passed() which is below. It will be moved in
 * a later patch when the call to i915_seqno_passed() is obsoleted...
 */

2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384
/*
 * A command that requires special handling by the command parser.
 */
struct drm_i915_cmd_descriptor {
	/*
	 * Flags describing how the command parser processes the command.
	 *
	 * CMD_DESC_FIXED: The command has a fixed length if this is set,
	 *                 a length mask if not set
	 * CMD_DESC_SKIP: The command is allowed but does not follow the
	 *                standard length encoding for the opcode range in
	 *                which it falls
	 * CMD_DESC_REJECT: The command is never allowed
	 * CMD_DESC_REGISTER: The command should be checked against the
	 *                    register whitelist for the appropriate ring
	 * CMD_DESC_MASTER: The command is allowed if the submitting process
	 *                  is the DRM master
	 */
	u32 flags;
#define CMD_DESC_FIXED    (1<<0)
#define CMD_DESC_SKIP     (1<<1)
#define CMD_DESC_REJECT   (1<<2)
#define CMD_DESC_REGISTER (1<<3)
#define CMD_DESC_BITMASK  (1<<4)
#define CMD_DESC_MASTER   (1<<5)

	/*
	 * The command's unique identification bits and the bitmask to get them.
	 * This isn't strictly the opcode field as defined in the spec and may
	 * also include type, subtype, and/or subop fields.
	 */
	struct {
		u32 value;
		u32 mask;
	} cmd;

	/*
	 * The command's length. The command is either fixed length (i.e. does
	 * not include a length field) or has a length field mask. The flag
	 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
	 * a length mask. All command entries in a command table must include
	 * length information.
	 */
	union {
		u32 fixed;
		u32 mask;
	} length;

	/*
	 * Describes where to find a register address in the command to check
	 * against the ring's register whitelist. Only valid if flags has the
	 * CMD_DESC_REGISTER bit set.
2385 2386 2387 2388
	 *
	 * A non-zero step value implies that the command may access multiple
	 * registers in sequence (e.g. LRI), in that case step gives the
	 * distance in dwords between individual offset fields.
2389 2390 2391 2392
	 */
	struct {
		u32 offset;
		u32 mask;
2393
		u32 step;
2394 2395 2396 2397 2398 2399 2400 2401 2402
	} reg;

#define MAX_CMD_DESC_BITMASKS 3
	/*
	 * Describes command checks where a particular dword is masked and
	 * compared against an expected value. If the command does not match
	 * the expected value, the parser rejects it. Only valid if flags has
	 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
	 * are valid.
2403 2404 2405 2406
	 *
	 * If the check specifies a non-zero condition_mask then the parser
	 * only performs the check when the bits specified by condition_mask
	 * are non-zero.
2407 2408 2409 2410 2411
	 */
	struct {
		u32 offset;
		u32 mask;
		u32 expected;
2412 2413
		u32 condition_offset;
		u32 condition_mask;
2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427
	} bits[MAX_CMD_DESC_BITMASKS];
};

/*
 * A table of commands requiring special handling by the command parser.
 *
 * Each ring has an array of tables. Each table consists of an array of command
 * descriptors, which must be sorted with command opcodes in ascending order.
 */
struct drm_i915_cmd_table {
	const struct drm_i915_cmd_descriptor *table;
	int count;
};

C
Chris Wilson 已提交
2428
/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2429 2430 2431 2432 2433 2434 2435 2436 2437 2438
#define __I915__(p) ({ \
	struct drm_i915_private *__p; \
	if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
		__p = (struct drm_i915_private *)p; \
	else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
		__p = to_i915((struct drm_device *)p); \
	else \
		BUILD_BUG(); \
	__p; \
})
C
Chris Wilson 已提交
2439
#define INTEL_INFO(p) 	(&__I915__(p)->info)
2440
#define INTEL_DEVID(p)	(INTEL_INFO(p)->device_id)
2441
#define INTEL_REVID(p)	(__I915__(p)->dev->pdev->revision)
2442

2443 2444
#define IS_I830(dev)		(INTEL_DEVID(dev) == 0x3577)
#define IS_845G(dev)		(INTEL_DEVID(dev) == 0x2562)
2445
#define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
2446
#define IS_I865G(dev)		(INTEL_DEVID(dev) == 0x2572)
2447
#define IS_I915G(dev)		(INTEL_INFO(dev)->is_i915g)
2448 2449
#define IS_I915GM(dev)		(INTEL_DEVID(dev) == 0x2592)
#define IS_I945G(dev)		(INTEL_DEVID(dev) == 0x2772)
2450 2451 2452
#define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)
#define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)
#define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)
2453
#define IS_GM45(dev)		(INTEL_DEVID(dev) == 0x2A42)
2454
#define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)
2455 2456
#define IS_PINEVIEW_G(dev)	(INTEL_DEVID(dev) == 0xa001)
#define IS_PINEVIEW_M(dev)	(INTEL_DEVID(dev) == 0xa011)
2457 2458
#define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
#define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
2459
#define IS_IRONLAKE_M(dev)	(INTEL_DEVID(dev) == 0x0046)
2460
#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
2461 2462 2463
#define IS_IVB_GT1(dev)		(INTEL_DEVID(dev) == 0x0156 || \
				 INTEL_DEVID(dev) == 0x0152 || \
				 INTEL_DEVID(dev) == 0x015a)
2464
#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
2465
#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2466
#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
2467
#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2468
#define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
2469
#define IS_BROXTON(dev)	(!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2470
#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
2471
#define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
2472
				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
B
Ben Widawsky 已提交
2473
#define IS_BDW_ULT(dev)		(IS_BROADWELL(dev) && \
2474
				 ((INTEL_DEVID(dev) & 0xf) == 0x6 ||	\
2475
				 (INTEL_DEVID(dev) & 0xf) == 0xb ||	\
2476
				 (INTEL_DEVID(dev) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2477 2478 2479
/* ULX machines are also considered ULT. */
#define IS_BDW_ULX(dev)		(IS_BROADWELL(dev) && \
				 (INTEL_DEVID(dev) & 0xf) == 0xe)
R
Rodrigo Vivi 已提交
2480 2481
#define IS_BDW_GT3(dev)		(IS_BROADWELL(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
B
Ben Widawsky 已提交
2482
#define IS_HSW_ULT(dev)		(IS_HASWELL(dev) && \
2483
				 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2484
#define IS_HSW_GT3(dev)		(IS_HASWELL(dev) && \
2485
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2486
/* ULX machines are also considered ULT. */
2487 2488
#define IS_HSW_ULX(dev)		(INTEL_DEVID(dev) == 0x0A0E || \
				 INTEL_DEVID(dev) == 0x0A1E)
2489 2490 2491 2492 2493 2494 2495 2496
#define IS_SKL_ULT(dev)		(INTEL_DEVID(dev) == 0x1906 || \
				 INTEL_DEVID(dev) == 0x1913 || \
				 INTEL_DEVID(dev) == 0x1916 || \
				 INTEL_DEVID(dev) == 0x1921 || \
				 INTEL_DEVID(dev) == 0x1926)
#define IS_SKL_ULX(dev)		(INTEL_DEVID(dev) == 0x190E || \
				 INTEL_DEVID(dev) == 0x1915 || \
				 INTEL_DEVID(dev) == 0x191E)
2497 2498 2499 2500 2501
#define IS_SKL_GT3(dev)		(IS_SKYLAKE(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
#define IS_SKL_GT4(dev)		(IS_SKYLAKE(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)

2502
#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2503

2504 2505 2506 2507
#define SKL_REVID_A0		(0x0)
#define SKL_REVID_B0		(0x1)
#define SKL_REVID_C0		(0x2)
#define SKL_REVID_D0		(0x3)
2508
#define SKL_REVID_E0		(0x4)
I
Imre Deak 已提交
2509
#define SKL_REVID_F0		(0x5)
2510

N
Nick Hoath 已提交
2511 2512
#define BXT_REVID_A0		(0x0)
#define BXT_REVID_B0		(0x3)
2513
#define BXT_REVID_C0		(0x9)
N
Nick Hoath 已提交
2514

2515 2516 2517 2518 2519 2520
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2521 2522 2523 2524 2525
#define IS_GEN2(dev)	(INTEL_INFO(dev)->gen == 2)
#define IS_GEN3(dev)	(INTEL_INFO(dev)->gen == 3)
#define IS_GEN4(dev)	(INTEL_INFO(dev)->gen == 4)
#define IS_GEN5(dev)	(INTEL_INFO(dev)->gen == 5)
#define IS_GEN6(dev)	(INTEL_INFO(dev)->gen == 6)
2526
#define IS_GEN7(dev)	(INTEL_INFO(dev)->gen == 7)
B
Ben Widawsky 已提交
2527
#define IS_GEN8(dev)	(INTEL_INFO(dev)->gen == 8)
2528
#define IS_GEN9(dev)	(INTEL_INFO(dev)->gen == 9)
2529

2530 2531 2532 2533
#define RENDER_RING		(1<<RCS)
#define BSD_RING		(1<<VCS)
#define BLT_RING		(1<<BCS)
#define VEBOX_RING		(1<<VECS)
2534
#define BSD2_RING		(1<<VCS2)
2535
#define HAS_BSD(dev)		(INTEL_INFO(dev)->ring_mask & BSD_RING)
2536
#define HAS_BSD2(dev)		(INTEL_INFO(dev)->ring_mask & BSD2_RING)
2537 2538 2539 2540
#define HAS_BLT(dev)		(INTEL_INFO(dev)->ring_mask & BLT_RING)
#define HAS_VEBOX(dev)		(INTEL_INFO(dev)->ring_mask & VEBOX_RING)
#define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
#define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2541
				 __I915__(dev)->ellc_size)
2542 2543
#define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)

2544
#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
2545
#define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 8)
2546
#define USES_PPGTT(dev)		(i915.enable_ppgtt)
2547 2548
#define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev)	(i915.enable_ppgtt == 3)
2549

2550
#define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
2551 2552
#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)

2553 2554
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))
2555 2556 2557 2558 2559 2560 2561 2562
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2563

2564 2565 2566 2567 2568 2569 2570 2571 2572 2573
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
						      IS_I915GM(dev)))
#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)

#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2574
#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2575

2576
#define HAS_IPS(dev)		(IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2577

2578 2579 2580
#define HAS_DP_MST(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
				 INTEL_INFO(dev)->gen >= 9)

2581
#define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
2582
#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
2583
#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2584 2585
				 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
				 IS_SKYLAKE(dev))
2586
#define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
S
Suketu Shah 已提交
2587 2588
				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
				 IS_SKYLAKE(dev))
2589 2590
#define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
#define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
P
Paulo Zanoni 已提交
2591

2592
#define HAS_CSR(dev)	(IS_GEN9(dev))
2593

2594 2595 2596
#define HAS_GUC_UCODE(dev)	(IS_GEN9(dev))
#define HAS_GUC_SCHED(dev)	(IS_GEN9(dev))

2597 2598 2599
#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
				    INTEL_INFO(dev)->gen >= 8)

2600
#define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
2601
				 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
2602

2603 2604 2605 2606 2607 2608
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2609 2610
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2611
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2612

2613
#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2614
#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2615
#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2616
#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2617 2618
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
B
Ben Widawsky 已提交
2619
#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2620
#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2621

2622 2623
#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))

2624 2625 2626
/* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2627

2628
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2629
#define GEN9_FREQ_SCALER 3
2630

2631 2632
#include "i915_trace.h"

R
Rob Clark 已提交
2633
extern const struct drm_ioctl_desc i915_ioctls[];
2634 2635
extern int i915_max_ioctl;

2636 2637
extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
extern int i915_resume_switcheroo(struct drm_device *dev);
2638

2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649
/* i915_params.c */
struct i915_params {
	int modeset;
	int panel_ignore_lid;
	int semaphores;
	int lvds_channel_mode;
	int panel_use_ssc;
	int vbt_sdvo_panel_type;
	int enable_rc6;
	int enable_fbc;
	int enable_ppgtt;
2650
	int enable_execlists;
2651 2652 2653 2654
	int enable_psr;
	unsigned int preliminary_hw_support;
	int disable_power_well;
	int enable_ips;
2655
	int invert_brightness;
2656
	int enable_cmd_parser;
2657 2658
	/* leave bools at the end to not create holes */
	bool enable_hangcheck;
2659
	bool prefault_disable;
2660
	bool load_detect_test;
2661
	bool reset;
2662
	bool disable_display;
2663
	bool disable_vtd_wa;
2664 2665
	bool enable_guc_submission;
	int guc_log_level;
2666
	int use_mmio_flip;
2667
	int mmio_debug;
R
Rob Clark 已提交
2668
	bool verbose_state_checks;
2669
	bool nuclear_pageflip;
2670
	int edp_vswing;
2671 2672 2673
};
extern struct i915_params i915 __read_mostly;

L
Linus Torvalds 已提交
2674
				/* i915_dma.c */
2675
extern int i915_driver_load(struct drm_device *, unsigned long flags);
J
Jesse Barnes 已提交
2676
extern int i915_driver_unload(struct drm_device *);
2677
extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2678
extern void i915_driver_lastclose(struct drm_device * dev);
2679
extern void i915_driver_preclose(struct drm_device *dev,
2680
				 struct drm_file *file);
2681
extern void i915_driver_postclose(struct drm_device *dev,
2682
				  struct drm_file *file);
2683
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2684 2685
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2686
#endif
2687
extern int intel_gpu_reset(struct drm_device *dev);
2688
extern bool intel_has_gpu_reset(struct drm_device *dev);
2689
extern int i915_reset(struct drm_device *dev);
2690 2691 2692 2693
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2694
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2695
void i915_firmware_load_error_print(const char *fw_path, int err);
2696

2697 2698 2699 2700 2701
/* intel_hotplug.c */
void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2702
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2703

L
Linus Torvalds 已提交
2704
/* i915_irq.c */
2705
void i915_queue_hangcheck(struct drm_device *dev);
2706 2707 2708
__printf(3, 4)
void i915_handle_error(struct drm_device *dev, bool wedged,
		       const char *fmt, ...);
L
Linus Torvalds 已提交
2709

2710
extern void intel_irq_init(struct drm_i915_private *dev_priv);
2711 2712
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2713 2714

extern void intel_uncore_sanitize(struct drm_device *dev);
2715 2716
extern void intel_uncore_early_sanitize(struct drm_device *dev,
					bool restore_forcewake);
2717 2718
extern void intel_uncore_init(struct drm_device *dev);
extern void intel_uncore_check_errors(struct drm_device *dev);
2719
extern void intel_uncore_fini(struct drm_device *dev);
2720
extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2721
const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2722
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2723
				enum forcewake_domains domains);
2724
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2725
				enum forcewake_domains domains);
2726 2727 2728 2729 2730 2731 2732
/* Like above but the caller must manage the uncore.lock itself.
 * Must be used with I915_READ_FW and friends.
 */
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
2733
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2734 2735 2736 2737
static inline bool intel_vgpu_active(struct drm_device *dev)
{
	return to_i915(dev)->vgpu.active;
}
2738

2739
void
2740
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2741
		     u32 status_mask);
2742 2743

void
2744
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2745
		      u32 status_mask);
2746

2747 2748
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2749 2750 2751
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762
void
ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
void
ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
#define ibx_enable_display_interrupt(dev_priv, bits) \
	ibx_display_interrupt_update((dev_priv), (bits), (bits))
#define ibx_disable_display_interrupt(dev_priv, bits) \
	ibx_display_interrupt_update((dev_priv), (bits), 0)
2763

2764 2765 2766 2767 2768 2769 2770 2771 2772
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2773 2774
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2775 2776 2777 2778
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
2779
void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2780
					struct drm_i915_gem_request *req);
2781
void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2782
int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2783
				   struct drm_i915_gem_execbuffer2 *args,
2784
				   struct list_head *vmas);
2785 2786
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
2787 2788
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
2789 2790
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
2791 2792 2793 2794
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
2795 2796
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
2797 2798
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
2799 2800 2801 2802
int i915_gem_set_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_get_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2803 2804 2805
int i915_gem_init_userptr(struct drm_device *dev);
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
2806 2807
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
2808 2809
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2810
void i915_gem_load(struct drm_device *dev);
2811 2812
void *i915_gem_object_alloc(struct drm_device *dev);
void i915_gem_object_free(struct drm_i915_gem_object *obj);
2813 2814
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
2815 2816
struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
						  size_t size);
2817 2818
struct drm_i915_gem_object *i915_gem_object_create_from_data(
		struct drm_device *dev, const void *data, size_t size);
2819
void i915_gem_free_object(struct drm_gem_object *obj);
B
Ben Widawsky 已提交
2820
void i915_gem_vma_destroy(struct i915_vma *vma);
2821

2822 2823 2824 2825 2826 2827 2828
/* Flags used by pin/bind&friends. */
#define PIN_MAPPABLE	(1<<0)
#define PIN_NONBLOCK	(1<<1)
#define PIN_GLOBAL	(1<<2)
#define PIN_OFFSET_BIAS	(1<<3)
#define PIN_USER	(1<<4)
#define PIN_UPDATE	(1<<5)
2829
#define PIN_OFFSET_MASK (~4095)
2830 2831 2832 2833 2834 2835 2836 2837 2838 2839
int __must_check
i915_gem_object_pin(struct drm_i915_gem_object *obj,
		    struct i915_address_space *vm,
		    uint32_t alignment,
		    uint64_t flags);
int __must_check
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
			 uint32_t alignment,
			 uint64_t flags);
2840 2841 2842

int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
		  u32 flags);
2843
int __must_check i915_vma_unbind(struct i915_vma *vma);
2844
int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2845
void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2846
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2847

2848 2849 2850
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    int *needs_clflush);

2851
int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2852 2853

static inline int __sg_page_count(struct scatterlist *sg)
2854
{
2855 2856
	return sg->length >> PAGE_SHIFT;
}
2857

2858 2859
static inline struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2860
{
2861 2862
	if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
		return NULL;
2863

2864 2865 2866 2867
	if (n < obj->get_page.last) {
		obj->get_page.sg = obj->pages->sgl;
		obj->get_page.last = 0;
	}
2868

2869 2870 2871 2872 2873
	while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
		obj->get_page.last += __sg_page_count(obj->get_page.sg++);
		if (unlikely(sg_is_chain(obj->get_page.sg)))
			obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
	}
2874

2875
	return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2876
}
2877

2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888
static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages == NULL);
	obj->pages_pin_count++;
}
static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages_pin_count == 0);
	obj->pages_pin_count--;
}

2889
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2890
int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2891 2892
			 struct intel_engine_cs *to,
			 struct drm_i915_gem_request **to_req);
B
Ben Widawsky 已提交
2893
void i915_vma_move_to_active(struct i915_vma *vma,
2894
			     struct drm_i915_gem_request *req);
2895 2896 2897
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
2898 2899
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
2900 2901 2902 2903 2904 2905 2906 2907 2908
/**
 * Returns true if seq1 is later than seq2.
 */
static inline bool
i915_seqno_passed(uint32_t seq1, uint32_t seq2)
{
	return (int32_t)(seq1 - seq2) >= 0;
}

2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920
static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
					      bool lazy_coherency)
{
	u32 seqno;

	BUG_ON(req == NULL);

	seqno = req->ring->get_seqno(req->ring, lazy_coherency);

	return i915_seqno_passed(seqno, req->seqno);
}

2921 2922
int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2923

2924
struct drm_i915_gem_request *
2925
i915_gem_find_active_request(struct intel_engine_cs *ring);
2926

2927
bool i915_gem_retire_requests(struct drm_device *dev);
2928
void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2929
int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2930
				      bool interruptible);
2931

2932 2933 2934
static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
{
	return unlikely(atomic_read(&error->reset_counter)
M
Mika Kuoppala 已提交
2935
			& (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2936 2937 2938 2939
}

static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
{
M
Mika Kuoppala 已提交
2940 2941 2942 2943 2944 2945
	return atomic_read(&error->reset_counter) & I915_WEDGED;
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
	return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2946
}
2947

2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959
static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
{
	return dev_priv->gpu_error.stop_rings == 0 ||
		dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
}

static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
{
	return dev_priv->gpu_error.stop_rings == 0 ||
		dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
}

2960
void i915_gem_reset(struct drm_device *dev);
2961
bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2962
int __must_check i915_gem_init(struct drm_device *dev);
2963
int i915_gem_init_rings(struct drm_device *dev);
2964
int __must_check i915_gem_init_hw(struct drm_device *dev);
2965
int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
2966
void i915_gem_init_swizzling(struct drm_device *dev);
J
Jesse Barnes 已提交
2967
void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2968
int __must_check i915_gpu_idle(struct drm_device *dev);
2969
int __must_check i915_gem_suspend(struct drm_device *dev);
2970
void __i915_add_request(struct drm_i915_gem_request *req,
2971 2972
			struct drm_i915_gem_object *batch_obj,
			bool flush_caches);
2973
#define i915_add_request(req) \
2974
	__i915_add_request(req, NULL, true)
2975
#define i915_add_request_no_flush(req) \
2976
	__i915_add_request(req, NULL, false)
2977
int __i915_wait_request(struct drm_i915_gem_request *req,
2978 2979 2980
			unsigned reset_counter,
			bool interruptible,
			s64 *timeout,
2981
			struct intel_rps_client *rps);
2982
int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2983
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2984
int __must_check
2985 2986 2987
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
			       bool readonly);
int __must_check
2988 2989 2990
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
				  bool write);
int __must_check
2991 2992
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
int __must_check
2993 2994
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
2995
				     struct intel_engine_cs *pipelined,
2996
				     struct drm_i915_gem_request **pipelined_request,
2997 2998 2999
				     const struct i915_ggtt_view *view);
void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
					      const struct i915_ggtt_view *view);
3000
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3001
				int align);
3002
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3003
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3004

3005 3006
uint32_t
i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3007
uint32_t
3008 3009
i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
			    int tiling_mode, bool fenced);
3010

3011 3012 3013
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3014 3015 3016 3017 3018 3019
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3020 3021 3022 3023 3024
u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
				  const struct i915_ggtt_view *view);
u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
			struct i915_address_space *vm);
static inline u64
3025
i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3026
{
3027
	return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3028
}
3029

3030
bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3031
bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3032
				  const struct i915_ggtt_view *view);
3033
bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3034
			struct i915_address_space *vm);
3035

3036 3037
unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
				struct i915_address_space *vm);
3038
struct i915_vma *
3039 3040 3041 3042 3043
i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
		    struct i915_address_space *vm);
struct i915_vma *
i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
			  const struct i915_ggtt_view *view);
3044

3045 3046
struct i915_vma *
i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3047 3048 3049 3050
				  struct i915_address_space *vm);
struct i915_vma *
i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
				       const struct i915_ggtt_view *view);
3051

3052 3053 3054 3055
static inline struct i915_vma *
i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
{
	return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
B
Ben Widawsky 已提交
3056
}
3057
bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3058

3059
/* Some GGTT VM helpers */
3060
#define i915_obj_to_ggtt(obj) \
3061 3062 3063 3064 3065 3066 3067 3068
	(&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
static inline bool i915_is_ggtt(struct i915_address_space *vm)
{
	struct i915_address_space *ggtt =
		&((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
	return vm == ggtt;
}

3069 3070 3071 3072 3073 3074 3075 3076 3077
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	WARN_ON(i915_is_ggtt(vm));

	return container_of(vm, struct i915_hw_ppgtt, base);
}


3078 3079
static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
{
3080
	return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3081 3082 3083 3084 3085
}

static inline unsigned long
i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
{
3086
	return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3087
}
B
Ben Widawsky 已提交
3088 3089 3090 3091

static inline int __must_check
i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
		      uint32_t alignment,
3092
		      unsigned flags)
B
Ben Widawsky 已提交
3093
{
3094 3095
	return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
				   alignment, flags | PIN_GLOBAL);
B
Ben Widawsky 已提交
3096
}
3097

3098 3099 3100 3101 3102 3103
static inline int
i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
{
	return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
}

3104 3105 3106 3107 3108 3109 3110
void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
				     const struct i915_ggtt_view *view);
static inline void
i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
{
	i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
}
3111

3112 3113 3114 3115 3116 3117 3118 3119 3120
/* i915_gem_fence.c */
int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);

bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);

void i915_gem_restore_fences(struct drm_device *dev);

3121 3122 3123 3124
void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);

3125
/* i915_gem_context.c */
3126
int __must_check i915_gem_context_init(struct drm_device *dev);
3127
void i915_gem_context_fini(struct drm_device *dev);
3128
void i915_gem_context_reset(struct drm_device *dev);
3129
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3130
int i915_gem_context_enable(struct drm_i915_gem_request *req);
3131
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3132
int i915_switch_context(struct drm_i915_gem_request *req);
3133
struct intel_context *
3134
i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3135
void i915_gem_context_free(struct kref *ctx_ref);
3136 3137
struct drm_i915_gem_object *
i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3138
static inline void i915_gem_context_reference(struct intel_context *ctx)
3139
{
3140
	kref_get(&ctx->ref);
3141 3142
}

3143
static inline void i915_gem_context_unreference(struct intel_context *ctx)
3144
{
3145
	kref_put(&ctx->ref, i915_gem_context_free);
3146 3147
}

3148
static inline bool i915_gem_context_is_default(const struct intel_context *c)
3149
{
3150
	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3151 3152
}

3153 3154 3155 3156
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file);
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
				   struct drm_file *file);
3157 3158 3159 3160
int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
3161

3162 3163 3164 3165 3166 3167
/* i915_gem_evict.c */
int __must_check i915_gem_evict_something(struct drm_device *dev,
					  struct i915_address_space *vm,
					  int min_size,
					  unsigned alignment,
					  unsigned cache_level,
3168 3169
					  unsigned long start,
					  unsigned long end,
3170
					  unsigned flags);
3171 3172
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
int i915_gem_evict_everything(struct drm_device *dev);
3173

3174
/* belongs in i915_gem_gtt.h */
3175
static inline void i915_gem_chipset_flush(struct drm_device *dev)
3176 3177 3178 3179
{
	if (INTEL_INFO(dev)->gen < 6)
		intel_gtt_chipset_flush();
}
3180

3181
/* i915_gem_stolen.c */
3182 3183 3184
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3185 3186 3187 3188
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3189 3190
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3191 3192
int i915_gem_init_stolen(struct drm_device *dev);
void i915_gem_cleanup_stolen(struct drm_device *dev);
3193 3194
struct drm_i915_gem_object *
i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3195 3196 3197 3198 3199
struct drm_i915_gem_object *
i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3200

3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
			      long target,
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);


3212
/* i915_gem_tiling.c */
3213
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3214
{
3215
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3216 3217 3218 3219 3220

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
		obj->tiling_mode != I915_TILING_NONE;
}

3221
/* i915_gem_debug.c */
3222 3223
#if WATCH_LISTS
int i915_verify_lists(struct drm_device *dev);
3224
#else
3225
#define i915_verify_lists(dev) 0
3226
#endif
L
Linus Torvalds 已提交
3227

3228
/* i915_debugfs.c */
3229 3230
int i915_debugfs_init(struct drm_minor *minor);
void i915_debugfs_cleanup(struct drm_minor *minor);
3231
#ifdef CONFIG_DEBUG_FS
J
Jani Nikula 已提交
3232
int i915_debugfs_connector_add(struct drm_connector *connector);
3233 3234
void intel_display_crc_init(struct drm_device *dev);
#else
3235 3236
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3237
static inline void intel_display_crc_init(struct drm_device *dev) {}
3238
#endif
3239 3240

/* i915_gpu_error.c */
3241 3242
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3243 3244
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
			    const struct i915_error_state_file_priv *error);
3245
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3246
			      struct drm_i915_private *i915,
3247 3248 3249 3250 3251 3252
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3253 3254
void i915_capture_error_state(struct drm_device *dev, bool wedge,
			      const char *error_msg);
3255 3256 3257 3258 3259 3260
void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv);
void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
void i915_destroy_error_state(struct drm_device *dev);

void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3261
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3262

3263
/* i915_cmd_parser.c */
3264
int i915_cmd_parser_get_version(void);
3265 3266 3267 3268
int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
int i915_parse_cmds(struct intel_engine_cs *ring,
3269
		    struct drm_i915_gem_object *batch_obj,
3270
		    struct drm_i915_gem_object *shadow_batch_obj,
3271
		    u32 batch_start_offset,
3272
		    u32 batch_len,
3273 3274
		    bool is_master);

3275 3276 3277
/* i915_suspend.c */
extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev);
3278

B
Ben Widawsky 已提交
3279 3280 3281 3282
/* i915_sysfs.c */
void i915_setup_sysfs(struct drm_device *dev_priv);
void i915_teardown_sysfs(struct drm_device *dev_priv);

3283 3284 3285
/* intel_i2c.c */
extern int intel_setup_gmbus(struct drm_device *dev);
extern void intel_teardown_gmbus(struct drm_device *dev);
3286 3287
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3288

3289 3290
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3291 3292
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3293
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3294 3295 3296
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3297 3298
extern void intel_i2c_reset(struct drm_device *dev);

3299
/* intel_opregion.c */
3300
#ifdef CONFIG_ACPI
3301
extern int intel_opregion_setup(struct drm_device *dev);
3302 3303
extern void intel_opregion_init(struct drm_device *dev);
extern void intel_opregion_fini(struct drm_device *dev);
3304
extern void intel_opregion_asle_intr(struct drm_device *dev);
3305 3306
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
3307 3308
extern int intel_opregion_notify_adapter(struct drm_device *dev,
					 pci_power_t state);
3309
#else
3310
static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3311 3312
static inline void intel_opregion_init(struct drm_device *dev) { return; }
static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3313
static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3314 3315 3316 3317 3318
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
3319 3320 3321 3322 3323
static inline int
intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
{
	return 0;
}
3324
#endif
3325

J
Jesse Barnes 已提交
3326 3327 3328 3329 3330 3331 3332 3333 3334
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

J
Jesse Barnes 已提交
3335
/* modesetting */
3336
extern void intel_modeset_init_hw(struct drm_device *dev);
J
Jesse Barnes 已提交
3337
extern void intel_modeset_init(struct drm_device *dev);
3338
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3339
extern void intel_modeset_cleanup(struct drm_device *dev);
3340
extern void intel_connector_unregister(struct intel_connector *);
3341
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3342
extern void intel_display_resume(struct drm_device *dev);
3343
extern void i915_redisable_vga(struct drm_device *dev);
3344
extern void i915_redisable_vga_power_on(struct drm_device *dev);
3345
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
P
Paulo Zanoni 已提交
3346
extern void intel_init_pch_refclk(struct drm_device *dev);
3347
extern void intel_set_rps(struct drm_device *dev, u8 val);
3348 3349
extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
				  bool enable);
3350 3351
extern void intel_detect_pch(struct drm_device *dev);
extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
B
Ben Widawsky 已提交
3352
extern int intel_enable_rc6(const struct drm_device *dev);
3353

3354
extern bool i915_semaphore_is_enabled(struct drm_device *dev);
B
Ben Widawsky 已提交
3355 3356
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3357 3358
int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
3359

3360 3361
/* overlay */
extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3362 3363
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3364 3365

extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3366
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3367 3368
					    struct drm_device *dev,
					    struct intel_display_error_state *error);
3369

3370 3371
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3372 3373

/* intel_sideband.c */
3374 3375
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3376
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3377 3378 3379 3380 3381 3382
u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3383 3384
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3385 3386
u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3387 3388
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3389 3390 3391 3392
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3393 3394
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3395

3396 3397
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3398

3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3412 3413 3414 3415 3416 3417
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
 * machine death. You have been warned.
 */
3418 3419
#define I915_WRITE64(reg, val)	dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3420

3421
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3422 3423
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3424
	do {								\
3425
		old_upper = upper;					\
3426
		lower = I915_READ(lower_reg);				\
3427 3428
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3429
	(u64)upper << 32 | lower; })
3430

3431 3432 3433
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444
/* These are untraced mmio-accessors that are only valid to be used inside
 * criticial sections inside IRQ handlers where forcewake is explicitly
 * controlled.
 * Think twice, and think again, before using these.
 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
 * intel_uncore_forcewake_irqunlock().
 */
#define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
#define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

3445 3446 3447 3448
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
3449

3450 3451
static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
{
3452
	if (IS_VALLEYVIEW(dev))
3453
		return VLV_VGACNTRL;
3454 3455
	else if (INTEL_INFO(dev)->gen >= 5)
		return CPU_VGACNTRL;
3456 3457 3458 3459
	else
		return VGACNTRL;
}

V
Ville Syrjälä 已提交
3460 3461 3462 3463 3464
static inline void __user *to_user_ptr(u64 address)
{
	return (void __user *)(uintptr_t)address;
}

3465 3466 3467 3468 3469 3470 3471
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3472 3473 3474 3475 3476
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

3477 3478 3479 3480 3481 3482 3483 3484
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3485 3486 3487 3488 3489 3490 3491 3492 3493
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
3494
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3495 3496 3497 3498 3499 3500 3501 3502 3503 3504

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
3505 3506 3507 3508
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
3509 3510 3511
	}
}

3512 3513 3514 3515 3516 3517 3518
static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
				      struct drm_i915_gem_request *req)
{
	if (ring->trace_irq_req == NULL && ring->irq_get(ring))
		i915_gem_request_assign(&ring->trace_irq_req, req);
}

L
Linus Torvalds 已提交
3519
#endif