amd64_edac.c 90.8 KB
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#include "amd64_edac.h"
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#include <asm/amd_nb.h>
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static struct edac_pci_ctl_info *pci_ctl;
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static int report_gart_errors;
module_param(report_gart_errors, int, 0644);

/*
 * Set by command line parameter. If BIOS has enabled the ECC, this override is
 * cleared to prevent re-enabling the hardware by this driver.
 */
static int ecc_enable_override;
module_param(ecc_enable_override, int, 0644);

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static struct msr __percpu *msrs;
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/* Per-node stuff */
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static struct ecc_settings **ecc_stngs;
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/* Number of Unified Memory Controllers */
static u8 num_umcs;

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/*
 * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing
 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
 * or higher value'.
 *
 *FIXME: Produce a better mapping/linearisation.
 */
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static const struct scrubrate {
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       u32 scrubval;           /* bit pattern for scrub rate */
       u32 bandwidth;          /* bandwidth consumed (bytes/sec) */
} scrubrates[] = {
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	{ 0x01, 1600000000UL},
	{ 0x02, 800000000UL},
	{ 0x03, 400000000UL},
	{ 0x04, 200000000UL},
	{ 0x05, 100000000UL},
	{ 0x06, 50000000UL},
	{ 0x07, 25000000UL},
	{ 0x08, 12284069UL},
	{ 0x09, 6274509UL},
	{ 0x0A, 3121951UL},
	{ 0x0B, 1560975UL},
	{ 0x0C, 781440UL},
	{ 0x0D, 390720UL},
	{ 0x0E, 195300UL},
	{ 0x0F, 97650UL},
	{ 0x10, 48854UL},
	{ 0x11, 24427UL},
	{ 0x12, 12213UL},
	{ 0x13, 6101UL},
	{ 0x14, 3051UL},
	{ 0x15, 1523UL},
	{ 0x16, 761UL},
	{ 0x00, 0UL},        /* scrubbing off */
};

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int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
			       u32 *val, const char *func)
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{
	int err = 0;

	err = pci_read_config_dword(pdev, offset, val);
	if (err)
		amd64_warn("%s: error reading F%dx%03x.\n",
			   func, PCI_FUNC(pdev->devfn), offset);

	return err;
}

int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
				u32 val, const char *func)
{
	int err = 0;

	err = pci_write_config_dword(pdev, offset, val);
	if (err)
		amd64_warn("%s: error writing to F%dx%03x.\n",
			   func, PCI_FUNC(pdev->devfn), offset);

	return err;
}

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/*
 * Select DCT to which PCI cfg accesses are routed
 */
static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct)
{
	u32 reg = 0;

	amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, &reg);
	reg &= (pvt->model == 0x30) ? ~3 : ~1;
	reg |= dct;
	amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);
}

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/*
 *
 * Depending on the family, F2 DCT reads need special handling:
 *
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 * K8: has a single DCT only and no address offsets >= 0x100
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 *
 * F10h: each DCT has its own set of regs
 *	DCT0 -> F2x040..
 *	DCT1 -> F2x140..
 *
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 * F16h: has only 1 DCT
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 *
 * F15h: we select which DCT we access using F1x10C[DctCfgSel]
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 */
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static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct,
					 int offset, u32 *val)
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{
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	switch (pvt->fam) {
	case 0xf:
		if (dct || offset >= 0x100)
			return -EINVAL;
		break;
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	case 0x10:
		if (dct) {
			/*
			 * Note: If ganging is enabled, barring the regs
			 * F2x[1,0]98 and F2x[1,0]9C; reads reads to F2x1xx
			 * return 0. (cf. Section 2.8.1 F10h BKDG)
			 */
			if (dct_ganging_enabled(pvt))
				return 0;
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			offset += 0x100;
		}
		break;
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	case 0x15:
		/*
		 * F15h: F2x1xx addresses do not map explicitly to DCT1.
		 * We should select which DCT we access using F1x10C[DctCfgSel]
		 */
		dct = (dct && pvt->model == 0x30) ? 3 : dct;
		f15h_select_dct(pvt, dct);
		break;
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	case 0x16:
		if (dct)
			return -EINVAL;
		break;
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	default:
		break;
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	}
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	return amd64_read_pci_cfg(pvt->F2, offset, val);
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}

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/*
 * Memory scrubber control interface. For K8, memory scrubbing is handled by
 * hardware and can involve L2 cache, dcache as well as the main memory. With
 * F10, this is extended to L3 cache scrubbing on CPU models sporting that
 * functionality.
 *
 * This causes the "units" for the scrubbing speed to vary from 64 byte blocks
 * (dram) over to cache lines. This is nasty, so we will use bandwidth in
 * bytes/sec for the setting.
 *
 * Currently, we only do dram scrubbing. If the scrubbing is done in software on
 * other archs, we might not have access to the caches directly.
 */

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static inline void __f17h_set_scrubval(struct amd64_pvt *pvt, u32 scrubval)
{
	/*
	 * Fam17h supports scrub values between 0x5 and 0x14. Also, the values
	 * are shifted down by 0x5, so scrubval 0x5 is written to the register
	 * as 0x0, scrubval 0x6 as 0x1, etc.
	 */
	if (scrubval >= 0x5 && scrubval <= 0x14) {
		scrubval -= 0x5;
		pci_write_bits32(pvt->F6, F17H_SCR_LIMIT_ADDR, scrubval, 0xF);
		pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 1, 0x1);
	} else {
		pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 0, 0x1);
	}
}
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/*
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 * Scan the scrub rate mapping table for a close or matching bandwidth value to
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 * issue. If requested is too big, then use last maximum value found.
 */
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static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate)
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{
	u32 scrubval;
	int i;

	/*
	 * map the configured rate (new_bw) to a value specific to the AMD64
	 * memory controller and apply to register. Search for the first
	 * bandwidth entry that is greater or equal than the setting requested
	 * and program that. If at last entry, turn off DRAM scrubbing.
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	 *
	 * If no suitable bandwidth is found, turn off DRAM scrubbing entirely
	 * by falling back to the last element in scrubrates[].
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	 */
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	for (i = 0; i < ARRAY_SIZE(scrubrates) - 1; i++) {
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		/*
		 * skip scrub rates which aren't recommended
		 * (see F10 BKDG, F3x58)
		 */
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		if (scrubrates[i].scrubval < min_rate)
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			continue;

		if (scrubrates[i].bandwidth <= new_bw)
			break;
	}

	scrubval = scrubrates[i].scrubval;

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	if (pvt->fam == 0x17 || pvt->fam == 0x18) {
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		__f17h_set_scrubval(pvt, scrubval);
	} else if (pvt->fam == 0x15 && pvt->model == 0x60) {
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		f15h_select_dct(pvt, 0);
		pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
		f15h_select_dct(pvt, 1);
		pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
	} else {
		pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F);
	}
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	if (scrubval)
		return scrubrates[i].bandwidth;

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	return 0;
}

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static int set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
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{
	struct amd64_pvt *pvt = mci->pvt_info;
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	u32 min_scrubrate = 0x5;
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	if (pvt->fam == 0xf)
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		min_scrubrate = 0x0;

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	if (pvt->fam == 0x15) {
		/* Erratum #505 */
		if (pvt->model < 0x10)
			f15h_select_dct(pvt, 0);
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		if (pvt->model == 0x60)
			min_scrubrate = 0x6;
	}
	return __set_scrub_rate(pvt, bw, min_scrubrate);
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}

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static int get_scrub_rate(struct mem_ctl_info *mci)
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{
	struct amd64_pvt *pvt = mci->pvt_info;
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	int i, retval = -EINVAL;
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	u32 scrubval = 0;
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	switch (pvt->fam) {
	case 0x15:
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		/* Erratum #505 */
		if (pvt->model < 0x10)
			f15h_select_dct(pvt, 0);
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		if (pvt->model == 0x60)
			amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval);
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		break;

	case 0x17:
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	case 0x18:
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		amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval);
		if (scrubval & BIT(0)) {
			amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval);
			scrubval &= 0xF;
			scrubval += 0x5;
		} else {
			scrubval = 0;
		}
		break;

	default:
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		amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
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		break;
	}
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	scrubval = scrubval & 0x001F;

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	for (i = 0; i < ARRAY_SIZE(scrubrates); i++) {
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		if (scrubrates[i].scrubval == scrubval) {
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			retval = scrubrates[i].bandwidth;
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			break;
		}
	}
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	return retval;
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}

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/*
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 * returns true if the SysAddr given by sys_addr matches the
 * DRAM base/limit associated with node_id
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 */
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static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid)
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{
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	u64 addr;
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	/* The K8 treats this as a 40-bit value.  However, bits 63-40 will be
	 * all ones if the most significant implemented address bit is 1.
	 * Here we discard bits 63-40.  See section 3.4.2 of AMD publication
	 * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1
	 * Application Programming.
	 */
	addr = sys_addr & 0x000000ffffffffffull;

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	return ((addr >= get_dram_base(pvt, nid)) &&
		(addr <= get_dram_limit(pvt, nid)));
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}

/*
 * Attempt to map a SysAddr to a node. On success, return a pointer to the
 * mem_ctl_info structure for the node that the SysAddr maps to.
 *
 * On failure, return NULL.
 */
static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
						u64 sys_addr)
{
	struct amd64_pvt *pvt;
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	u8 node_id;
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	u32 intlv_en, bits;

	/*
	 * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section
	 * 3.4.4.2) registers to map the SysAddr to a node ID.
	 */
	pvt = mci->pvt_info;

	/*
	 * The value of this field should be the same for all DRAM Base
	 * registers.  Therefore we arbitrarily choose to read it from the
	 * register for node 0.
	 */
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	intlv_en = dram_intlv_en(pvt, 0);
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	if (intlv_en == 0) {
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		for (node_id = 0; node_id < DRAM_RANGES; node_id++) {
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			if (base_limit_match(pvt, sys_addr, node_id))
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				goto found;
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		}
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		goto err_no_match;
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	}

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	if (unlikely((intlv_en != 0x01) &&
		     (intlv_en != 0x03) &&
		     (intlv_en != 0x07))) {
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		amd64_warn("DRAM Base[IntlvEn] junk value: 0x%x, BIOS bug?\n", intlv_en);
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		return NULL;
	}

	bits = (((u32) sys_addr) >> 12) & intlv_en;

	for (node_id = 0; ; ) {
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		if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits)
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			break;	/* intlv_sel field matches */

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		if (++node_id >= DRAM_RANGES)
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			goto err_no_match;
	}

	/* sanity test for sys_addr */
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	if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) {
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		amd64_warn("%s: sys_addr 0x%llx falls outside base/limit address"
			   "range for node %d with node interleaving enabled.\n",
			   __func__, sys_addr, node_id);
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		return NULL;
	}

found:
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	return edac_mc_find((int)node_id);
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err_no_match:
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	edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n",
		 (unsigned long)sys_addr);
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	return NULL;
}
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/*
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 * compute the CS base address of the @csrow on the DRAM controller @dct.
 * For details see F2x[5C:40] in the processor's BKDG
389
 */
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static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct,
				 u64 *base, u64 *mask)
392
{
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	u64 csbase, csmask, base_bits, mask_bits;
	u8 addr_shift;
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	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {
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		csbase		= pvt->csels[dct].csbases[csrow];
		csmask		= pvt->csels[dct].csmasks[csrow];
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		base_bits	= GENMASK_ULL(31, 21) | GENMASK_ULL(15, 9);
		mask_bits	= GENMASK_ULL(29, 21) | GENMASK_ULL(15, 9);
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		addr_shift	= 4;
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	/*
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	 * F16h and F15h, models 30h and later need two addr_shift values:
	 * 8 for high and 6 for low (cf. F16h BKDG).
	 */
	} else if (pvt->fam == 0x16 ||
		  (pvt->fam == 0x15 && pvt->model >= 0x30)) {
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		csbase          = pvt->csels[dct].csbases[csrow];
		csmask          = pvt->csels[dct].csmasks[csrow >> 1];

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		*base  = (csbase & GENMASK_ULL(15,  5)) << 6;
		*base |= (csbase & GENMASK_ULL(30, 19)) << 8;
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		*mask = ~0ULL;
		/* poke holes for the csmask */
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		*mask &= ~((GENMASK_ULL(15, 5)  << 6) |
			   (GENMASK_ULL(30, 19) << 8));
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		*mask |= (csmask & GENMASK_ULL(15, 5))  << 6;
		*mask |= (csmask & GENMASK_ULL(30, 19)) << 8;
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		return;
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	} else {
		csbase		= pvt->csels[dct].csbases[csrow];
		csmask		= pvt->csels[dct].csmasks[csrow >> 1];
		addr_shift	= 8;
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		if (pvt->fam == 0x15)
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			base_bits = mask_bits =
				GENMASK_ULL(30,19) | GENMASK_ULL(13,5);
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		else
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			base_bits = mask_bits =
				GENMASK_ULL(28,19) | GENMASK_ULL(13,5);
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	}
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	*base  = (csbase & base_bits) << addr_shift;
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	*mask  = ~0ULL;
	/* poke holes for the csmask */
	*mask &= ~(mask_bits << addr_shift);
	/* OR them in */
	*mask |= (csmask & mask_bits) << addr_shift;
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}

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#define for_each_chip_select(i, dct, pvt) \
	for (i = 0; i < pvt->csels[dct].b_cnt; i++)

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#define chip_select_base(i, dct, pvt) \
	pvt->csels[dct].csbases[i]

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#define for_each_chip_select_mask(i, dct, pvt) \
	for (i = 0; i < pvt->csels[dct].m_cnt; i++)

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#define for_each_umc(i) \
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	for (i = 0; i < num_umcs; i++)
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/*
 * @input_addr is an InputAddr associated with the node given by mci. Return the
 * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
 */
static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
{
	struct amd64_pvt *pvt;
	int csrow;
	u64 base, mask;

	pvt = mci->pvt_info;

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	for_each_chip_select(csrow, 0, pvt) {
		if (!csrow_enabled(csrow, 0, pvt))
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			continue;

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		get_cs_base_and_mask(pvt, csrow, 0, &base, &mask);

		mask = ~mask;
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		if ((input_addr & mask) == (base & mask)) {
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			edac_dbg(2, "InputAddr 0x%lx matches csrow %d (node %d)\n",
				 (unsigned long)input_addr, csrow,
				 pvt->mc_node_id);
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			return csrow;
		}
	}
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	edac_dbg(2, "no matching csrow for InputAddr 0x%lx (MC node %d)\n",
		 (unsigned long)input_addr, pvt->mc_node_id);
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	return -1;
}

/*
 * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094)
 * for the node represented by mci. Info is passed back in *hole_base,
 * *hole_offset, and *hole_size.  Function returns 0 if info is valid or 1 if
 * info is invalid. Info may be invalid for either of the following reasons:
 *
 * - The revision of the node is not E or greater.  In this case, the DRAM Hole
 *   Address Register does not exist.
 *
 * - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
 *   indicating that its contents are not valid.
 *
 * The values passed back in *hole_base, *hole_offset, and *hole_size are
 * complete 32-bit values despite the fact that the bitfields in the DHAR
 * only represent bits 31-24 of the base and offset values.
 */
int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
			     u64 *hole_offset, u64 *hole_size)
{
	struct amd64_pvt *pvt = mci->pvt_info;

	/* only revE and later have the DRAM Hole Address Register */
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	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) {
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		edac_dbg(1, "  revision %d for node %d does not support DHAR\n",
			 pvt->ext_model, pvt->mc_node_id);
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		return 1;
	}

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	/* valid for Fam10h and above */
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	if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) {
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		edac_dbg(1, "  Dram Memory Hoisting is DISABLED on this system\n");
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		return 1;
	}

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	if (!dhar_valid(pvt)) {
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		edac_dbg(1, "  Dram Memory Hoisting is DISABLED on this node %d\n",
			 pvt->mc_node_id);
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		return 1;
	}

	/* This node has Memory Hoisting */

	/* +------------------+--------------------+--------------------+-----
	 * | memory           | DRAM hole          | relocated          |
	 * | [0, (x - 1)]     | [x, 0xffffffff]    | addresses from     |
	 * |                  |                    | DRAM hole          |
	 * |                  |                    | [0x100000000,      |
	 * |                  |                    |  (0x100000000+     |
	 * |                  |                    |   (0xffffffff-x))] |
	 * +------------------+--------------------+--------------------+-----
	 *
	 * Above is a diagram of physical memory showing the DRAM hole and the
	 * relocated addresses from the DRAM hole.  As shown, the DRAM hole
	 * starts at address x (the base address) and extends through address
	 * 0xffffffff.  The DRAM Hole Address Register (DHAR) relocates the
	 * addresses in the hole so that they start at 0x100000000.
	 */

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	*hole_base = dhar_base(pvt);
	*hole_size = (1ULL << 32) - *hole_base;
552

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	*hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt)
					: k8_dhar_offset(pvt);
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	edac_dbg(1, "  DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
		 pvt->mc_node_id, (unsigned long)*hole_base,
		 (unsigned long)*hole_offset, (unsigned long)*hole_size);
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	return 0;
}
EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info);

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/*
 * Return the DramAddr that the SysAddr given by @sys_addr maps to.  It is
 * assumed that sys_addr maps to the node given by mci.
 *
 * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section
 * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a
 * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled,
 * then it is also involved in translating a SysAddr to a DramAddr. Sections
 * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting.
 * These parts of the documentation are unclear. I interpret them as follows:
 *
 * When node n receives a SysAddr, it processes the SysAddr as follows:
 *
 * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM
 *    Limit registers for node n. If the SysAddr is not within the range
 *    specified by the base and limit values, then node n ignores the Sysaddr
 *    (since it does not map to node n). Otherwise continue to step 2 below.
 *
 * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is
 *    disabled so skip to step 3 below. Otherwise see if the SysAddr is within
 *    the range of relocated addresses (starting at 0x100000000) from the DRAM
 *    hole. If not, skip to step 3 below. Else get the value of the
 *    DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the
 *    offset defined by this value from the SysAddr.
 *
 * 3. Obtain the base address for node n from the DRAMBase field of the DRAM
 *    Base register for node n. To obtain the DramAddr, subtract the base
 *    address from the SysAddr, as shown near the start of section 3.4.4 (p.70).
 */
static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
{
595
	struct amd64_pvt *pvt = mci->pvt_info;
596
	u64 dram_base, hole_base, hole_offset, hole_size, dram_addr;
597
	int ret;
598

599
	dram_base = get_dram_base(pvt, pvt->mc_node_id);
600 601 602 603

	ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset,
				      &hole_size);
	if (!ret) {
604 605
		if ((sys_addr >= (1ULL << 32)) &&
		    (sys_addr < ((1ULL << 32) + hole_size))) {
606 607 608
			/* use DHAR to translate SysAddr to DramAddr */
			dram_addr = sys_addr - hole_offset;

609 610 611
			edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
				 (unsigned long)sys_addr,
				 (unsigned long)dram_addr);
612 613 614 615 616 617 618 619 620 621 622 623 624 625

			return dram_addr;
		}
	}

	/*
	 * Translate the SysAddr to a DramAddr as shown near the start of
	 * section 3.4.4 (p. 70).  Although sys_addr is a 64-bit value, the k8
	 * only deals with 40-bit values.  Therefore we discard bits 63-40 of
	 * sys_addr below.  If bit 39 of sys_addr is 1 then the bits we
	 * discard are all 1s.  Otherwise the bits we discard are all 0s.  See
	 * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture
	 * Programmer's Manual Volume 1 Application Programming.
	 */
626
	dram_addr = (sys_addr & GENMASK_ULL(39, 0)) - dram_base;
627

628 629
	edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
		 (unsigned long)sys_addr, (unsigned long)dram_addr);
630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660
	return dram_addr;
}

/*
 * @intlv_en is the value of the IntlvEn field from a DRAM Base register
 * (section 3.4.4.1).  Return the number of bits from a SysAddr that are used
 * for node interleaving.
 */
static int num_node_interleave_bits(unsigned intlv_en)
{
	static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 };
	int n;

	BUG_ON(intlv_en > 7);
	n = intlv_shift_table[intlv_en];
	return n;
}

/* Translate the DramAddr given by @dram_addr to an InputAddr. */
static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr)
{
	struct amd64_pvt *pvt;
	int intlv_shift;
	u64 input_addr;

	pvt = mci->pvt_info;

	/*
	 * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
	 * concerning translating a DramAddr to an InputAddr.
	 */
661
	intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
662
	input_addr = ((dram_addr >> intlv_shift) & GENMASK_ULL(35, 12)) +
663
		      (dram_addr & 0xfff);
664

665 666 667
	edac_dbg(2, "  Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",
		 intlv_shift, (unsigned long)dram_addr,
		 (unsigned long)input_addr);
668 669 670 671 672 673 674 675 676 677 678 679 680 681 682

	return input_addr;
}

/*
 * Translate the SysAddr represented by @sys_addr to an InputAddr.  It is
 * assumed that @sys_addr maps to the node given by mci.
 */
static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr)
{
	u64 input_addr;

	input_addr =
	    dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr));

M
Masanari Iida 已提交
683
	edac_dbg(2, "SysAddr 0x%lx translates to InputAddr 0x%lx\n",
684
		 (unsigned long)sys_addr, (unsigned long)input_addr);
685 686 687 688 689 690

	return input_addr;
}

/* Map the Error address to a PAGE and PAGE OFFSET. */
static inline void error_address_to_page_and_offset(u64 error_address,
691
						    struct err_info *err)
692
{
693 694
	err->page = (u32) (error_address >> PAGE_SHIFT);
	err->offset = ((u32) error_address) & ~PAGE_MASK;
695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711
}

/*
 * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address
 * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers
 * of a node that detected an ECC memory error.  mci represents the node that
 * the error address maps to (possibly different from the node that detected
 * the error).  Return the number of the csrow that sys_addr maps to, or -1 on
 * error.
 */
static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr)
{
	int csrow;

	csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr));

	if (csrow == -1)
712 713
		amd64_mc_err(mci, "Failed to translate InputAddr to csrow for "
				  "address 0x%lx\n", (unsigned long)sys_addr);
714 715
	return csrow;
}
716

717
static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
718 719 720 721 722

/*
 * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
 * are ECC capable.
 */
723
static unsigned long determine_edac_cap(struct amd64_pvt *pvt)
724
{
725
	unsigned long edac_cap = EDAC_FLAG_NONE;
726 727 728 729
	u8 bit;

	if (pvt->umc) {
		u8 i, umc_en_mask = 0, dimm_ecc_en_mask = 0;
730

731
		for_each_umc(i) {
732 733
			if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT))
				continue;
734

735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751
			umc_en_mask |= BIT(i);

			/* UMC Configuration bit 12 (DimmEccEn) */
			if (pvt->umc[i].umc_cfg & BIT(12))
				dimm_ecc_en_mask |= BIT(i);
		}

		if (umc_en_mask == dimm_ecc_en_mask)
			edac_cap = EDAC_FLAG_SECDED;
	} else {
		bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F)
			? 19
			: 17;

		if (pvt->dclr0 & BIT(bit))
			edac_cap = EDAC_FLAG_SECDED;
	}
752 753 754 755

	return edac_cap;
}

756
static void debug_display_dimm_sizes(struct amd64_pvt *, u8);
757

758
static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan)
759
{
760
	edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);
761

762 763 764 765 766 767 768 769 770 771 772 773 774
	if (pvt->dram_type == MEM_LRDDR3) {
		u32 dcsm = pvt->csels[chan].csmasks[0];
		/*
		 * It's assumed all LRDIMMs in a DCT are going to be of
		 * same 'type' until proven otherwise. So, use a cs
		 * value of '0' here to get dcsm value.
		 */
		edac_dbg(1, " LRDIMM %dx rank multiply\n", (dcsm & 0x3));
	}

	edac_dbg(1, "All DIMMs support ECC:%s\n",
		    (dclr & BIT(19)) ? "yes" : "no");

775

776 777
	edac_dbg(1, "  PAR/ERR parity: %s\n",
		 (dclr & BIT(8)) ?  "enabled" : "disabled");
778

779
	if (pvt->fam == 0x10)
780 781
		edac_dbg(1, "  DCT 128bit mode width: %s\n",
			 (dclr & BIT(11)) ?  "128b" : "64b");
782

783 784 785 786 787
	edac_dbg(1, "  x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",
		 (dclr & BIT(12)) ?  "yes" : "no",
		 (dclr & BIT(13)) ?  "yes" : "no",
		 (dclr & BIT(14)) ?  "yes" : "no",
		 (dclr & BIT(15)) ?  "yes" : "no");
788 789
}

790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805
/*
 * The Address Mask should be a contiguous set of bits in the non-interleaved
 * case. So to check for CS interleaving, find the most- and least-significant
 * bits of the mask, generate a contiguous bitmask, and compare the two.
 */
static bool f17_cs_interleaved(struct amd64_pvt *pvt, u8 ctrl, int cs)
{
	u32 mask = pvt->csels[ctrl].csmasks[cs >> 1];
	u32 msb = fls(mask) - 1, lsb = ffs(mask) - 1;
	u32 test_mask = GENMASK(msb, lsb);

	edac_dbg(1, "mask=0x%08x test_mask=0x%08x\n", mask, test_mask);

	return mask ^ test_mask;
}

806 807
static void debug_display_dimm_sizes_df(struct amd64_pvt *pvt, u8 ctrl)
{
808
	int dimm, size0, size1, cs0, cs1;
809 810 811 812 813

	edac_printk(KERN_DEBUG, EDAC_MC, "UMC%d chip selects:\n", ctrl);

	for (dimm = 0; dimm < 4; dimm++) {
		size0 = 0;
814
		cs0 = dimm * 2;
815

816 817
		if (csrow_enabled(cs0, ctrl, pvt))
			size0 = pvt->ops->dbam_to_cs(pvt, ctrl, 0, cs0);
818 819

		size1 = 0;
820 821
		cs1 = dimm * 2 + 1;

822 823 824 825 826 827 828 829 830 831 832 833 834
		if (csrow_enabled(cs1, ctrl, pvt)) {
			/*
			 * CS interleaving is only supported if both CSes have
			 * the same amount of memory. Because they are
			 * interleaved, it will look like both CSes have the
			 * full amount of memory. Save the size for both as
			 * half the amount we found on CS0, if interleaved.
			 */
			if (f17_cs_interleaved(pvt, ctrl, cs1))
				size1 = size0 = (size0 >> 1);
			else
				size1 = pvt->ops->dbam_to_cs(pvt, ctrl, 0, cs1);
		}
835 836

		amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n",
837 838
				cs0,	size0,
				cs1,	size1);
839 840 841 842 843 844 845 846
	}
}

static void __dump_misc_regs_df(struct amd64_pvt *pvt)
{
	struct amd64_umc *umc;
	u32 i, tmp, umc_base;

847
	for_each_umc(i) {
848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885
		umc_base = get_umc_base(i);
		umc = &pvt->umc[i];

		edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg);
		edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);
		edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);
		edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);

		amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ECC_BAD_SYMBOL, &tmp);
		edac_dbg(1, "UMC%d ECC bad symbol: 0x%x\n", i, tmp);

		amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_UMC_CAP, &tmp);
		edac_dbg(1, "UMC%d UMC cap: 0x%x\n", i, tmp);
		edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi);

		edac_dbg(1, "UMC%d ECC capable: %s, ChipKill ECC capable: %s\n",
				i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no",
				    (umc->umc_cap_hi & BIT(31)) ? "yes" : "no");
		edac_dbg(1, "UMC%d All DIMMs support ECC: %s\n",
				i, (umc->umc_cfg & BIT(12)) ? "yes" : "no");
		edac_dbg(1, "UMC%d x4 DIMMs present: %s\n",
				i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no");
		edac_dbg(1, "UMC%d x16 DIMMs present: %s\n",
				i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no");

		if (pvt->dram_type == MEM_LRDDR4) {
			amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ADDR_CFG, &tmp);
			edac_dbg(1, "UMC%d LRDIMM %dx rank multiply\n",
					i, 1 << ((tmp >> 4) & 0x3));
		}

		debug_display_dimm_sizes_df(pvt, i);
	}

	edac_dbg(1, "F0x104 (DRAM Hole Address): 0x%08x, base: 0x%08x\n",
		 pvt->dhar, dhar_base(pvt));
}

886
/* Display and decode various NB registers for debug purposes. */
887
static void __dump_misc_regs(struct amd64_pvt *pvt)
888
{
889
	edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
890

891 892
	edac_dbg(1, "  NB two channel DRAM capable: %s\n",
		 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no");
893

894 895 896
	edac_dbg(1, "  ECC capable: %s, ChipKill ECC capable: %s\n",
		 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no",
		 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no");
897

898
	debug_dump_dramcfg_low(pvt, pvt->dclr0, 0);
899

900
	edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);
901

902 903
	edac_dbg(1, "F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, offset: 0x%08x\n",
		 pvt->dhar, dhar_base(pvt),
904 905
		 (pvt->fam == 0xf) ? k8_dhar_offset(pvt)
				   : f10_dhar_offset(pvt));
906

907
	debug_display_dimm_sizes(pvt, 0);
908

909
	/* everything below this point is Fam10h and above */
910
	if (pvt->fam == 0xf)
911
		return;
912

913
	debug_display_dimm_sizes(pvt, 1);
914

915
	/* Only if NOT ganged does dclr1 have valid info */
916
	if (!dct_ganging_enabled(pvt))
917
		debug_dump_dramcfg_low(pvt, pvt->dclr1, 1);
918 919
}

920 921 922 923 924 925 926 927 928 929
/* Display and decode various NB registers for debug purposes. */
static void dump_misc_regs(struct amd64_pvt *pvt)
{
	if (pvt->umc)
		__dump_misc_regs_df(pvt);
	else
		__dump_misc_regs(pvt);

	edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");

930
	amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz);
931 932
}

933
/*
934
 * See BKDG, F2x[1,0][5C:40], F2[1,0][6C:60]
935
 */
936
static void prep_chip_selects(struct amd64_pvt *pvt)
937
{
938
	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {
939 940
		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8;
941
	} else if (pvt->fam == 0x15 && pvt->model == 0x30) {
942 943
		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4;
		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2;
944 945 946 947 948 949 950 951
	} else if (pvt->fam >= 0x17) {
		int umc;

		for_each_umc(umc) {
			pvt->csels[umc].b_cnt = 8;
			pvt->csels[umc].m_cnt = 4;
		}

952
	} else {
953 954
		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4;
955 956 957
	}
}

958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983
static void read_umc_base_mask(struct amd64_pvt *pvt)
{
	int cs, umc;

	for_each_umc(umc) {
		u32 umc_base_reg = get_umc_base(umc) + UMCCH_BASE_ADDR;
		u32 umc_mask_reg = get_umc_base(umc) + UMCCH_ADDR_MASK;

		for_each_chip_select(cs, 0, pvt) {
			u32 *base = &pvt->csels[umc].csbases[cs];
			u32 *mask = &pvt->csels[umc].csmasks[cs];

			u32 base_reg = umc_base_reg + (cs * 4);
			u32 mask_reg = umc_mask_reg + ((cs >> 1) * 4);

			if (!amd_smn_read(pvt->mc_node_id, base_reg, base))
				edac_dbg(0, "  DCSB%d[%d]=0x%08x reg: 0x%x\n",
					 umc, cs, *base, base_reg);

			if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask))
				edac_dbg(0, "    DCSM%d[%d]=0x%08x reg: 0x%x\n",
					 umc, cs, *mask, mask_reg);
		}
	}
}

984
/*
985
 * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers
986
 */
987
static void read_dct_base_mask(struct amd64_pvt *pvt)
988
{
989
	int cs;
990

991
	prep_chip_selects(pvt);
992

993 994
	if (pvt->umc)
		return read_umc_base_mask(pvt);
995

996
	for_each_chip_select(cs, 0, pvt) {
997 998
		int reg0   = DCSB0 + (cs * 4);
		int reg1   = DCSB1 + (cs * 4);
999 1000
		u32 *base0 = &pvt->csels[0].csbases[cs];
		u32 *base1 = &pvt->csels[1].csbases[cs];
1001

1002 1003 1004
		if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0))
			edac_dbg(0, "  DCSB0[%d]=0x%08x reg: F2x%x\n",
				 cs, *base0, reg0);
1005

1006 1007
		if (pvt->fam == 0xf)
			continue;
1008

1009 1010 1011 1012
		if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, base1))
			edac_dbg(0, "  DCSB1[%d]=0x%08x reg: F2x%x\n",
				 cs, *base1, (pvt->fam == 0x10) ? reg1
							: reg0);
1013 1014
	}

1015
	for_each_chip_select_mask(cs, 0, pvt) {
1016 1017
		int reg0   = DCSM0 + (cs * 4);
		int reg1   = DCSM1 + (cs * 4);
1018 1019
		u32 *mask0 = &pvt->csels[0].csmasks[cs];
		u32 *mask1 = &pvt->csels[1].csmasks[cs];
1020

1021 1022 1023
		if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0))
			edac_dbg(0, "    DCSM0[%d]=0x%08x reg: F2x%x\n",
				 cs, *mask0, reg0);
1024

1025 1026
		if (pvt->fam == 0xf)
			continue;
1027

1028 1029 1030 1031
		if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1))
			edac_dbg(0, "    DCSM1[%d]=0x%08x reg: F2x%x\n",
				 cs, *mask1, (pvt->fam == 0x10) ? reg1
							: reg0);
1032 1033 1034
	}
}

1035
static void determine_memory_type(struct amd64_pvt *pvt)
1036
{
1037
	u32 dram_ctrl, dcsm;
1038

1039 1040 1041 1042 1043 1044 1045 1046 1047
	switch (pvt->fam) {
	case 0xf:
		if (pvt->ext_model >= K8_REV_F)
			goto ddr3;

		pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR;
		return;

	case 0x10:
1048
		if (pvt->dchr0 & DDR3_MODE)
1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075
			goto ddr3;

		pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2;
		return;

	case 0x15:
		if (pvt->model < 0x60)
			goto ddr3;

		/*
		 * Model 0x60h needs special handling:
		 *
		 * We use a Chip Select value of '0' to obtain dcsm.
		 * Theoretically, it is possible to populate LRDIMMs of different
		 * 'Rank' value on a DCT. But this is not the common case. So,
		 * it's reasonable to assume all DIMMs are going to be of same
		 * 'type' until proven otherwise.
		 */
		amd64_read_dct_pci_cfg(pvt, 0, DRAM_CONTROL, &dram_ctrl);
		dcsm = pvt->csels[0].csmasks[0];

		if (((dram_ctrl >> 8) & 0x7) == 0x2)
			pvt->dram_type = MEM_DDR4;
		else if (pvt->dclr0 & BIT(16))
			pvt->dram_type = MEM_DDR3;
		else if (dcsm & 0x3)
			pvt->dram_type = MEM_LRDDR3;
1076
		else
1077
			pvt->dram_type = MEM_RDDR3;
1078

1079 1080 1081 1082 1083
		return;

	case 0x16:
		goto ddr3;

1084
	case 0x17:
1085
	case 0x18:
1086 1087 1088 1089 1090 1091 1092 1093
		if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5))
			pvt->dram_type = MEM_LRDDR4;
		else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4))
			pvt->dram_type = MEM_RDDR4;
		else
			pvt->dram_type = MEM_DDR4;
		return;

1094 1095 1096 1097 1098
	default:
		WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam);
		pvt->dram_type = MEM_EMPTY;
	}
	return;
1099

1100 1101
ddr3:
	pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3;
1102 1103
}

1104
/* Get the number of DCT channels the memory controller is using. */
1105 1106
static int k8_early_channel_count(struct amd64_pvt *pvt)
{
1107
	int flag;
1108

1109
	if (pvt->ext_model >= K8_REV_F)
1110
		/* RevF (NPT) and later */
1111
		flag = pvt->dclr0 & WIDTH_128;
1112
	else
1113 1114 1115 1116 1117 1118 1119 1120 1121
		/* RevE and earlier */
		flag = pvt->dclr0 & REVE_WIDTH_128;

	/* not used */
	pvt->dclr1 = 0;

	return (flag) ? 2 : 1;
}

1122
/* On F10h and later ErrAddr is MC4_ADDR[47:1] */
1123
static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m)
1124
{
1125 1126
	u16 mce_nid = amd_get_nb_id(m->extcpu);
	struct mem_ctl_info *mci;
1127 1128
	u8 start_bit = 1;
	u8 end_bit   = 47;
1129 1130 1131 1132 1133 1134 1135
	u64 addr;

	mci = edac_mc_find(mce_nid);
	if (!mci)
		return 0;

	pvt = mci->pvt_info;
1136

1137
	if (pvt->fam == 0xf) {
1138 1139 1140 1141
		start_bit = 3;
		end_bit   = 39;
	}

1142
	addr = m->addr & GENMASK_ULL(end_bit, start_bit);
1143 1144 1145 1146

	/*
	 * Erratum 637 workaround
	 */
1147
	if (pvt->fam == 0x15) {
1148 1149
		u64 cc6_base, tmp_addr;
		u32 tmp;
1150
		u8 intlv_en;
1151

1152
		if ((addr & GENMASK_ULL(47, 24)) >> 24 != 0x00fdf7)
1153 1154 1155 1156 1157 1158 1159
			return addr;


		amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp);
		intlv_en = tmp >> 21 & 0x7;

		/* add [47:27] + 3 trailing bits */
1160
		cc6_base  = (tmp & GENMASK_ULL(20, 0)) << 3;
1161 1162 1163 1164 1165 1166 1167 1168

		/* reverse and add DramIntlvEn */
		cc6_base |= intlv_en ^ 0x7;

		/* pin at [47:24] */
		cc6_base <<= 24;

		if (!intlv_en)
1169
			return cc6_base | (addr & GENMASK_ULL(23, 0));
1170 1171 1172 1173

		amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp);

							/* faster log2 */
1174
		tmp_addr  = (addr & GENMASK_ULL(23, 12)) << __fls(intlv_en + 1);
1175 1176

		/* OR DramIntlvSel into bits [14:12] */
1177
		tmp_addr |= (tmp & GENMASK_ULL(23, 21)) >> 9;
1178 1179

		/* add remaining [11:0] bits from original MC4_ADDR */
1180
		tmp_addr |= addr & GENMASK_ULL(11, 0);
1181 1182 1183 1184 1185

		return cc6_base | tmp_addr;
	}

	return addr;
1186 1187
}

1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203
static struct pci_dev *pci_get_related_function(unsigned int vendor,
						unsigned int device,
						struct pci_dev *related)
{
	struct pci_dev *dev = NULL;

	while ((dev = pci_get_device(vendor, device, dev))) {
		if (pci_domain_nr(dev->bus) == pci_domain_nr(related->bus) &&
		    (dev->bus->number == related->bus->number) &&
		    (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn)))
			break;
	}

	return dev;
}

1204
static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
1205
{
1206
	struct amd_northbridge *nb;
1207 1208
	struct pci_dev *f1 = NULL;
	unsigned int pci_func;
1209
	int off = range << 3;
1210
	u32 llim;
1211

1212 1213
	amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off,  &pvt->ranges[range].base.lo);
	amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo);
1214

1215
	if (pvt->fam == 0xf)
1216
		return;
1217

1218 1219
	if (!dram_rw(pvt, range))
		return;
1220

1221 1222
	amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off,  &pvt->ranges[range].base.hi);
	amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi);
1223

1224
	/* F15h: factor in CC6 save area by reading dst node's limit reg */
1225
	if (pvt->fam != 0x15)
1226
		return;
1227

1228 1229 1230
	nb = node_to_amd_nb(dram_dst_node(pvt, range));
	if (WARN_ON(!nb))
		return;
1231

1232 1233 1234 1235 1236 1237
	if (pvt->model == 0x60)
		pci_func = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1;
	else if (pvt->model == 0x30)
		pci_func = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1;
	else
		pci_func = PCI_DEVICE_ID_AMD_15H_NB_F1;
1238 1239

	f1 = pci_get_related_function(nb->misc->vendor, pci_func, nb->misc);
1240 1241
	if (WARN_ON(!f1))
		return;
1242

1243
	amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim);
1244

1245
	pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0);
1246

1247 1248
				    /* {[39:27],111b} */
	pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16;
1249

1250
	pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0);
1251

1252 1253 1254 1255
				    /* [47:40] */
	pvt->ranges[range].lim.hi |= llim >> 13;

	pci_dev_put(f1);
1256 1257
}

1258
static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
1259
				    struct err_info *err)
1260
{
1261
	struct amd64_pvt *pvt = mci->pvt_info;
1262

1263
	error_address_to_page_and_offset(sys_addr, err);
1264 1265 1266 1267 1268

	/*
	 * Find out which node the error address belongs to. This may be
	 * different from the node that detected the error.
	 */
1269 1270
	err->src_mci = find_mc_by_sys_addr(mci, sys_addr);
	if (!err->src_mci) {
1271 1272
		amd64_mc_err(mci, "failed to map error addr 0x%lx to a node\n",
			     (unsigned long)sys_addr);
1273
		err->err_code = ERR_NODE;
1274 1275 1276 1277
		return;
	}

	/* Now map the sys_addr to a CSROW */
1278 1279 1280
	err->csrow = sys_addr_to_csrow(err->src_mci, sys_addr);
	if (err->csrow < 0) {
		err->err_code = ERR_CSROW;
1281 1282 1283
		return;
	}

1284
	/* CHIPKILL enabled */
1285
	if (pvt->nbcfg & NBCFG_CHIPKILL) {
1286 1287
		err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome);
		if (err->channel < 0) {
1288 1289 1290 1291 1292
			/*
			 * Syndrome didn't map, so we don't know which of the
			 * 2 DIMMs is in error. So we need to ID 'both' of them
			 * as suspect.
			 */
1293
			amd64_mc_warn(err->src_mci, "unknown syndrome 0x%04x - "
1294
				      "possible error reporting race\n",
1295 1296
				      err->syndrome);
			err->err_code = ERR_CHANNEL;
1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307
			return;
		}
	} else {
		/*
		 * non-chipkill ecc mode
		 *
		 * The k8 documentation is unclear about how to determine the
		 * channel number when using non-chipkill memory.  This method
		 * was obtained from email communication with someone at AMD.
		 * (Wish the email was placed in this comment - norsk)
		 */
1308
		err->channel = ((sys_addr & BIT(3)) != 0);
1309 1310 1311
	}
}

1312
static int ddr2_cs_size(unsigned i, bool dct_width)
1313
{
1314
	unsigned shift = 0;
1315

1316 1317 1318 1319
	if (i <= 2)
		shift = i;
	else if (!(i & 0x1))
		shift = i >> 1;
1320
	else
1321
		shift = (i + 1) >> 1;
1322

1323 1324 1325 1326
	return 128 << (shift + !!dct_width);
}

static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1327
				  unsigned cs_mode, int cs_mask_nr)
1328 1329 1330 1331 1332 1333 1334 1335
{
	u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;

	if (pvt->ext_model >= K8_REV_F) {
		WARN_ON(cs_mode > 11);
		return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
	}
	else if (pvt->ext_model >= K8_REV_D) {
1336
		unsigned diff;
1337 1338
		WARN_ON(cs_mode > 10);

1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365
		/*
		 * the below calculation, besides trying to win an obfuscated C
		 * contest, maps cs_mode values to DIMM chip select sizes. The
		 * mappings are:
		 *
		 * cs_mode	CS size (mb)
		 * =======	============
		 * 0		32
		 * 1		64
		 * 2		128
		 * 3		128
		 * 4		256
		 * 5		512
		 * 6		256
		 * 7		512
		 * 8		1024
		 * 9		1024
		 * 10		2048
		 *
		 * Basically, it calculates a value with which to shift the
		 * smallest CS size of 32MB.
		 *
		 * ddr[23]_cs_size have a similar purpose.
		 */
		diff = cs_mode/3 + (unsigned)(cs_mode > 5);

		return 32 << (cs_mode - diff);
1366 1367 1368 1369 1370
	}
	else {
		WARN_ON(cs_mode > 6);
		return 32 << cs_mode;
	}
1371 1372
}

1373 1374 1375 1376 1377 1378 1379 1380
/*
 * Get the number of DCT channels in use.
 *
 * Return:
 *	number of Memory Channels in operation
 * Pass back:
 *	contents of the DCL0_LOW register
 */
1381
static int f1x_early_channel_count(struct amd64_pvt *pvt)
1382
{
1383
	int i, j, channels = 0;
1384

1385
	/* On F10h, if we are in 128 bit mode, then we are using 2 channels */
1386
	if (pvt->fam == 0x10 && (pvt->dclr0 & WIDTH_128))
1387
		return 2;
1388 1389

	/*
1390 1391 1392
	 * Need to check if in unganged mode: In such, there are 2 channels,
	 * but they are not in 128 bit mode and thus the above 'dclr0' status
	 * bit will be OFF.
1393 1394 1395 1396
	 *
	 * Need to check DCT0[0] and DCT1[0] to see if only one of them has
	 * their CSEnable bit on. If so, then SINGLE DIMM case.
	 */
1397
	edac_dbg(0, "Data width is not 128 bits - need more decoding\n");
1398

1399 1400 1401 1402 1403
	/*
	 * Check DRAM Bank Address Mapping values for each DIMM to see if there
	 * is more than just one DIMM present in unganged mode. Need to check
	 * both controllers since DIMMs can be placed in either one.
	 */
1404 1405
	for (i = 0; i < 2; i++) {
		u32 dbam = (i ? pvt->dbam1 : pvt->dbam0);
1406

1407 1408 1409 1410 1411 1412
		for (j = 0; j < 4; j++) {
			if (DBAM_DIMM(j, dbam) > 0) {
				channels++;
				break;
			}
		}
1413 1414
	}

1415 1416 1417
	if (channels > 2)
		channels = 2;

1418
	amd64_info("MCT channel count: %d\n", channels);
1419 1420 1421 1422

	return channels;
}

1423 1424 1425 1426 1427
static int f17_early_channel_count(struct amd64_pvt *pvt)
{
	int i, channels = 0;

	/* SDP Control bit 31 (SdpInit) is clear for unused UMC channels */
1428
	for_each_umc(i)
1429 1430 1431 1432 1433 1434 1435
		channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT);

	amd64_info("MCT channel count: %d\n", channels);

	return channels;
}

1436
static int ddr3_cs_size(unsigned i, bool dct_width)
1437
{
1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457
	unsigned shift = 0;
	int cs_size = 0;

	if (i == 0 || i == 3 || i == 4)
		cs_size = -1;
	else if (i <= 2)
		shift = i;
	else if (i == 12)
		shift = 7;
	else if (!(i & 0x1))
		shift = i >> 1;
	else
		shift = (i + 1) >> 1;

	if (cs_size != -1)
		cs_size = (128 * (1 << !!dct_width)) << shift;

	return cs_size;
}

1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492
static int ddr3_lrdimm_cs_size(unsigned i, unsigned rank_multiply)
{
	unsigned shift = 0;
	int cs_size = 0;

	if (i < 4 || i == 6)
		cs_size = -1;
	else if (i == 12)
		shift = 7;
	else if (!(i & 0x1))
		shift = i >> 1;
	else
		shift = (i + 1) >> 1;

	if (cs_size != -1)
		cs_size = rank_multiply * (128 << shift);

	return cs_size;
}

static int ddr4_cs_size(unsigned i)
{
	int cs_size = 0;

	if (i == 0)
		cs_size = -1;
	else if (i == 1)
		cs_size = 1024;
	else
		/* Min cs_size = 1G */
		cs_size = 1024 * (1 << (i >> 1));

	return cs_size;
}

1493
static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1494
				   unsigned cs_mode, int cs_mask_nr)
1495 1496 1497 1498
{
	u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;

	WARN_ON(cs_mode > 11);
1499 1500

	if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE)
1501
		return ddr3_cs_size(cs_mode, dclr & WIDTH_128);
1502
	else
1503 1504 1505 1506 1507 1508 1509
		return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
}

/*
 * F15h supports only 64bit DCT interfaces
 */
static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1510
				   unsigned cs_mode, int cs_mask_nr)
1511 1512
{
	WARN_ON(cs_mode > 12);
1513

1514
	return ddr3_cs_size(cs_mode, false);
1515 1516
}

1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547
/* F15h M60h supports DDR4 mapping as well.. */
static int f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
					unsigned cs_mode, int cs_mask_nr)
{
	int cs_size;
	u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr];

	WARN_ON(cs_mode > 12);

	if (pvt->dram_type == MEM_DDR4) {
		if (cs_mode > 9)
			return -1;

		cs_size = ddr4_cs_size(cs_mode);
	} else if (pvt->dram_type == MEM_LRDDR3) {
		unsigned rank_multiply = dcsm & 0xf;

		if (rank_multiply == 3)
			rank_multiply = 4;
		cs_size = ddr3_lrdimm_cs_size(cs_mode, rank_multiply);
	} else {
		/* Minimum cs size is 512mb for F15hM60h*/
		if (cs_mode == 0x1)
			return -1;

		cs_size = ddr3_cs_size(cs_mode, false);
	}

	return cs_size;
}

1548
/*
1549
 * F16h and F15h model 30h have only limited cs_modes.
1550 1551
 */
static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1552
				unsigned cs_mode, int cs_mask_nr)
1553 1554 1555 1556 1557 1558 1559 1560 1561 1562
{
	WARN_ON(cs_mode > 12);

	if (cs_mode == 6 || cs_mode == 8 ||
	    cs_mode == 9 || cs_mode == 12)
		return -1;
	else
		return ddr3_cs_size(cs_mode, false);
}

1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579
static int f17_base_addr_to_cs_size(struct amd64_pvt *pvt, u8 umc,
				    unsigned int cs_mode, int csrow_nr)
{
	u32 base_addr = pvt->csels[umc].csbases[csrow_nr];

	/*  Each mask is used for every two base addresses. */
	u32 addr_mask = pvt->csels[umc].csmasks[csrow_nr >> 1];

	/*  Register [31:1] = Address [39:9]. Size is in kBs here. */
	u32 size = ((addr_mask >> 1) - (base_addr >> 1) + 1) >> 1;

	edac_dbg(1, "BaseAddr: 0x%x, AddrMask: 0x%x\n", base_addr, addr_mask);

	/* Return size in MBs. */
	return size >> 10;
}

1580
static void read_dram_ctl_register(struct amd64_pvt *pvt)
1581 1582
{

1583
	if (pvt->fam == 0xf)
1584 1585
		return;

1586
	if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) {
1587 1588
		edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",
			 pvt->dct_sel_lo, dct_sel_baseaddr(pvt));
1589

1590 1591
		edac_dbg(0, "  DCTs operate in %s mode\n",
			 (dct_ganging_enabled(pvt) ? "ganged" : "unganged"));
1592 1593

		if (!dct_ganging_enabled(pvt))
1594 1595
			edac_dbg(0, "  Address range split per DCT: %s\n",
				 (dct_high_range_enabled(pvt) ? "yes" : "no"));
1596

1597 1598 1599
		edac_dbg(0, "  data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n",
			 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),
			 (dct_memory_cleared(pvt) ? "yes" : "no"));
1600

1601 1602 1603 1604
		edac_dbg(0, "  channel interleave: %s, "
			 "interleave bits selector: 0x%x\n",
			 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"),
			 dct_sel_interleave_addr(pvt));
1605 1606
	}

1607
	amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi);
1608 1609
}

1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626
/*
 * Determine channel (DCT) based on the interleaving mode (see F15h M30h BKDG,
 * 2.10.12 Memory Interleaving Modes).
 */
static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
				     u8 intlv_en, int num_dcts_intlv,
				     u32 dct_sel)
{
	u8 channel = 0;
	u8 select;

	if (!(intlv_en))
		return (u8)(dct_sel);

	if (num_dcts_intlv == 2) {
		select = (sys_addr >> 8) & 0x3;
		channel = select ? 0x3 : 0;
1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637
	} else if (num_dcts_intlv == 4) {
		u8 intlv_addr = dct_sel_interleave_addr(pvt);
		switch (intlv_addr) {
		case 0x4:
			channel = (sys_addr >> 8) & 0x3;
			break;
		case 0x5:
			channel = (sys_addr >> 9) & 0x3;
			break;
		}
	}
1638 1639 1640
	return channel;
}

1641
/*
1642
 * Determine channel (DCT) based on the interleaving mode: F10h BKDG, 2.8.9 Memory
1643 1644
 * Interleaving Modes.
 */
1645
static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
1646
				bool hi_range_sel, u8 intlv_en)
1647
{
1648
	u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1;
1649 1650

	if (dct_ganging_enabled(pvt))
1651
		return 0;
1652

1653 1654
	if (hi_range_sel)
		return dct_sel_high;
1655

1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667
	/*
	 * see F2x110[DctSelIntLvAddr] - channel interleave mode
	 */
	if (dct_interleave_enabled(pvt)) {
		u8 intlv_addr = dct_sel_interleave_addr(pvt);

		/* return DCT select function: 0=DCT0, 1=DCT1 */
		if (!intlv_addr)
			return sys_addr >> 6 & 1;

		if (intlv_addr & 0x2) {
			u8 shift = intlv_addr & 0x1 ? 9 : 6;
1668
			u32 temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) & 1;
1669 1670 1671 1672

			return ((sys_addr >> shift) & 1) ^ temp;
		}

1673 1674 1675 1676 1677 1678
		if (intlv_addr & 0x4) {
			u8 shift = intlv_addr & 0x1 ? 9 : 8;

			return (sys_addr >> shift) & 1;
		}

1679 1680 1681 1682 1683
		return (sys_addr >> (12 + hweight8(intlv_en))) & 1;
	}

	if (dct_high_range_enabled(pvt))
		return ~dct_sel_high & 1;
1684 1685 1686 1687

	return 0;
}

1688
/* Convert the sys_addr to the normalized DCT address */
1689
static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range,
1690 1691
				 u64 sys_addr, bool hi_rng,
				 u32 dct_sel_base_addr)
1692 1693
{
	u64 chan_off;
1694 1695
	u64 dram_base		= get_dram_base(pvt, range);
	u64 hole_off		= f10_dhar_offset(pvt);
1696
	u64 dct_sel_base_off	= (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16;
1697

1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711
	if (hi_rng) {
		/*
		 * if
		 * base address of high range is below 4Gb
		 * (bits [47:27] at [31:11])
		 * DRAM address space on this DCT is hoisted above 4Gb	&&
		 * sys_addr > 4Gb
		 *
		 *	remove hole offset from sys_addr
		 * else
		 *	remove high range offset from sys_addr
		 */
		if ((!(dct_sel_base_addr >> 16) ||
		     dct_sel_base_addr < dhar_base(pvt)) &&
1712
		    dhar_valid(pvt) &&
1713
		    (sys_addr >= BIT_64(32)))
1714
			chan_off = hole_off;
1715 1716 1717
		else
			chan_off = dct_sel_base_off;
	} else {
1718 1719 1720 1721 1722 1723 1724 1725 1726
		/*
		 * if
		 * we have a valid hole		&&
		 * sys_addr > 4Gb
		 *
		 *	remove hole
		 * else
		 *	remove dram base to normalize to DCT address
		 */
1727
		if (dhar_valid(pvt) && (sys_addr >= BIT_64(32)))
1728
			chan_off = hole_off;
1729
		else
1730
			chan_off = dram_base;
1731 1732
	}

1733
	return (sys_addr & GENMASK_ULL(47,6)) - (chan_off & GENMASK_ULL(47,23));
1734 1735 1736 1737 1738 1739
}

/*
 * checks if the csrow passed in is marked as SPARED, if so returns the new
 * spare row
 */
1740
static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow)
1741
{
1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752
	int tmp_cs;

	if (online_spare_swap_done(pvt, dct) &&
	    csrow == online_spare_bad_dramcs(pvt, dct)) {

		for_each_chip_select(tmp_cs, dct, pvt) {
			if (chip_select_base(tmp_cs, dct, pvt) & 0x2) {
				csrow = tmp_cs;
				break;
			}
		}
1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764
	}
	return csrow;
}

/*
 * Iterate over the DRAM DCT "base" and "mask" registers looking for a
 * SystemAddr match on the specified 'ChannelSelect' and 'NodeID'
 *
 * Return:
 *	-EINVAL:  NOT FOUND
 *	0..csrow = Chip-Select Row
 */
1765
static int f1x_lookup_addr_in_dct(u64 in_addr, u8 nid, u8 dct)
1766 1767 1768
{
	struct mem_ctl_info *mci;
	struct amd64_pvt *pvt;
1769
	u64 cs_base, cs_mask;
1770 1771 1772
	int cs_found = -EINVAL;
	int csrow;

1773
	mci = edac_mc_find(nid);
1774 1775 1776 1777 1778
	if (!mci)
		return cs_found;

	pvt = mci->pvt_info;

1779
	edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct);
1780

1781 1782
	for_each_chip_select(csrow, dct, pvt) {
		if (!csrow_enabled(csrow, dct, pvt))
1783 1784
			continue;

1785
		get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask);
1786

1787 1788
		edac_dbg(1, "    CSROW=%d CSBase=0x%llx CSMask=0x%llx\n",
			 csrow, cs_base, cs_mask);
1789

1790
		cs_mask = ~cs_mask;
1791

1792 1793
		edac_dbg(1, "    (InputAddr & ~CSMask)=0x%llx (CSBase & ~CSMask)=0x%llx\n",
			 (in_addr & cs_mask), (cs_base & cs_mask));
1794

1795
		if ((in_addr & cs_mask) == (cs_base & cs_mask)) {
1796 1797 1798 1799
			if (pvt->fam == 0x15 && pvt->model >= 0x30) {
				cs_found =  csrow;
				break;
			}
1800
			cs_found = f10_process_possible_spare(pvt, dct, csrow);
1801

1802
			edac_dbg(1, " MATCH csrow=%d\n", cs_found);
1803 1804 1805 1806 1807 1808
			break;
		}
	}
	return cs_found;
}

1809 1810 1811 1812 1813
/*
 * See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is
 * swapped with a region located at the bottom of memory so that the GPU can use
 * the interleaved region and thus two channels.
 */
1814
static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr)
1815 1816 1817
{
	u32 swap_reg, swap_base, swap_limit, rgn_size, tmp_addr;

1818
	if (pvt->fam == 0x10) {
1819
		/* only revC3 and revE have that feature */
1820
		if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3))
1821 1822 1823
			return sys_addr;
	}

1824
	amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg);
1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842

	if (!(swap_reg & 0x1))
		return sys_addr;

	swap_base	= (swap_reg >> 3) & 0x7f;
	swap_limit	= (swap_reg >> 11) & 0x7f;
	rgn_size	= (swap_reg >> 20) & 0x7f;
	tmp_addr	= sys_addr >> 27;

	if (!(sys_addr >> 34) &&
	    (((tmp_addr >= swap_base) &&
	     (tmp_addr <= swap_limit)) ||
	     (tmp_addr < rgn_size)))
		return sys_addr ^ (u64)swap_base << 27;

	return sys_addr;
}

1843
/* For a given @dram_range, check if @sys_addr falls within it. */
1844
static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
1845
				  u64 sys_addr, int *chan_sel)
1846
{
1847
	int cs_found = -EINVAL;
1848
	u64 chan_addr;
1849
	u32 dct_sel_base;
1850
	u8 channel;
1851
	bool high_range = false;
1852

1853
	u8 node_id    = dram_dst_node(pvt, range);
1854
	u8 intlv_en   = dram_intlv_en(pvt, range);
1855
	u32 intlv_sel = dram_intlv_sel(pvt, range);
1856

1857 1858
	edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
		 range, sys_addr, get_dram_limit(pvt, range));
1859

1860 1861 1862 1863 1864 1865 1866 1867
	if (dhar_valid(pvt) &&
	    dhar_base(pvt) <= sys_addr &&
	    sys_addr < BIT_64(32)) {
		amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n",
			    sys_addr);
		return -EINVAL;
	}

1868
	if (intlv_en && (intlv_sel != ((sys_addr >> 12) & intlv_en)))
1869 1870
		return -EINVAL;

1871
	sys_addr = f1x_swap_interleaved_region(pvt, sys_addr);
1872

1873 1874 1875 1876 1877 1878 1879 1880 1881
	dct_sel_base = dct_sel_baseaddr(pvt);

	/*
	 * check whether addresses >= DctSelBaseAddr[47:27] are to be used to
	 * select between DCT0 and DCT1.
	 */
	if (dct_high_range_enabled(pvt) &&
	   !dct_ganging_enabled(pvt) &&
	   ((sys_addr >> 27) >= (dct_sel_base >> 11)))
1882
		high_range = true;
1883

1884
	channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en);
1885

1886
	chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr,
1887
					  high_range, dct_sel_base);
1888

1889 1890 1891 1892
	/* Remove node interleaving, see F1x120 */
	if (intlv_en)
		chan_addr = ((chan_addr >> (12 + hweight8(intlv_en))) << 12) |
			    (chan_addr & 0xfff);
1893

1894
	/* remove channel interleave */
1895 1896 1897
	if (dct_interleave_enabled(pvt) &&
	   !dct_high_range_enabled(pvt) &&
	   !dct_ganging_enabled(pvt)) {
1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911

		if (dct_sel_interleave_addr(pvt) != 1) {
			if (dct_sel_interleave_addr(pvt) == 0x3)
				/* hash 9 */
				chan_addr = ((chan_addr >> 10) << 9) |
					     (chan_addr & 0x1ff);
			else
				/* A[6] or hash 6 */
				chan_addr = ((chan_addr >> 7) << 6) |
					     (chan_addr & 0x3f);
		} else
			/* A[12] */
			chan_addr = ((chan_addr >> 13) << 12) |
				     (chan_addr & 0xfff);
1912 1913
	}

1914
	edac_dbg(1, "   Normalized DCT addr: 0x%llx\n", chan_addr);
1915

1916
	cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, channel);
1917

1918
	if (cs_found >= 0)
1919
		*chan_sel = channel;
1920

1921 1922 1923
	return cs_found;
}

1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960
static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
					u64 sys_addr, int *chan_sel)
{
	int cs_found = -EINVAL;
	int num_dcts_intlv = 0;
	u64 chan_addr, chan_offset;
	u64 dct_base, dct_limit;
	u32 dct_cont_base_reg, dct_cont_limit_reg, tmp;
	u8 channel, alias_channel, leg_mmio_hole, dct_sel, dct_offset_en;

	u64 dhar_offset		= f10_dhar_offset(pvt);
	u8 intlv_addr		= dct_sel_interleave_addr(pvt);
	u8 node_id		= dram_dst_node(pvt, range);
	u8 intlv_en		= dram_intlv_en(pvt, range);

	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg);
	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg);

	dct_offset_en		= (u8) ((dct_cont_base_reg >> 3) & BIT(0));
	dct_sel			= (u8) ((dct_cont_base_reg >> 4) & 0x7);

	edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
		 range, sys_addr, get_dram_limit(pvt, range));

	if (!(get_dram_base(pvt, range)  <= sys_addr) &&
	    !(get_dram_limit(pvt, range) >= sys_addr))
		return -EINVAL;

	if (dhar_valid(pvt) &&
	    dhar_base(pvt) <= sys_addr &&
	    sys_addr < BIT_64(32)) {
		amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n",
			    sys_addr);
		return -EINVAL;
	}

	/* Verify sys_addr is within DCT Range. */
1961 1962
	dct_base = (u64) dct_sel_baseaddr(pvt);
	dct_limit = (dct_cont_limit_reg >> 11) & 0x1FFF;
1963 1964

	if (!(dct_cont_base_reg & BIT(0)) &&
1965 1966
	    !(dct_base <= (sys_addr >> 27) &&
	      dct_limit >= (sys_addr >> 27)))
1967 1968 1969 1970 1971 1972 1973 1974
		return -EINVAL;

	/* Verify number of dct's that participate in channel interleaving. */
	num_dcts_intlv = (int) hweight8(intlv_en);

	if (!(num_dcts_intlv % 2 == 0) || (num_dcts_intlv > 4))
		return -EINVAL;

1975 1976 1977 1978 1979
	if (pvt->model >= 0x60)
		channel = f1x_determine_channel(pvt, sys_addr, false, intlv_en);
	else
		channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en,
						     num_dcts_intlv, dct_sel);
1980 1981

	/* Verify we stay within the MAX number of channels allowed */
1982
	if (channel > 3)
1983 1984 1985 1986 1987 1988 1989 1990
		return -EINVAL;

	leg_mmio_hole = (u8) (dct_cont_base_reg >> 1 & BIT(0));

	/* Get normalized DCT addr */
	if (leg_mmio_hole && (sys_addr >= BIT_64(32)))
		chan_offset = dhar_offset;
	else
1991
		chan_offset = dct_base << 27;
1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

	chan_addr = sys_addr - chan_offset;

	/* remove channel interleave */
	if (num_dcts_intlv == 2) {
		if (intlv_addr == 0x4)
			chan_addr = ((chan_addr >> 9) << 8) |
						(chan_addr & 0xff);
		else if (intlv_addr == 0x5)
			chan_addr = ((chan_addr >> 10) << 9) |
						(chan_addr & 0x1ff);
		else
			return -EINVAL;

	} else if (num_dcts_intlv == 4) {
		if (intlv_addr == 0x4)
			chan_addr = ((chan_addr >> 10) << 8) |
							(chan_addr & 0xff);
		else if (intlv_addr == 0x5)
			chan_addr = ((chan_addr >> 11) << 9) |
							(chan_addr & 0x1ff);
		else
			return -EINVAL;
	}

	if (dct_offset_en) {
		amd64_read_pci_cfg(pvt->F1,
				   DRAM_CONT_HIGH_OFF + (int) channel * 4,
				   &tmp);
2021
		chan_addr +=  (u64) ((tmp >> 11) & 0xfff) << 27;
2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048
	}

	f15h_select_dct(pvt, channel);

	edac_dbg(1, "   Normalized DCT addr: 0x%llx\n", chan_addr);

	/*
	 * Find Chip select:
	 * if channel = 3, then alias it to 1. This is because, in F15 M30h,
	 * there is support for 4 DCT's, but only 2 are currently functional.
	 * They are DCT0 and DCT3. But we have read all registers of DCT3 into
	 * pvt->csels[1]. So we need to use '1' here to get correct info.
	 * Refer F15 M30h BKDG Section 2.10 and 2.10.3 for clarifications.
	 */
	alias_channel =  (channel == 3) ? 1 : channel;

	cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, alias_channel);

	if (cs_found >= 0)
		*chan_sel = alias_channel;

	return cs_found;
}

static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt,
					u64 sys_addr,
					int *chan_sel)
2049
{
2050 2051
	int cs_found = -EINVAL;
	unsigned range;
2052

2053 2054
	for (range = 0; range < DRAM_RANGES; range++) {
		if (!dram_rw(pvt, range))
2055 2056
			continue;

2057 2058 2059 2060
		if (pvt->fam == 0x15 && pvt->model >= 0x30)
			cs_found = f15_m30h_match_to_this_node(pvt, range,
							       sys_addr,
							       chan_sel);
2061

2062 2063
		else if ((get_dram_base(pvt, range)  <= sys_addr) &&
			 (get_dram_limit(pvt, range) >= sys_addr)) {
2064
			cs_found = f1x_match_to_this_node(pvt, range,
2065
							  sys_addr, chan_sel);
2066 2067 2068 2069 2070 2071 2072 2073
			if (cs_found >= 0)
				break;
		}
	}
	return cs_found;
}

/*
2074 2075
 * For reference see "2.8.5 Routing DRAM Requests" in F10 BKDG. This code maps
 * a @sys_addr to NodeID, DCT (channel) and chip select (CSROW).
2076
 *
2077 2078
 * The @sys_addr is usually an error address received from the hardware
 * (MCX_ADDR).
2079
 */
2080
static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
2081
				     struct err_info *err)
2082 2083 2084
{
	struct amd64_pvt *pvt = mci->pvt_info;

2085
	error_address_to_page_and_offset(sys_addr, err);
2086

2087 2088 2089
	err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel);
	if (err->csrow < 0) {
		err->err_code = ERR_CSROW;
2090 2091 2092 2093 2094 2095 2096 2097
		return;
	}

	/*
	 * We need the syndromes for channel detection only when we're
	 * ganged. Otherwise @chan should already contain the channel at
	 * this point.
	 */
2098
	if (dct_ganging_enabled(pvt))
2099
		err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome);
2100 2101 2102
}

/*
2103
 * debug routine to display the memory sizes of all logical DIMMs and its
2104
 * CSROWs
2105
 */
2106
static void debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
2107
{
2108
	int dimm, size0, size1;
2109 2110
	u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;
	u32 dbam  = ctrl ? pvt->dbam1 : pvt->dbam0;
2111

2112
	if (pvt->fam == 0xf) {
2113
		/* K8 families < revF not supported yet */
2114
	       if (pvt->ext_model < K8_REV_F)
2115 2116 2117 2118 2119
			return;
	       else
		       WARN_ON(ctrl != 0);
	}

2120 2121 2122 2123 2124 2125 2126 2127 2128 2129
	if (pvt->fam == 0x10) {
		dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1
							   : pvt->dbam0;
		dcsb = (ctrl && !dct_ganging_enabled(pvt)) ?
				 pvt->csels[1].csbases :
				 pvt->csels[0].csbases;
	} else if (ctrl) {
		dbam = pvt->dbam0;
		dcsb = pvt->csels[1].csbases;
	}
2130 2131
	edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",
		 ctrl, dbam);
2132

2133 2134
	edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);

2135 2136 2137 2138
	/* Dump memory sizes for DIMM and its CSROWs */
	for (dimm = 0; dimm < 4; dimm++) {

		size0 = 0;
2139
		if (dcsb[dimm*2] & DCSB_CS_ENABLE)
2140 2141 2142
			/*
			 * For F15m60h, we need multiplier for LRDIMM cs_size
			 * calculation. We pass dimm value to the dbam_to_cs
2143 2144 2145
			 * mapper so we can find the multiplier from the
			 * corresponding DCSM.
			 */
2146
			size0 = pvt->ops->dbam_to_cs(pvt, ctrl,
2147 2148
						     DBAM_DIMM(dimm, dbam),
						     dimm);
2149 2150

		size1 = 0;
2151
		if (dcsb[dimm*2 + 1] & DCSB_CS_ENABLE)
2152
			size1 = pvt->ops->dbam_to_cs(pvt, ctrl,
2153 2154
						     DBAM_DIMM(dimm, dbam),
						     dimm);
2155

2156
		amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n",
2157 2158
				dimm * 2,     size0,
				dimm * 2 + 1, size1);
2159 2160 2161
	}
}

2162
static struct amd64_family_type family_types[] = {
2163
	[K8_CPUS] = {
2164
		.ctl_name = "K8",
2165
		.f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP,
2166
		.f2_id = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,
2167
		.ops = {
2168 2169 2170
			.early_channel_count	= k8_early_channel_count,
			.map_sysaddr_to_csrow	= k8_map_sysaddr_to_csrow,
			.dbam_to_cs		= k8_dbam_to_chip_select,
2171 2172 2173
		}
	},
	[F10_CPUS] = {
2174
		.ctl_name = "F10h",
2175
		.f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP,
2176
		.f2_id = PCI_DEVICE_ID_AMD_10H_NB_DRAM,
2177
		.ops = {
2178
			.early_channel_count	= f1x_early_channel_count,
2179
			.map_sysaddr_to_csrow	= f1x_map_sysaddr_to_csrow,
2180
			.dbam_to_cs		= f10_dbam_to_chip_select,
2181 2182 2183 2184
		}
	},
	[F15_CPUS] = {
		.ctl_name = "F15h",
2185
		.f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1,
2186
		.f2_id = PCI_DEVICE_ID_AMD_15H_NB_F2,
2187
		.ops = {
2188
			.early_channel_count	= f1x_early_channel_count,
2189
			.map_sysaddr_to_csrow	= f1x_map_sysaddr_to_csrow,
2190
			.dbam_to_cs		= f15_dbam_to_chip_select,
2191 2192
		}
	},
2193 2194 2195
	[F15_M30H_CPUS] = {
		.ctl_name = "F15h_M30h",
		.f1_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1,
2196
		.f2_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F2,
2197 2198 2199 2200 2201 2202
		.ops = {
			.early_channel_count	= f1x_early_channel_count,
			.map_sysaddr_to_csrow	= f1x_map_sysaddr_to_csrow,
			.dbam_to_cs		= f16_dbam_to_chip_select,
		}
	},
2203 2204 2205
	[F15_M60H_CPUS] = {
		.ctl_name = "F15h_M60h",
		.f1_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1,
2206
		.f2_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F2,
2207 2208 2209 2210 2211 2212
		.ops = {
			.early_channel_count	= f1x_early_channel_count,
			.map_sysaddr_to_csrow	= f1x_map_sysaddr_to_csrow,
			.dbam_to_cs		= f15_m60h_dbam_to_chip_select,
		}
	},
2213 2214 2215
	[F16_CPUS] = {
		.ctl_name = "F16h",
		.f1_id = PCI_DEVICE_ID_AMD_16H_NB_F1,
2216
		.f2_id = PCI_DEVICE_ID_AMD_16H_NB_F2,
2217 2218 2219 2220 2221 2222
		.ops = {
			.early_channel_count	= f1x_early_channel_count,
			.map_sysaddr_to_csrow	= f1x_map_sysaddr_to_csrow,
			.dbam_to_cs		= f16_dbam_to_chip_select,
		}
	},
2223 2224 2225
	[F16_M30H_CPUS] = {
		.ctl_name = "F16h_M30h",
		.f1_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F1,
2226
		.f2_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F2,
2227 2228 2229 2230 2231 2232
		.ops = {
			.early_channel_count	= f1x_early_channel_count,
			.map_sysaddr_to_csrow	= f1x_map_sysaddr_to_csrow,
			.dbam_to_cs		= f16_dbam_to_chip_select,
		}
	},
2233 2234 2235 2236 2237 2238 2239 2240 2241
	[F17_CPUS] = {
		.ctl_name = "F17h",
		.f0_id = PCI_DEVICE_ID_AMD_17H_DF_F0,
		.f6_id = PCI_DEVICE_ID_AMD_17H_DF_F6,
		.ops = {
			.early_channel_count	= f17_early_channel_count,
			.dbam_to_cs		= f17_base_addr_to_cs_size,
		}
	},
2242 2243 2244 2245 2246 2247 2248 2249 2250
	[F17_M10H_CPUS] = {
		.ctl_name = "F17h_M10h",
		.f0_id = PCI_DEVICE_ID_AMD_17H_M10H_DF_F0,
		.f6_id = PCI_DEVICE_ID_AMD_17H_M10H_DF_F6,
		.ops = {
			.early_channel_count	= f17_early_channel_count,
			.dbam_to_cs		= f17_base_addr_to_cs_size,
		}
	},
2251 2252 2253 2254 2255 2256 2257 2258 2259
	[F17_M30H_CPUS] = {
		.ctl_name = "F17h_M30h",
		.f0_id = PCI_DEVICE_ID_AMD_17H_M30H_DF_F0,
		.f6_id = PCI_DEVICE_ID_AMD_17H_M30H_DF_F6,
		.ops = {
			.early_channel_count	= f17_early_channel_count,
			.dbam_to_cs		= f17_base_addr_to_cs_size,
		}
	},
2260 2261
};

2262
/*
2263 2264 2265
 * These are tables of eigenvectors (one per line) which can be used for the
 * construction of the syndrome tables. The modified syndrome search algorithm
 * uses those to find the symbol in error and thus the DIMM.
2266
 *
2267
 * Algorithm courtesy of Ross LaFetra from AMD.
2268
 */
2269
static const u16 x4_vectors[] = {
2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305
	0x2f57, 0x1afe, 0x66cc, 0xdd88,
	0x11eb, 0x3396, 0x7f4c, 0xeac8,
	0x0001, 0x0002, 0x0004, 0x0008,
	0x1013, 0x3032, 0x4044, 0x8088,
	0x106b, 0x30d6, 0x70fc, 0xe0a8,
	0x4857, 0xc4fe, 0x13cc, 0x3288,
	0x1ac5, 0x2f4a, 0x5394, 0xa1e8,
	0x1f39, 0x251e, 0xbd6c, 0x6bd8,
	0x15c1, 0x2a42, 0x89ac, 0x4758,
	0x2b03, 0x1602, 0x4f0c, 0xca08,
	0x1f07, 0x3a0e, 0x6b04, 0xbd08,
	0x8ba7, 0x465e, 0x244c, 0x1cc8,
	0x2b87, 0x164e, 0x642c, 0xdc18,
	0x40b9, 0x80de, 0x1094, 0x20e8,
	0x27db, 0x1eb6, 0x9dac, 0x7b58,
	0x11c1, 0x2242, 0x84ac, 0x4c58,
	0x1be5, 0x2d7a, 0x5e34, 0xa718,
	0x4b39, 0x8d1e, 0x14b4, 0x28d8,
	0x4c97, 0xc87e, 0x11fc, 0x33a8,
	0x8e97, 0x497e, 0x2ffc, 0x1aa8,
	0x16b3, 0x3d62, 0x4f34, 0x8518,
	0x1e2f, 0x391a, 0x5cac, 0xf858,
	0x1d9f, 0x3b7a, 0x572c, 0xfe18,
	0x15f5, 0x2a5a, 0x5264, 0xa3b8,
	0x1dbb, 0x3b66, 0x715c, 0xe3f8,
	0x4397, 0xc27e, 0x17fc, 0x3ea8,
	0x1617, 0x3d3e, 0x6464, 0xb8b8,
	0x23ff, 0x12aa, 0xab6c, 0x56d8,
	0x2dfb, 0x1ba6, 0x913c, 0x7328,
	0x185d, 0x2ca6, 0x7914, 0x9e28,
	0x171b, 0x3e36, 0x7d7c, 0xebe8,
	0x4199, 0x82ee, 0x19f4, 0x2e58,
	0x4807, 0xc40e, 0x130c, 0x3208,
	0x1905, 0x2e0a, 0x5804, 0xac08,
	0x213f, 0x132a, 0xadfc, 0x5ba8,
	0x19a9, 0x2efe, 0xb5cc, 0x6f88,
2306 2307
};

2308
static const u16 x8_vectors[] = {
2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329
	0x0145, 0x028a, 0x2374, 0x43c8, 0xa1f0, 0x0520, 0x0a40, 0x1480,
	0x0211, 0x0422, 0x0844, 0x1088, 0x01b0, 0x44e0, 0x23c0, 0xed80,
	0x1011, 0x0116, 0x022c, 0x0458, 0x08b0, 0x8c60, 0x2740, 0x4e80,
	0x0411, 0x0822, 0x1044, 0x0158, 0x02b0, 0x2360, 0x46c0, 0xab80,
	0x0811, 0x1022, 0x012c, 0x0258, 0x04b0, 0x4660, 0x8cc0, 0x2780,
	0x2071, 0x40e2, 0xa0c4, 0x0108, 0x0210, 0x0420, 0x0840, 0x1080,
	0x4071, 0x80e2, 0x0104, 0x0208, 0x0410, 0x0820, 0x1040, 0x2080,
	0x8071, 0x0102, 0x0204, 0x0408, 0x0810, 0x1020, 0x2040, 0x4080,
	0x019d, 0x03d6, 0x136c, 0x2198, 0x50b0, 0xb2e0, 0x0740, 0x0e80,
	0x0189, 0x03ea, 0x072c, 0x0e58, 0x1cb0, 0x56e0, 0x37c0, 0xf580,
	0x01fd, 0x0376, 0x06ec, 0x0bb8, 0x1110, 0x2220, 0x4440, 0x8880,
	0x0163, 0x02c6, 0x1104, 0x0758, 0x0eb0, 0x2be0, 0x6140, 0xc280,
	0x02fd, 0x01c6, 0x0b5c, 0x1108, 0x07b0, 0x25a0, 0x8840, 0x6180,
	0x0801, 0x012e, 0x025c, 0x04b8, 0x1370, 0x26e0, 0x57c0, 0xb580,
	0x0401, 0x0802, 0x015c, 0x02b8, 0x22b0, 0x13e0, 0x7140, 0xe280,
	0x0201, 0x0402, 0x0804, 0x01b8, 0x11b0, 0x31a0, 0x8040, 0x7180,
	0x0101, 0x0202, 0x0404, 0x0808, 0x1010, 0x2020, 0x4040, 0x8080,
	0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
	0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000,
};

2330
static int decode_syndrome(u16 syndrome, const u16 *vectors, unsigned num_vecs,
2331
			   unsigned v_dim)
2332
{
2333 2334 2335 2336
	unsigned int i, err_sym;

	for (err_sym = 0; err_sym < num_vecs / v_dim; err_sym++) {
		u16 s = syndrome;
2337 2338
		unsigned v_idx =  err_sym * v_dim;
		unsigned v_end = (err_sym + 1) * v_dim;
2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350

		/* walk over all 16 bits of the syndrome */
		for (i = 1; i < (1U << 16); i <<= 1) {

			/* if bit is set in that eigenvector... */
			if (v_idx < v_end && vectors[v_idx] & i) {
				u16 ev_comp = vectors[v_idx++];

				/* ... and bit set in the modified syndrome, */
				if (s & i) {
					/* remove it. */
					s ^= ev_comp;
2351

2352 2353 2354
					if (!s)
						return err_sym;
				}
2355

2356 2357 2358 2359
			} else if (s & i)
				/* can't get to zero, move to next symbol */
				break;
		}
2360 2361
	}

2362
	edac_dbg(0, "syndrome(%x) not found\n", syndrome);
2363 2364
	return -1;
}
2365

2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407
static int map_err_sym_to_channel(int err_sym, int sym_size)
{
	if (sym_size == 4)
		switch (err_sym) {
		case 0x20:
		case 0x21:
			return 0;
			break;
		case 0x22:
		case 0x23:
			return 1;
			break;
		default:
			return err_sym >> 4;
			break;
		}
	/* x8 symbols */
	else
		switch (err_sym) {
		/* imaginary bits not in a DIMM */
		case 0x10:
			WARN(1, KERN_ERR "Invalid error symbol: 0x%x\n",
					  err_sym);
			return -1;
			break;

		case 0x11:
			return 0;
			break;
		case 0x12:
			return 1;
			break;
		default:
			return err_sym >> 3;
			break;
		}
	return -1;
}

static int get_channel_from_ecc_syndrome(struct mem_ctl_info *mci, u16 syndrome)
{
	struct amd64_pvt *pvt = mci->pvt_info;
2408 2409
	int err_sym = -1;

2410
	if (pvt->ecc_sym_sz == 8)
2411 2412
		err_sym = decode_syndrome(syndrome, x8_vectors,
					  ARRAY_SIZE(x8_vectors),
2413 2414
					  pvt->ecc_sym_sz);
	else if (pvt->ecc_sym_sz == 4)
2415 2416
		err_sym = decode_syndrome(syndrome, x4_vectors,
					  ARRAY_SIZE(x4_vectors),
2417
					  pvt->ecc_sym_sz);
2418
	else {
2419
		amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz);
2420
		return err_sym;
2421
	}
2422

2423
	return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz);
2424 2425
}

2426
static void __log_ecc_error(struct mem_ctl_info *mci, struct err_info *err,
2427
			    u8 ecc_type)
2428
{
2429 2430
	enum hw_event_mc_err_type err_type;
	const char *string;
2431

2432 2433 2434 2435
	if (ecc_type == 2)
		err_type = HW_EVENT_ERR_CORRECTED;
	else if (ecc_type == 1)
		err_type = HW_EVENT_ERR_UNCORRECTED;
2436 2437
	else if (ecc_type == 3)
		err_type = HW_EVENT_ERR_DEFERRED;
2438 2439
	else {
		WARN(1, "Something is rotten in the state of Denmark.\n");
2440 2441 2442
		return;
	}

2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453
	switch (err->err_code) {
	case DECODE_OK:
		string = "";
		break;
	case ERR_NODE:
		string = "Failed to map error addr to a node";
		break;
	case ERR_CSROW:
		string = "Failed to map error addr to a csrow";
		break;
	case ERR_CHANNEL:
2454 2455 2456 2457 2458 2459 2460
		string = "Unknown syndrome - possible error reporting race";
		break;
	case ERR_SYND:
		string = "MCA_SYND not valid - unknown syndrome and csrow";
		break;
	case ERR_NORM_ADDR:
		string = "Cannot decode normalized address";
2461 2462 2463 2464
		break;
	default:
		string = "WTF error";
		break;
2465
	}
2466 2467 2468 2469 2470

	edac_mc_handle_error(err_type, mci, 1,
			     err->page, err->offset, err->syndrome,
			     err->csrow, err->channel, -1,
			     string, "");
2471 2472
}

2473
static inline void decode_bus_error(int node_id, struct mce *m)
2474
{
2475 2476
	struct mem_ctl_info *mci;
	struct amd64_pvt *pvt;
2477
	u8 ecc_type = (m->status >> 45) & 0x3;
2478 2479
	u8 xec = XEC(m->status, 0x1f);
	u16 ec = EC(m->status);
2480 2481
	u64 sys_addr;
	struct err_info err;
2482

2483 2484 2485 2486 2487 2488
	mci = edac_mc_find(node_id);
	if (!mci)
		return;

	pvt = mci->pvt_info;

2489
	/* Bail out early if this was an 'observed' error */
2490
	if (PP(ec) == NBSL_PP_OBS)
2491
		return;
2492

2493 2494
	/* Do only ECC errors */
	if (xec && xec != F10_NBSL_EXT_ERR_ECC)
2495 2496
		return;

2497 2498
	memset(&err, 0, sizeof(err));

2499
	sys_addr = get_error_address(pvt, m);
2500

2501
	if (ecc_type == 2)
2502 2503 2504 2505
		err.syndrome = extract_syndrome(m->status);

	pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err);

2506
	__log_ecc_error(mci, &err, ecc_type);
2507 2508
}

2509 2510 2511 2512
/*
 * To find the UMC channel represented by this bank we need to match on its
 * instance_id. The instance_id of a bank is held in the lower 32 bits of its
 * IPID.
2513 2514 2515 2516
 *
 * Currently, we can derive the channel number by looking at the 6th nibble in
 * the instance_id. For example, instance_id=0xYXXXXX where Y is the channel
 * number.
2517
 */
2518
static int find_umc_channel(struct mce *m)
2519
{
2520
	return (m->ipid & GENMASK(31, 0)) >> 20;
2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541
}

static void decode_umc_error(int node_id, struct mce *m)
{
	u8 ecc_type = (m->status >> 45) & 0x3;
	struct mem_ctl_info *mci;
	struct amd64_pvt *pvt;
	struct err_info err;
	u64 sys_addr;

	mci = edac_mc_find(node_id);
	if (!mci)
		return;

	pvt = mci->pvt_info;

	memset(&err, 0, sizeof(err));

	if (m->status & MCI_STATUS_DEFERRED)
		ecc_type = 3;

2542
	err.channel = find_umc_channel(m);
2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559

	if (!(m->status & MCI_STATUS_SYNDV)) {
		err.err_code = ERR_SYND;
		goto log_error;
	}

	if (ecc_type == 2) {
		u8 length = (m->synd >> 18) & 0x3f;

		if (length)
			err.syndrome = (m->synd >> 32) & GENMASK(length - 1, 0);
		else
			err.err_code = ERR_CHANNEL;
	}

	err.csrow = m->synd & 0x7;

2560 2561 2562 2563 2564 2565 2566
	if (umc_normaddr_to_sysaddr(m->addr, pvt->mc_node_id, err.channel, &sys_addr)) {
		err.err_code = ERR_NORM_ADDR;
		goto log_error;
	}

	error_address_to_page_and_offset(sys_addr, &err);

2567 2568 2569 2570
log_error:
	__log_ecc_error(mci, &err, ecc_type);
}

2571
/*
2572 2573
 * Use pvt->F3 which contains the F3 CPU PCI device to get the related
 * F1 (AddrMap) and F2 (Dct) devices. Return negative value on error.
2574
 * Reserve F0 and F6 on systems with a UMC.
2575
 */
2576 2577 2578 2579 2580 2581
static int
reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2)
{
	if (pvt->umc) {
		pvt->F0 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);
		if (!pvt->F0) {
2582
			amd64_err("F0 not found, device 0x%x (broken BIOS?)\n", pci_id1);
2583 2584 2585 2586 2587 2588 2589 2590
			return -ENODEV;
		}

		pvt->F6 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3);
		if (!pvt->F6) {
			pci_dev_put(pvt->F0);
			pvt->F0 = NULL;

2591
			amd64_err("F6 not found: device 0x%x (broken BIOS?)\n", pci_id2);
2592 2593
			return -ENODEV;
		}
2594

2595 2596 2597 2598 2599 2600 2601
		edac_dbg(1, "F0: %s\n", pci_name(pvt->F0));
		edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
		edac_dbg(1, "F6: %s\n", pci_name(pvt->F6));

		return 0;
	}

2602
	/* Reserve the ADDRESS MAP Device */
2603
	pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);
2604
	if (!pvt->F1) {
2605
		amd64_err("F1 not found: device 0x%x (broken BIOS?)\n", pci_id1);
2606
		return -ENODEV;
2607 2608
	}

2609
	/* Reserve the DCT Device */
2610
	pvt->F2 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3);
2611
	if (!pvt->F2) {
2612 2613
		pci_dev_put(pvt->F1);
		pvt->F1 = NULL;
2614

2615 2616
		amd64_err("F2 not found: device 0x%x (broken BIOS?)\n", pci_id2);
		return -ENODEV;
2617
	}
2618

2619 2620 2621
	edac_dbg(1, "F1: %s\n", pci_name(pvt->F1));
	edac_dbg(1, "F2: %s\n", pci_name(pvt->F2));
	edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
2622 2623 2624 2625

	return 0;
}

2626
static void free_mc_sibling_devs(struct amd64_pvt *pvt)
2627
{
2628 2629 2630 2631 2632 2633 2634
	if (pvt->umc) {
		pci_dev_put(pvt->F0);
		pci_dev_put(pvt->F6);
	} else {
		pci_dev_put(pvt->F1);
		pci_dev_put(pvt->F2);
	}
2635 2636
}

2637 2638 2639 2640 2641 2642 2643
static void determine_ecc_sym_sz(struct amd64_pvt *pvt)
{
	pvt->ecc_sym_sz = 4;

	if (pvt->umc) {
		u8 i;

2644
		for_each_umc(i) {
2645
			/* Check enabled channels only: */
2646 2647 2648 2649 2650 2651 2652 2653
			if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {
				if (pvt->umc[i].ecc_ctrl & BIT(9)) {
					pvt->ecc_sym_sz = 16;
					return;
				} else if (pvt->umc[i].ecc_ctrl & BIT(7)) {
					pvt->ecc_sym_sz = 8;
					return;
				}
2654 2655
			}
		}
2656
	} else if (pvt->fam >= 0x10) {
2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679
		u32 tmp;

		amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
		/* F16h has only DCT0, so no need to read dbam1. */
		if (pvt->fam != 0x16)
			amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1);

		/* F10h, revD and later can do x8 ECC too. */
		if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25))
			pvt->ecc_sym_sz = 8;
	}
}

/*
 * Retrieve the hardware registers of the memory controller.
 */
static void __read_mc_regs_df(struct amd64_pvt *pvt)
{
	u8 nid = pvt->mc_node_id;
	struct amd64_umc *umc;
	u32 i, umc_base;

	/* Read registers from each UMC */
2680
	for_each_umc(i) {
2681 2682 2683 2684

		umc_base = get_umc_base(i);
		umc = &pvt->umc[i];

2685 2686
		amd_smn_read(nid, umc_base + UMCCH_DIMM_CFG, &umc->dimm_cfg);
		amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg);
2687 2688
		amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl);
		amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl);
2689
		amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi);
2690 2691 2692
	}
}

2693 2694 2695 2696
/*
 * Retrieve the hardware registers of the memory controller (this includes the
 * 'Address Map' and 'Misc' device regs)
 */
2697
static void read_mc_regs(struct amd64_pvt *pvt)
2698
{
2699
	unsigned int range;
2700 2701 2702 2703
	u64 msr_val;

	/*
	 * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since
2704
	 * those are Read-As-Zero.
2705
	 */
2706
	rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem);
2707
	edac_dbg(0, "  TOP_MEM:  0x%016llx\n", pvt->top_mem);
2708

2709
	/* Check first whether TOP_MEM2 is enabled: */
2710
	rdmsrl(MSR_K8_SYSCFG, msr_val);
2711
	if (msr_val & BIT(21)) {
2712
		rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2);
2713
		edac_dbg(0, "  TOP_MEM2: 0x%016llx\n", pvt->top_mem2);
2714
	} else {
2715
		edac_dbg(0, "  TOP_MEM2 disabled\n");
2716 2717 2718 2719 2720 2721 2722 2723
	}

	if (pvt->umc) {
		__read_mc_regs_df(pvt);
		amd64_read_pci_cfg(pvt->F0, DF_DHAR, &pvt->dhar);

		goto skip;
	}
2724

2725
	amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap);
2726

2727
	read_dram_ctl_register(pvt);
2728

2729 2730
	for (range = 0; range < DRAM_RANGES; range++) {
		u8 rw;
2731

2732 2733 2734 2735 2736 2737 2738
		/* read settings for this DRAM range */
		read_dram_base_limit_regs(pvt, range);

		rw = dram_rw(pvt, range);
		if (!rw)
			continue;

2739 2740 2741 2742
		edac_dbg(1, "  DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n",
			 range,
			 get_dram_base(pvt, range),
			 get_dram_limit(pvt, range));
2743

2744 2745 2746 2747 2748 2749
		edac_dbg(1, "   IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n",
			 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled",
			 (rw & 0x1) ? "R" : "-",
			 (rw & 0x2) ? "W" : "-",
			 dram_intlv_sel(pvt, range),
			 dram_dst_node(pvt, range));
2750 2751
	}

2752
	amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar);
2753
	amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0);
2754

2755
	amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare);
2756

2757 2758
	amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0);
	amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0);
2759

2760
	if (!dct_ganging_enabled(pvt)) {
2761 2762
		amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1);
		amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1);
2763
	}
2764

2765 2766 2767
skip:
	read_dct_base_mask(pvt);

2768 2769
	determine_memory_type(pvt);
	edac_dbg(1, "  DIMM type: %s\n", edac_mem_types[pvt->dram_type]);
2770

2771
	determine_ecc_sym_sz(pvt);
2772

2773
	dump_misc_regs(pvt);
2774 2775 2776 2777 2778 2779
}

/*
 * NOTE: CPU Revision Dependent code
 *
 * Input:
2780
 *	@csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1)
2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809
 *	k8 private pointer to -->
 *			DRAM Bank Address mapping register
 *			node_id
 *			DCL register where dual_channel_active is
 *
 * The DBAM register consists of 4 sets of 4 bits each definitions:
 *
 * Bits:	CSROWs
 * 0-3		CSROWs 0 and 1
 * 4-7		CSROWs 2 and 3
 * 8-11		CSROWs 4 and 5
 * 12-15	CSROWs 6 and 7
 *
 * Values range from: 0 to 15
 * The meaning of the values depends on CPU revision and dual-channel state,
 * see relevant BKDG more info.
 *
 * The memory controller provides for total of only 8 CSROWs in its current
 * architecture. Each "pair" of CSROWs normally represents just one DIMM in
 * single channel or two (2) DIMMs in dual channel mode.
 *
 * The following code logic collapses the various tables for CSROW based on CPU
 * revision.
 *
 * Returns:
 *	The number of PAGE_SIZE pages on the specified CSROW number it
 *	encompasses
 *
 */
2810
static u32 get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig)
2811
{
2812
	u32 dbam = dct ? pvt->dbam1 : pvt->dbam0;
2813 2814
	int csrow_nr = csrow_nr_orig;
	u32 cs_mode, nr_pages;
2815

2816 2817
	if (!pvt->umc)
		csrow_nr >>= 1;
2818

2819
	cs_mode = DBAM_DIMM(csrow_nr, dbam);
2820

2821 2822
	nr_pages   = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr);
	nr_pages <<= 20 - PAGE_SHIFT;
2823

2824
	edac_dbg(0, "csrow: %d, channel: %d, DBAM idx: %d\n",
2825
		    csrow_nr_orig, dct,  cs_mode);
2826
	edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);
2827 2828 2829 2830 2831 2832 2833 2834

	return nr_pages;
}

/*
 * Initialize the array of csrow attribute instances, based on the values
 * from pci config hardware registers.
 */
2835
static int init_csrows(struct mem_ctl_info *mci)
2836
{
2837
	struct amd64_pvt *pvt = mci->pvt_info;
2838
	enum edac_type edac_mode = EDAC_NONE;
2839
	struct csrow_info *csrow;
2840
	struct dimm_info *dimm;
2841
	int i, j, empty = 1;
2842
	int nr_pages = 0;
2843
	u32 val;
2844

2845 2846
	if (!pvt->umc) {
		amd64_read_pci_cfg(pvt->F3, NBCFG, &val);
2847

2848
		pvt->nbcfg = val;
2849

2850 2851 2852 2853
		edac_dbg(0, "node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",
			 pvt->mc_node_id, val,
			 !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE));
	}
2854

2855 2856 2857
	/*
	 * We iterate over DCT0 here but we look at DCT1 in parallel, if needed.
	 */
2858
	for_each_chip_select(i, 0, pvt) {
2859 2860
		bool row_dct0 = !!csrow_enabled(i, 0, pvt);
		bool row_dct1 = false;
2861

2862
		if (pvt->fam != 0xf)
2863 2864 2865
			row_dct1 = !!csrow_enabled(i, 1, pvt);

		if (!row_dct0 && !row_dct1)
2866 2867
			continue;

2868
		csrow = mci->csrows[i];
2869
		empty = 0;
2870 2871 2872 2873

		edac_dbg(1, "MC node: %d, csrow: %d\n",
			    pvt->mc_node_id, i);

2874
		if (row_dct0) {
2875
			nr_pages = get_csrow_nr_pages(pvt, 0, i);
2876 2877
			csrow->channels[0]->dimm->nr_pages = nr_pages;
		}
2878

2879
		/* K8 has only one DCT */
2880
		if (pvt->fam != 0xf && row_dct1) {
2881
			int row_dct1_pages = get_csrow_nr_pages(pvt, 1, i);
2882 2883 2884 2885

			csrow->channels[1]->dimm->nr_pages = row_dct1_pages;
			nr_pages += row_dct1_pages;
		}
2886

2887
		edac_dbg(1, "Total csrow%d pages: %u\n", i, nr_pages);
2888

2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900
		/* Determine DIMM ECC mode: */
		if (pvt->umc) {
			if (mci->edac_ctl_cap & EDAC_FLAG_S4ECD4ED)
				edac_mode = EDAC_S4ECD4ED;
			else if (mci->edac_ctl_cap & EDAC_FLAG_SECDED)
				edac_mode = EDAC_SECDED;

		} else if (pvt->nbcfg & NBCFG_ECC_ENABLE) {
			edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL)
					? EDAC_S4ECD4ED
					: EDAC_SECDED;
		}
2901 2902

		for (j = 0; j < pvt->channel_count; j++) {
2903
			dimm = csrow->channels[j]->dimm;
2904
			dimm->mtype = pvt->dram_type;
2905
			dimm->edac_mode = edac_mode;
2906
		}
2907 2908 2909 2910
	}

	return empty;
}
2911

2912
/* get all cores on this DCT */
2913
static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, u16 nid)
2914 2915 2916 2917 2918 2919 2920 2921 2922
{
	int cpu;

	for_each_online_cpu(cpu)
		if (amd_get_nb_id(cpu) == nid)
			cpumask_set_cpu(cpu, mask);
}

/* check MCG_CTL on all the cpus on this node */
2923
static bool nb_mce_bank_enabled_on_node(u16 nid)
2924 2925
{
	cpumask_var_t mask;
2926
	int cpu, nbe;
2927 2928 2929
	bool ret = false;

	if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) {
2930
		amd64_warn("%s: Error allocating mask\n", __func__);
2931 2932 2933 2934 2935 2936 2937 2938
		return false;
	}

	get_cpus_on_this_dct_cpumask(mask, nid);

	rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs);

	for_each_cpu(cpu, mask) {
2939
		struct msr *reg = per_cpu_ptr(msrs, cpu);
2940
		nbe = reg->l & MSR_MCGCTL_NBE;
2941

2942 2943 2944
		edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
			 cpu, reg->q,
			 (nbe ? "enabled" : "disabled"));
2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955

		if (!nbe)
			goto out;
	}
	ret = true;

out:
	free_cpumask_var(mask);
	return ret;
}

2956
static int toggle_ecc_err_reporting(struct ecc_settings *s, u16 nid, bool on)
2957 2958
{
	cpumask_var_t cmask;
2959
	int cpu;
2960 2961

	if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) {
2962
		amd64_warn("%s: error allocating mask\n", __func__);
P
Pan Bian 已提交
2963
		return -ENOMEM;
2964 2965
	}

2966
	get_cpus_on_this_dct_cpumask(cmask, nid);
2967 2968 2969 2970 2971

	rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);

	for_each_cpu(cpu, cmask) {

2972 2973
		struct msr *reg = per_cpu_ptr(msrs, cpu);

2974
		if (on) {
2975
			if (reg->l & MSR_MCGCTL_NBE)
2976
				s->flags.nb_mce_enable = 1;
2977

2978
			reg->l |= MSR_MCGCTL_NBE;
2979 2980
		} else {
			/*
2981
			 * Turn off NB MCE reporting only when it was off before
2982
			 */
2983
			if (!s->flags.nb_mce_enable)
2984
				reg->l &= ~MSR_MCGCTL_NBE;
2985 2986 2987 2988 2989 2990 2991 2992 2993
		}
	}
	wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);

	free_cpumask_var(cmask);

	return 0;
}

2994
static bool enable_ecc_error_reporting(struct ecc_settings *s, u16 nid,
2995
				       struct pci_dev *F3)
2996
{
2997
	bool ret = true;
B
Borislav Petkov 已提交
2998
	u32 value, mask = 0x3;		/* UECC/CECC enable */
2999

3000 3001 3002 3003 3004
	if (toggle_ecc_err_reporting(s, nid, ON)) {
		amd64_warn("Error enabling ECC reporting over MCGCTL!\n");
		return false;
	}

B
Borislav Petkov 已提交
3005
	amd64_read_pci_cfg(F3, NBCTL, &value);
3006

3007 3008
	s->old_nbctl   = value & mask;
	s->nbctl_valid = true;
3009 3010

	value |= mask;
B
Borislav Petkov 已提交
3011
	amd64_write_pci_cfg(F3, NBCTL, value);
3012

3013
	amd64_read_pci_cfg(F3, NBCFG, &value);
3014

3015 3016
	edac_dbg(0, "1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
		 nid, value, !!(value & NBCFG_ECC_ENABLE));
3017

3018
	if (!(value & NBCFG_ECC_ENABLE)) {
3019
		amd64_warn("DRAM ECC disabled on this node, enabling...\n");
3020

3021
		s->flags.nb_ecc_prev = 0;
3022

3023
		/* Attempt to turn on DRAM ECC Enable */
3024 3025
		value |= NBCFG_ECC_ENABLE;
		amd64_write_pci_cfg(F3, NBCFG, value);
3026

3027
		amd64_read_pci_cfg(F3, NBCFG, &value);
3028

3029
		if (!(value & NBCFG_ECC_ENABLE)) {
3030 3031
			amd64_warn("Hardware rejected DRAM ECC enable,"
				   "check memory DIMM configuration.\n");
3032
			ret = false;
3033
		} else {
3034
			amd64_info("Hardware accepted DRAM ECC Enable\n");
3035
		}
3036
	} else {
3037
		s->flags.nb_ecc_prev = 1;
3038
	}
3039

3040 3041
	edac_dbg(0, "2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
		 nid, value, !!(value & NBCFG_ECC_ENABLE));
3042

3043
	return ret;
3044 3045
}

3046
static void restore_ecc_error_reporting(struct ecc_settings *s, u16 nid,
3047
					struct pci_dev *F3)
3048
{
B
Borislav Petkov 已提交
3049 3050
	u32 value, mask = 0x3;		/* UECC/CECC enable */

3051
	if (!s->nbctl_valid)
3052 3053
		return;

B
Borislav Petkov 已提交
3054
	amd64_read_pci_cfg(F3, NBCTL, &value);
3055
	value &= ~mask;
3056
	value |= s->old_nbctl;
3057

B
Borislav Petkov 已提交
3058
	amd64_write_pci_cfg(F3, NBCTL, value);
3059

3060 3061
	/* restore previous BIOS DRAM ECC "off" setting we force-enabled */
	if (!s->flags.nb_ecc_prev) {
3062 3063 3064
		amd64_read_pci_cfg(F3, NBCFG, &value);
		value &= ~NBCFG_ECC_ENABLE;
		amd64_write_pci_cfg(F3, NBCFG, value);
3065 3066 3067
	}

	/* restore the NB Enable MCGCTL bit */
3068
	if (toggle_ecc_err_reporting(s, nid, OFF))
3069
		amd64_warn("Error restoring NB MCGCTL settings!\n");
3070 3071 3072
}

/*
3073 3074 3075 3076
 * EDAC requires that the BIOS have ECC enabled before
 * taking over the processing of ECC errors. A command line
 * option allows to force-enable hardware ECC later in
 * enable_ecc_error_reporting().
3077
 */
3078 3079 3080 3081 3082
static const char *ecc_msg =
	"ECC disabled in the BIOS or no ECC capability, module will not load.\n"
	" Either enable ECC checking or force module loading by setting "
	"'ecc_enable_override'.\n"
	" (Note that use of the override may cause unknown side effects.)\n";
3083

3084
static bool ecc_enabled(struct pci_dev *F3, u16 nid)
3085
{
3086
	bool nb_mce_en = false;
3087 3088
	u8 ecc_en = 0, i;
	u32 value;
3089

3090 3091
	if (boot_cpu_data.x86 >= 0x17) {
		u8 umc_en_mask = 0, ecc_en_mask = 0;
3092

3093
		for_each_umc(i) {
3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114
			u32 base = get_umc_base(i);

			/* Only check enabled UMCs. */
			if (amd_smn_read(nid, base + UMCCH_SDP_CTRL, &value))
				continue;

			if (!(value & UMC_SDP_INIT))
				continue;

			umc_en_mask |= BIT(i);

			if (amd_smn_read(nid, base + UMCCH_UMC_CAP_HI, &value))
				continue;

			if (value & UMC_ECC_ENABLED)
				ecc_en_mask |= BIT(i);
		}

		/* Check whether at least one UMC is enabled: */
		if (umc_en_mask)
			ecc_en = umc_en_mask == ecc_en_mask;
3115 3116
		else
			edac_dbg(0, "Node %d: No enabled UMCs.\n", nid);
3117 3118 3119 3120 3121

		/* Assume UMC MCA banks are enabled. */
		nb_mce_en = true;
	} else {
		amd64_read_pci_cfg(F3, NBCFG, &value);
3122

3123 3124 3125 3126
		ecc_en = !!(value & NBCFG_ECC_ENABLE);

		nb_mce_en = nb_mce_bank_enabled_on_node(nid);
		if (!nb_mce_en)
3127
			edac_dbg(0, "NB MCE bank disabled, set MSR 0x%08x[4] on node %d to enable.\n",
3128 3129 3130
				     MSR_IA32_MCG_CTL, nid);
	}

3131 3132
	amd64_info("Node %d: DRAM ECC %s.\n",
		   nid, (ecc_en ? "enabled" : "disabled"));
3133

3134
	if (!ecc_en || !nb_mce_en) {
3135
		amd64_info("%s", ecc_msg);
3136 3137 3138
		return false;
	}
	return true;
3139 3140
}

3141 3142 3143
static inline void
f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt)
{
3144
	u8 i, ecc_en = 1, cpk_en = 1, dev_x4 = 1, dev_x16 = 1;
3145

3146
	for_each_umc(i) {
3147 3148 3149
		if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {
			ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED);
			cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP);
3150 3151 3152

			dev_x4  &= !!(pvt->umc[i].dimm_cfg & BIT(6));
			dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7));
3153 3154 3155 3156 3157 3158 3159
		}
	}

	/* Set chipkill only if ECC is enabled: */
	if (ecc_en) {
		mci->edac_ctl_cap |= EDAC_FLAG_SECDED;

3160 3161 3162 3163
		if (!cpk_en)
			return;

		if (dev_x4)
3164
			mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
3165 3166 3167 3168
		else if (dev_x16)
			mci->edac_ctl_cap |= EDAC_FLAG_S16ECD16ED;
		else
			mci->edac_ctl_cap |= EDAC_FLAG_S8ECD8ED;
3169 3170 3171
	}
}

3172 3173
static void setup_mci_misc_attrs(struct mem_ctl_info *mci,
				 struct amd64_family_type *fam)
3174 3175 3176 3177 3178 3179
{
	struct amd64_pvt *pvt = mci->pvt_info;

	mci->mtype_cap		= MEM_FLAG_DDR2 | MEM_FLAG_RDDR2;
	mci->edac_ctl_cap	= EDAC_FLAG_NONE;

3180 3181 3182 3183 3184
	if (pvt->umc) {
		f17h_determine_edac_ctl_cap(mci, pvt);
	} else {
		if (pvt->nbcap & NBCAP_SECDED)
			mci->edac_ctl_cap |= EDAC_FLAG_SECDED;
3185

3186 3187 3188
		if (pvt->nbcap & NBCAP_CHIPKILL)
			mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
	}
3189

3190
	mci->edac_cap		= determine_edac_cap(pvt);
3191
	mci->mod_name		= EDAC_MOD_STR;
3192
	mci->ctl_name		= fam->ctl_name;
3193
	mci->dev_name		= pci_name(pvt->F3);
3194 3195 3196
	mci->ctl_page_to_phys	= NULL;

	/* memory scrubber interface */
3197 3198
	mci->set_sdram_scrub_rate = set_scrub_rate;
	mci->get_sdram_scrub_rate = get_scrub_rate;
3199 3200
}

3201 3202 3203
/*
 * returns a pointer to the family descriptor on success, NULL otherwise.
 */
3204
static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
3205
{
3206 3207
	struct amd64_family_type *fam_type = NULL;

3208
	pvt->ext_model  = boot_cpu_data.x86_model >> 4;
3209
	pvt->stepping	= boot_cpu_data.x86_stepping;
3210 3211 3212 3213
	pvt->model	= boot_cpu_data.x86_model;
	pvt->fam	= boot_cpu_data.x86;

	switch (pvt->fam) {
3214
	case 0xf:
3215 3216
		fam_type	= &family_types[K8_CPUS];
		pvt->ops	= &family_types[K8_CPUS].ops;
3217
		break;
3218

3219
	case 0x10:
3220 3221
		fam_type	= &family_types[F10_CPUS];
		pvt->ops	= &family_types[F10_CPUS].ops;
3222 3223 3224
		break;

	case 0x15:
3225
		if (pvt->model == 0x30) {
3226 3227
			fam_type = &family_types[F15_M30H_CPUS];
			pvt->ops = &family_types[F15_M30H_CPUS].ops;
3228
			break;
3229 3230 3231 3232
		} else if (pvt->model == 0x60) {
			fam_type = &family_types[F15_M60H_CPUS];
			pvt->ops = &family_types[F15_M60H_CPUS].ops;
			break;
3233 3234
		}

3235 3236
		fam_type	= &family_types[F15_CPUS];
		pvt->ops	= &family_types[F15_CPUS].ops;
3237 3238
		break;

3239
	case 0x16:
3240 3241 3242 3243 3244
		if (pvt->model == 0x30) {
			fam_type = &family_types[F16_M30H_CPUS];
			pvt->ops = &family_types[F16_M30H_CPUS].ops;
			break;
		}
3245 3246
		fam_type	= &family_types[F16_CPUS];
		pvt->ops	= &family_types[F16_CPUS].ops;
3247 3248
		break;

3249
	case 0x17:
3250 3251 3252 3253
		if (pvt->model >= 0x10 && pvt->model <= 0x2f) {
			fam_type = &family_types[F17_M10H_CPUS];
			pvt->ops = &family_types[F17_M10H_CPUS].ops;
			break;
3254 3255 3256 3257
		} else if (pvt->model >= 0x30 && pvt->model <= 0x3f) {
			fam_type = &family_types[F17_M30H_CPUS];
			pvt->ops = &family_types[F17_M30H_CPUS].ops;
			break;
3258
		}
3259 3260
		/* fall through */
	case 0x18:
3261 3262
		fam_type	= &family_types[F17_CPUS];
		pvt->ops	= &family_types[F17_CPUS].ops;
3263 3264 3265

		if (pvt->fam == 0x18)
			family_types[F17_CPUS].ctl_name = "F18h";
3266 3267
		break;

3268
	default:
3269
		amd64_err("Unsupported family!\n");
3270
		return NULL;
3271
	}
3272

3273
	amd64_info("%s %sdetected (node %d).\n", fam_type->ctl_name,
3274
		     (pvt->fam == 0xf ?
3275 3276 3277
				(pvt->ext_model >= K8_REV_F  ? "revF or later "
							     : "revE or earlier ")
				 : ""), pvt->mc_node_id);
3278
	return fam_type;
3279 3280
}

3281 3282 3283 3284 3285 3286 3287 3288 3289 3290
static const struct attribute_group *amd64_edac_attr_groups[] = {
#ifdef CONFIG_EDAC_DEBUG
	&amd64_edac_dbg_group,
#endif
#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
	&amd64_edac_inj_group,
#endif
	NULL
};

3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306
/* Set the number of Unified Memory Controllers in the system. */
static void compute_num_umcs(void)
{
	u8 model = boot_cpu_data.x86_model;

	if (boot_cpu_data.x86 < 0x17)
		return;

	if (model >= 0x30 && model <= 0x3f)
		num_umcs = 8;
	else
		num_umcs = 2;

	edac_dbg(1, "Number of UMCs: %x", num_umcs);
}

3307
static int init_one_instance(unsigned int nid)
3308
{
3309
	struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
3310
	struct amd64_family_type *fam_type = NULL;
3311
	struct mem_ctl_info *mci = NULL;
3312
	struct edac_mc_layer layers[2];
3313
	struct amd64_pvt *pvt = NULL;
3314
	u16 pci_id1, pci_id2;
3315 3316 3317 3318 3319
	int err = 0, ret;

	ret = -ENOMEM;
	pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL);
	if (!pvt)
3320
		goto err_ret;
3321

3322
	pvt->mc_node_id	= nid;
3323
	pvt->F3 = F3;
3324

3325
	ret = -EINVAL;
3326
	fam_type = per_family_init(pvt);
3327
	if (!fam_type)
3328 3329
		goto err_free;

3330
	if (pvt->fam >= 0x17) {
3331
		pvt->umc = kcalloc(num_umcs, sizeof(struct amd64_umc), GFP_KERNEL);
3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344
		if (!pvt->umc) {
			ret = -ENOMEM;
			goto err_free;
		}

		pci_id1 = fam_type->f0_id;
		pci_id2 = fam_type->f6_id;
	} else {
		pci_id1 = fam_type->f1_id;
		pci_id2 = fam_type->f2_id;
	}

	err = reserve_mc_sibling_devs(pvt, pci_id1, pci_id2);
3345
	if (err)
3346
		goto err_post_init;
3347

3348
	read_mc_regs(pvt);
3349 3350 3351 3352

	/*
	 * We need to determine how many memory channels there are. Then use
	 * that information for calculating the size of the dynamic instance
3353
	 * tables in the 'mci' structure.
3354
	 */
3355
	ret = -EINVAL;
3356 3357
	pvt->channel_count = pvt->ops->early_channel_count(pvt);
	if (pvt->channel_count < 0)
3358
		goto err_siblings;
3359 3360

	ret = -ENOMEM;
3361 3362 3363 3364
	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = pvt->csels[0].b_cnt;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
3365 3366 3367 3368 3369

	/*
	 * Always allocate two channels since we can have setups with DIMMs on
	 * only one channel. Also, this simplifies handling later for the price
	 * of a couple of KBs tops.
3370 3371 3372
	 *
	 * On Fam17h+, the number of controllers may be greater than two. So set
	 * the size equal to the maximum number of UMCs.
3373
	 */
3374 3375 3376 3377
	if (pvt->fam >= 0x17)
		layers[1].size = num_umcs;
	else
		layers[1].size = 2;
3378
	layers[1].is_virt_csrow = false;
3379

3380
	mci = edac_mc_alloc(nid, ARRAY_SIZE(layers), layers, 0);
3381
	if (!mci)
3382
		goto err_siblings;
3383 3384

	mci->pvt_info = pvt;
3385
	mci->pdev = &pvt->F3->dev;
3386

3387
	setup_mci_misc_attrs(mci, fam_type);
3388 3389

	if (init_csrows(mci))
3390 3391 3392
		mci->edac_cap = EDAC_FLAG_NONE;

	ret = -ENODEV;
3393
	if (edac_mc_add_mc_with_groups(mci, amd64_edac_attr_groups)) {
3394
		edac_dbg(1, "failed edac_mc_add_mc()\n");
3395 3396 3397 3398 3399 3400 3401 3402
		goto err_add_mc;
	}

	return 0;

err_add_mc:
	edac_mc_free(mci);

3403 3404
err_siblings:
	free_mc_sibling_devs(pvt);
3405

3406 3407 3408 3409
err_post_init:
	if (pvt->fam >= 0x17)
		kfree(pvt->umc);

3410 3411
err_free:
	kfree(pvt);
3412

3413
err_ret:
3414 3415 3416
	return ret;
}

3417
static int probe_one_instance(unsigned int nid)
3418
{
3419
	struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
3420
	struct ecc_settings *s;
3421
	int ret;
3422

3423 3424 3425
	ret = -ENOMEM;
	s = kzalloc(sizeof(struct ecc_settings), GFP_KERNEL);
	if (!s)
3426
		goto err_out;
3427 3428 3429

	ecc_stngs[nid] = s;

3430
	if (!ecc_enabled(F3, nid)) {
3431
		ret = 0;
3432 3433 3434 3435

		if (!ecc_enable_override)
			goto err_enable;

3436 3437 3438 3439 3440
		if (boot_cpu_data.x86 >= 0x17) {
			amd64_warn("Forcing ECC on is not recommended on newer systems. Please enable ECC in BIOS.");
			goto err_enable;
		} else
			amd64_warn("Forcing ECC on!\n");
3441 3442 3443 3444 3445

		if (!enable_ecc_error_reporting(s, nid, F3))
			goto err_enable;
	}

3446
	ret = init_one_instance(nid);
3447
	if (ret < 0) {
3448
		amd64_err("Error probing instance: %d\n", nid);
3449 3450 3451

		if (boot_cpu_data.x86 < 0x17)
			restore_ecc_error_reporting(s, nid, F3);
3452 3453

		goto err_enable;
3454
	}
3455 3456

	return ret;
3457 3458 3459 3460 3461 3462 3463

err_enable:
	kfree(s);
	ecc_stngs[nid] = NULL;

err_out:
	return ret;
3464 3465
}

3466
static void remove_one_instance(unsigned int nid)
3467
{
3468 3469
	struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
	struct ecc_settings *s = ecc_stngs[nid];
3470 3471
	struct mem_ctl_info *mci;
	struct amd64_pvt *pvt;
3472

3473
	mci = find_mci_by_dev(&F3->dev);
3474 3475
	WARN_ON(!mci);

3476
	/* Remove from EDAC CORE tracking list */
3477
	mci = edac_mc_del_mc(&F3->dev);
3478 3479 3480 3481 3482
	if (!mci)
		return;

	pvt = mci->pvt_info;

3483
	restore_ecc_error_reporting(s, nid, F3);
3484

3485
	free_mc_sibling_devs(pvt);
3486

3487 3488
	kfree(ecc_stngs[nid]);
	ecc_stngs[nid] = NULL;
3489

3490
	/* Free the EDAC CORE resources */
3491 3492 3493
	mci->pvt_info = NULL;

	kfree(pvt);
3494 3495 3496
	edac_mc_free(mci);
}

3497
static void setup_pci_device(void)
3498 3499 3500 3501
{
	struct mem_ctl_info *mci;
	struct amd64_pvt *pvt;

3502
	if (pci_ctl)
3503 3504
		return;

3505
	mci = edac_mc_find(0);
3506 3507
	if (!mci)
		return;
3508

3509
	pvt = mci->pvt_info;
3510 3511 3512 3513
	if (pvt->umc)
		pci_ctl = edac_pci_create_generic_ctl(&pvt->F0->dev, EDAC_MOD_STR);
	else
		pci_ctl = edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR);
3514 3515 3516
	if (!pci_ctl) {
		pr_warn("%s(): Unable to create PCI control\n", __func__);
		pr_warn("%s(): PCI error report via EDAC not set\n", __func__);
3517 3518 3519
	}
}

3520 3521 3522 3523 3524
static const struct x86_cpu_id amd64_cpuids[] = {
	{ X86_VENDOR_AMD, 0xF,	X86_MODEL_ANY,	X86_FEATURE_ANY, 0 },
	{ X86_VENDOR_AMD, 0x10, X86_MODEL_ANY,	X86_FEATURE_ANY, 0 },
	{ X86_VENDOR_AMD, 0x15, X86_MODEL_ANY,	X86_FEATURE_ANY, 0 },
	{ X86_VENDOR_AMD, 0x16, X86_MODEL_ANY,	X86_FEATURE_ANY, 0 },
3525
	{ X86_VENDOR_AMD, 0x17, X86_MODEL_ANY,	X86_FEATURE_ANY, 0 },
3526
	{ X86_VENDOR_HYGON, 0x18, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
3527 3528 3529 3530
	{ }
};
MODULE_DEVICE_TABLE(x86cpu, amd64_cpuids);

3531 3532
static int __init amd64_edac_init(void)
{
3533
	const char *owner;
3534
	int err = -ENODEV;
3535
	int i;
3536

3537 3538 3539 3540
	owner = edac_get_owner();
	if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
		return -EBUSY;

3541 3542 3543
	if (!x86_match_cpu(amd64_cpuids))
		return -ENODEV;

3544
	if (amd_cache_northbridges() < 0)
3545
		return -ENODEV;
3546

3547 3548
	opstate_init();

3549
	err = -ENOMEM;
K
Kees Cook 已提交
3550
	ecc_stngs = kcalloc(amd_nb_num(), sizeof(ecc_stngs[0]), GFP_KERNEL);
3551
	if (!ecc_stngs)
3552
		goto err_free;
3553

3554
	msrs = msrs_alloc();
3555
	if (!msrs)
3556
		goto err_free;
3557

3558 3559
	compute_num_umcs();

3560 3561 3562
	for (i = 0; i < amd_nb_num(); i++) {
		err = probe_one_instance(i);
		if (err) {
3563 3564 3565
			/* unwind properly */
			while (--i >= 0)
				remove_one_instance(i);
3566

3567 3568
			goto err_pci;
		}
3569
	}
3570

3571 3572 3573 3574 3575
	if (!edac_has_mcs()) {
		err = -ENODEV;
		goto err_pci;
	}

3576 3577 3578 3579 3580 3581 3582 3583 3584
	/* register stuff with EDAC MCE */
	if (report_gart_errors)
		amd_report_gart_errors(true);

	if (boot_cpu_data.x86 >= 0x17)
		amd_register_ecc_decoder(decode_umc_error);
	else
		amd_register_ecc_decoder(decode_bus_error);

3585
	setup_pci_device();
T
Tomasz Pala 已提交
3586 3587 3588 3589 3590

#ifdef CONFIG_X86_32
	amd64_err("%s on 32-bit is unsupported. USE AT YOUR OWN RISK!\n", EDAC_MOD_STR);
#endif

3591 3592
	printk(KERN_INFO "AMD64 EDAC driver v%s\n", EDAC_AMD64_VERSION);

3593
	return 0;
3594

3595 3596 3597
err_pci:
	msrs_free(msrs);
	msrs = NULL;
3598

3599 3600 3601 3602
err_free:
	kfree(ecc_stngs);
	ecc_stngs = NULL;

3603 3604 3605 3606 3607
	return err;
}

static void __exit amd64_edac_exit(void)
{
3608 3609
	int i;

3610 3611
	if (pci_ctl)
		edac_pci_release_generic_ctl(pci_ctl);
3612

3613 3614 3615 3616 3617 3618 3619 3620
	/* unregister from EDAC MCE */
	amd_report_gart_errors(false);

	if (boot_cpu_data.x86 >= 0x17)
		amd_unregister_ecc_decoder(decode_umc_error);
	else
		amd_unregister_ecc_decoder(decode_bus_error);

3621 3622
	for (i = 0; i < amd_nb_num(); i++)
		remove_one_instance(i);
3623

3624 3625 3626
	kfree(ecc_stngs);
	ecc_stngs = NULL;

3627 3628
	msrs_free(msrs);
	msrs = NULL;
3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641
}

module_init(amd64_edac_init);
module_exit(amd64_edac_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, "
		"Dave Peterson, Thayne Harbaugh");
MODULE_DESCRIPTION("MC support for AMD64 memory controllers - "
		EDAC_AMD64_VERSION);

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");