amd64_edac.c 88.3 KB
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#include "amd64_edac.h"
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#include <asm/amd_nb.h>
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static struct edac_pci_ctl_info *pci_ctl;
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static int report_gart_errors;
module_param(report_gart_errors, int, 0644);

/*
 * Set by command line parameter. If BIOS has enabled the ECC, this override is
 * cleared to prevent re-enabling the hardware by this driver.
 */
static int ecc_enable_override;
module_param(ecc_enable_override, int, 0644);

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static struct msr __percpu *msrs;
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/* Per-node stuff */
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static struct ecc_settings **ecc_stngs;
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/*
 * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing
 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
 * or higher value'.
 *
 *FIXME: Produce a better mapping/linearisation.
 */
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static const struct scrubrate {
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       u32 scrubval;           /* bit pattern for scrub rate */
       u32 bandwidth;          /* bandwidth consumed (bytes/sec) */
} scrubrates[] = {
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	{ 0x01, 1600000000UL},
	{ 0x02, 800000000UL},
	{ 0x03, 400000000UL},
	{ 0x04, 200000000UL},
	{ 0x05, 100000000UL},
	{ 0x06, 50000000UL},
	{ 0x07, 25000000UL},
	{ 0x08, 12284069UL},
	{ 0x09, 6274509UL},
	{ 0x0A, 3121951UL},
	{ 0x0B, 1560975UL},
	{ 0x0C, 781440UL},
	{ 0x0D, 390720UL},
	{ 0x0E, 195300UL},
	{ 0x0F, 97650UL},
	{ 0x10, 48854UL},
	{ 0x11, 24427UL},
	{ 0x12, 12213UL},
	{ 0x13, 6101UL},
	{ 0x14, 3051UL},
	{ 0x15, 1523UL},
	{ 0x16, 761UL},
	{ 0x00, 0UL},        /* scrubbing off */
};

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int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
			       u32 *val, const char *func)
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{
	int err = 0;

	err = pci_read_config_dword(pdev, offset, val);
	if (err)
		amd64_warn("%s: error reading F%dx%03x.\n",
			   func, PCI_FUNC(pdev->devfn), offset);

	return err;
}

int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
				u32 val, const char *func)
{
	int err = 0;

	err = pci_write_config_dword(pdev, offset, val);
	if (err)
		amd64_warn("%s: error writing to F%dx%03x.\n",
			   func, PCI_FUNC(pdev->devfn), offset);

	return err;
}

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/*
 * Select DCT to which PCI cfg accesses are routed
 */
static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct)
{
	u32 reg = 0;

	amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, &reg);
	reg &= (pvt->model == 0x30) ? ~3 : ~1;
	reg |= dct;
	amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);
}

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/*
 *
 * Depending on the family, F2 DCT reads need special handling:
 *
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 * K8: has a single DCT only and no address offsets >= 0x100
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 *
 * F10h: each DCT has its own set of regs
 *	DCT0 -> F2x040..
 *	DCT1 -> F2x140..
 *
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 * F16h: has only 1 DCT
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 *
 * F15h: we select which DCT we access using F1x10C[DctCfgSel]
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 */
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static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct,
					 int offset, u32 *val)
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{
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	switch (pvt->fam) {
	case 0xf:
		if (dct || offset >= 0x100)
			return -EINVAL;
		break;
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	case 0x10:
		if (dct) {
			/*
			 * Note: If ganging is enabled, barring the regs
			 * F2x[1,0]98 and F2x[1,0]9C; reads reads to F2x1xx
			 * return 0. (cf. Section 2.8.1 F10h BKDG)
			 */
			if (dct_ganging_enabled(pvt))
				return 0;
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			offset += 0x100;
		}
		break;
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	case 0x15:
		/*
		 * F15h: F2x1xx addresses do not map explicitly to DCT1.
		 * We should select which DCT we access using F1x10C[DctCfgSel]
		 */
		dct = (dct && pvt->model == 0x30) ? 3 : dct;
		f15h_select_dct(pvt, dct);
		break;
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	case 0x16:
		if (dct)
			return -EINVAL;
		break;
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	default:
		break;
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	}
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	return amd64_read_pci_cfg(pvt->F2, offset, val);
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}

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/*
 * Memory scrubber control interface. For K8, memory scrubbing is handled by
 * hardware and can involve L2 cache, dcache as well as the main memory. With
 * F10, this is extended to L3 cache scrubbing on CPU models sporting that
 * functionality.
 *
 * This causes the "units" for the scrubbing speed to vary from 64 byte blocks
 * (dram) over to cache lines. This is nasty, so we will use bandwidth in
 * bytes/sec for the setting.
 *
 * Currently, we only do dram scrubbing. If the scrubbing is done in software on
 * other archs, we might not have access to the caches directly.
 */

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static inline void __f17h_set_scrubval(struct amd64_pvt *pvt, u32 scrubval)
{
	/*
	 * Fam17h supports scrub values between 0x5 and 0x14. Also, the values
	 * are shifted down by 0x5, so scrubval 0x5 is written to the register
	 * as 0x0, scrubval 0x6 as 0x1, etc.
	 */
	if (scrubval >= 0x5 && scrubval <= 0x14) {
		scrubval -= 0x5;
		pci_write_bits32(pvt->F6, F17H_SCR_LIMIT_ADDR, scrubval, 0xF);
		pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 1, 0x1);
	} else {
		pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 0, 0x1);
	}
}
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/*
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 * Scan the scrub rate mapping table for a close or matching bandwidth value to
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 * issue. If requested is too big, then use last maximum value found.
 */
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static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate)
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{
	u32 scrubval;
	int i;

	/*
	 * map the configured rate (new_bw) to a value specific to the AMD64
	 * memory controller and apply to register. Search for the first
	 * bandwidth entry that is greater or equal than the setting requested
	 * and program that. If at last entry, turn off DRAM scrubbing.
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	 *
	 * If no suitable bandwidth is found, turn off DRAM scrubbing entirely
	 * by falling back to the last element in scrubrates[].
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	 */
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	for (i = 0; i < ARRAY_SIZE(scrubrates) - 1; i++) {
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		/*
		 * skip scrub rates which aren't recommended
		 * (see F10 BKDG, F3x58)
		 */
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		if (scrubrates[i].scrubval < min_rate)
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			continue;

		if (scrubrates[i].bandwidth <= new_bw)
			break;
	}

	scrubval = scrubrates[i].scrubval;

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	if (pvt->fam == 0x17) {
		__f17h_set_scrubval(pvt, scrubval);
	} else if (pvt->fam == 0x15 && pvt->model == 0x60) {
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		f15h_select_dct(pvt, 0);
		pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
		f15h_select_dct(pvt, 1);
		pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
	} else {
		pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F);
	}
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	if (scrubval)
		return scrubrates[i].bandwidth;

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	return 0;
}

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static int set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
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{
	struct amd64_pvt *pvt = mci->pvt_info;
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	u32 min_scrubrate = 0x5;
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	if (pvt->fam == 0xf)
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		min_scrubrate = 0x0;

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	if (pvt->fam == 0x15) {
		/* Erratum #505 */
		if (pvt->model < 0x10)
			f15h_select_dct(pvt, 0);
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		if (pvt->model == 0x60)
			min_scrubrate = 0x6;
	}
	return __set_scrub_rate(pvt, bw, min_scrubrate);
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}

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static int get_scrub_rate(struct mem_ctl_info *mci)
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{
	struct amd64_pvt *pvt = mci->pvt_info;
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	int i, retval = -EINVAL;
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	u32 scrubval = 0;
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	switch (pvt->fam) {
	case 0x15:
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		/* Erratum #505 */
		if (pvt->model < 0x10)
			f15h_select_dct(pvt, 0);
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		if (pvt->model == 0x60)
			amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval);
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		break;

	case 0x17:
		amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval);
		if (scrubval & BIT(0)) {
			amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval);
			scrubval &= 0xF;
			scrubval += 0x5;
		} else {
			scrubval = 0;
		}
		break;

	default:
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		amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
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		break;
	}
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	scrubval = scrubval & 0x001F;

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	for (i = 0; i < ARRAY_SIZE(scrubrates); i++) {
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		if (scrubrates[i].scrubval == scrubval) {
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			retval = scrubrates[i].bandwidth;
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			break;
		}
	}
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	return retval;
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}

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/*
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 * returns true if the SysAddr given by sys_addr matches the
 * DRAM base/limit associated with node_id
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 */
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static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid)
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{
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	u64 addr;
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	/* The K8 treats this as a 40-bit value.  However, bits 63-40 will be
	 * all ones if the most significant implemented address bit is 1.
	 * Here we discard bits 63-40.  See section 3.4.2 of AMD publication
	 * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1
	 * Application Programming.
	 */
	addr = sys_addr & 0x000000ffffffffffull;

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	return ((addr >= get_dram_base(pvt, nid)) &&
		(addr <= get_dram_limit(pvt, nid)));
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}

/*
 * Attempt to map a SysAddr to a node. On success, return a pointer to the
 * mem_ctl_info structure for the node that the SysAddr maps to.
 *
 * On failure, return NULL.
 */
static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
						u64 sys_addr)
{
	struct amd64_pvt *pvt;
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	u8 node_id;
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	u32 intlv_en, bits;

	/*
	 * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section
	 * 3.4.4.2) registers to map the SysAddr to a node ID.
	 */
	pvt = mci->pvt_info;

	/*
	 * The value of this field should be the same for all DRAM Base
	 * registers.  Therefore we arbitrarily choose to read it from the
	 * register for node 0.
	 */
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	intlv_en = dram_intlv_en(pvt, 0);
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	if (intlv_en == 0) {
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		for (node_id = 0; node_id < DRAM_RANGES; node_id++) {
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			if (base_limit_match(pvt, sys_addr, node_id))
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				goto found;
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		}
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		goto err_no_match;
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	}

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	if (unlikely((intlv_en != 0x01) &&
		     (intlv_en != 0x03) &&
		     (intlv_en != 0x07))) {
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		amd64_warn("DRAM Base[IntlvEn] junk value: 0x%x, BIOS bug?\n", intlv_en);
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		return NULL;
	}

	bits = (((u32) sys_addr) >> 12) & intlv_en;

	for (node_id = 0; ; ) {
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		if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits)
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			break;	/* intlv_sel field matches */

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		if (++node_id >= DRAM_RANGES)
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			goto err_no_match;
	}

	/* sanity test for sys_addr */
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	if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) {
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		amd64_warn("%s: sys_addr 0x%llx falls outside base/limit address"
			   "range for node %d with node interleaving enabled.\n",
			   __func__, sys_addr, node_id);
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		return NULL;
	}

found:
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	return edac_mc_find((int)node_id);
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err_no_match:
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	edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n",
		 (unsigned long)sys_addr);
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	return NULL;
}
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/*
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 * compute the CS base address of the @csrow on the DRAM controller @dct.
 * For details see F2x[5C:40] in the processor's BKDG
385
 */
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static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct,
				 u64 *base, u64 *mask)
388
{
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	u64 csbase, csmask, base_bits, mask_bits;
	u8 addr_shift;
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	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {
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		csbase		= pvt->csels[dct].csbases[csrow];
		csmask		= pvt->csels[dct].csmasks[csrow];
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		base_bits	= GENMASK_ULL(31, 21) | GENMASK_ULL(15, 9);
		mask_bits	= GENMASK_ULL(29, 21) | GENMASK_ULL(15, 9);
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		addr_shift	= 4;
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	/*
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	 * F16h and F15h, models 30h and later need two addr_shift values:
	 * 8 for high and 6 for low (cf. F16h BKDG).
	 */
	} else if (pvt->fam == 0x16 ||
		  (pvt->fam == 0x15 && pvt->model >= 0x30)) {
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		csbase          = pvt->csels[dct].csbases[csrow];
		csmask          = pvt->csels[dct].csmasks[csrow >> 1];

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		*base  = (csbase & GENMASK_ULL(15,  5)) << 6;
		*base |= (csbase & GENMASK_ULL(30, 19)) << 8;
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		*mask = ~0ULL;
		/* poke holes for the csmask */
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		*mask &= ~((GENMASK_ULL(15, 5)  << 6) |
			   (GENMASK_ULL(30, 19) << 8));
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		*mask |= (csmask & GENMASK_ULL(15, 5))  << 6;
		*mask |= (csmask & GENMASK_ULL(30, 19)) << 8;
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		return;
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	} else {
		csbase		= pvt->csels[dct].csbases[csrow];
		csmask		= pvt->csels[dct].csmasks[csrow >> 1];
		addr_shift	= 8;
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		if (pvt->fam == 0x15)
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			base_bits = mask_bits =
				GENMASK_ULL(30,19) | GENMASK_ULL(13,5);
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		else
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			base_bits = mask_bits =
				GENMASK_ULL(28,19) | GENMASK_ULL(13,5);
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	}
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	*base  = (csbase & base_bits) << addr_shift;
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	*mask  = ~0ULL;
	/* poke holes for the csmask */
	*mask &= ~(mask_bits << addr_shift);
	/* OR them in */
	*mask |= (csmask & mask_bits) << addr_shift;
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}

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#define for_each_chip_select(i, dct, pvt) \
	for (i = 0; i < pvt->csels[dct].b_cnt; i++)

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#define chip_select_base(i, dct, pvt) \
	pvt->csels[dct].csbases[i]

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#define for_each_chip_select_mask(i, dct, pvt) \
	for (i = 0; i < pvt->csels[dct].m_cnt; i++)

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/*
 * @input_addr is an InputAddr associated with the node given by mci. Return the
 * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
 */
static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
{
	struct amd64_pvt *pvt;
	int csrow;
	u64 base, mask;

	pvt = mci->pvt_info;

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	for_each_chip_select(csrow, 0, pvt) {
		if (!csrow_enabled(csrow, 0, pvt))
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			continue;

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		get_cs_base_and_mask(pvt, csrow, 0, &base, &mask);

		mask = ~mask;
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		if ((input_addr & mask) == (base & mask)) {
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			edac_dbg(2, "InputAddr 0x%lx matches csrow %d (node %d)\n",
				 (unsigned long)input_addr, csrow,
				 pvt->mc_node_id);
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			return csrow;
		}
	}
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	edac_dbg(2, "no matching csrow for InputAddr 0x%lx (MC node %d)\n",
		 (unsigned long)input_addr, pvt->mc_node_id);
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	return -1;
}

/*
 * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094)
 * for the node represented by mci. Info is passed back in *hole_base,
 * *hole_offset, and *hole_size.  Function returns 0 if info is valid or 1 if
 * info is invalid. Info may be invalid for either of the following reasons:
 *
 * - The revision of the node is not E or greater.  In this case, the DRAM Hole
 *   Address Register does not exist.
 *
 * - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
 *   indicating that its contents are not valid.
 *
 * The values passed back in *hole_base, *hole_offset, and *hole_size are
 * complete 32-bit values despite the fact that the bitfields in the DHAR
 * only represent bits 31-24 of the base and offset values.
 */
int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
			     u64 *hole_offset, u64 *hole_size)
{
	struct amd64_pvt *pvt = mci->pvt_info;

	/* only revE and later have the DRAM Hole Address Register */
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	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) {
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		edac_dbg(1, "  revision %d for node %d does not support DHAR\n",
			 pvt->ext_model, pvt->mc_node_id);
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		return 1;
	}

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	/* valid for Fam10h and above */
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	if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) {
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		edac_dbg(1, "  Dram Memory Hoisting is DISABLED on this system\n");
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		return 1;
	}

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	if (!dhar_valid(pvt)) {
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		edac_dbg(1, "  Dram Memory Hoisting is DISABLED on this node %d\n",
			 pvt->mc_node_id);
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		return 1;
	}

	/* This node has Memory Hoisting */

	/* +------------------+--------------------+--------------------+-----
	 * | memory           | DRAM hole          | relocated          |
	 * | [0, (x - 1)]     | [x, 0xffffffff]    | addresses from     |
	 * |                  |                    | DRAM hole          |
	 * |                  |                    | [0x100000000,      |
	 * |                  |                    |  (0x100000000+     |
	 * |                  |                    |   (0xffffffff-x))] |
	 * +------------------+--------------------+--------------------+-----
	 *
	 * Above is a diagram of physical memory showing the DRAM hole and the
	 * relocated addresses from the DRAM hole.  As shown, the DRAM hole
	 * starts at address x (the base address) and extends through address
	 * 0xffffffff.  The DRAM Hole Address Register (DHAR) relocates the
	 * addresses in the hole so that they start at 0x100000000.
	 */

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	*hole_base = dhar_base(pvt);
	*hole_size = (1ULL << 32) - *hole_base;
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	*hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt)
					: k8_dhar_offset(pvt);
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	edac_dbg(1, "  DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
		 pvt->mc_node_id, (unsigned long)*hole_base,
		 (unsigned long)*hole_offset, (unsigned long)*hole_size);
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	return 0;
}
EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info);

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/*
 * Return the DramAddr that the SysAddr given by @sys_addr maps to.  It is
 * assumed that sys_addr maps to the node given by mci.
 *
 * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section
 * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a
 * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled,
 * then it is also involved in translating a SysAddr to a DramAddr. Sections
 * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting.
 * These parts of the documentation are unclear. I interpret them as follows:
 *
 * When node n receives a SysAddr, it processes the SysAddr as follows:
 *
 * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM
 *    Limit registers for node n. If the SysAddr is not within the range
 *    specified by the base and limit values, then node n ignores the Sysaddr
 *    (since it does not map to node n). Otherwise continue to step 2 below.
 *
 * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is
 *    disabled so skip to step 3 below. Otherwise see if the SysAddr is within
 *    the range of relocated addresses (starting at 0x100000000) from the DRAM
 *    hole. If not, skip to step 3 below. Else get the value of the
 *    DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the
 *    offset defined by this value from the SysAddr.
 *
 * 3. Obtain the base address for node n from the DRAMBase field of the DRAM
 *    Base register for node n. To obtain the DramAddr, subtract the base
 *    address from the SysAddr, as shown near the start of section 3.4.4 (p.70).
 */
static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
{
588
	struct amd64_pvt *pvt = mci->pvt_info;
589
	u64 dram_base, hole_base, hole_offset, hole_size, dram_addr;
590
	int ret;
591

592
	dram_base = get_dram_base(pvt, pvt->mc_node_id);
593 594 595 596

	ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset,
				      &hole_size);
	if (!ret) {
597 598
		if ((sys_addr >= (1ULL << 32)) &&
		    (sys_addr < ((1ULL << 32) + hole_size))) {
599 600 601
			/* use DHAR to translate SysAddr to DramAddr */
			dram_addr = sys_addr - hole_offset;

602 603 604
			edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
				 (unsigned long)sys_addr,
				 (unsigned long)dram_addr);
605 606 607 608 609 610 611 612 613 614 615 616 617 618

			return dram_addr;
		}
	}

	/*
	 * Translate the SysAddr to a DramAddr as shown near the start of
	 * section 3.4.4 (p. 70).  Although sys_addr is a 64-bit value, the k8
	 * only deals with 40-bit values.  Therefore we discard bits 63-40 of
	 * sys_addr below.  If bit 39 of sys_addr is 1 then the bits we
	 * discard are all 1s.  Otherwise the bits we discard are all 0s.  See
	 * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture
	 * Programmer's Manual Volume 1 Application Programming.
	 */
619
	dram_addr = (sys_addr & GENMASK_ULL(39, 0)) - dram_base;
620

621 622
	edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
		 (unsigned long)sys_addr, (unsigned long)dram_addr);
623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653
	return dram_addr;
}

/*
 * @intlv_en is the value of the IntlvEn field from a DRAM Base register
 * (section 3.4.4.1).  Return the number of bits from a SysAddr that are used
 * for node interleaving.
 */
static int num_node_interleave_bits(unsigned intlv_en)
{
	static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 };
	int n;

	BUG_ON(intlv_en > 7);
	n = intlv_shift_table[intlv_en];
	return n;
}

/* Translate the DramAddr given by @dram_addr to an InputAddr. */
static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr)
{
	struct amd64_pvt *pvt;
	int intlv_shift;
	u64 input_addr;

	pvt = mci->pvt_info;

	/*
	 * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
	 * concerning translating a DramAddr to an InputAddr.
	 */
654
	intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
655
	input_addr = ((dram_addr >> intlv_shift) & GENMASK_ULL(35, 12)) +
656
		      (dram_addr & 0xfff);
657

658 659 660
	edac_dbg(2, "  Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",
		 intlv_shift, (unsigned long)dram_addr,
		 (unsigned long)input_addr);
661 662 663 664 665 666 667 668 669 670 671 672 673 674 675

	return input_addr;
}

/*
 * Translate the SysAddr represented by @sys_addr to an InputAddr.  It is
 * assumed that @sys_addr maps to the node given by mci.
 */
static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr)
{
	u64 input_addr;

	input_addr =
	    dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr));

M
Masanari Iida 已提交
676
	edac_dbg(2, "SysAddr 0x%lx translates to InputAddr 0x%lx\n",
677
		 (unsigned long)sys_addr, (unsigned long)input_addr);
678 679 680 681 682 683

	return input_addr;
}

/* Map the Error address to a PAGE and PAGE OFFSET. */
static inline void error_address_to_page_and_offset(u64 error_address,
684
						    struct err_info *err)
685
{
686 687
	err->page = (u32) (error_address >> PAGE_SHIFT);
	err->offset = ((u32) error_address) & ~PAGE_MASK;
688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704
}

/*
 * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address
 * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers
 * of a node that detected an ECC memory error.  mci represents the node that
 * the error address maps to (possibly different from the node that detected
 * the error).  Return the number of the csrow that sys_addr maps to, or -1 on
 * error.
 */
static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr)
{
	int csrow;

	csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr));

	if (csrow == -1)
705 706
		amd64_mc_err(mci, "Failed to translate InputAddr to csrow for "
				  "address 0x%lx\n", (unsigned long)sys_addr);
707 708
	return csrow;
}
709

710
static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
711 712 713 714 715

/*
 * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
 * are ECC capable.
 */
716
static unsigned long determine_edac_cap(struct amd64_pvt *pvt)
717
{
718
	unsigned long edac_cap = EDAC_FLAG_NONE;
719 720 721 722
	u8 bit;

	if (pvt->umc) {
		u8 i, umc_en_mask = 0, dimm_ecc_en_mask = 0;
723

724 725 726
		for (i = 0; i < NUM_UMCS; i++) {
			if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT))
				continue;
727

728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744
			umc_en_mask |= BIT(i);

			/* UMC Configuration bit 12 (DimmEccEn) */
			if (pvt->umc[i].umc_cfg & BIT(12))
				dimm_ecc_en_mask |= BIT(i);
		}

		if (umc_en_mask == dimm_ecc_en_mask)
			edac_cap = EDAC_FLAG_SECDED;
	} else {
		bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F)
			? 19
			: 17;

		if (pvt->dclr0 & BIT(bit))
			edac_cap = EDAC_FLAG_SECDED;
	}
745 746 747 748

	return edac_cap;
}

749
static void debug_display_dimm_sizes(struct amd64_pvt *, u8);
750

751
static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan)
752
{
753
	edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);
754

755 756 757 758 759 760 761 762 763 764 765 766 767
	if (pvt->dram_type == MEM_LRDDR3) {
		u32 dcsm = pvt->csels[chan].csmasks[0];
		/*
		 * It's assumed all LRDIMMs in a DCT are going to be of
		 * same 'type' until proven otherwise. So, use a cs
		 * value of '0' here to get dcsm value.
		 */
		edac_dbg(1, " LRDIMM %dx rank multiply\n", (dcsm & 0x3));
	}

	edac_dbg(1, "All DIMMs support ECC:%s\n",
		    (dclr & BIT(19)) ? "yes" : "no");

768

769 770
	edac_dbg(1, "  PAR/ERR parity: %s\n",
		 (dclr & BIT(8)) ?  "enabled" : "disabled");
771

772
	if (pvt->fam == 0x10)
773 774
		edac_dbg(1, "  DCT 128bit mode width: %s\n",
			 (dclr & BIT(11)) ?  "128b" : "64b");
775

776 777 778 779 780
	edac_dbg(1, "  x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",
		 (dclr & BIT(12)) ?  "yes" : "no",
		 (dclr & BIT(13)) ?  "yes" : "no",
		 (dclr & BIT(14)) ?  "yes" : "no",
		 (dclr & BIT(15)) ?  "yes" : "no");
781 782
}

783 784
static void debug_display_dimm_sizes_df(struct amd64_pvt *pvt, u8 ctrl)
{
785
	int dimm, size0, size1, cs0, cs1;
786 787 788 789 790

	edac_printk(KERN_DEBUG, EDAC_MC, "UMC%d chip selects:\n", ctrl);

	for (dimm = 0; dimm < 4; dimm++) {
		size0 = 0;
791
		cs0 = dimm * 2;
792

793 794
		if (csrow_enabled(cs0, ctrl, pvt))
			size0 = pvt->ops->dbam_to_cs(pvt, ctrl, 0, cs0);
795 796

		size1 = 0;
797 798 799 800
		cs1 = dimm * 2 + 1;

		if (csrow_enabled(cs1, ctrl, pvt))
			size1 = pvt->ops->dbam_to_cs(pvt, ctrl, 0, cs1);
801 802

		amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n",
803 804
				cs0,	size0,
				cs1,	size1);
805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851
	}
}

static void __dump_misc_regs_df(struct amd64_pvt *pvt)
{
	struct amd64_umc *umc;
	u32 i, tmp, umc_base;

	for (i = 0; i < NUM_UMCS; i++) {
		umc_base = get_umc_base(i);
		umc = &pvt->umc[i];

		edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg);
		edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);
		edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);
		edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);

		amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ECC_BAD_SYMBOL, &tmp);
		edac_dbg(1, "UMC%d ECC bad symbol: 0x%x\n", i, tmp);

		amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_UMC_CAP, &tmp);
		edac_dbg(1, "UMC%d UMC cap: 0x%x\n", i, tmp);
		edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi);

		edac_dbg(1, "UMC%d ECC capable: %s, ChipKill ECC capable: %s\n",
				i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no",
				    (umc->umc_cap_hi & BIT(31)) ? "yes" : "no");
		edac_dbg(1, "UMC%d All DIMMs support ECC: %s\n",
				i, (umc->umc_cfg & BIT(12)) ? "yes" : "no");
		edac_dbg(1, "UMC%d x4 DIMMs present: %s\n",
				i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no");
		edac_dbg(1, "UMC%d x16 DIMMs present: %s\n",
				i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no");

		if (pvt->dram_type == MEM_LRDDR4) {
			amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ADDR_CFG, &tmp);
			edac_dbg(1, "UMC%d LRDIMM %dx rank multiply\n",
					i, 1 << ((tmp >> 4) & 0x3));
		}

		debug_display_dimm_sizes_df(pvt, i);
	}

	edac_dbg(1, "F0x104 (DRAM Hole Address): 0x%08x, base: 0x%08x\n",
		 pvt->dhar, dhar_base(pvt));
}

852
/* Display and decode various NB registers for debug purposes. */
853
static void __dump_misc_regs(struct amd64_pvt *pvt)
854
{
855
	edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
856

857 858
	edac_dbg(1, "  NB two channel DRAM capable: %s\n",
		 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no");
859

860 861 862
	edac_dbg(1, "  ECC capable: %s, ChipKill ECC capable: %s\n",
		 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no",
		 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no");
863

864
	debug_dump_dramcfg_low(pvt, pvt->dclr0, 0);
865

866
	edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);
867

868 869
	edac_dbg(1, "F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, offset: 0x%08x\n",
		 pvt->dhar, dhar_base(pvt),
870 871
		 (pvt->fam == 0xf) ? k8_dhar_offset(pvt)
				   : f10_dhar_offset(pvt));
872

873
	debug_display_dimm_sizes(pvt, 0);
874

875
	/* everything below this point is Fam10h and above */
876
	if (pvt->fam == 0xf)
877
		return;
878

879
	debug_display_dimm_sizes(pvt, 1);
880

881
	/* Only if NOT ganged does dclr1 have valid info */
882
	if (!dct_ganging_enabled(pvt))
883
		debug_dump_dramcfg_low(pvt, pvt->dclr1, 1);
884 885
}

886 887 888 889 890 891 892 893 894 895 896 897 898 899
/* Display and decode various NB registers for debug purposes. */
static void dump_misc_regs(struct amd64_pvt *pvt)
{
	if (pvt->umc)
		__dump_misc_regs_df(pvt);
	else
		__dump_misc_regs(pvt);

	edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");

	amd64_info("using %s syndromes.\n",
			((pvt->ecc_sym_sz == 8) ? "x8" : "x4"));
}

900
/*
901
 * See BKDG, F2x[1,0][5C:40], F2[1,0][6C:60]
902
 */
903
static void prep_chip_selects(struct amd64_pvt *pvt)
904
{
905
	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {
906 907
		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8;
908
	} else if (pvt->fam == 0x15 && pvt->model == 0x30) {
909 910
		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4;
		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2;
911
	} else {
912 913
		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4;
914 915 916 917
	}
}

/*
918
 * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers
919
 */
920
static void read_dct_base_mask(struct amd64_pvt *pvt)
921
{
922
	int base_reg0, base_reg1, mask_reg0, mask_reg1, cs;
923

924
	prep_chip_selects(pvt);
925

926 927 928 929 930 931 932 933 934 935 936 937
	if (pvt->umc) {
		base_reg0 = get_umc_base(0) + UMCCH_BASE_ADDR;
		base_reg1 = get_umc_base(1) + UMCCH_BASE_ADDR;
		mask_reg0 = get_umc_base(0) + UMCCH_ADDR_MASK;
		mask_reg1 = get_umc_base(1) + UMCCH_ADDR_MASK;
	} else {
		base_reg0 = DCSB0;
		base_reg1 = DCSB1;
		mask_reg0 = DCSM0;
		mask_reg1 = DCSM1;
	}

938
	for_each_chip_select(cs, 0, pvt) {
939 940
		int reg0   = base_reg0 + (cs * 4);
		int reg1   = base_reg1 + (cs * 4);
941 942
		u32 *base0 = &pvt->csels[0].csbases[cs];
		u32 *base1 = &pvt->csels[1].csbases[cs];
943

944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962
		if (pvt->umc) {
			if (!amd_smn_read(pvt->mc_node_id, reg0, base0))
				edac_dbg(0, "  DCSB0[%d]=0x%08x reg: 0x%x\n",
					 cs, *base0, reg0);

			if (!amd_smn_read(pvt->mc_node_id, reg1, base1))
				edac_dbg(0, "  DCSB1[%d]=0x%08x reg: 0x%x\n",
					 cs, *base1, reg1);
		} else {
			if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0))
				edac_dbg(0, "  DCSB0[%d]=0x%08x reg: F2x%x\n",
					 cs, *base0, reg0);

			if (pvt->fam == 0xf)
				continue;

			if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, base1))
				edac_dbg(0, "  DCSB1[%d]=0x%08x reg: F2x%x\n",
					 cs, *base1, (pvt->fam == 0x10) ? reg1
963
								: reg0);
964
		}
965 966
	}

967
	for_each_chip_select_mask(cs, 0, pvt) {
968 969
		int reg0   = mask_reg0 + (cs * 4);
		int reg1   = mask_reg1 + (cs * 4);
970 971
		u32 *mask0 = &pvt->csels[0].csmasks[cs];
		u32 *mask1 = &pvt->csels[1].csmasks[cs];
972

973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991
		if (pvt->umc) {
			if (!amd_smn_read(pvt->mc_node_id, reg0, mask0))
				edac_dbg(0, "    DCSM0[%d]=0x%08x reg: 0x%x\n",
					 cs, *mask0, reg0);

			if (!amd_smn_read(pvt->mc_node_id, reg1, mask1))
				edac_dbg(0, "    DCSM1[%d]=0x%08x reg: 0x%x\n",
					 cs, *mask1, reg1);
		} else {
			if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0))
				edac_dbg(0, "    DCSM0[%d]=0x%08x reg: F2x%x\n",
					 cs, *mask0, reg0);

			if (pvt->fam == 0xf)
				continue;

			if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1))
				edac_dbg(0, "    DCSM1[%d]=0x%08x reg: F2x%x\n",
					 cs, *mask1, (pvt->fam == 0x10) ? reg1
992
								: reg0);
993
		}
994 995 996
	}
}

997
static void determine_memory_type(struct amd64_pvt *pvt)
998
{
999
	u32 dram_ctrl, dcsm;
1000

1001 1002 1003 1004 1005 1006 1007 1008 1009
	switch (pvt->fam) {
	case 0xf:
		if (pvt->ext_model >= K8_REV_F)
			goto ddr3;

		pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR;
		return;

	case 0x10:
1010
		if (pvt->dchr0 & DDR3_MODE)
1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037
			goto ddr3;

		pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2;
		return;

	case 0x15:
		if (pvt->model < 0x60)
			goto ddr3;

		/*
		 * Model 0x60h needs special handling:
		 *
		 * We use a Chip Select value of '0' to obtain dcsm.
		 * Theoretically, it is possible to populate LRDIMMs of different
		 * 'Rank' value on a DCT. But this is not the common case. So,
		 * it's reasonable to assume all DIMMs are going to be of same
		 * 'type' until proven otherwise.
		 */
		amd64_read_dct_pci_cfg(pvt, 0, DRAM_CONTROL, &dram_ctrl);
		dcsm = pvt->csels[0].csmasks[0];

		if (((dram_ctrl >> 8) & 0x7) == 0x2)
			pvt->dram_type = MEM_DDR4;
		else if (pvt->dclr0 & BIT(16))
			pvt->dram_type = MEM_DDR3;
		else if (dcsm & 0x3)
			pvt->dram_type = MEM_LRDDR3;
1038
		else
1039
			pvt->dram_type = MEM_RDDR3;
1040

1041 1042 1043 1044 1045
		return;

	case 0x16:
		goto ddr3;

1046 1047 1048 1049 1050 1051 1052 1053 1054
	case 0x17:
		if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5))
			pvt->dram_type = MEM_LRDDR4;
		else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4))
			pvt->dram_type = MEM_RDDR4;
		else
			pvt->dram_type = MEM_DDR4;
		return;

1055 1056 1057 1058 1059
	default:
		WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam);
		pvt->dram_type = MEM_EMPTY;
	}
	return;
1060

1061 1062
ddr3:
	pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3;
1063 1064
}

1065
/* Get the number of DCT channels the memory controller is using. */
1066 1067
static int k8_early_channel_count(struct amd64_pvt *pvt)
{
1068
	int flag;
1069

1070
	if (pvt->ext_model >= K8_REV_F)
1071
		/* RevF (NPT) and later */
1072
		flag = pvt->dclr0 & WIDTH_128;
1073
	else
1074 1075 1076 1077 1078 1079 1080 1081 1082
		/* RevE and earlier */
		flag = pvt->dclr0 & REVE_WIDTH_128;

	/* not used */
	pvt->dclr1 = 0;

	return (flag) ? 2 : 1;
}

1083
/* On F10h and later ErrAddr is MC4_ADDR[47:1] */
1084
static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m)
1085
{
1086 1087
	u16 mce_nid = amd_get_nb_id(m->extcpu);
	struct mem_ctl_info *mci;
1088 1089
	u8 start_bit = 1;
	u8 end_bit   = 47;
1090 1091 1092 1093 1094 1095 1096
	u64 addr;

	mci = edac_mc_find(mce_nid);
	if (!mci)
		return 0;

	pvt = mci->pvt_info;
1097

1098
	if (pvt->fam == 0xf) {
1099 1100 1101 1102
		start_bit = 3;
		end_bit   = 39;
	}

1103
	addr = m->addr & GENMASK_ULL(end_bit, start_bit);
1104 1105 1106 1107

	/*
	 * Erratum 637 workaround
	 */
1108
	if (pvt->fam == 0x15) {
1109 1110
		u64 cc6_base, tmp_addr;
		u32 tmp;
1111
		u8 intlv_en;
1112

1113
		if ((addr & GENMASK_ULL(47, 24)) >> 24 != 0x00fdf7)
1114 1115 1116 1117 1118 1119 1120
			return addr;


		amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp);
		intlv_en = tmp >> 21 & 0x7;

		/* add [47:27] + 3 trailing bits */
1121
		cc6_base  = (tmp & GENMASK_ULL(20, 0)) << 3;
1122 1123 1124 1125 1126 1127 1128 1129

		/* reverse and add DramIntlvEn */
		cc6_base |= intlv_en ^ 0x7;

		/* pin at [47:24] */
		cc6_base <<= 24;

		if (!intlv_en)
1130
			return cc6_base | (addr & GENMASK_ULL(23, 0));
1131 1132 1133 1134

		amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp);

							/* faster log2 */
1135
		tmp_addr  = (addr & GENMASK_ULL(23, 12)) << __fls(intlv_en + 1);
1136 1137

		/* OR DramIntlvSel into bits [14:12] */
1138
		tmp_addr |= (tmp & GENMASK_ULL(23, 21)) >> 9;
1139 1140

		/* add remaining [11:0] bits from original MC4_ADDR */
1141
		tmp_addr |= addr & GENMASK_ULL(11, 0);
1142 1143 1144 1145 1146

		return cc6_base | tmp_addr;
	}

	return addr;
1147 1148
}

1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164
static struct pci_dev *pci_get_related_function(unsigned int vendor,
						unsigned int device,
						struct pci_dev *related)
{
	struct pci_dev *dev = NULL;

	while ((dev = pci_get_device(vendor, device, dev))) {
		if (pci_domain_nr(dev->bus) == pci_domain_nr(related->bus) &&
		    (dev->bus->number == related->bus->number) &&
		    (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn)))
			break;
	}

	return dev;
}

1165
static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
1166
{
1167
	struct amd_northbridge *nb;
1168 1169
	struct pci_dev *f1 = NULL;
	unsigned int pci_func;
1170
	int off = range << 3;
1171
	u32 llim;
1172

1173 1174
	amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off,  &pvt->ranges[range].base.lo);
	amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo);
1175

1176
	if (pvt->fam == 0xf)
1177
		return;
1178

1179 1180
	if (!dram_rw(pvt, range))
		return;
1181

1182 1183
	amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off,  &pvt->ranges[range].base.hi);
	amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi);
1184

1185
	/* F15h: factor in CC6 save area by reading dst node's limit reg */
1186
	if (pvt->fam != 0x15)
1187
		return;
1188

1189 1190 1191
	nb = node_to_amd_nb(dram_dst_node(pvt, range));
	if (WARN_ON(!nb))
		return;
1192

1193 1194 1195 1196 1197 1198
	if (pvt->model == 0x60)
		pci_func = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1;
	else if (pvt->model == 0x30)
		pci_func = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1;
	else
		pci_func = PCI_DEVICE_ID_AMD_15H_NB_F1;
1199 1200

	f1 = pci_get_related_function(nb->misc->vendor, pci_func, nb->misc);
1201 1202
	if (WARN_ON(!f1))
		return;
1203

1204
	amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim);
1205

1206
	pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0);
1207

1208 1209
				    /* {[39:27],111b} */
	pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16;
1210

1211
	pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0);
1212

1213 1214 1215 1216
				    /* [47:40] */
	pvt->ranges[range].lim.hi |= llim >> 13;

	pci_dev_put(f1);
1217 1218
}

1219
static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
1220
				    struct err_info *err)
1221
{
1222
	struct amd64_pvt *pvt = mci->pvt_info;
1223

1224
	error_address_to_page_and_offset(sys_addr, err);
1225 1226 1227 1228 1229

	/*
	 * Find out which node the error address belongs to. This may be
	 * different from the node that detected the error.
	 */
1230 1231
	err->src_mci = find_mc_by_sys_addr(mci, sys_addr);
	if (!err->src_mci) {
1232 1233
		amd64_mc_err(mci, "failed to map error addr 0x%lx to a node\n",
			     (unsigned long)sys_addr);
1234
		err->err_code = ERR_NODE;
1235 1236 1237 1238
		return;
	}

	/* Now map the sys_addr to a CSROW */
1239 1240 1241
	err->csrow = sys_addr_to_csrow(err->src_mci, sys_addr);
	if (err->csrow < 0) {
		err->err_code = ERR_CSROW;
1242 1243 1244
		return;
	}

1245
	/* CHIPKILL enabled */
1246
	if (pvt->nbcfg & NBCFG_CHIPKILL) {
1247 1248
		err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome);
		if (err->channel < 0) {
1249 1250 1251 1252 1253
			/*
			 * Syndrome didn't map, so we don't know which of the
			 * 2 DIMMs is in error. So we need to ID 'both' of them
			 * as suspect.
			 */
1254
			amd64_mc_warn(err->src_mci, "unknown syndrome 0x%04x - "
1255
				      "possible error reporting race\n",
1256 1257
				      err->syndrome);
			err->err_code = ERR_CHANNEL;
1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268
			return;
		}
	} else {
		/*
		 * non-chipkill ecc mode
		 *
		 * The k8 documentation is unclear about how to determine the
		 * channel number when using non-chipkill memory.  This method
		 * was obtained from email communication with someone at AMD.
		 * (Wish the email was placed in this comment - norsk)
		 */
1269
		err->channel = ((sys_addr & BIT(3)) != 0);
1270 1271 1272
	}
}

1273
static int ddr2_cs_size(unsigned i, bool dct_width)
1274
{
1275
	unsigned shift = 0;
1276

1277 1278 1279 1280
	if (i <= 2)
		shift = i;
	else if (!(i & 0x1))
		shift = i >> 1;
1281
	else
1282
		shift = (i + 1) >> 1;
1283

1284 1285 1286 1287
	return 128 << (shift + !!dct_width);
}

static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1288
				  unsigned cs_mode, int cs_mask_nr)
1289 1290 1291 1292 1293 1294 1295 1296
{
	u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;

	if (pvt->ext_model >= K8_REV_F) {
		WARN_ON(cs_mode > 11);
		return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
	}
	else if (pvt->ext_model >= K8_REV_D) {
1297
		unsigned diff;
1298 1299
		WARN_ON(cs_mode > 10);

1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326
		/*
		 * the below calculation, besides trying to win an obfuscated C
		 * contest, maps cs_mode values to DIMM chip select sizes. The
		 * mappings are:
		 *
		 * cs_mode	CS size (mb)
		 * =======	============
		 * 0		32
		 * 1		64
		 * 2		128
		 * 3		128
		 * 4		256
		 * 5		512
		 * 6		256
		 * 7		512
		 * 8		1024
		 * 9		1024
		 * 10		2048
		 *
		 * Basically, it calculates a value with which to shift the
		 * smallest CS size of 32MB.
		 *
		 * ddr[23]_cs_size have a similar purpose.
		 */
		diff = cs_mode/3 + (unsigned)(cs_mode > 5);

		return 32 << (cs_mode - diff);
1327 1328 1329 1330 1331
	}
	else {
		WARN_ON(cs_mode > 6);
		return 32 << cs_mode;
	}
1332 1333
}

1334 1335 1336 1337 1338 1339 1340 1341
/*
 * Get the number of DCT channels in use.
 *
 * Return:
 *	number of Memory Channels in operation
 * Pass back:
 *	contents of the DCL0_LOW register
 */
1342
static int f1x_early_channel_count(struct amd64_pvt *pvt)
1343
{
1344
	int i, j, channels = 0;
1345

1346
	/* On F10h, if we are in 128 bit mode, then we are using 2 channels */
1347
	if (pvt->fam == 0x10 && (pvt->dclr0 & WIDTH_128))
1348
		return 2;
1349 1350

	/*
1351 1352 1353
	 * Need to check if in unganged mode: In such, there are 2 channels,
	 * but they are not in 128 bit mode and thus the above 'dclr0' status
	 * bit will be OFF.
1354 1355 1356 1357
	 *
	 * Need to check DCT0[0] and DCT1[0] to see if only one of them has
	 * their CSEnable bit on. If so, then SINGLE DIMM case.
	 */
1358
	edac_dbg(0, "Data width is not 128 bits - need more decoding\n");
1359

1360 1361 1362 1363 1364
	/*
	 * Check DRAM Bank Address Mapping values for each DIMM to see if there
	 * is more than just one DIMM present in unganged mode. Need to check
	 * both controllers since DIMMs can be placed in either one.
	 */
1365 1366
	for (i = 0; i < 2; i++) {
		u32 dbam = (i ? pvt->dbam1 : pvt->dbam0);
1367

1368 1369 1370 1371 1372 1373
		for (j = 0; j < 4; j++) {
			if (DBAM_DIMM(j, dbam) > 0) {
				channels++;
				break;
			}
		}
1374 1375
	}

1376 1377 1378
	if (channels > 2)
		channels = 2;

1379
	amd64_info("MCT channel count: %d\n", channels);
1380 1381 1382 1383

	return channels;
}

1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396
static int f17_early_channel_count(struct amd64_pvt *pvt)
{
	int i, channels = 0;

	/* SDP Control bit 31 (SdpInit) is clear for unused UMC channels */
	for (i = 0; i < NUM_UMCS; i++)
		channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT);

	amd64_info("MCT channel count: %d\n", channels);

	return channels;
}

1397
static int ddr3_cs_size(unsigned i, bool dct_width)
1398
{
1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418
	unsigned shift = 0;
	int cs_size = 0;

	if (i == 0 || i == 3 || i == 4)
		cs_size = -1;
	else if (i <= 2)
		shift = i;
	else if (i == 12)
		shift = 7;
	else if (!(i & 0x1))
		shift = i >> 1;
	else
		shift = (i + 1) >> 1;

	if (cs_size != -1)
		cs_size = (128 * (1 << !!dct_width)) << shift;

	return cs_size;
}

1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453
static int ddr3_lrdimm_cs_size(unsigned i, unsigned rank_multiply)
{
	unsigned shift = 0;
	int cs_size = 0;

	if (i < 4 || i == 6)
		cs_size = -1;
	else if (i == 12)
		shift = 7;
	else if (!(i & 0x1))
		shift = i >> 1;
	else
		shift = (i + 1) >> 1;

	if (cs_size != -1)
		cs_size = rank_multiply * (128 << shift);

	return cs_size;
}

static int ddr4_cs_size(unsigned i)
{
	int cs_size = 0;

	if (i == 0)
		cs_size = -1;
	else if (i == 1)
		cs_size = 1024;
	else
		/* Min cs_size = 1G */
		cs_size = 1024 * (1 << (i >> 1));

	return cs_size;
}

1454
static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1455
				   unsigned cs_mode, int cs_mask_nr)
1456 1457 1458 1459
{
	u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;

	WARN_ON(cs_mode > 11);
1460 1461

	if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE)
1462
		return ddr3_cs_size(cs_mode, dclr & WIDTH_128);
1463
	else
1464 1465 1466 1467 1468 1469 1470
		return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
}

/*
 * F15h supports only 64bit DCT interfaces
 */
static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1471
				   unsigned cs_mode, int cs_mask_nr)
1472 1473
{
	WARN_ON(cs_mode > 12);
1474

1475
	return ddr3_cs_size(cs_mode, false);
1476 1477
}

1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508
/* F15h M60h supports DDR4 mapping as well.. */
static int f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
					unsigned cs_mode, int cs_mask_nr)
{
	int cs_size;
	u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr];

	WARN_ON(cs_mode > 12);

	if (pvt->dram_type == MEM_DDR4) {
		if (cs_mode > 9)
			return -1;

		cs_size = ddr4_cs_size(cs_mode);
	} else if (pvt->dram_type == MEM_LRDDR3) {
		unsigned rank_multiply = dcsm & 0xf;

		if (rank_multiply == 3)
			rank_multiply = 4;
		cs_size = ddr3_lrdimm_cs_size(cs_mode, rank_multiply);
	} else {
		/* Minimum cs size is 512mb for F15hM60h*/
		if (cs_mode == 0x1)
			return -1;

		cs_size = ddr3_cs_size(cs_mode, false);
	}

	return cs_size;
}

1509
/*
1510
 * F16h and F15h model 30h have only limited cs_modes.
1511 1512
 */
static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1513
				unsigned cs_mode, int cs_mask_nr)
1514 1515 1516 1517 1518 1519 1520 1521 1522 1523
{
	WARN_ON(cs_mode > 12);

	if (cs_mode == 6 || cs_mode == 8 ||
	    cs_mode == 9 || cs_mode == 12)
		return -1;
	else
		return ddr3_cs_size(cs_mode, false);
}

1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540
static int f17_base_addr_to_cs_size(struct amd64_pvt *pvt, u8 umc,
				    unsigned int cs_mode, int csrow_nr)
{
	u32 base_addr = pvt->csels[umc].csbases[csrow_nr];

	/*  Each mask is used for every two base addresses. */
	u32 addr_mask = pvt->csels[umc].csmasks[csrow_nr >> 1];

	/*  Register [31:1] = Address [39:9]. Size is in kBs here. */
	u32 size = ((addr_mask >> 1) - (base_addr >> 1) + 1) >> 1;

	edac_dbg(1, "BaseAddr: 0x%x, AddrMask: 0x%x\n", base_addr, addr_mask);

	/* Return size in MBs. */
	return size >> 10;
}

1541
static void read_dram_ctl_register(struct amd64_pvt *pvt)
1542 1543
{

1544
	if (pvt->fam == 0xf)
1545 1546
		return;

1547
	if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) {
1548 1549
		edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",
			 pvt->dct_sel_lo, dct_sel_baseaddr(pvt));
1550

1551 1552
		edac_dbg(0, "  DCTs operate in %s mode\n",
			 (dct_ganging_enabled(pvt) ? "ganged" : "unganged"));
1553 1554

		if (!dct_ganging_enabled(pvt))
1555 1556
			edac_dbg(0, "  Address range split per DCT: %s\n",
				 (dct_high_range_enabled(pvt) ? "yes" : "no"));
1557

1558 1559 1560
		edac_dbg(0, "  data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n",
			 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),
			 (dct_memory_cleared(pvt) ? "yes" : "no"));
1561

1562 1563 1564 1565
		edac_dbg(0, "  channel interleave: %s, "
			 "interleave bits selector: 0x%x\n",
			 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"),
			 dct_sel_interleave_addr(pvt));
1566 1567
	}

1568
	amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi);
1569 1570
}

1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587
/*
 * Determine channel (DCT) based on the interleaving mode (see F15h M30h BKDG,
 * 2.10.12 Memory Interleaving Modes).
 */
static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
				     u8 intlv_en, int num_dcts_intlv,
				     u32 dct_sel)
{
	u8 channel = 0;
	u8 select;

	if (!(intlv_en))
		return (u8)(dct_sel);

	if (num_dcts_intlv == 2) {
		select = (sys_addr >> 8) & 0x3;
		channel = select ? 0x3 : 0;
1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598
	} else if (num_dcts_intlv == 4) {
		u8 intlv_addr = dct_sel_interleave_addr(pvt);
		switch (intlv_addr) {
		case 0x4:
			channel = (sys_addr >> 8) & 0x3;
			break;
		case 0x5:
			channel = (sys_addr >> 9) & 0x3;
			break;
		}
	}
1599 1600 1601
	return channel;
}

1602
/*
1603
 * Determine channel (DCT) based on the interleaving mode: F10h BKDG, 2.8.9 Memory
1604 1605
 * Interleaving Modes.
 */
1606
static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
1607
				bool hi_range_sel, u8 intlv_en)
1608
{
1609
	u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1;
1610 1611

	if (dct_ganging_enabled(pvt))
1612
		return 0;
1613

1614 1615
	if (hi_range_sel)
		return dct_sel_high;
1616

1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628
	/*
	 * see F2x110[DctSelIntLvAddr] - channel interleave mode
	 */
	if (dct_interleave_enabled(pvt)) {
		u8 intlv_addr = dct_sel_interleave_addr(pvt);

		/* return DCT select function: 0=DCT0, 1=DCT1 */
		if (!intlv_addr)
			return sys_addr >> 6 & 1;

		if (intlv_addr & 0x2) {
			u8 shift = intlv_addr & 0x1 ? 9 : 6;
1629
			u32 temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) & 1;
1630 1631 1632 1633

			return ((sys_addr >> shift) & 1) ^ temp;
		}

1634 1635 1636 1637 1638 1639
		if (intlv_addr & 0x4) {
			u8 shift = intlv_addr & 0x1 ? 9 : 8;

			return (sys_addr >> shift) & 1;
		}

1640 1641 1642 1643 1644
		return (sys_addr >> (12 + hweight8(intlv_en))) & 1;
	}

	if (dct_high_range_enabled(pvt))
		return ~dct_sel_high & 1;
1645 1646 1647 1648

	return 0;
}

1649
/* Convert the sys_addr to the normalized DCT address */
1650
static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range,
1651 1652
				 u64 sys_addr, bool hi_rng,
				 u32 dct_sel_base_addr)
1653 1654
{
	u64 chan_off;
1655 1656
	u64 dram_base		= get_dram_base(pvt, range);
	u64 hole_off		= f10_dhar_offset(pvt);
1657
	u64 dct_sel_base_off	= (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16;
1658

1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672
	if (hi_rng) {
		/*
		 * if
		 * base address of high range is below 4Gb
		 * (bits [47:27] at [31:11])
		 * DRAM address space on this DCT is hoisted above 4Gb	&&
		 * sys_addr > 4Gb
		 *
		 *	remove hole offset from sys_addr
		 * else
		 *	remove high range offset from sys_addr
		 */
		if ((!(dct_sel_base_addr >> 16) ||
		     dct_sel_base_addr < dhar_base(pvt)) &&
1673
		    dhar_valid(pvt) &&
1674
		    (sys_addr >= BIT_64(32)))
1675
			chan_off = hole_off;
1676 1677 1678
		else
			chan_off = dct_sel_base_off;
	} else {
1679 1680 1681 1682 1683 1684 1685 1686 1687
		/*
		 * if
		 * we have a valid hole		&&
		 * sys_addr > 4Gb
		 *
		 *	remove hole
		 * else
		 *	remove dram base to normalize to DCT address
		 */
1688
		if (dhar_valid(pvt) && (sys_addr >= BIT_64(32)))
1689
			chan_off = hole_off;
1690
		else
1691
			chan_off = dram_base;
1692 1693
	}

1694
	return (sys_addr & GENMASK_ULL(47,6)) - (chan_off & GENMASK_ULL(47,23));
1695 1696 1697 1698 1699 1700
}

/*
 * checks if the csrow passed in is marked as SPARED, if so returns the new
 * spare row
 */
1701
static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow)
1702
{
1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713
	int tmp_cs;

	if (online_spare_swap_done(pvt, dct) &&
	    csrow == online_spare_bad_dramcs(pvt, dct)) {

		for_each_chip_select(tmp_cs, dct, pvt) {
			if (chip_select_base(tmp_cs, dct, pvt) & 0x2) {
				csrow = tmp_cs;
				break;
			}
		}
1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725
	}
	return csrow;
}

/*
 * Iterate over the DRAM DCT "base" and "mask" registers looking for a
 * SystemAddr match on the specified 'ChannelSelect' and 'NodeID'
 *
 * Return:
 *	-EINVAL:  NOT FOUND
 *	0..csrow = Chip-Select Row
 */
1726
static int f1x_lookup_addr_in_dct(u64 in_addr, u8 nid, u8 dct)
1727 1728 1729
{
	struct mem_ctl_info *mci;
	struct amd64_pvt *pvt;
1730
	u64 cs_base, cs_mask;
1731 1732 1733
	int cs_found = -EINVAL;
	int csrow;

1734
	mci = edac_mc_find(nid);
1735 1736 1737 1738 1739
	if (!mci)
		return cs_found;

	pvt = mci->pvt_info;

1740
	edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct);
1741

1742 1743
	for_each_chip_select(csrow, dct, pvt) {
		if (!csrow_enabled(csrow, dct, pvt))
1744 1745
			continue;

1746
		get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask);
1747

1748 1749
		edac_dbg(1, "    CSROW=%d CSBase=0x%llx CSMask=0x%llx\n",
			 csrow, cs_base, cs_mask);
1750

1751
		cs_mask = ~cs_mask;
1752

1753 1754
		edac_dbg(1, "    (InputAddr & ~CSMask)=0x%llx (CSBase & ~CSMask)=0x%llx\n",
			 (in_addr & cs_mask), (cs_base & cs_mask));
1755

1756
		if ((in_addr & cs_mask) == (cs_base & cs_mask)) {
1757 1758 1759 1760
			if (pvt->fam == 0x15 && pvt->model >= 0x30) {
				cs_found =  csrow;
				break;
			}
1761
			cs_found = f10_process_possible_spare(pvt, dct, csrow);
1762

1763
			edac_dbg(1, " MATCH csrow=%d\n", cs_found);
1764 1765 1766 1767 1768 1769
			break;
		}
	}
	return cs_found;
}

1770 1771 1772 1773 1774
/*
 * See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is
 * swapped with a region located at the bottom of memory so that the GPU can use
 * the interleaved region and thus two channels.
 */
1775
static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr)
1776 1777 1778
{
	u32 swap_reg, swap_base, swap_limit, rgn_size, tmp_addr;

1779
	if (pvt->fam == 0x10) {
1780
		/* only revC3 and revE have that feature */
1781
		if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3))
1782 1783 1784
			return sys_addr;
	}

1785
	amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg);
1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803

	if (!(swap_reg & 0x1))
		return sys_addr;

	swap_base	= (swap_reg >> 3) & 0x7f;
	swap_limit	= (swap_reg >> 11) & 0x7f;
	rgn_size	= (swap_reg >> 20) & 0x7f;
	tmp_addr	= sys_addr >> 27;

	if (!(sys_addr >> 34) &&
	    (((tmp_addr >= swap_base) &&
	     (tmp_addr <= swap_limit)) ||
	     (tmp_addr < rgn_size)))
		return sys_addr ^ (u64)swap_base << 27;

	return sys_addr;
}

1804
/* For a given @dram_range, check if @sys_addr falls within it. */
1805
static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
1806
				  u64 sys_addr, int *chan_sel)
1807
{
1808
	int cs_found = -EINVAL;
1809
	u64 chan_addr;
1810
	u32 dct_sel_base;
1811
	u8 channel;
1812
	bool high_range = false;
1813

1814
	u8 node_id    = dram_dst_node(pvt, range);
1815
	u8 intlv_en   = dram_intlv_en(pvt, range);
1816
	u32 intlv_sel = dram_intlv_sel(pvt, range);
1817

1818 1819
	edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
		 range, sys_addr, get_dram_limit(pvt, range));
1820

1821 1822 1823 1824 1825 1826 1827 1828
	if (dhar_valid(pvt) &&
	    dhar_base(pvt) <= sys_addr &&
	    sys_addr < BIT_64(32)) {
		amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n",
			    sys_addr);
		return -EINVAL;
	}

1829
	if (intlv_en && (intlv_sel != ((sys_addr >> 12) & intlv_en)))
1830 1831
		return -EINVAL;

1832
	sys_addr = f1x_swap_interleaved_region(pvt, sys_addr);
1833

1834 1835 1836 1837 1838 1839 1840 1841 1842
	dct_sel_base = dct_sel_baseaddr(pvt);

	/*
	 * check whether addresses >= DctSelBaseAddr[47:27] are to be used to
	 * select between DCT0 and DCT1.
	 */
	if (dct_high_range_enabled(pvt) &&
	   !dct_ganging_enabled(pvt) &&
	   ((sys_addr >> 27) >= (dct_sel_base >> 11)))
1843
		high_range = true;
1844

1845
	channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en);
1846

1847
	chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr,
1848
					  high_range, dct_sel_base);
1849

1850 1851 1852 1853
	/* Remove node interleaving, see F1x120 */
	if (intlv_en)
		chan_addr = ((chan_addr >> (12 + hweight8(intlv_en))) << 12) |
			    (chan_addr & 0xfff);
1854

1855
	/* remove channel interleave */
1856 1857 1858
	if (dct_interleave_enabled(pvt) &&
	   !dct_high_range_enabled(pvt) &&
	   !dct_ganging_enabled(pvt)) {
1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872

		if (dct_sel_interleave_addr(pvt) != 1) {
			if (dct_sel_interleave_addr(pvt) == 0x3)
				/* hash 9 */
				chan_addr = ((chan_addr >> 10) << 9) |
					     (chan_addr & 0x1ff);
			else
				/* A[6] or hash 6 */
				chan_addr = ((chan_addr >> 7) << 6) |
					     (chan_addr & 0x3f);
		} else
			/* A[12] */
			chan_addr = ((chan_addr >> 13) << 12) |
				     (chan_addr & 0xfff);
1873 1874
	}

1875
	edac_dbg(1, "   Normalized DCT addr: 0x%llx\n", chan_addr);
1876

1877
	cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, channel);
1878

1879
	if (cs_found >= 0)
1880
		*chan_sel = channel;
1881

1882 1883 1884
	return cs_found;
}

1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921
static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
					u64 sys_addr, int *chan_sel)
{
	int cs_found = -EINVAL;
	int num_dcts_intlv = 0;
	u64 chan_addr, chan_offset;
	u64 dct_base, dct_limit;
	u32 dct_cont_base_reg, dct_cont_limit_reg, tmp;
	u8 channel, alias_channel, leg_mmio_hole, dct_sel, dct_offset_en;

	u64 dhar_offset		= f10_dhar_offset(pvt);
	u8 intlv_addr		= dct_sel_interleave_addr(pvt);
	u8 node_id		= dram_dst_node(pvt, range);
	u8 intlv_en		= dram_intlv_en(pvt, range);

	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg);
	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg);

	dct_offset_en		= (u8) ((dct_cont_base_reg >> 3) & BIT(0));
	dct_sel			= (u8) ((dct_cont_base_reg >> 4) & 0x7);

	edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
		 range, sys_addr, get_dram_limit(pvt, range));

	if (!(get_dram_base(pvt, range)  <= sys_addr) &&
	    !(get_dram_limit(pvt, range) >= sys_addr))
		return -EINVAL;

	if (dhar_valid(pvt) &&
	    dhar_base(pvt) <= sys_addr &&
	    sys_addr < BIT_64(32)) {
		amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n",
			    sys_addr);
		return -EINVAL;
	}

	/* Verify sys_addr is within DCT Range. */
1922 1923
	dct_base = (u64) dct_sel_baseaddr(pvt);
	dct_limit = (dct_cont_limit_reg >> 11) & 0x1FFF;
1924 1925

	if (!(dct_cont_base_reg & BIT(0)) &&
1926 1927
	    !(dct_base <= (sys_addr >> 27) &&
	      dct_limit >= (sys_addr >> 27)))
1928 1929 1930 1931 1932 1933 1934 1935
		return -EINVAL;

	/* Verify number of dct's that participate in channel interleaving. */
	num_dcts_intlv = (int) hweight8(intlv_en);

	if (!(num_dcts_intlv % 2 == 0) || (num_dcts_intlv > 4))
		return -EINVAL;

1936 1937 1938 1939 1940
	if (pvt->model >= 0x60)
		channel = f1x_determine_channel(pvt, sys_addr, false, intlv_en);
	else
		channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en,
						     num_dcts_intlv, dct_sel);
1941 1942

	/* Verify we stay within the MAX number of channels allowed */
1943
	if (channel > 3)
1944 1945 1946 1947 1948 1949 1950 1951
		return -EINVAL;

	leg_mmio_hole = (u8) (dct_cont_base_reg >> 1 & BIT(0));

	/* Get normalized DCT addr */
	if (leg_mmio_hole && (sys_addr >= BIT_64(32)))
		chan_offset = dhar_offset;
	else
1952
		chan_offset = dct_base << 27;
1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981

	chan_addr = sys_addr - chan_offset;

	/* remove channel interleave */
	if (num_dcts_intlv == 2) {
		if (intlv_addr == 0x4)
			chan_addr = ((chan_addr >> 9) << 8) |
						(chan_addr & 0xff);
		else if (intlv_addr == 0x5)
			chan_addr = ((chan_addr >> 10) << 9) |
						(chan_addr & 0x1ff);
		else
			return -EINVAL;

	} else if (num_dcts_intlv == 4) {
		if (intlv_addr == 0x4)
			chan_addr = ((chan_addr >> 10) << 8) |
							(chan_addr & 0xff);
		else if (intlv_addr == 0x5)
			chan_addr = ((chan_addr >> 11) << 9) |
							(chan_addr & 0x1ff);
		else
			return -EINVAL;
	}

	if (dct_offset_en) {
		amd64_read_pci_cfg(pvt->F1,
				   DRAM_CONT_HIGH_OFF + (int) channel * 4,
				   &tmp);
1982
		chan_addr +=  (u64) ((tmp >> 11) & 0xfff) << 27;
1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009
	}

	f15h_select_dct(pvt, channel);

	edac_dbg(1, "   Normalized DCT addr: 0x%llx\n", chan_addr);

	/*
	 * Find Chip select:
	 * if channel = 3, then alias it to 1. This is because, in F15 M30h,
	 * there is support for 4 DCT's, but only 2 are currently functional.
	 * They are DCT0 and DCT3. But we have read all registers of DCT3 into
	 * pvt->csels[1]. So we need to use '1' here to get correct info.
	 * Refer F15 M30h BKDG Section 2.10 and 2.10.3 for clarifications.
	 */
	alias_channel =  (channel == 3) ? 1 : channel;

	cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, alias_channel);

	if (cs_found >= 0)
		*chan_sel = alias_channel;

	return cs_found;
}

static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt,
					u64 sys_addr,
					int *chan_sel)
2010
{
2011 2012
	int cs_found = -EINVAL;
	unsigned range;
2013

2014 2015
	for (range = 0; range < DRAM_RANGES; range++) {
		if (!dram_rw(pvt, range))
2016 2017
			continue;

2018 2019 2020 2021
		if (pvt->fam == 0x15 && pvt->model >= 0x30)
			cs_found = f15_m30h_match_to_this_node(pvt, range,
							       sys_addr,
							       chan_sel);
2022

2023 2024
		else if ((get_dram_base(pvt, range)  <= sys_addr) &&
			 (get_dram_limit(pvt, range) >= sys_addr)) {
2025
			cs_found = f1x_match_to_this_node(pvt, range,
2026
							  sys_addr, chan_sel);
2027 2028 2029 2030 2031 2032 2033 2034
			if (cs_found >= 0)
				break;
		}
	}
	return cs_found;
}

/*
2035 2036
 * For reference see "2.8.5 Routing DRAM Requests" in F10 BKDG. This code maps
 * a @sys_addr to NodeID, DCT (channel) and chip select (CSROW).
2037
 *
2038 2039
 * The @sys_addr is usually an error address received from the hardware
 * (MCX_ADDR).
2040
 */
2041
static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
2042
				     struct err_info *err)
2043 2044 2045
{
	struct amd64_pvt *pvt = mci->pvt_info;

2046
	error_address_to_page_and_offset(sys_addr, err);
2047

2048 2049 2050
	err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel);
	if (err->csrow < 0) {
		err->err_code = ERR_CSROW;
2051 2052 2053 2054 2055 2056 2057 2058
		return;
	}

	/*
	 * We need the syndromes for channel detection only when we're
	 * ganged. Otherwise @chan should already contain the channel at
	 * this point.
	 */
2059
	if (dct_ganging_enabled(pvt))
2060
		err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome);
2061 2062 2063
}

/*
2064
 * debug routine to display the memory sizes of all logical DIMMs and its
2065
 * CSROWs
2066
 */
2067
static void debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
2068
{
2069
	int dimm, size0, size1;
2070 2071
	u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;
	u32 dbam  = ctrl ? pvt->dbam1 : pvt->dbam0;
2072

2073
	if (pvt->fam == 0xf) {
2074
		/* K8 families < revF not supported yet */
2075
	       if (pvt->ext_model < K8_REV_F)
2076 2077 2078 2079 2080
			return;
	       else
		       WARN_ON(ctrl != 0);
	}

2081 2082 2083 2084 2085 2086 2087 2088 2089 2090
	if (pvt->fam == 0x10) {
		dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1
							   : pvt->dbam0;
		dcsb = (ctrl && !dct_ganging_enabled(pvt)) ?
				 pvt->csels[1].csbases :
				 pvt->csels[0].csbases;
	} else if (ctrl) {
		dbam = pvt->dbam0;
		dcsb = pvt->csels[1].csbases;
	}
2091 2092
	edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",
		 ctrl, dbam);
2093

2094 2095
	edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);

2096 2097 2098 2099
	/* Dump memory sizes for DIMM and its CSROWs */
	for (dimm = 0; dimm < 4; dimm++) {

		size0 = 0;
2100
		if (dcsb[dimm*2] & DCSB_CS_ENABLE)
2101 2102 2103
			/*
			 * For F15m60h, we need multiplier for LRDIMM cs_size
			 * calculation. We pass dimm value to the dbam_to_cs
2104 2105 2106
			 * mapper so we can find the multiplier from the
			 * corresponding DCSM.
			 */
2107
			size0 = pvt->ops->dbam_to_cs(pvt, ctrl,
2108 2109
						     DBAM_DIMM(dimm, dbam),
						     dimm);
2110 2111

		size1 = 0;
2112
		if (dcsb[dimm*2 + 1] & DCSB_CS_ENABLE)
2113
			size1 = pvt->ops->dbam_to_cs(pvt, ctrl,
2114 2115
						     DBAM_DIMM(dimm, dbam),
						     dimm);
2116

2117
		amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n",
2118 2119
				dimm * 2,     size0,
				dimm * 2 + 1, size1);
2120 2121 2122
	}
}

2123
static struct amd64_family_type family_types[] = {
2124
	[K8_CPUS] = {
2125
		.ctl_name = "K8",
2126
		.f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP,
2127
		.f2_id = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,
2128
		.ops = {
2129 2130 2131
			.early_channel_count	= k8_early_channel_count,
			.map_sysaddr_to_csrow	= k8_map_sysaddr_to_csrow,
			.dbam_to_cs		= k8_dbam_to_chip_select,
2132 2133 2134
		}
	},
	[F10_CPUS] = {
2135
		.ctl_name = "F10h",
2136
		.f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP,
2137
		.f2_id = PCI_DEVICE_ID_AMD_10H_NB_DRAM,
2138
		.ops = {
2139
			.early_channel_count	= f1x_early_channel_count,
2140
			.map_sysaddr_to_csrow	= f1x_map_sysaddr_to_csrow,
2141
			.dbam_to_cs		= f10_dbam_to_chip_select,
2142 2143 2144 2145
		}
	},
	[F15_CPUS] = {
		.ctl_name = "F15h",
2146
		.f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1,
2147
		.f2_id = PCI_DEVICE_ID_AMD_15H_NB_F2,
2148
		.ops = {
2149
			.early_channel_count	= f1x_early_channel_count,
2150
			.map_sysaddr_to_csrow	= f1x_map_sysaddr_to_csrow,
2151
			.dbam_to_cs		= f15_dbam_to_chip_select,
2152 2153
		}
	},
2154 2155 2156
	[F15_M30H_CPUS] = {
		.ctl_name = "F15h_M30h",
		.f1_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1,
2157
		.f2_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F2,
2158 2159 2160 2161 2162 2163
		.ops = {
			.early_channel_count	= f1x_early_channel_count,
			.map_sysaddr_to_csrow	= f1x_map_sysaddr_to_csrow,
			.dbam_to_cs		= f16_dbam_to_chip_select,
		}
	},
2164 2165 2166
	[F15_M60H_CPUS] = {
		.ctl_name = "F15h_M60h",
		.f1_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1,
2167
		.f2_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F2,
2168 2169 2170 2171 2172 2173
		.ops = {
			.early_channel_count	= f1x_early_channel_count,
			.map_sysaddr_to_csrow	= f1x_map_sysaddr_to_csrow,
			.dbam_to_cs		= f15_m60h_dbam_to_chip_select,
		}
	},
2174 2175 2176
	[F16_CPUS] = {
		.ctl_name = "F16h",
		.f1_id = PCI_DEVICE_ID_AMD_16H_NB_F1,
2177
		.f2_id = PCI_DEVICE_ID_AMD_16H_NB_F2,
2178 2179 2180 2181 2182 2183
		.ops = {
			.early_channel_count	= f1x_early_channel_count,
			.map_sysaddr_to_csrow	= f1x_map_sysaddr_to_csrow,
			.dbam_to_cs		= f16_dbam_to_chip_select,
		}
	},
2184 2185 2186
	[F16_M30H_CPUS] = {
		.ctl_name = "F16h_M30h",
		.f1_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F1,
2187
		.f2_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F2,
2188 2189 2190 2191 2192 2193
		.ops = {
			.early_channel_count	= f1x_early_channel_count,
			.map_sysaddr_to_csrow	= f1x_map_sysaddr_to_csrow,
			.dbam_to_cs		= f16_dbam_to_chip_select,
		}
	},
2194 2195 2196 2197 2198 2199 2200 2201 2202
	[F17_CPUS] = {
		.ctl_name = "F17h",
		.f0_id = PCI_DEVICE_ID_AMD_17H_DF_F0,
		.f6_id = PCI_DEVICE_ID_AMD_17H_DF_F6,
		.ops = {
			.early_channel_count	= f17_early_channel_count,
			.dbam_to_cs		= f17_base_addr_to_cs_size,
		}
	},
2203 2204
};

2205
/*
2206 2207 2208
 * These are tables of eigenvectors (one per line) which can be used for the
 * construction of the syndrome tables. The modified syndrome search algorithm
 * uses those to find the symbol in error and thus the DIMM.
2209
 *
2210
 * Algorithm courtesy of Ross LaFetra from AMD.
2211
 */
2212
static const u16 x4_vectors[] = {
2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248
	0x2f57, 0x1afe, 0x66cc, 0xdd88,
	0x11eb, 0x3396, 0x7f4c, 0xeac8,
	0x0001, 0x0002, 0x0004, 0x0008,
	0x1013, 0x3032, 0x4044, 0x8088,
	0x106b, 0x30d6, 0x70fc, 0xe0a8,
	0x4857, 0xc4fe, 0x13cc, 0x3288,
	0x1ac5, 0x2f4a, 0x5394, 0xa1e8,
	0x1f39, 0x251e, 0xbd6c, 0x6bd8,
	0x15c1, 0x2a42, 0x89ac, 0x4758,
	0x2b03, 0x1602, 0x4f0c, 0xca08,
	0x1f07, 0x3a0e, 0x6b04, 0xbd08,
	0x8ba7, 0x465e, 0x244c, 0x1cc8,
	0x2b87, 0x164e, 0x642c, 0xdc18,
	0x40b9, 0x80de, 0x1094, 0x20e8,
	0x27db, 0x1eb6, 0x9dac, 0x7b58,
	0x11c1, 0x2242, 0x84ac, 0x4c58,
	0x1be5, 0x2d7a, 0x5e34, 0xa718,
	0x4b39, 0x8d1e, 0x14b4, 0x28d8,
	0x4c97, 0xc87e, 0x11fc, 0x33a8,
	0x8e97, 0x497e, 0x2ffc, 0x1aa8,
	0x16b3, 0x3d62, 0x4f34, 0x8518,
	0x1e2f, 0x391a, 0x5cac, 0xf858,
	0x1d9f, 0x3b7a, 0x572c, 0xfe18,
	0x15f5, 0x2a5a, 0x5264, 0xa3b8,
	0x1dbb, 0x3b66, 0x715c, 0xe3f8,
	0x4397, 0xc27e, 0x17fc, 0x3ea8,
	0x1617, 0x3d3e, 0x6464, 0xb8b8,
	0x23ff, 0x12aa, 0xab6c, 0x56d8,
	0x2dfb, 0x1ba6, 0x913c, 0x7328,
	0x185d, 0x2ca6, 0x7914, 0x9e28,
	0x171b, 0x3e36, 0x7d7c, 0xebe8,
	0x4199, 0x82ee, 0x19f4, 0x2e58,
	0x4807, 0xc40e, 0x130c, 0x3208,
	0x1905, 0x2e0a, 0x5804, 0xac08,
	0x213f, 0x132a, 0xadfc, 0x5ba8,
	0x19a9, 0x2efe, 0xb5cc, 0x6f88,
2249 2250
};

2251
static const u16 x8_vectors[] = {
2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272
	0x0145, 0x028a, 0x2374, 0x43c8, 0xa1f0, 0x0520, 0x0a40, 0x1480,
	0x0211, 0x0422, 0x0844, 0x1088, 0x01b0, 0x44e0, 0x23c0, 0xed80,
	0x1011, 0x0116, 0x022c, 0x0458, 0x08b0, 0x8c60, 0x2740, 0x4e80,
	0x0411, 0x0822, 0x1044, 0x0158, 0x02b0, 0x2360, 0x46c0, 0xab80,
	0x0811, 0x1022, 0x012c, 0x0258, 0x04b0, 0x4660, 0x8cc0, 0x2780,
	0x2071, 0x40e2, 0xa0c4, 0x0108, 0x0210, 0x0420, 0x0840, 0x1080,
	0x4071, 0x80e2, 0x0104, 0x0208, 0x0410, 0x0820, 0x1040, 0x2080,
	0x8071, 0x0102, 0x0204, 0x0408, 0x0810, 0x1020, 0x2040, 0x4080,
	0x019d, 0x03d6, 0x136c, 0x2198, 0x50b0, 0xb2e0, 0x0740, 0x0e80,
	0x0189, 0x03ea, 0x072c, 0x0e58, 0x1cb0, 0x56e0, 0x37c0, 0xf580,
	0x01fd, 0x0376, 0x06ec, 0x0bb8, 0x1110, 0x2220, 0x4440, 0x8880,
	0x0163, 0x02c6, 0x1104, 0x0758, 0x0eb0, 0x2be0, 0x6140, 0xc280,
	0x02fd, 0x01c6, 0x0b5c, 0x1108, 0x07b0, 0x25a0, 0x8840, 0x6180,
	0x0801, 0x012e, 0x025c, 0x04b8, 0x1370, 0x26e0, 0x57c0, 0xb580,
	0x0401, 0x0802, 0x015c, 0x02b8, 0x22b0, 0x13e0, 0x7140, 0xe280,
	0x0201, 0x0402, 0x0804, 0x01b8, 0x11b0, 0x31a0, 0x8040, 0x7180,
	0x0101, 0x0202, 0x0404, 0x0808, 0x1010, 0x2020, 0x4040, 0x8080,
	0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
	0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000,
};

2273
static int decode_syndrome(u16 syndrome, const u16 *vectors, unsigned num_vecs,
2274
			   unsigned v_dim)
2275
{
2276 2277 2278 2279
	unsigned int i, err_sym;

	for (err_sym = 0; err_sym < num_vecs / v_dim; err_sym++) {
		u16 s = syndrome;
2280 2281
		unsigned v_idx =  err_sym * v_dim;
		unsigned v_end = (err_sym + 1) * v_dim;
2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293

		/* walk over all 16 bits of the syndrome */
		for (i = 1; i < (1U << 16); i <<= 1) {

			/* if bit is set in that eigenvector... */
			if (v_idx < v_end && vectors[v_idx] & i) {
				u16 ev_comp = vectors[v_idx++];

				/* ... and bit set in the modified syndrome, */
				if (s & i) {
					/* remove it. */
					s ^= ev_comp;
2294

2295 2296 2297
					if (!s)
						return err_sym;
				}
2298

2299 2300 2301 2302
			} else if (s & i)
				/* can't get to zero, move to next symbol */
				break;
		}
2303 2304
	}

2305
	edac_dbg(0, "syndrome(%x) not found\n", syndrome);
2306 2307
	return -1;
}
2308

2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350
static int map_err_sym_to_channel(int err_sym, int sym_size)
{
	if (sym_size == 4)
		switch (err_sym) {
		case 0x20:
		case 0x21:
			return 0;
			break;
		case 0x22:
		case 0x23:
			return 1;
			break;
		default:
			return err_sym >> 4;
			break;
		}
	/* x8 symbols */
	else
		switch (err_sym) {
		/* imaginary bits not in a DIMM */
		case 0x10:
			WARN(1, KERN_ERR "Invalid error symbol: 0x%x\n",
					  err_sym);
			return -1;
			break;

		case 0x11:
			return 0;
			break;
		case 0x12:
			return 1;
			break;
		default:
			return err_sym >> 3;
			break;
		}
	return -1;
}

static int get_channel_from_ecc_syndrome(struct mem_ctl_info *mci, u16 syndrome)
{
	struct amd64_pvt *pvt = mci->pvt_info;
2351 2352
	int err_sym = -1;

2353
	if (pvt->ecc_sym_sz == 8)
2354 2355
		err_sym = decode_syndrome(syndrome, x8_vectors,
					  ARRAY_SIZE(x8_vectors),
2356 2357
					  pvt->ecc_sym_sz);
	else if (pvt->ecc_sym_sz == 4)
2358 2359
		err_sym = decode_syndrome(syndrome, x4_vectors,
					  ARRAY_SIZE(x4_vectors),
2360
					  pvt->ecc_sym_sz);
2361
	else {
2362
		amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz);
2363
		return err_sym;
2364
	}
2365

2366
	return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz);
2367 2368
}

2369
static void __log_ecc_error(struct mem_ctl_info *mci, struct err_info *err,
2370
			    u8 ecc_type)
2371
{
2372 2373
	enum hw_event_mc_err_type err_type;
	const char *string;
2374

2375 2376 2377 2378
	if (ecc_type == 2)
		err_type = HW_EVENT_ERR_CORRECTED;
	else if (ecc_type == 1)
		err_type = HW_EVENT_ERR_UNCORRECTED;
2379 2380
	else if (ecc_type == 3)
		err_type = HW_EVENT_ERR_DEFERRED;
2381 2382
	else {
		WARN(1, "Something is rotten in the state of Denmark.\n");
2383 2384 2385
		return;
	}

2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396
	switch (err->err_code) {
	case DECODE_OK:
		string = "";
		break;
	case ERR_NODE:
		string = "Failed to map error addr to a node";
		break;
	case ERR_CSROW:
		string = "Failed to map error addr to a csrow";
		break;
	case ERR_CHANNEL:
2397 2398 2399 2400 2401 2402 2403
		string = "Unknown syndrome - possible error reporting race";
		break;
	case ERR_SYND:
		string = "MCA_SYND not valid - unknown syndrome and csrow";
		break;
	case ERR_NORM_ADDR:
		string = "Cannot decode normalized address";
2404 2405 2406 2407
		break;
	default:
		string = "WTF error";
		break;
2408
	}
2409 2410 2411 2412 2413

	edac_mc_handle_error(err_type, mci, 1,
			     err->page, err->offset, err->syndrome,
			     err->csrow, err->channel, -1,
			     string, "");
2414 2415
}

2416
static inline void decode_bus_error(int node_id, struct mce *m)
2417
{
2418 2419
	struct mem_ctl_info *mci;
	struct amd64_pvt *pvt;
2420
	u8 ecc_type = (m->status >> 45) & 0x3;
2421 2422
	u8 xec = XEC(m->status, 0x1f);
	u16 ec = EC(m->status);
2423 2424
	u64 sys_addr;
	struct err_info err;
2425

2426 2427 2428 2429 2430 2431
	mci = edac_mc_find(node_id);
	if (!mci)
		return;

	pvt = mci->pvt_info;

2432
	/* Bail out early if this was an 'observed' error */
2433
	if (PP(ec) == NBSL_PP_OBS)
2434
		return;
2435

2436 2437
	/* Do only ECC errors */
	if (xec && xec != F10_NBSL_EXT_ERR_ECC)
2438 2439
		return;

2440 2441
	memset(&err, 0, sizeof(err));

2442
	sys_addr = get_error_address(pvt, m);
2443

2444
	if (ecc_type == 2)
2445 2446 2447 2448
		err.syndrome = extract_syndrome(m->status);

	pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err);

2449
	__log_ecc_error(mci, &err, ecc_type);
2450 2451
}

2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521
/*
 * To find the UMC channel represented by this bank we need to match on its
 * instance_id. The instance_id of a bank is held in the lower 32 bits of its
 * IPID.
 */
static int find_umc_channel(struct amd64_pvt *pvt, struct mce *m)
{
	u32 umc_instance_id[] = {0x50f00, 0x150f00};
	u32 instance_id = m->ipid & GENMASK(31, 0);
	int i, channel = -1;

	for (i = 0; i < ARRAY_SIZE(umc_instance_id); i++)
		if (umc_instance_id[i] == instance_id)
			channel = i;

	return channel;
}

static void decode_umc_error(int node_id, struct mce *m)
{
	u8 ecc_type = (m->status >> 45) & 0x3;
	struct mem_ctl_info *mci;
	struct amd64_pvt *pvt;
	struct err_info err;
	u64 sys_addr;

	mci = edac_mc_find(node_id);
	if (!mci)
		return;

	pvt = mci->pvt_info;

	memset(&err, 0, sizeof(err));

	if (m->status & MCI_STATUS_DEFERRED)
		ecc_type = 3;

	err.channel = find_umc_channel(pvt, m);
	if (err.channel < 0) {
		err.err_code = ERR_CHANNEL;
		goto log_error;
	}

	if (umc_normaddr_to_sysaddr(m->addr, pvt->mc_node_id, err.channel, &sys_addr)) {
		err.err_code = ERR_NORM_ADDR;
		goto log_error;
	}

	error_address_to_page_and_offset(sys_addr, &err);

	if (!(m->status & MCI_STATUS_SYNDV)) {
		err.err_code = ERR_SYND;
		goto log_error;
	}

	if (ecc_type == 2) {
		u8 length = (m->synd >> 18) & 0x3f;

		if (length)
			err.syndrome = (m->synd >> 32) & GENMASK(length - 1, 0);
		else
			err.err_code = ERR_CHANNEL;
	}

	err.csrow = m->synd & 0x7;

log_error:
	__log_ecc_error(mci, &err, ecc_type);
}

2522
/*
2523 2524
 * Use pvt->F3 which contains the F3 CPU PCI device to get the related
 * F1 (AddrMap) and F2 (Dct) devices. Return negative value on error.
2525
 * Reserve F0 and F6 on systems with a UMC.
2526
 */
2527 2528 2529 2530 2531 2532
static int
reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2)
{
	if (pvt->umc) {
		pvt->F0 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);
		if (!pvt->F0) {
2533
			amd64_err("F0 not found, device 0x%x (broken BIOS?)\n", pci_id1);
2534 2535 2536 2537 2538 2539 2540 2541
			return -ENODEV;
		}

		pvt->F6 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3);
		if (!pvt->F6) {
			pci_dev_put(pvt->F0);
			pvt->F0 = NULL;

2542
			amd64_err("F6 not found: device 0x%x (broken BIOS?)\n", pci_id2);
2543 2544
			return -ENODEV;
		}
2545

2546 2547 2548 2549 2550 2551 2552
		edac_dbg(1, "F0: %s\n", pci_name(pvt->F0));
		edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
		edac_dbg(1, "F6: %s\n", pci_name(pvt->F6));

		return 0;
	}

2553
	/* Reserve the ADDRESS MAP Device */
2554
	pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);
2555
	if (!pvt->F1) {
2556
		amd64_err("F1 not found: device 0x%x (broken BIOS?)\n", pci_id1);
2557
		return -ENODEV;
2558 2559
	}

2560
	/* Reserve the DCT Device */
2561
	pvt->F2 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3);
2562
	if (!pvt->F2) {
2563 2564
		pci_dev_put(pvt->F1);
		pvt->F1 = NULL;
2565

2566 2567
		amd64_err("F2 not found: device 0x%x (broken BIOS?)\n", pci_id2);
		return -ENODEV;
2568
	}
2569

2570 2571 2572
	edac_dbg(1, "F1: %s\n", pci_name(pvt->F1));
	edac_dbg(1, "F2: %s\n", pci_name(pvt->F2));
	edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
2573 2574 2575 2576

	return 0;
}

2577
static void free_mc_sibling_devs(struct amd64_pvt *pvt)
2578
{
2579 2580 2581 2582 2583 2584 2585
	if (pvt->umc) {
		pci_dev_put(pvt->F0);
		pci_dev_put(pvt->F6);
	} else {
		pci_dev_put(pvt->F1);
		pci_dev_put(pvt->F2);
	}
2586 2587
}

2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635
static void determine_ecc_sym_sz(struct amd64_pvt *pvt)
{
	pvt->ecc_sym_sz = 4;

	if (pvt->umc) {
		u8 i;

		for (i = 0; i < NUM_UMCS; i++) {
			/* Check enabled channels only: */
			if ((pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) &&
			    (pvt->umc[i].ecc_ctrl & BIT(7))) {
				pvt->ecc_sym_sz = 8;
				break;
			}
		}

		return;
	}

	if (pvt->fam >= 0x10) {
		u32 tmp;

		amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
		/* F16h has only DCT0, so no need to read dbam1. */
		if (pvt->fam != 0x16)
			amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1);

		/* F10h, revD and later can do x8 ECC too. */
		if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25))
			pvt->ecc_sym_sz = 8;
	}
}

/*
 * Retrieve the hardware registers of the memory controller.
 */
static void __read_mc_regs_df(struct amd64_pvt *pvt)
{
	u8 nid = pvt->mc_node_id;
	struct amd64_umc *umc;
	u32 i, umc_base;

	/* Read registers from each UMC */
	for (i = 0; i < NUM_UMCS; i++) {

		umc_base = get_umc_base(i);
		umc = &pvt->umc[i];

2636 2637
		amd_smn_read(nid, umc_base + UMCCH_DIMM_CFG, &umc->dimm_cfg);
		amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg);
2638 2639
		amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl);
		amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl);
2640
		amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi);
2641 2642 2643
	}
}

2644 2645 2646 2647
/*
 * Retrieve the hardware registers of the memory controller (this includes the
 * 'Address Map' and 'Misc' device regs)
 */
2648
static void read_mc_regs(struct amd64_pvt *pvt)
2649
{
2650
	unsigned int range;
2651 2652 2653 2654
	u64 msr_val;

	/*
	 * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since
2655
	 * those are Read-As-Zero.
2656
	 */
2657
	rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem);
2658
	edac_dbg(0, "  TOP_MEM:  0x%016llx\n", pvt->top_mem);
2659

2660
	/* Check first whether TOP_MEM2 is enabled: */
2661
	rdmsrl(MSR_K8_SYSCFG, msr_val);
2662
	if (msr_val & BIT(21)) {
2663
		rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2);
2664
		edac_dbg(0, "  TOP_MEM2: 0x%016llx\n", pvt->top_mem2);
2665
	} else {
2666
		edac_dbg(0, "  TOP_MEM2 disabled\n");
2667 2668 2669 2670 2671 2672 2673 2674
	}

	if (pvt->umc) {
		__read_mc_regs_df(pvt);
		amd64_read_pci_cfg(pvt->F0, DF_DHAR, &pvt->dhar);

		goto skip;
	}
2675

2676
	amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap);
2677

2678
	read_dram_ctl_register(pvt);
2679

2680 2681
	for (range = 0; range < DRAM_RANGES; range++) {
		u8 rw;
2682

2683 2684 2685 2686 2687 2688 2689
		/* read settings for this DRAM range */
		read_dram_base_limit_regs(pvt, range);

		rw = dram_rw(pvt, range);
		if (!rw)
			continue;

2690 2691 2692 2693
		edac_dbg(1, "  DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n",
			 range,
			 get_dram_base(pvt, range),
			 get_dram_limit(pvt, range));
2694

2695 2696 2697 2698 2699 2700
		edac_dbg(1, "   IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n",
			 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled",
			 (rw & 0x1) ? "R" : "-",
			 (rw & 0x2) ? "W" : "-",
			 dram_intlv_sel(pvt, range),
			 dram_dst_node(pvt, range));
2701 2702
	}

2703
	amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar);
2704
	amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0);
2705

2706
	amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare);
2707

2708 2709
	amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0);
	amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0);
2710

2711
	if (!dct_ganging_enabled(pvt)) {
2712 2713
		amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1);
		amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1);
2714
	}
2715

2716 2717 2718
skip:
	read_dct_base_mask(pvt);

2719 2720
	determine_memory_type(pvt);
	edac_dbg(1, "  DIMM type: %s\n", edac_mem_types[pvt->dram_type]);
2721

2722
	determine_ecc_sym_sz(pvt);
2723

2724
	dump_misc_regs(pvt);
2725 2726 2727 2728 2729 2730
}

/*
 * NOTE: CPU Revision Dependent code
 *
 * Input:
2731
 *	@csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1)
2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760
 *	k8 private pointer to -->
 *			DRAM Bank Address mapping register
 *			node_id
 *			DCL register where dual_channel_active is
 *
 * The DBAM register consists of 4 sets of 4 bits each definitions:
 *
 * Bits:	CSROWs
 * 0-3		CSROWs 0 and 1
 * 4-7		CSROWs 2 and 3
 * 8-11		CSROWs 4 and 5
 * 12-15	CSROWs 6 and 7
 *
 * Values range from: 0 to 15
 * The meaning of the values depends on CPU revision and dual-channel state,
 * see relevant BKDG more info.
 *
 * The memory controller provides for total of only 8 CSROWs in its current
 * architecture. Each "pair" of CSROWs normally represents just one DIMM in
 * single channel or two (2) DIMMs in dual channel mode.
 *
 * The following code logic collapses the various tables for CSROW based on CPU
 * revision.
 *
 * Returns:
 *	The number of PAGE_SIZE pages on the specified CSROW number it
 *	encompasses
 *
 */
2761
static u32 get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig)
2762
{
2763
	u32 dbam = dct ? pvt->dbam1 : pvt->dbam0;
2764 2765
	int csrow_nr = csrow_nr_orig;
	u32 cs_mode, nr_pages;
2766

2767 2768
	if (!pvt->umc)
		csrow_nr >>= 1;
2769

2770
	cs_mode = DBAM_DIMM(csrow_nr, dbam);
2771

2772 2773
	nr_pages   = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr);
	nr_pages <<= 20 - PAGE_SHIFT;
2774

2775
	edac_dbg(0, "csrow: %d, channel: %d, DBAM idx: %d\n",
2776
		    csrow_nr_orig, dct,  cs_mode);
2777
	edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);
2778 2779 2780 2781 2782 2783 2784 2785

	return nr_pages;
}

/*
 * Initialize the array of csrow attribute instances, based on the values
 * from pci config hardware registers.
 */
2786
static int init_csrows(struct mem_ctl_info *mci)
2787
{
2788
	struct amd64_pvt *pvt = mci->pvt_info;
2789
	enum edac_type edac_mode = EDAC_NONE;
2790
	struct csrow_info *csrow;
2791
	struct dimm_info *dimm;
2792
	int i, j, empty = 1;
2793
	int nr_pages = 0;
2794
	u32 val;
2795

2796 2797
	if (!pvt->umc) {
		amd64_read_pci_cfg(pvt->F3, NBCFG, &val);
2798

2799
		pvt->nbcfg = val;
2800

2801 2802 2803 2804
		edac_dbg(0, "node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",
			 pvt->mc_node_id, val,
			 !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE));
	}
2805

2806 2807 2808
	/*
	 * We iterate over DCT0 here but we look at DCT1 in parallel, if needed.
	 */
2809
	for_each_chip_select(i, 0, pvt) {
2810 2811
		bool row_dct0 = !!csrow_enabled(i, 0, pvt);
		bool row_dct1 = false;
2812

2813
		if (pvt->fam != 0xf)
2814 2815 2816
			row_dct1 = !!csrow_enabled(i, 1, pvt);

		if (!row_dct0 && !row_dct1)
2817 2818
			continue;

2819
		csrow = mci->csrows[i];
2820
		empty = 0;
2821 2822 2823 2824

		edac_dbg(1, "MC node: %d, csrow: %d\n",
			    pvt->mc_node_id, i);

2825
		if (row_dct0) {
2826
			nr_pages = get_csrow_nr_pages(pvt, 0, i);
2827 2828
			csrow->channels[0]->dimm->nr_pages = nr_pages;
		}
2829

2830
		/* K8 has only one DCT */
2831
		if (pvt->fam != 0xf && row_dct1) {
2832
			int row_dct1_pages = get_csrow_nr_pages(pvt, 1, i);
2833 2834 2835 2836

			csrow->channels[1]->dimm->nr_pages = row_dct1_pages;
			nr_pages += row_dct1_pages;
		}
2837

2838
		edac_dbg(1, "Total csrow%d pages: %u\n", i, nr_pages);
2839

2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851
		/* Determine DIMM ECC mode: */
		if (pvt->umc) {
			if (mci->edac_ctl_cap & EDAC_FLAG_S4ECD4ED)
				edac_mode = EDAC_S4ECD4ED;
			else if (mci->edac_ctl_cap & EDAC_FLAG_SECDED)
				edac_mode = EDAC_SECDED;

		} else if (pvt->nbcfg & NBCFG_ECC_ENABLE) {
			edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL)
					? EDAC_S4ECD4ED
					: EDAC_SECDED;
		}
2852 2853

		for (j = 0; j < pvt->channel_count; j++) {
2854
			dimm = csrow->channels[j]->dimm;
2855
			dimm->mtype = pvt->dram_type;
2856
			dimm->edac_mode = edac_mode;
2857
		}
2858 2859 2860 2861
	}

	return empty;
}
2862

2863
/* get all cores on this DCT */
2864
static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, u16 nid)
2865 2866 2867 2868 2869 2870 2871 2872 2873
{
	int cpu;

	for_each_online_cpu(cpu)
		if (amd_get_nb_id(cpu) == nid)
			cpumask_set_cpu(cpu, mask);
}

/* check MCG_CTL on all the cpus on this node */
2874
static bool nb_mce_bank_enabled_on_node(u16 nid)
2875 2876
{
	cpumask_var_t mask;
2877
	int cpu, nbe;
2878 2879 2880
	bool ret = false;

	if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) {
2881
		amd64_warn("%s: Error allocating mask\n", __func__);
2882 2883 2884 2885 2886 2887 2888 2889
		return false;
	}

	get_cpus_on_this_dct_cpumask(mask, nid);

	rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs);

	for_each_cpu(cpu, mask) {
2890
		struct msr *reg = per_cpu_ptr(msrs, cpu);
2891
		nbe = reg->l & MSR_MCGCTL_NBE;
2892

2893 2894 2895
		edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
			 cpu, reg->q,
			 (nbe ? "enabled" : "disabled"));
2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906

		if (!nbe)
			goto out;
	}
	ret = true;

out:
	free_cpumask_var(mask);
	return ret;
}

2907
static int toggle_ecc_err_reporting(struct ecc_settings *s, u16 nid, bool on)
2908 2909
{
	cpumask_var_t cmask;
2910
	int cpu;
2911 2912

	if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) {
2913
		amd64_warn("%s: error allocating mask\n", __func__);
P
Pan Bian 已提交
2914
		return -ENOMEM;
2915 2916
	}

2917
	get_cpus_on_this_dct_cpumask(cmask, nid);
2918 2919 2920 2921 2922

	rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);

	for_each_cpu(cpu, cmask) {

2923 2924
		struct msr *reg = per_cpu_ptr(msrs, cpu);

2925
		if (on) {
2926
			if (reg->l & MSR_MCGCTL_NBE)
2927
				s->flags.nb_mce_enable = 1;
2928

2929
			reg->l |= MSR_MCGCTL_NBE;
2930 2931
		} else {
			/*
2932
			 * Turn off NB MCE reporting only when it was off before
2933
			 */
2934
			if (!s->flags.nb_mce_enable)
2935
				reg->l &= ~MSR_MCGCTL_NBE;
2936 2937 2938 2939 2940 2941 2942 2943 2944
		}
	}
	wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);

	free_cpumask_var(cmask);

	return 0;
}

2945
static bool enable_ecc_error_reporting(struct ecc_settings *s, u16 nid,
2946
				       struct pci_dev *F3)
2947
{
2948
	bool ret = true;
B
Borislav Petkov 已提交
2949
	u32 value, mask = 0x3;		/* UECC/CECC enable */
2950

2951 2952 2953 2954 2955
	if (toggle_ecc_err_reporting(s, nid, ON)) {
		amd64_warn("Error enabling ECC reporting over MCGCTL!\n");
		return false;
	}

B
Borislav Petkov 已提交
2956
	amd64_read_pci_cfg(F3, NBCTL, &value);
2957

2958 2959
	s->old_nbctl   = value & mask;
	s->nbctl_valid = true;
2960 2961

	value |= mask;
B
Borislav Petkov 已提交
2962
	amd64_write_pci_cfg(F3, NBCTL, value);
2963

2964
	amd64_read_pci_cfg(F3, NBCFG, &value);
2965

2966 2967
	edac_dbg(0, "1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
		 nid, value, !!(value & NBCFG_ECC_ENABLE));
2968

2969
	if (!(value & NBCFG_ECC_ENABLE)) {
2970
		amd64_warn("DRAM ECC disabled on this node, enabling...\n");
2971

2972
		s->flags.nb_ecc_prev = 0;
2973

2974
		/* Attempt to turn on DRAM ECC Enable */
2975 2976
		value |= NBCFG_ECC_ENABLE;
		amd64_write_pci_cfg(F3, NBCFG, value);
2977

2978
		amd64_read_pci_cfg(F3, NBCFG, &value);
2979

2980
		if (!(value & NBCFG_ECC_ENABLE)) {
2981 2982
			amd64_warn("Hardware rejected DRAM ECC enable,"
				   "check memory DIMM configuration.\n");
2983
			ret = false;
2984
		} else {
2985
			amd64_info("Hardware accepted DRAM ECC Enable\n");
2986
		}
2987
	} else {
2988
		s->flags.nb_ecc_prev = 1;
2989
	}
2990

2991 2992
	edac_dbg(0, "2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
		 nid, value, !!(value & NBCFG_ECC_ENABLE));
2993

2994
	return ret;
2995 2996
}

2997
static void restore_ecc_error_reporting(struct ecc_settings *s, u16 nid,
2998
					struct pci_dev *F3)
2999
{
B
Borislav Petkov 已提交
3000 3001
	u32 value, mask = 0x3;		/* UECC/CECC enable */

3002
	if (!s->nbctl_valid)
3003 3004
		return;

B
Borislav Petkov 已提交
3005
	amd64_read_pci_cfg(F3, NBCTL, &value);
3006
	value &= ~mask;
3007
	value |= s->old_nbctl;
3008

B
Borislav Petkov 已提交
3009
	amd64_write_pci_cfg(F3, NBCTL, value);
3010

3011 3012
	/* restore previous BIOS DRAM ECC "off" setting we force-enabled */
	if (!s->flags.nb_ecc_prev) {
3013 3014 3015
		amd64_read_pci_cfg(F3, NBCFG, &value);
		value &= ~NBCFG_ECC_ENABLE;
		amd64_write_pci_cfg(F3, NBCFG, value);
3016 3017 3018
	}

	/* restore the NB Enable MCGCTL bit */
3019
	if (toggle_ecc_err_reporting(s, nid, OFF))
3020
		amd64_warn("Error restoring NB MCGCTL settings!\n");
3021 3022 3023
}

/*
3024 3025 3026 3027
 * EDAC requires that the BIOS have ECC enabled before
 * taking over the processing of ECC errors. A command line
 * option allows to force-enable hardware ECC later in
 * enable_ecc_error_reporting().
3028
 */
3029 3030 3031 3032 3033
static const char *ecc_msg =
	"ECC disabled in the BIOS or no ECC capability, module will not load.\n"
	" Either enable ECC checking or force module loading by setting "
	"'ecc_enable_override'.\n"
	" (Note that use of the override may cause unknown side effects.)\n";
3034

3035
static bool ecc_enabled(struct pci_dev *F3, u16 nid)
3036
{
3037
	bool nb_mce_en = false;
3038 3039
	u8 ecc_en = 0, i;
	u32 value;
3040

3041 3042
	if (boot_cpu_data.x86 >= 0x17) {
		u8 umc_en_mask = 0, ecc_en_mask = 0;
3043

3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065
		for (i = 0; i < NUM_UMCS; i++) {
			u32 base = get_umc_base(i);

			/* Only check enabled UMCs. */
			if (amd_smn_read(nid, base + UMCCH_SDP_CTRL, &value))
				continue;

			if (!(value & UMC_SDP_INIT))
				continue;

			umc_en_mask |= BIT(i);

			if (amd_smn_read(nid, base + UMCCH_UMC_CAP_HI, &value))
				continue;

			if (value & UMC_ECC_ENABLED)
				ecc_en_mask |= BIT(i);
		}

		/* Check whether at least one UMC is enabled: */
		if (umc_en_mask)
			ecc_en = umc_en_mask == ecc_en_mask;
3066 3067
		else
			edac_dbg(0, "Node %d: No enabled UMCs.\n", nid);
3068 3069 3070 3071 3072

		/* Assume UMC MCA banks are enabled. */
		nb_mce_en = true;
	} else {
		amd64_read_pci_cfg(F3, NBCFG, &value);
3073

3074 3075 3076 3077
		ecc_en = !!(value & NBCFG_ECC_ENABLE);

		nb_mce_en = nb_mce_bank_enabled_on_node(nid);
		if (!nb_mce_en)
3078
			edac_dbg(0, "NB MCE bank disabled, set MSR 0x%08x[4] on node %d to enable.\n",
3079 3080 3081
				     MSR_IA32_MCG_CTL, nid);
	}

3082 3083
	amd64_info("Node %d: DRAM ECC %s.\n",
		   nid, (ecc_en ? "enabled" : "disabled"));
3084

3085
	if (!ecc_en || !nb_mce_en) {
3086
		amd64_info("%s", ecc_msg);
3087 3088 3089
		return false;
	}
	return true;
3090 3091
}

3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112
static inline void
f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt)
{
	u8 i, ecc_en = 1, cpk_en = 1;

	for (i = 0; i < NUM_UMCS; i++) {
		if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {
			ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED);
			cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP);
		}
	}

	/* Set chipkill only if ECC is enabled: */
	if (ecc_en) {
		mci->edac_ctl_cap |= EDAC_FLAG_SECDED;

		if (cpk_en)
			mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
	}
}

3113 3114
static void setup_mci_misc_attrs(struct mem_ctl_info *mci,
				 struct amd64_family_type *fam)
3115 3116 3117 3118 3119 3120
{
	struct amd64_pvt *pvt = mci->pvt_info;

	mci->mtype_cap		= MEM_FLAG_DDR2 | MEM_FLAG_RDDR2;
	mci->edac_ctl_cap	= EDAC_FLAG_NONE;

3121 3122 3123 3124 3125
	if (pvt->umc) {
		f17h_determine_edac_ctl_cap(mci, pvt);
	} else {
		if (pvt->nbcap & NBCAP_SECDED)
			mci->edac_ctl_cap |= EDAC_FLAG_SECDED;
3126

3127 3128 3129
		if (pvt->nbcap & NBCAP_CHIPKILL)
			mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
	}
3130

3131
	mci->edac_cap		= determine_edac_cap(pvt);
3132
	mci->mod_name		= EDAC_MOD_STR;
3133
	mci->ctl_name		= fam->ctl_name;
3134
	mci->dev_name		= pci_name(pvt->F3);
3135 3136 3137
	mci->ctl_page_to_phys	= NULL;

	/* memory scrubber interface */
3138 3139
	mci->set_sdram_scrub_rate = set_scrub_rate;
	mci->get_sdram_scrub_rate = get_scrub_rate;
3140 3141
}

3142 3143 3144
/*
 * returns a pointer to the family descriptor on success, NULL otherwise.
 */
3145
static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
3146
{
3147 3148
	struct amd64_family_type *fam_type = NULL;

3149
	pvt->ext_model  = boot_cpu_data.x86_model >> 4;
3150
	pvt->stepping	= boot_cpu_data.x86_stepping;
3151 3152 3153 3154
	pvt->model	= boot_cpu_data.x86_model;
	pvt->fam	= boot_cpu_data.x86;

	switch (pvt->fam) {
3155
	case 0xf:
3156 3157
		fam_type	= &family_types[K8_CPUS];
		pvt->ops	= &family_types[K8_CPUS].ops;
3158
		break;
3159

3160
	case 0x10:
3161 3162
		fam_type	= &family_types[F10_CPUS];
		pvt->ops	= &family_types[F10_CPUS].ops;
3163 3164 3165
		break;

	case 0x15:
3166
		if (pvt->model == 0x30) {
3167 3168
			fam_type = &family_types[F15_M30H_CPUS];
			pvt->ops = &family_types[F15_M30H_CPUS].ops;
3169
			break;
3170 3171 3172 3173
		} else if (pvt->model == 0x60) {
			fam_type = &family_types[F15_M60H_CPUS];
			pvt->ops = &family_types[F15_M60H_CPUS].ops;
			break;
3174 3175
		}

3176 3177
		fam_type	= &family_types[F15_CPUS];
		pvt->ops	= &family_types[F15_CPUS].ops;
3178 3179
		break;

3180
	case 0x16:
3181 3182 3183 3184 3185
		if (pvt->model == 0x30) {
			fam_type = &family_types[F16_M30H_CPUS];
			pvt->ops = &family_types[F16_M30H_CPUS].ops;
			break;
		}
3186 3187
		fam_type	= &family_types[F16_CPUS];
		pvt->ops	= &family_types[F16_CPUS].ops;
3188 3189
		break;

3190 3191 3192 3193 3194
	case 0x17:
		fam_type	= &family_types[F17_CPUS];
		pvt->ops	= &family_types[F17_CPUS].ops;
		break;

3195
	default:
3196
		amd64_err("Unsupported family!\n");
3197
		return NULL;
3198
	}
3199

3200
	amd64_info("%s %sdetected (node %d).\n", fam_type->ctl_name,
3201
		     (pvt->fam == 0xf ?
3202 3203 3204
				(pvt->ext_model >= K8_REV_F  ? "revF or later "
							     : "revE or earlier ")
				 : ""), pvt->mc_node_id);
3205
	return fam_type;
3206 3207
}

3208 3209 3210 3211 3212 3213 3214 3215 3216 3217
static const struct attribute_group *amd64_edac_attr_groups[] = {
#ifdef CONFIG_EDAC_DEBUG
	&amd64_edac_dbg_group,
#endif
#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
	&amd64_edac_inj_group,
#endif
	NULL
};

3218
static int init_one_instance(unsigned int nid)
3219
{
3220
	struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
3221
	struct amd64_family_type *fam_type = NULL;
3222
	struct mem_ctl_info *mci = NULL;
3223
	struct edac_mc_layer layers[2];
3224
	struct amd64_pvt *pvt = NULL;
3225
	u16 pci_id1, pci_id2;
3226 3227 3228 3229 3230
	int err = 0, ret;

	ret = -ENOMEM;
	pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL);
	if (!pvt)
3231
		goto err_ret;
3232

3233
	pvt->mc_node_id	= nid;
3234
	pvt->F3 = F3;
3235

3236
	ret = -EINVAL;
3237
	fam_type = per_family_init(pvt);
3238
	if (!fam_type)
3239 3240
		goto err_free;

3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255
	if (pvt->fam >= 0x17) {
		pvt->umc = kcalloc(NUM_UMCS, sizeof(struct amd64_umc), GFP_KERNEL);
		if (!pvt->umc) {
			ret = -ENOMEM;
			goto err_free;
		}

		pci_id1 = fam_type->f0_id;
		pci_id2 = fam_type->f6_id;
	} else {
		pci_id1 = fam_type->f1_id;
		pci_id2 = fam_type->f2_id;
	}

	err = reserve_mc_sibling_devs(pvt, pci_id1, pci_id2);
3256
	if (err)
3257
		goto err_post_init;
3258

3259
	read_mc_regs(pvt);
3260 3261 3262 3263

	/*
	 * We need to determine how many memory channels there are. Then use
	 * that information for calculating the size of the dynamic instance
3264
	 * tables in the 'mci' structure.
3265
	 */
3266
	ret = -EINVAL;
3267 3268
	pvt->channel_count = pvt->ops->early_channel_count(pvt);
	if (pvt->channel_count < 0)
3269
		goto err_siblings;
3270 3271

	ret = -ENOMEM;
3272 3273 3274 3275
	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = pvt->csels[0].b_cnt;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
3276 3277 3278 3279 3280 3281 3282

	/*
	 * Always allocate two channels since we can have setups with DIMMs on
	 * only one channel. Also, this simplifies handling later for the price
	 * of a couple of KBs tops.
	 */
	layers[1].size = 2;
3283
	layers[1].is_virt_csrow = false;
3284

3285
	mci = edac_mc_alloc(nid, ARRAY_SIZE(layers), layers, 0);
3286
	if (!mci)
3287
		goto err_siblings;
3288 3289

	mci->pvt_info = pvt;
3290
	mci->pdev = &pvt->F3->dev;
3291

3292
	setup_mci_misc_attrs(mci, fam_type);
3293 3294

	if (init_csrows(mci))
3295 3296 3297
		mci->edac_cap = EDAC_FLAG_NONE;

	ret = -ENODEV;
3298
	if (edac_mc_add_mc_with_groups(mci, amd64_edac_attr_groups)) {
3299
		edac_dbg(1, "failed edac_mc_add_mc()\n");
3300 3301 3302 3303 3304 3305 3306 3307
		goto err_add_mc;
	}

	return 0;

err_add_mc:
	edac_mc_free(mci);

3308 3309
err_siblings:
	free_mc_sibling_devs(pvt);
3310

3311 3312 3313 3314
err_post_init:
	if (pvt->fam >= 0x17)
		kfree(pvt->umc);

3315 3316
err_free:
	kfree(pvt);
3317

3318
err_ret:
3319 3320 3321
	return ret;
}

3322
static int probe_one_instance(unsigned int nid)
3323
{
3324
	struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
3325
	struct ecc_settings *s;
3326
	int ret;
3327

3328 3329 3330
	ret = -ENOMEM;
	s = kzalloc(sizeof(struct ecc_settings), GFP_KERNEL);
	if (!s)
3331
		goto err_out;
3332 3333 3334

	ecc_stngs[nid] = s;

3335
	if (!ecc_enabled(F3, nid)) {
3336
		ret = 0;
3337 3338 3339 3340

		if (!ecc_enable_override)
			goto err_enable;

3341 3342 3343 3344 3345
		if (boot_cpu_data.x86 >= 0x17) {
			amd64_warn("Forcing ECC on is not recommended on newer systems. Please enable ECC in BIOS.");
			goto err_enable;
		} else
			amd64_warn("Forcing ECC on!\n");
3346 3347 3348 3349 3350

		if (!enable_ecc_error_reporting(s, nid, F3))
			goto err_enable;
	}

3351
	ret = init_one_instance(nid);
3352
	if (ret < 0) {
3353
		amd64_err("Error probing instance: %d\n", nid);
3354 3355 3356

		if (boot_cpu_data.x86 < 0x17)
			restore_ecc_error_reporting(s, nid, F3);
3357 3358

		goto err_enable;
3359
	}
3360 3361

	return ret;
3362 3363 3364 3365 3366 3367 3368

err_enable:
	kfree(s);
	ecc_stngs[nid] = NULL;

err_out:
	return ret;
3369 3370
}

3371
static void remove_one_instance(unsigned int nid)
3372
{
3373 3374
	struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
	struct ecc_settings *s = ecc_stngs[nid];
3375 3376
	struct mem_ctl_info *mci;
	struct amd64_pvt *pvt;
3377

3378
	mci = find_mci_by_dev(&F3->dev);
3379 3380
	WARN_ON(!mci);

3381
	/* Remove from EDAC CORE tracking list */
3382
	mci = edac_mc_del_mc(&F3->dev);
3383 3384 3385 3386 3387
	if (!mci)
		return;

	pvt = mci->pvt_info;

3388
	restore_ecc_error_reporting(s, nid, F3);
3389

3390
	free_mc_sibling_devs(pvt);
3391

3392 3393
	kfree(ecc_stngs[nid]);
	ecc_stngs[nid] = NULL;
3394

3395
	/* Free the EDAC CORE resources */
3396 3397 3398
	mci->pvt_info = NULL;

	kfree(pvt);
3399 3400 3401
	edac_mc_free(mci);
}

3402
static void setup_pci_device(void)
3403 3404 3405 3406
{
	struct mem_ctl_info *mci;
	struct amd64_pvt *pvt;

3407
	if (pci_ctl)
3408 3409
		return;

3410
	mci = edac_mc_find(0);
3411 3412
	if (!mci)
		return;
3413

3414
	pvt = mci->pvt_info;
3415 3416 3417 3418
	if (pvt->umc)
		pci_ctl = edac_pci_create_generic_ctl(&pvt->F0->dev, EDAC_MOD_STR);
	else
		pci_ctl = edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR);
3419 3420 3421
	if (!pci_ctl) {
		pr_warn("%s(): Unable to create PCI control\n", __func__);
		pr_warn("%s(): PCI error report via EDAC not set\n", __func__);
3422 3423 3424
	}
}

3425 3426 3427 3428 3429
static const struct x86_cpu_id amd64_cpuids[] = {
	{ X86_VENDOR_AMD, 0xF,	X86_MODEL_ANY,	X86_FEATURE_ANY, 0 },
	{ X86_VENDOR_AMD, 0x10, X86_MODEL_ANY,	X86_FEATURE_ANY, 0 },
	{ X86_VENDOR_AMD, 0x15, X86_MODEL_ANY,	X86_FEATURE_ANY, 0 },
	{ X86_VENDOR_AMD, 0x16, X86_MODEL_ANY,	X86_FEATURE_ANY, 0 },
3430
	{ X86_VENDOR_AMD, 0x17, X86_MODEL_ANY,	X86_FEATURE_ANY, 0 },
3431 3432 3433 3434
	{ }
};
MODULE_DEVICE_TABLE(x86cpu, amd64_cpuids);

3435 3436
static int __init amd64_edac_init(void)
{
3437
	const char *owner;
3438
	int err = -ENODEV;
3439
	int i;
3440

3441 3442 3443 3444
	owner = edac_get_owner();
	if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
		return -EBUSY;

3445 3446 3447
	if (!x86_match_cpu(amd64_cpuids))
		return -ENODEV;

3448
	if (amd_cache_northbridges() < 0)
3449
		return -ENODEV;
3450

3451 3452
	opstate_init();

3453
	err = -ENOMEM;
3454
	ecc_stngs = kzalloc(amd_nb_num() * sizeof(ecc_stngs[0]), GFP_KERNEL);
3455
	if (!ecc_stngs)
3456
		goto err_free;
3457

3458
	msrs = msrs_alloc();
3459
	if (!msrs)
3460
		goto err_free;
3461

3462 3463 3464
	for (i = 0; i < amd_nb_num(); i++) {
		err = probe_one_instance(i);
		if (err) {
3465 3466 3467
			/* unwind properly */
			while (--i >= 0)
				remove_one_instance(i);
3468

3469 3470
			goto err_pci;
		}
3471
	}
3472

3473 3474 3475 3476 3477
	if (!edac_has_mcs()) {
		err = -ENODEV;
		goto err_pci;
	}

3478 3479 3480 3481 3482 3483 3484 3485 3486
	/* register stuff with EDAC MCE */
	if (report_gart_errors)
		amd_report_gart_errors(true);

	if (boot_cpu_data.x86 >= 0x17)
		amd_register_ecc_decoder(decode_umc_error);
	else
		amd_register_ecc_decoder(decode_bus_error);

3487
	setup_pci_device();
T
Tomasz Pala 已提交
3488 3489 3490 3491 3492

#ifdef CONFIG_X86_32
	amd64_err("%s on 32-bit is unsupported. USE AT YOUR OWN RISK!\n", EDAC_MOD_STR);
#endif

3493 3494
	printk(KERN_INFO "AMD64 EDAC driver v%s\n", EDAC_AMD64_VERSION);

3495
	return 0;
3496

3497 3498 3499
err_pci:
	msrs_free(msrs);
	msrs = NULL;
3500

3501 3502 3503 3504
err_free:
	kfree(ecc_stngs);
	ecc_stngs = NULL;

3505 3506 3507 3508 3509
	return err;
}

static void __exit amd64_edac_exit(void)
{
3510 3511
	int i;

3512 3513
	if (pci_ctl)
		edac_pci_release_generic_ctl(pci_ctl);
3514

3515 3516 3517 3518 3519 3520 3521 3522
	/* unregister from EDAC MCE */
	amd_report_gart_errors(false);

	if (boot_cpu_data.x86 >= 0x17)
		amd_unregister_ecc_decoder(decode_umc_error);
	else
		amd_unregister_ecc_decoder(decode_bus_error);

3523 3524
	for (i = 0; i < amd_nb_num(); i++)
		remove_one_instance(i);
3525

3526 3527 3528
	kfree(ecc_stngs);
	ecc_stngs = NULL;

3529 3530
	msrs_free(msrs);
	msrs = NULL;
3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543
}

module_init(amd64_edac_init);
module_exit(amd64_edac_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, "
		"Dave Peterson, Thayne Harbaugh");
MODULE_DESCRIPTION("MC support for AMD64 memory controllers - "
		EDAC_AMD64_VERSION);

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");