i915_drv.h 104.9 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include "i915_reg.h"
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#include "intel_bios.h"
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#include "intel_ringbuffer.h"
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#include "intel_lrc.h"
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#include "i915_gem_gtt.h"
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#include "i915_gem_render_state.h"
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <drm/intel-gtt.h>
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#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
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#include <drm/drm_gem.h>
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#include <linux/backlight.h>
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#include <linux/hashtable.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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#include "intel_guc.h"
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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20150828"
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#undef WARN_ON
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/* Many gcc seem to no see through this and fall over :( */
#if 0
#define WARN_ON(x) ({ \
	bool __i915_warn_cond = (x); \
	if (__builtin_constant_p(__i915_warn_cond)) \
		BUILD_BUG_ON(__i915_warn_cond); \
	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
#else
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#define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
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#endif

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#undef WARN_ON_ONCE
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#define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
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#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
			     (long) (x), __func__);
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
	if (unlikely(__ret_warn_on)) {					\
		if (i915.verbose_state_checks)				\
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			WARN(1, format);				\
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		else 							\
			DRM_ERROR(format);				\
	}								\
	unlikely(__ret_warn_on);					\
})

#define I915_STATE_WARN_ON(condition) ({				\
	int __ret_warn_on = !!(condition);				\
	if (unlikely(__ret_warn_on)) {					\
		if (i915.verbose_state_checks)				\
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			WARN(1, "WARN_ON(" #condition ")\n");		\
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		else 							\
			DRM_ERROR("WARN_ON(" #condition ")\n");		\
	}								\
	unlikely(__ret_warn_on);					\
})
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static inline const char *yesno(bool v)
{
	return v ? "yes" : "no";
}

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enum pipe {
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	INVALID_PIPE = -1,
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	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
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	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
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	TRANSCODER_EDP,
	I915_MAX_TRANSCODERS
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};
#define transcoder_name(t) ((t) + 'A')

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/*
 * This is the maximum (across all platforms) number of planes (primary +
 * sprites) that can be active at the same time on one pipe.
 *
 * This value doesn't count the cursor plane.
 */
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#define I915_MAX_PLANES	4
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enum plane {
	PLANE_A = 0,
	PLANE_B,
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	PLANE_C,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
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enum port {
	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

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#define I915_NUM_PHYS_VLV 2
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enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
	DPIO_PHY1
};

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enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
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	POWER_DOMAIN_TRANSCODER_EDP,
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	POWER_DOMAIN_PORT_DDI_A_2_LANES,
	POWER_DOMAIN_PORT_DDI_A_4_LANES,
	POWER_DOMAIN_PORT_DDI_B_2_LANES,
	POWER_DOMAIN_PORT_DDI_B_4_LANES,
	POWER_DOMAIN_PORT_DDI_C_2_LANES,
	POWER_DOMAIN_PORT_DDI_C_4_LANES,
	POWER_DOMAIN_PORT_DDI_D_2_LANES,
	POWER_DOMAIN_PORT_DDI_D_4_LANES,
	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
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	POWER_DOMAIN_VGA,
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	POWER_DOMAIN_AUDIO,
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	POWER_DOMAIN_PLLS,
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	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
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	POWER_DOMAIN_INIT,
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	POWER_DOMAIN_NUM,
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};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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#define for_each_plane(__dev_priv, __pipe, __p)				\
	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)
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#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)
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#define for_each_crtc(dev, crtc) \
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)

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#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
			    &dev->mode_config.plane_list,	\
			    base.head)

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#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
		if ((intel_plane)->pipe == (intel_crtc)->pipe)

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#define for_each_intel_crtc(dev, intel_crtc) \
	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)

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#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

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#define for_each_intel_connector(dev, intel_connector)		\
	list_for_each_entry(intel_connector,			\
			    &dev->mode_config.connector_list,	\
			    base.head)

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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
		if ((intel_encoder)->base.crtc == (__crtc))

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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
		if ((intel_connector)->base.encoder == (__encoder))

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#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
		if ((1 << (domain)) & (mask))

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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
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/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
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	} mm;
	struct idr context_idr;

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	struct intel_rps_client {
		struct list_head link;
		unsigned boosts;
	} rps;
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	struct intel_engine_cs *bsd_ring;
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};

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enum intel_dpll_id {
	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
	/* real shared dpll ids must be >= 0 */
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	DPLL_ID_PCH_PLL_A = 0,
	DPLL_ID_PCH_PLL_B = 1,
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	/* hsw/bdw */
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	DPLL_ID_WRPLL1 = 0,
	DPLL_ID_WRPLL2 = 1,
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	/* skl */
	DPLL_ID_SKL_DPLL1 = 0,
	DPLL_ID_SKL_DPLL2 = 1,
	DPLL_ID_SKL_DPLL3 = 2,
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};
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#define I915_NUM_PLLS 3
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struct intel_dpll_hw_state {
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	/* i9xx, pch plls */
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	uint32_t dpll;
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	uint32_t dpll_md;
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	uint32_t fp0;
	uint32_t fp1;
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	/* hsw, bdw */
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	uint32_t wrpll;
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	/* skl */
	/*
	 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
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	 * lower part of ctrl1 and they get shifted into position when writing
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	 * the register.  This allows us to easily compare the state to share
	 * the DPLL.
	 */
	uint32_t ctrl1;
	/* HDMI only, 0 when used for DP */
	uint32_t cfgcr1, cfgcr2;
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	/* bxt */
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	uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
		 pcsdw12;
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};

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struct intel_shared_dpll_config {
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	unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
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	struct intel_dpll_hw_state hw_state;
};

struct intel_shared_dpll {
	struct intel_shared_dpll_config config;
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	int active; /* count of number of active CRTCs (i.e. DPMS on) */
	bool on; /* is the PLL actually active? Disabled during modeset */
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	const char *name;
	/* should match the index in the dev_priv->shared_dplls array */
	enum intel_dpll_id id;
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	/* The mode_set hook is optional and should be used together with the
	 * intel_prepare_shared_dpll function. */
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	void (*mode_set)(struct drm_i915_private *dev_priv,
			 struct intel_shared_dpll *pll);
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	void (*enable)(struct drm_i915_private *dev_priv,
		       struct intel_shared_dpll *pll);
	void (*disable)(struct drm_i915_private *dev_priv,
			struct intel_shared_dpll *pll);
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	bool (*get_hw_state)(struct drm_i915_private *dev_priv,
			     struct intel_shared_dpll *pll,
			     struct intel_dpll_hw_state *hw_state);
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};

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#define SKL_DPLL0 0
#define SKL_DPLL1 1
#define SKL_DPLL2 2
#define SKL_DPLL3 3

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/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

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/* Interface history:
 *
 * 1.1: Original.
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 * 1.2: Add Power Management
 * 1.3: Add vblank support
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 * 1.4: Fix cmdbuffer path, add heap destroy
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 * 1.5: Add vblank pipe configuration
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 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
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 */
#define DRIVER_MAJOR		1
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#define DRIVER_MINOR		6
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#define DRIVER_PATCHLEVEL	0

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#define WATCH_LISTS	0
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struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

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struct intel_opregion {
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	struct opregion_header __iomem *header;
	struct opregion_acpi __iomem *acpi;
	struct opregion_swsci __iomem *swsci;
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	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
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	struct opregion_asle __iomem *asle;
	void __iomem *vbt;
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	u32 __iomem *lid_state;
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	struct work_struct asle_work;
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};
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#define OPREGION_SIZE            (8*1024)
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struct intel_overlay;
struct intel_overlay_error_state;

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#define I915_FENCE_REG_NONE -1
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#define I915_MAX_NUM_FENCES 32
/* 32 fences + sign bit for FENCE_REG_NONE */
#define I915_MAX_NUM_FENCE_BITS 6
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struct drm_i915_fence_reg {
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	struct list_head lru_list;
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	struct drm_i915_gem_object *obj;
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	int pin_count;
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};
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struct sdvo_device_mapping {
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	u8 initialized;
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	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
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	u8 i2c_pin;
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	u8 ddc_pin;
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};

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struct intel_display_error_state;

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struct drm_i915_error_state {
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	struct kref ref;
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	struct timeval time;

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	char error_msg[128];
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	int iommu;
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	u32 reset_count;
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	u32 suspend_count;
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	/* Generic register state */
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	u32 eir;
	u32 pgtbl_er;
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	u32 ier;
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	u32 gtier[4];
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	u32 ccid;
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	u32 derrmr;
	u32 forcewake;
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	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
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	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
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	u32 done_reg;
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	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
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	u32 extra_instdone[I915_NUM_INSTDONE_REG];
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
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	struct drm_i915_error_object *semaphore_obj;
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	struct drm_i915_error_ring {
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		bool valid;
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		/* Software tracked state */
		bool waiting;
		int hangcheck_score;
		enum intel_ring_hangcheck_action hangcheck_action;
		int num_requests;

		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

		u32 semaphore_seqno[I915_NUM_RINGS - 1];

		/* Register state */
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		u32 start;
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		u32 tail;
		u32 head;
		u32 ctl;
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 instdone;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
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		u64 acthd;
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		u32 fault_reg;
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		u64 faddr;
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		u32 rc_psmi; /* sleep state */
		u32 semaphore_mboxes[I915_NUM_RINGS - 1];

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		struct drm_i915_error_object {
			int page_count;
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			u64 gtt_offset;
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			u32 *pages[0];
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		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
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		struct drm_i915_error_request {
			long jiffies;
			u32 seqno;
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			u32 tail;
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		} *requests;
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		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;
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		pid_t pid;
		char comm[TASK_COMM_LEN];
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	} ring[I915_NUM_RINGS];
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	struct drm_i915_error_buffer {
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		u32 size;
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		u32 name;
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		u32 rseqno[I915_NUM_RINGS], wseqno;
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		u64 gtt_offset;
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		u32 read_domains;
		u32 write_domain;
585
		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
586 587 588 589
		s32 pinned:2;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
590
		u32 userptr:1;
591
		s32 ring:4;
592
		u32 cache_level:3;
593
	} **active_bo, **pinned_bo;
594

595
	u32 *active_bo_count, *pinned_bo_count;
596
	u32 vm_count;
597 598
};

599
struct intel_connector;
600
struct intel_encoder;
601
struct intel_crtc_state;
602
struct intel_initial_plane_config;
603
struct intel_crtc;
604 605
struct intel_limit;
struct dpll;
606

607 608 609
struct drm_i915_display_funcs {
	int (*get_display_clock_speed)(struct drm_device *dev);
	int (*get_fifo_size)(struct drm_device *dev, int plane);
610 611 612 613 614 615 616 617 618 619 620 621 622 623
	/**
	 * find_dpll() - Find the best values for the PLL
	 * @limit: limits for the PLL
	 * @crtc: current CRTC
	 * @target: target frequency in kHz
	 * @refclk: reference clock frequency in kHz
	 * @match_clock: if provided, @best_clock P divider must
	 *               match the P divider from @match_clock
	 *               used for LVDS downclocking
	 * @best_clock: best PLL values found
	 *
	 * Returns true on success, false on failure.
	 */
	bool (*find_dpll)(const struct intel_limit *limit,
624
			  struct intel_crtc_state *crtc_state,
625 626 627
			  int target, int refclk,
			  struct dpll *match_clock,
			  struct dpll *best_clock);
628
	void (*update_wm)(struct drm_crtc *crtc);
629 630
	void (*update_sprite_wm)(struct drm_plane *plane,
				 struct drm_crtc *crtc,
631 632
				 uint32_t sprite_width, uint32_t sprite_height,
				 int pixel_size, bool enable, bool scaled);
633 634
	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
	void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
635 636 637
	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
638
				struct intel_crtc_state *);
639 640
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
641 642
	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
643 644
	void (*crtc_enable)(struct drm_crtc *crtc);
	void (*crtc_disable)(struct drm_crtc *crtc);
645 646 647 648
	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
				   struct drm_display_mode *mode);
	void (*audio_codec_disable)(struct intel_encoder *encoder);
649
	void (*fdi_link_train)(struct drm_crtc *crtc);
650
	void (*init_clock_gating)(struct drm_device *dev);
651 652
	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
653
			  struct drm_i915_gem_object *obj,
654
			  struct drm_i915_gem_request *req,
655
			  uint32_t flags);
656 657 658
	void (*update_primary_plane)(struct drm_crtc *crtc,
				     struct drm_framebuffer *fb,
				     int x, int y);
659
	void (*hpd_irq_setup)(struct drm_device *dev);
660 661 662 663 664
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
665

666
	int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
667 668 669 670 671
	uint32_t (*get_backlight)(struct intel_connector *connector);
	void (*set_backlight)(struct intel_connector *connector,
			      uint32_t level);
	void (*disable_backlight)(struct intel_connector *connector);
	void (*enable_backlight)(struct intel_connector *connector);
672 673
};

674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690
enum forcewake_domain_id {
	FW_DOMAIN_ID_RENDER = 0,
	FW_DOMAIN_ID_BLITTER,
	FW_DOMAIN_ID_MEDIA,

	FW_DOMAIN_ID_COUNT
};

enum forcewake_domains {
	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
	FORCEWAKE_MEDIA	= (1 << FW_DOMAIN_ID_MEDIA),
	FORCEWAKE_ALL = (FORCEWAKE_RENDER |
			 FORCEWAKE_BLITTER |
			 FORCEWAKE_MEDIA)
};

691
struct intel_uncore_funcs {
692
	void (*force_wake_get)(struct drm_i915_private *dev_priv,
693
							enum forcewake_domains domains);
694
	void (*force_wake_put)(struct drm_i915_private *dev_priv,
695
							enum forcewake_domains domains);
696 697 698 699 700 701 702 703 704 705 706 707 708 709

	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);

	void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
				uint8_t val, bool trace);
	void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
				uint16_t val, bool trace);
	void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
				uint32_t val, bool trace);
	void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
				uint64_t val, bool trace);
710 711
};

712 713 714 715 716 717
struct intel_uncore {
	spinlock_t lock; /** lock is also taken in irq contexts. */

	struct intel_uncore_funcs funcs;

	unsigned fifo_count;
718
	enum forcewake_domains fw_domains;
719 720 721

	struct intel_uncore_forcewake_domain {
		struct drm_i915_private *i915;
722
		enum forcewake_domain_id id;
723 724
		unsigned wake_count;
		struct timer_list timer;
725 726 727 728 729 730
		u32 reg_set;
		u32 val_set;
		u32 val_clear;
		u32 reg_ack;
		u32 reg_post;
		u32 val_reset;
731 732 733 734 735 736 737 738 739 740 741 742
	} fw_domain[FW_DOMAIN_ID_COUNT];
};

/* Iterate over initialised fw domains */
#define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
	for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
	     (i__) < FW_DOMAIN_ID_COUNT; \
	     (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
		if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))

#define for_each_fw_domain(domain__, dev_priv__, i__) \
	for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
743

744 745 746 747 748 749
enum csr_state {
	FW_UNINITIALIZED = 0,
	FW_LOADED,
	FW_FAILED
};

750 751
struct intel_csr {
	const char *fw_path;
752
	uint32_t *dmc_payload;
753 754 755 756
	uint32_t dmc_fw_size;
	uint32_t mmio_count;
	uint32_t mmioaddr[8];
	uint32_t mmiodata[8];
757
	enum csr_state state;
758 759
};

760 761 762 763 764 765 766 767 768 769 770 771 772 773
#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
	func(is_mobile) sep \
	func(is_i85x) sep \
	func(is_i915g) sep \
	func(is_i945gm) sep \
	func(is_g33) sep \
	func(need_gfx_hws) sep \
	func(is_g4x) sep \
	func(is_pineview) sep \
	func(is_broadwater) sep \
	func(is_crestline) sep \
	func(is_ivybridge) sep \
	func(is_valleyview) sep \
	func(is_haswell) sep \
774
	func(is_skylake) sep \
775
	func(is_preliminary) sep \
776 777 778 779 780 781 782
	func(has_fbc) sep \
	func(has_pipe_cxsr) sep \
	func(has_hotplug) sep \
	func(cursor_needs_physical) sep \
	func(has_overlay) sep \
	func(overlay_needs_physical) sep \
	func(supports_tv) sep \
783
	func(has_llc) sep \
784 785
	func(has_ddi) sep \
	func(has_fpga_dbg)
D
Daniel Vetter 已提交
786

787 788
#define DEFINE_FLAG(name) u8 name:1
#define SEP_SEMICOLON ;
D
Daniel Vetter 已提交
789

790
struct intel_device_info {
791
	u32 display_mmio_offset;
792
	u16 device_id;
793
	u8 num_pipes:3;
794
	u8 num_sprites[I915_MAX_PIPES];
795
	u8 gen;
796
	u8 ring_mask; /* Rings supported by the HW */
797
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
798 799 800 801
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
802
	int cursor_offsets[I915_MAX_PIPES];
803 804 805 806 807 808 809

	/* Slice/subslice/EU info */
	u8 slice_total;
	u8 subslice_total;
	u8 subslice_per_slice;
	u8 eu_total;
	u8 eu_per_subslice;
810 811
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
812 813 814
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
815 816
};

817 818 819
#undef DEFINE_FLAG
#undef SEP_SEMICOLON

820 821
enum i915_cache_level {
	I915_CACHE_NONE = 0,
822 823 824 825 826
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
827
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
828 829
};

830 831 832 833 834 835
struct i915_ctx_hang_stats {
	/* This context had batch pending when hang was declared */
	unsigned batch_pending;

	/* This context had batch active when hang was declared */
	unsigned batch_active;
836 837 838 839

	/* Time when this context was last blamed for a GPU reset */
	unsigned long guilty_ts;

840 841 842 843 844
	/* If the contexts causes a second GPU hang within this time,
	 * it is permanently banned from submitting any more work.
	 */
	unsigned long ban_period_seconds;

845 846
	/* This context is banned to submit more work */
	bool banned;
847
};
848 849

/* This must match up with the value previously used for execbuf2.rsvd1. */
850
#define DEFAULT_CONTEXT_HANDLE 0
851 852

#define CONTEXT_NO_ZEROMAP (1<<0)
853 854 855 856 857
/**
 * struct intel_context - as the name implies, represents a context.
 * @ref: reference count.
 * @user_handle: userspace tracking identity for this context.
 * @remap_slice: l3 row remapping information.
858 859
 * @flags: context specific flags:
 *         CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
860 861 862 863
 * @file_priv: filp associated with this context (NULL for global default
 *	       context).
 * @hang_stats: information about the role of this context in possible GPU
 *		hangs.
864
 * @ppgtt: virtual memory space used by this context.
865 866 867 868 869 870 871
 * @legacy_hw_ctx: render context backing object and whether it is correctly
 *                initialized (legacy ring submission mechanism only).
 * @link: link in the global list of contexts.
 *
 * Contexts are memory images used by the hardware to store copies of their
 * internal state.
 */
872
struct intel_context {
873
	struct kref ref;
874
	int user_handle;
875
	uint8_t remap_slice;
876
	struct drm_i915_private *i915;
877
	int flags;
878
	struct drm_i915_file_private *file_priv;
879
	struct i915_ctx_hang_stats hang_stats;
880
	struct i915_hw_ppgtt *ppgtt;
881

882
	/* Legacy ring buffer submission */
883 884 885 886 887
	struct {
		struct drm_i915_gem_object *rcs_state;
		bool initialized;
	} legacy_hw_ctx;

888
	/* Execlists */
889
	bool rcs_initialized;
890 891
	struct {
		struct drm_i915_gem_object *state;
892
		struct intel_ringbuffer *ringbuf;
893
		int pin_count;
894 895
	} engine[I915_NUM_RINGS];

896
	struct list_head link;
897 898
};

899 900 901 902 903
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
904
	ORIGIN_DIRTYFB,
905 906
};

907
struct i915_fbc {
P
Paulo Zanoni 已提交
908 909 910
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
911
	unsigned long uncompressed_size;
B
Ben Widawsky 已提交
912
	unsigned threshold;
913
	unsigned int fb_id;
914 915
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
916
	struct intel_crtc *crtc;
917 918
	int y;

919
	struct drm_mm_node compressed_fb;
920 921
	struct drm_mm_node *compressed_llb;

922 923
	bool false_color;

924 925 926 927
	/* Tracks whether the HW is actually enabled, not whether the feature is
	 * possible. */
	bool enabled;

928 929
	struct intel_fbc_work {
		struct delayed_work work;
930
		struct intel_crtc *crtc;
931 932 933
		struct drm_framebuffer *fb;
	} *fbc_work;

934 935 936
	enum no_fbc_reason {
		FBC_OK, /* FBC is enabled */
		FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
937 938 939 940 941 942 943 944 945
		FBC_NO_OUTPUT, /* no outputs enabled to compress */
		FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
		FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
		FBC_MODE_TOO_LARGE, /* mode too large for compression */
		FBC_BAD_PLANE, /* fbc not supported on plane */
		FBC_NOT_TILED, /* buffer not tiled */
		FBC_MULTIPLE_PIPES, /* more than one pipe active */
		FBC_MODULE_PARAM,
		FBC_CHIP_DEFAULT, /* disabled by default on this chip */
946
		FBC_ROTATION, /* rotation is not supported */
947
		FBC_IN_DBG_MASTER, /* kernel debugger is active */
948
	} no_fbc_reason;
949

950
	bool (*fbc_enabled)(struct drm_i915_private *dev_priv);
951
	void (*enable_fbc)(struct intel_crtc *crtc);
952
	void (*disable_fbc)(struct drm_i915_private *dev_priv);
953 954
};

955 956 957 958 959 960 961 962 963 964 965 966 967 968 969
/**
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
970 971
};

972
struct intel_dp;
973 974 975 976 977 978 979 980 981
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
982
struct i915_psr {
983
	struct mutex lock;
R
Rodrigo Vivi 已提交
984 985
	bool sink_support;
	bool source_ok;
986
	struct intel_dp *enabled;
987 988
	bool active;
	struct delayed_work work;
989
	unsigned busy_frontbuffer_bits;
990 991
	bool psr2_support;
	bool aux_frame_sync;
992
};
993

994
enum intel_pch {
995
	PCH_NONE = 0,	/* No PCH present */
996 997
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
998
	PCH_LPT,	/* Lynxpoint PCH */
999
	PCH_SPT,        /* Sunrisepoint PCH */
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Ben Widawsky 已提交
1000
	PCH_NOP,
1001 1002
};

1003 1004 1005 1006 1007
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

1008
#define QUIRK_PIPEA_FORCE (1<<0)
1009
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1010
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1011
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1012
#define QUIRK_PIPEB_FORCE (1<<4)
1013
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1014

1015
struct intel_fbdev;
1016
struct intel_fbc_work;
1017

1018 1019
struct intel_gmbus {
	struct i2c_adapter adapter;
1020
	u32 force_bit;
1021
	u32 reg0;
1022
	u32 gpio_reg;
1023
	struct i2c_algo_bit_data bit_algo;
1024 1025 1026
	struct drm_i915_private *dev_priv;
};

1027
struct i915_suspend_saved_registers {
1028
	u32 saveDSPARB;
J
Jesse Barnes 已提交
1029
	u32 saveLVDS;
1030 1031
	u32 savePP_ON_DELAYS;
	u32 savePP_OFF_DELAYS;
J
Jesse Barnes 已提交
1032 1033 1034
	u32 savePP_ON;
	u32 savePP_OFF;
	u32 savePP_CONTROL;
1035
	u32 savePP_DIVISOR;
J
Jesse Barnes 已提交
1036
	u32 saveFBC_CONTROL;
1037 1038
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
J
Jesse Barnes 已提交
1039 1040 1041
	u32 saveSWF0[16];
	u32 saveSWF1[16];
	u32 saveSWF2[3];
1042
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1043
	u32 savePCH_PORT_HOTPLUG;
1044
	u16 saveGCDGMBUS;
1045
};
1046

1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
1105
	u32 pcbr;
1106 1107 1108
	u32 clock_gate_dis2;
};

1109 1110 1111 1112
struct intel_rps_ei {
	u32 cz_clock;
	u32 render_c0;
	u32 media_c0;
1113 1114
};

1115
struct intel_gen6_power_mgmt {
I
Imre Deak 已提交
1116 1117 1118 1119
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1120
	struct work_struct work;
I
Imre Deak 已提交
1121
	bool interrupts_enabled;
1122
	u32 pm_iir;
1123

1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
1139
	u8 idle_freq;		/* Frequency to request when we are idle */
1140 1141 1142
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1143
	u32 cz_freq;
1144

1145 1146 1147
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

1148 1149 1150
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1151 1152 1153 1154
	spinlock_t client_lock;
	struct list_head clients;
	bool client_boost;

1155
	bool enabled;
1156
	struct delayed_work delayed_resume_work;
1157
	unsigned boosts;
1158

1159
	struct intel_rps_client semaphores, mmioflips;
1160

1161 1162 1163
	/* manual wa residency calculations */
	struct intel_rps_ei up_ei, down_ei;

1164 1165
	/*
	 * Protects RPS/RC6 register access and PCU communication.
1166 1167 1168
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
1169 1170
	 */
	struct mutex hw_lock;
1171 1172
};

D
Daniel Vetter 已提交
1173 1174 1175
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1187
	u64 last_time2;
1188 1189 1190 1191 1192 1193 1194
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1225 1226
/* Power well structure for haswell */
struct i915_power_well {
1227
	const char *name;
1228
	bool always_on;
1229 1230
	/* power well enable/disable usage count */
	int count;
1231 1232
	/* cached hw enabled state */
	bool hw_enabled;
1233
	unsigned long domains;
1234
	unsigned long data;
1235
	const struct i915_power_well_ops *ops;
1236 1237
};

1238
struct i915_power_domains {
1239 1240 1241 1242 1243
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1244
	bool initializing;
1245
	int power_well_count;
1246

1247
	struct mutex lock;
1248
	int domain_use_count[POWER_DOMAIN_NUM];
1249
	struct i915_power_well *power_wells;
1250 1251
};

1252
#define MAX_L3_SLICES 2
1253
struct intel_l3_parity {
1254
	u32 *remap_info[MAX_L3_SLICES];
1255
	struct work_struct error_work;
1256
	int which_slice;
1257 1258
};

1259 1260 1261
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1262 1263 1264 1265
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
	 * are idle and not used by the GPU) but still have
	 * (presumably uncached) pages still attached.
	 */
	struct list_head unbound_list;

	/** Usable portion of the GTT for GEM */
	unsigned long stolen_base; /* limited to low memory (32-bit) */

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1282
	struct notifier_block oom_notifier;
1283
	struct shrinker shrinker;
1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297
	bool shrinker_no_lock_stealing;

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

	/**
	 * We leave the user IRQ off as much as possible,
	 * but this means that requests will finish and never
	 * be retired once the system goes idle. Set a timer to
	 * fire periodically while the ring is running. When it
	 * fires, go retire requests.
	 */
	struct delayed_work retire_work;

1298 1299 1300 1301 1302 1303 1304 1305 1306
	/**
	 * When we detect an idle GPU, we want to turn on
	 * powersaving features. So once we see that there
	 * are no more requests outstanding and no more
	 * arrive within a small period of time, we fire
	 * off the idle_work.
	 */
	struct delayed_work idle_work;

1307 1308 1309 1310 1311 1312
	/**
	 * Are we in a non-interruptible section of code like
	 * modesetting?
	 */
	bool interruptible;

1313 1314 1315 1316 1317 1318 1319 1320
	/**
	 * Is the GPU currently considered idle, or busy executing userspace
	 * requests?  Whilst idle, we attempt to power down the hardware and
	 * display clocks. In order to reduce the effect on performance, there
	 * is a slight delay before we do so.
	 */
	bool busy;

1321 1322 1323
	/* the indicator for dispatch video commands on two BSD rings */
	int bsd_ring_dispatch_index;

1324 1325 1326 1327 1328 1329
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1330
	spinlock_t object_stat_lock;
1331 1332 1333 1334
	size_t object_memory;
	u32 object_count;
};

1335
struct drm_i915_error_state_buf {
1336
	struct drm_i915_private *i915;
1337 1338 1339 1340 1341 1342 1343 1344
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1345 1346 1347 1348 1349
struct i915_error_state_file_priv {
	struct drm_device *dev;
	struct drm_i915_error_state *error;
};

1350 1351 1352 1353
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1354 1355 1356
	/* Hang gpu twice in this window and your context gets banned */
#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)

1357 1358
	struct workqueue_struct *hangcheck_wq;
	struct delayed_work hangcheck_work;
1359 1360 1361 1362 1363

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
	struct drm_i915_error_state *first_error;
1364 1365 1366

	unsigned long missed_irq_rings;

1367
	/**
M
Mika Kuoppala 已提交
1368
	 * State variable controlling the reset flow and count
1369
	 *
M
Mika Kuoppala 已提交
1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382
	 * This is a counter which gets incremented when reset is triggered,
	 * and again when reset has been handled. So odd values (lowest bit set)
	 * means that reset is in progress and even values that
	 * (reset_counter >> 1):th reset was successfully completed.
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1383 1384 1385 1386
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1387 1388 1389 1390
	 */
	atomic_t reset_counter;

#define I915_RESET_IN_PROGRESS_FLAG	1
M
Mika Kuoppala 已提交
1391
#define I915_WEDGED			(1 << 31)
1392 1393 1394 1395 1396 1397

	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1398

1399 1400 1401 1402 1403 1404
	/* Userspace knobs for gpu hang simulation;
	 * combines both a ring mask, and extra flags
	 */
	u32 stop_rings;
#define I915_STOP_RING_ALLOW_BAN       (1 << 31)
#define I915_STOP_RING_ALLOW_WARN      (1 << 30)
1405 1406 1407

	/* For missed irq/seqno simulation. */
	unsigned int test_irq_rings;
1408 1409 1410

	/* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset   */
	bool reload_in_reset;
1411 1412
};

1413 1414 1415 1416 1417 1418
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1419 1420 1421 1422 1423
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

1424
struct ddi_vbt_port_info {
1425 1426 1427 1428 1429 1430
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1431
	uint8_t hdmi_level_shift;
1432 1433 1434 1435

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1436 1437

	uint8_t alternate_aux_channel;
1438 1439 1440

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1441 1442
};

R
Rodrigo Vivi 已提交
1443 1444 1445 1446 1447
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1448 1449
};

1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1462
	unsigned int has_mipi:1;
1463 1464 1465
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1466 1467
	enum drrs_support_type drrs_type;

1468 1469 1470 1471 1472 1473 1474 1475 1476 1477
	/* eDP */
	int edp_rate;
	int edp_lanes;
	int edp_preemphasis;
	int edp_vswing;
	bool edp_initialized;
	bool edp_support;
	int edp_bpp;
	struct edp_power_seq edp_pps;

R
Rodrigo Vivi 已提交
1478 1479 1480 1481 1482 1483 1484 1485 1486
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1487 1488
	struct {
		u16 pwm_freq_hz;
1489
		bool present;
1490
		bool active_low_pwm;
1491
		u8 min_brightness;	/* min_brightness/255 of max */
1492 1493
	} backlight;

1494 1495
	/* MIPI DSI */
	struct {
1496
		u16 port;
1497
		u16 panel_id;
1498 1499 1500 1501 1502 1503
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
		u8 *sequence[MIPI_SEQ_MAX];
1504 1505
	} dsi;

1506 1507 1508
	int crt_ddc_pin;

	int child_dev_num;
1509
	union child_device_config *child_dev;
1510 1511

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1512 1513
};

1514 1515 1516 1517 1518
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1519 1520 1521 1522 1523 1524 1525 1526
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1527
struct ilk_wm_values {
1528 1529 1530 1531 1532 1533 1534 1535
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1536 1537 1538 1539 1540
struct vlv_pipe_wm {
	uint16_t primary;
	uint16_t sprite[2];
	uint8_t cursor;
};
1541

1542 1543 1544 1545
struct vlv_sr_wm {
	uint16_t plane;
	uint8_t cursor;
};
1546

1547 1548 1549
struct vlv_wm_values {
	struct vlv_pipe_wm pipe[3];
	struct vlv_sr_wm sr;
1550 1551 1552 1553 1554
	struct {
		uint8_t cursor;
		uint8_t sprite[2];
		uint8_t primary;
	} ddl[3];
1555 1556
	uint8_t level;
	bool cxsr;
1557 1558
};

1559
struct skl_ddb_entry {
1560
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1561 1562 1563 1564
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1565
	return entry->end - entry->start;
1566 1567
}

1568 1569 1570 1571 1572 1573 1574 1575 1576
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1577
struct skl_ddb_allocation {
1578
	struct skl_ddb_entry pipe[I915_MAX_PIPES];
1579 1580
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* y-plane */
1581 1582 1583
	struct skl_ddb_entry cursor[I915_MAX_PIPES];
};

1584 1585
struct skl_wm_values {
	bool dirty[I915_MAX_PIPES];
1586
	struct skl_ddb_allocation ddb;
1587 1588 1589 1590 1591 1592 1593 1594 1595
	uint32_t wm_linetime[I915_MAX_PIPES];
	uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
	uint32_t cursor[I915_MAX_PIPES][8];
	uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
	uint32_t cursor_trans[I915_MAX_PIPES];
};

struct skl_wm_level {
	bool plane_en[I915_MAX_PLANES];
1596
	bool cursor_en;
1597 1598 1599 1600 1601 1602
	uint16_t plane_res_b[I915_MAX_PLANES];
	uint8_t plane_res_l[I915_MAX_PLANES];
	uint16_t cursor_res_b;
	uint8_t cursor_res_l;
};

1603
/*
1604 1605 1606 1607
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1608
 *
1609 1610 1611
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1612
 *
1613 1614
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1615
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1616
 * it can be changed with the standard runtime PM files from sysfs.
1617 1618 1619 1620 1621
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1622
 * case it happens.
1623
 *
1624
 * For more, read the Documentation/power/runtime_pm.txt.
1625
 */
1626 1627
struct i915_runtime_pm {
	bool suspended;
1628
	bool irqs_enabled;
1629 1630
};

1631 1632 1633 1634 1635
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1636
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1637 1638 1639 1640 1641
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1642
	INTEL_PIPE_CRC_SOURCE_AUTO,
1643 1644 1645
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1646
struct intel_pipe_crc_entry {
1647
	uint32_t frame;
1648 1649 1650
	uint32_t crc[5];
};

1651
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1652
struct intel_pipe_crc {
1653 1654
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1655
	struct intel_pipe_crc_entry *entries;
1656
	enum intel_pipe_crc_source source;
1657
	int head, tail;
1658
	wait_queue_head_t wq;
1659 1660
};

1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671
struct i915_frontbuffer_tracking {
	struct mutex lock;

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685
struct i915_wa_reg {
	u32 addr;
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

#define I915_MAX_WA_REGS 16

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
};

1686 1687 1688 1689
struct i915_virtual_gpu {
	bool active;
};

1690 1691 1692 1693 1694
struct i915_execbuffer_params {
	struct drm_device               *dev;
	struct drm_file                 *file;
	uint32_t                        dispatch_flags;
	uint32_t                        args_batch_start_offset;
1695
	uint64_t                        batch_obj_vm_offset;
1696 1697 1698
	struct intel_engine_cs          *ring;
	struct drm_i915_gem_object      *batch_obj;
	struct intel_context            *ctx;
1699
	struct drm_i915_gem_request     *request;
1700 1701
};

1702
struct drm_i915_private {
1703
	struct drm_device *dev;
1704
	struct kmem_cache *objects;
1705
	struct kmem_cache *vmas;
1706
	struct kmem_cache *requests;
1707

1708
	const struct intel_device_info info;
1709 1710 1711 1712 1713

	int relative_constants_mode;

	void __iomem *regs;

1714
	struct intel_uncore uncore;
1715

1716 1717
	struct i915_virtual_gpu vgpu;

1718 1719
	struct intel_guc guc;

1720 1721 1722 1723 1724
	struct intel_csr csr;

	/* Display CSR-related protection */
	struct mutex csr_lock;

1725
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1726

1727 1728 1729 1730 1731 1732 1733 1734 1735
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

1736 1737 1738
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

1739 1740
	wait_queue_head_t gmbus_wait_queue;

1741
	struct pci_dev *bridge_dev;
1742
	struct intel_engine_cs ring[I915_NUM_RINGS];
1743
	struct drm_i915_gem_object *semaphore_obj;
1744
	uint32_t last_seqno, next_seqno;
1745

1746
	struct drm_dma_handle *status_page_dmah;
1747 1748 1749 1750 1751
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

1752 1753 1754
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

1755 1756
	bool display_irqs_enabled;

1757 1758 1759
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
1760 1761
	/* Sideband mailbox protection */
	struct mutex sb_lock;
1762 1763

	/** Cached value of IMR to avoid reads in updating the bitfield */
1764 1765 1766 1767
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
1768
	u32 gt_irq_mask;
1769
	u32 pm_irq_mask;
1770
	u32 pm_rps_events;
1771
	u32 pipestat_irq_mask[I915_MAX_PIPES];
1772

1773
	struct i915_hotplug hotplug;
1774
	struct i915_fbc fbc;
1775
	struct i915_drrs drrs;
1776
	struct intel_opregion opregion;
1777
	struct intel_vbt_data vbt;
1778

1779 1780
	bool preserve_bios_swizzle;

1781 1782 1783
	/* overlay */
	struct intel_overlay *overlay;

1784
	/* backlight registers and fields in struct intel_panel */
1785
	struct mutex backlight_lock;
1786

1787 1788 1789
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
1790 1791 1792
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

1793 1794 1795 1796 1797
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
1798
	unsigned int skl_boot_cdclk;
1799
	unsigned int cdclk_freq, max_cdclk_freq;
M
Mika Kahola 已提交
1800
	unsigned int max_dotclk_freq;
1801
	unsigned int hpll_freq;
1802

1803 1804 1805 1806 1807 1808 1809
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
1810 1811 1812 1813 1814 1815 1816
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
1817
	unsigned short pch_id;
1818 1819 1820

	unsigned long quirks;

1821 1822
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
1823

1824
	struct list_head vm_list; /* Global list of all address spaces */
1825
	struct i915_gtt gtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
1826

1827
	struct i915_gem_mm mm;
1828 1829
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
1830 1831 1832

	/* Kernel Modesetting */

1833
	struct sdvo_device_mapping sdvo_mappings[2];
1834

1835 1836
	struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1837 1838
	wait_queue_head_t pending_flip_queue;

1839 1840 1841 1842
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

D
Daniel Vetter 已提交
1843 1844
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1845
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1846

1847
	struct i915_workarounds workarounds;
1848

1849 1850
	/* Reclocking support */
	bool render_reclock_avail;
1851 1852 1853

	struct i915_frontbuffer_tracking fb_tracking;

1854
	u16 orig_clock;
1855

1856
	bool mchbar_need_disable;
1857

1858 1859
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
1860 1861 1862
	/* Cannot be determined by PCIID. You must always read a register. */
	size_t ellc_size;

1863
	/* gen6+ rps state */
1864
	struct intel_gen6_power_mgmt rps;
1865

1866 1867
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
1868
	struct intel_ilk_power_mgmt ips;
1869

1870
	struct i915_power_domains power_domains;
1871

R
Rodrigo Vivi 已提交
1872
	struct i915_psr psr;
1873

1874
	struct i915_gpu_error gpu_error;
1875

1876 1877
	struct drm_i915_gem_object *vlv_pctx;

1878
#ifdef CONFIG_DRM_I915_FBDEV
1879 1880
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
1881
	struct work_struct fbdev_suspend_work;
1882
#endif
1883 1884

	struct drm_property *broadcast_rgb_property;
1885
	struct drm_property *force_audio_property;
1886

I
Imre Deak 已提交
1887 1888 1889
	/* hda/i915 audio component */
	bool audio_component_registered;

1890
	uint32_t hw_context_size;
1891
	struct list_head context_list;
1892

1893
	u32 fdi_rx_config;
1894

1895 1896
	u32 chv_phy_control;

1897
	u32 suspend_count;
1898
	struct i915_suspend_saved_registers regfile;
1899
	struct vlv_s0ix_state vlv_s0ix_state;
1900

1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
1913 1914 1915 1916 1917 1918
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
1919

1920 1921 1922 1923 1924 1925 1926
		/*
		 * The skl_wm_values structure is a bit too big for stack
		 * allocation, so we keep the staging struct where we store
		 * intermediate results here instead.
		 */
		struct skl_wm_values skl_results;

1927
		/* current hardware state */
1928 1929 1930
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
1931
			struct vlv_wm_values vlv;
1932
		};
1933 1934
	} wm;

1935 1936
	struct i915_runtime_pm pm;

1937 1938
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
1939
		int (*execbuf_submit)(struct i915_execbuffer_params *params,
1940
				      struct drm_i915_gem_execbuffer2 *args,
1941
				      struct list_head *vmas);
1942 1943 1944 1945 1946
		int (*init_rings)(struct drm_device *dev);
		void (*cleanup_ring)(struct intel_engine_cs *ring);
		void (*stop_ring)(struct intel_engine_cs *ring);
	} gt;

1947 1948
	bool edp_low_vswing;

1949 1950 1951 1952
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
1953
};
L
Linus Torvalds 已提交
1954

1955 1956 1957 1958 1959
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
	return dev->dev_private;
}

I
Imre Deak 已提交
1960 1961 1962 1963 1964
static inline struct drm_i915_private *dev_to_i915(struct device *dev)
{
	return to_i915(dev_get_drvdata(dev));
}

1965 1966 1967 1968 1969
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

1970 1971 1972 1973 1974
/* Iterate over initialised rings */
#define for_each_ring(ring__, dev_priv__, i__) \
	for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
		if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))

1975 1976 1977 1978 1979 1980 1981
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

1982
#define I915_GTT_OFFSET_NONE ((u32)-1)
1983

1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999
struct drm_i915_gem_object_ops {
	/* Interface between the GEM object and its backing storage.
	 * get_pages() is called once prior to the use of the associated set
	 * of pages before to binding them into the GTT, and put_pages() is
	 * called after we no longer need them. As we expect there to be
	 * associated cost with migrating pages between the backing storage
	 * and making them available for the GPU (e.g. clflush), we may hold
	 * onto the pages after they are no longer referenced by the GPU
	 * in case they may be used again shortly (for example migrating the
	 * pages to a different memory domain within the GTT). put_pages()
	 * will therefore most likely be called when the object itself is
	 * being released or under memory pressure (where we attempt to
	 * reap pages for the shrinker).
	 */
	int (*get_pages)(struct drm_i915_gem_object *);
	void (*put_pages)(struct drm_i915_gem_object *);
2000 2001
	int (*dmabuf_export)(struct drm_i915_gem_object *);
	void (*release)(struct drm_i915_gem_object *);
2002 2003
};

2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
 * considered to be the frontbuffer for the given plane interface-vise. This
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
#define INTEL_FRONTBUFFER_BITS \
	(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
	(1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe) \
	(1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
	(1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2023 2024
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
	(0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2025

2026
struct drm_i915_gem_object {
2027
	struct drm_gem_object base;
2028

2029 2030
	const struct drm_i915_gem_object_ops *ops;

B
Ben Widawsky 已提交
2031 2032 2033
	/** List of VMAs backed by this object */
	struct list_head vma_list;

2034 2035
	/** Stolen memory for this object, instead of being backed by shmem. */
	struct drm_mm_node *stolen;
2036
	struct list_head global_list;
2037

2038
	struct list_head ring_list[I915_NUM_RINGS];
2039 2040
	/** Used in execbuf to temporarily hold a ref */
	struct list_head obj_exec_link;
2041

2042
	struct list_head batch_pool_link;
2043

2044
	/**
2045 2046 2047
	 * This is set if the object is on the active lists (has pending
	 * rendering and so a non-zero seqno), and is not set if it i s on
	 * inactive (ready to be unbound) list.
2048
	 */
2049
	unsigned int active:I915_NUM_RINGS;
2050 2051 2052 2053 2054

	/**
	 * This is set if the object has been written to since last bound
	 * to the GTT
	 */
2055
	unsigned int dirty:1;
2056 2057 2058 2059 2060 2061

	/**
	 * Fence register bits (if any) for this object.  Will be set
	 * as needed when mapped into the GTT.
	 * Protected by dev->struct_mutex.
	 */
2062
	signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2063 2064 2065 2066

	/**
	 * Advice: are the backing pages purgeable?
	 */
2067
	unsigned int madv:2;
2068 2069 2070 2071

	/**
	 * Current tiling mode for the object.
	 */
2072
	unsigned int tiling_mode:2;
2073 2074 2075 2076 2077 2078 2079 2080
	/**
	 * Whether the tiling parameters for the currently associated fence
	 * register have changed. Note that for the purposes of tracking
	 * tiling changes we also treat the unfenced register, the register
	 * slot that the object occupies whilst it executes a fenced
	 * command (such as BLT on gen2/3), as a "fence".
	 */
	unsigned int fence_dirty:1;
2081

2082 2083 2084 2085
	/**
	 * Is the object at the current location in the gtt mappable and
	 * fenceable? Used to avoid costly recalculations.
	 */
2086
	unsigned int map_and_fenceable:1;
2087

2088 2089 2090 2091 2092
	/**
	 * Whether the current gtt mapping needs to be mappable (and isn't just
	 * mappable by accident). Track pin and fault separate for a more
	 * accurate mappable working set.
	 */
2093
	unsigned int fault_mappable:1;
2094

2095 2096 2097 2098 2099
	/*
	 * Is the object to be mapped as read-only to the GPU
	 * Only honoured if hardware has relevant pte bit
	 */
	unsigned long gt_ro:1;
2100
	unsigned int cache_level:3;
2101
	unsigned int cache_dirty:1;
2102

2103 2104
	unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;

2105 2106
	unsigned int pin_display;

2107
	struct sg_table *pages;
2108
	int pages_pin_count;
2109 2110 2111 2112
	struct get_page {
		struct scatterlist *sg;
		int last;
	} get_page;
2113

2114
	/* prime dma-buf support */
2115 2116 2117
	void *dma_buf_vmapping;
	int vmapping_count;

2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128
	/** Breadcrumb of last rendering to the buffer.
	 * There can only be one writer, but we allow for multiple readers.
	 * If there is a writer that necessarily implies that all other
	 * read requests are complete - but we may only be lazily clearing
	 * the read requests. A read request is naturally the most recent
	 * request on a ring, so we may have two different write and read
	 * requests on one ring where the write request is older than the
	 * read request. This allows for the CPU to read from an active
	 * buffer by only waiting for the write to complete.
	 * */
	struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2129
	struct drm_i915_gem_request *last_write_req;
2130
	/** Breadcrumb of last fenced GPU access to the buffer. */
2131
	struct drm_i915_gem_request *last_fenced_req;
2132

2133
	/** Current tiling stride for the object, if it's tiled. */
2134
	uint32_t stride;
2135

2136 2137 2138
	/** References from framebuffers, locks out tiling changes. */
	unsigned long framebuffer_references;

2139
	/** Record of address bit 17 of each page at last unbind. */
2140
	unsigned long *bit_17;
2141

2142
	union {
2143 2144 2145
		/** for phy allocated objects */
		struct drm_dma_handle *phys_handle;

2146 2147 2148 2149 2150 2151
		struct i915_gem_userptr {
			uintptr_t ptr;
			unsigned read_only :1;
			unsigned workers :4;
#define I915_GEM_USERPTR_MAX_WORKERS 15

2152 2153
			struct i915_mm_struct *mm;
			struct i915_mmu_object *mmu_object;
2154 2155 2156 2157
			struct work_struct *work;
		} userptr;
	};
};
2158
#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2159

2160 2161 2162 2163
void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

2164 2165 2166 2167 2168 2169
/**
 * Request queue structure.
 *
 * The request queue allows us to note sequence numbers that have been emitted
 * and may be associated with active buffers to be retired.
 *
2170 2171 2172 2173
 * By keeping this list, we can avoid having to do questionable sequence
 * number comparisons on buffer last_read|write_seqno. It also allows an
 * emission time to be associated with the request for tracking how far ahead
 * of the GPU the submission is.
2174 2175 2176
 *
 * The requests are reference counted, so upon creation they should have an
 * initial reference taken using kref_init
2177 2178
 */
struct drm_i915_gem_request {
2179 2180
	struct kref ref;

2181
	/** On Which ring this request was generated */
2182
	struct drm_i915_private *i915;
2183
	struct intel_engine_cs *ring;
2184

2185 2186 2187
	/** GEM sequence number associated with this request. */
	uint32_t seqno;

2188 2189 2190
	/** Position in the ringbuffer of the start of the request */
	u32 head;

2191 2192 2193 2194 2195 2196 2197 2198
	/**
	 * Position in the ringbuffer of the start of the postfix.
	 * This is required to calculate the maximum available ringbuffer
	 * space without overwriting the postfix.
	 */
	 u32 postfix;

	/** Position in the ringbuffer of the end of the whole request */
2199 2200
	u32 tail;

2201
	/**
D
Dave Airlie 已提交
2202
	 * Context and ring buffer related to this request
2203 2204 2205 2206 2207 2208 2209 2210
	 * Contexts are refcounted, so when this request is associated with a
	 * context, we must increment the context's refcount, to guarantee that
	 * it persists while any request is linked to it. Requests themselves
	 * are also refcounted, so the request will only be freed when the last
	 * reference to it is dismissed, and the code in
	 * i915_gem_request_free() will then decrement the refcount on the
	 * context.
	 */
2211
	struct intel_context *ctx;
2212
	struct intel_ringbuffer *ringbuf;
2213

2214 2215
	/** Batch buffer related to this request if any (used for
	    error state dump only) */
2216 2217
	struct drm_i915_gem_object *batch_obj;

2218 2219 2220
	/** Time at which this request was emitted, in jiffies. */
	unsigned long emitted_jiffies;

2221
	/** global list entry for this request */
2222
	struct list_head list;
2223

2224
	struct drm_i915_file_private *file_priv;
2225 2226
	/** file_priv list entry for this request */
	struct list_head client_list;
2227

2228 2229 2230
	/** process identifier submitting this request */
	struct pid *pid;

2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249
	/**
	 * The ELSP only accepts two elements at a time, so we queue
	 * context/tail pairs on a given queue (ring->execlist_queue) until the
	 * hardware is available. The queue serves a double purpose: we also use
	 * it to keep track of the up to 2 contexts currently in the hardware
	 * (usually one in execution and the other queued up by the GPU): We
	 * only remove elements from the head of the queue when the hardware
	 * informs us that an element has been completed.
	 *
	 * All accesses to the queue are mediated by a spinlock
	 * (ring->execlist_lock).
	 */

	/** Execlist link in the submission queue.*/
	struct list_head execlist_link;

	/** Execlists no. of times this request has been sent to the ELSP */
	int elsp_submitted;

2250 2251
};

2252
int i915_gem_request_alloc(struct intel_engine_cs *ring,
2253 2254
			   struct intel_context *ctx,
			   struct drm_i915_gem_request **req_out);
2255
void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2256
void i915_gem_request_free(struct kref *req_ref);
2257 2258
int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
				   struct drm_file *file);
2259

2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271
static inline uint32_t
i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
{
	return req ? req->seqno : 0;
}

static inline struct intel_engine_cs *
i915_gem_request_get_ring(struct drm_i915_gem_request *req)
{
	return req ? req->ring : NULL;
}

2272
static inline struct drm_i915_gem_request *
2273 2274
i915_gem_request_reference(struct drm_i915_gem_request *req)
{
2275 2276 2277
	if (req)
		kref_get(&req->ref);
	return req;
2278 2279 2280 2281 2282
}

static inline void
i915_gem_request_unreference(struct drm_i915_gem_request *req)
{
2283
	WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2284 2285 2286
	kref_put(&req->ref, i915_gem_request_free);
}

2287 2288 2289
static inline void
i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
{
2290 2291 2292 2293
	struct drm_device *dev;

	if (!req)
		return;
2294

2295 2296
	dev = req->ring->dev;
	if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2297 2298 2299
		mutex_unlock(&dev->struct_mutex);
}

2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311
static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
					   struct drm_i915_gem_request *src)
{
	if (src)
		i915_gem_request_reference(src);

	if (*pdst)
		i915_gem_request_unreference(*pdst);

	*pdst = src;
}

2312 2313 2314 2315 2316 2317
/*
 * XXX: i915_gem_request_completed should be here but currently needs the
 * definition of i915_seqno_passed() which is below. It will be moved in
 * a later patch when the call to i915_seqno_passed() is obsoleted...
 */

2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369
/*
 * A command that requires special handling by the command parser.
 */
struct drm_i915_cmd_descriptor {
	/*
	 * Flags describing how the command parser processes the command.
	 *
	 * CMD_DESC_FIXED: The command has a fixed length if this is set,
	 *                 a length mask if not set
	 * CMD_DESC_SKIP: The command is allowed but does not follow the
	 *                standard length encoding for the opcode range in
	 *                which it falls
	 * CMD_DESC_REJECT: The command is never allowed
	 * CMD_DESC_REGISTER: The command should be checked against the
	 *                    register whitelist for the appropriate ring
	 * CMD_DESC_MASTER: The command is allowed if the submitting process
	 *                  is the DRM master
	 */
	u32 flags;
#define CMD_DESC_FIXED    (1<<0)
#define CMD_DESC_SKIP     (1<<1)
#define CMD_DESC_REJECT   (1<<2)
#define CMD_DESC_REGISTER (1<<3)
#define CMD_DESC_BITMASK  (1<<4)
#define CMD_DESC_MASTER   (1<<5)

	/*
	 * The command's unique identification bits and the bitmask to get them.
	 * This isn't strictly the opcode field as defined in the spec and may
	 * also include type, subtype, and/or subop fields.
	 */
	struct {
		u32 value;
		u32 mask;
	} cmd;

	/*
	 * The command's length. The command is either fixed length (i.e. does
	 * not include a length field) or has a length field mask. The flag
	 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
	 * a length mask. All command entries in a command table must include
	 * length information.
	 */
	union {
		u32 fixed;
		u32 mask;
	} length;

	/*
	 * Describes where to find a register address in the command to check
	 * against the ring's register whitelist. Only valid if flags has the
	 * CMD_DESC_REGISTER bit set.
2370 2371 2372 2373
	 *
	 * A non-zero step value implies that the command may access multiple
	 * registers in sequence (e.g. LRI), in that case step gives the
	 * distance in dwords between individual offset fields.
2374 2375 2376 2377
	 */
	struct {
		u32 offset;
		u32 mask;
2378
		u32 step;
2379 2380 2381 2382 2383 2384 2385 2386 2387
	} reg;

#define MAX_CMD_DESC_BITMASKS 3
	/*
	 * Describes command checks where a particular dword is masked and
	 * compared against an expected value. If the command does not match
	 * the expected value, the parser rejects it. Only valid if flags has
	 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
	 * are valid.
2388 2389 2390 2391
	 *
	 * If the check specifies a non-zero condition_mask then the parser
	 * only performs the check when the bits specified by condition_mask
	 * are non-zero.
2392 2393 2394 2395 2396
	 */
	struct {
		u32 offset;
		u32 mask;
		u32 expected;
2397 2398
		u32 condition_offset;
		u32 condition_mask;
2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412
	} bits[MAX_CMD_DESC_BITMASKS];
};

/*
 * A table of commands requiring special handling by the command parser.
 *
 * Each ring has an array of tables. Each table consists of an array of command
 * descriptors, which must be sorted with command opcodes in ascending order.
 */
struct drm_i915_cmd_table {
	const struct drm_i915_cmd_descriptor *table;
	int count;
};

C
Chris Wilson 已提交
2413
/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2414 2415 2416 2417 2418 2419 2420 2421 2422 2423
#define __I915__(p) ({ \
	struct drm_i915_private *__p; \
	if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
		__p = (struct drm_i915_private *)p; \
	else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
		__p = to_i915((struct drm_device *)p); \
	else \
		BUILD_BUG(); \
	__p; \
})
C
Chris Wilson 已提交
2424
#define INTEL_INFO(p) 	(&__I915__(p)->info)
2425
#define INTEL_DEVID(p)	(INTEL_INFO(p)->device_id)
2426
#define INTEL_REVID(p)	(__I915__(p)->dev->pdev->revision)
2427

2428 2429
#define IS_I830(dev)		(INTEL_DEVID(dev) == 0x3577)
#define IS_845G(dev)		(INTEL_DEVID(dev) == 0x2562)
2430
#define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
2431
#define IS_I865G(dev)		(INTEL_DEVID(dev) == 0x2572)
2432
#define IS_I915G(dev)		(INTEL_INFO(dev)->is_i915g)
2433 2434
#define IS_I915GM(dev)		(INTEL_DEVID(dev) == 0x2592)
#define IS_I945G(dev)		(INTEL_DEVID(dev) == 0x2772)
2435 2436 2437
#define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)
#define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)
#define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)
2438
#define IS_GM45(dev)		(INTEL_DEVID(dev) == 0x2A42)
2439
#define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)
2440 2441
#define IS_PINEVIEW_G(dev)	(INTEL_DEVID(dev) == 0xa001)
#define IS_PINEVIEW_M(dev)	(INTEL_DEVID(dev) == 0xa011)
2442 2443
#define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
#define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
2444
#define IS_IRONLAKE_M(dev)	(INTEL_DEVID(dev) == 0x0046)
2445
#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
2446 2447 2448
#define IS_IVB_GT1(dev)		(INTEL_DEVID(dev) == 0x0156 || \
				 INTEL_DEVID(dev) == 0x0152 || \
				 INTEL_DEVID(dev) == 0x015a)
2449
#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
2450
#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2451
#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
2452
#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2453
#define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
2454
#define IS_BROXTON(dev)	(!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2455
#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
2456
#define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
2457
				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
B
Ben Widawsky 已提交
2458
#define IS_BDW_ULT(dev)		(IS_BROADWELL(dev) && \
2459
				 ((INTEL_DEVID(dev) & 0xf) == 0x6 ||	\
2460
				 (INTEL_DEVID(dev) & 0xf) == 0xb ||	\
2461
				 (INTEL_DEVID(dev) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2462 2463 2464
/* ULX machines are also considered ULT. */
#define IS_BDW_ULX(dev)		(IS_BROADWELL(dev) && \
				 (INTEL_DEVID(dev) & 0xf) == 0xe)
R
Rodrigo Vivi 已提交
2465 2466
#define IS_BDW_GT3(dev)		(IS_BROADWELL(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
B
Ben Widawsky 已提交
2467
#define IS_HSW_ULT(dev)		(IS_HASWELL(dev) && \
2468
				 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2469
#define IS_HSW_GT3(dev)		(IS_HASWELL(dev) && \
2470
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2471
/* ULX machines are also considered ULT. */
2472 2473
#define IS_HSW_ULX(dev)		(INTEL_DEVID(dev) == 0x0A0E || \
				 INTEL_DEVID(dev) == 0x0A1E)
2474 2475 2476 2477 2478 2479 2480 2481
#define IS_SKL_ULT(dev)		(INTEL_DEVID(dev) == 0x1906 || \
				 INTEL_DEVID(dev) == 0x1913 || \
				 INTEL_DEVID(dev) == 0x1916 || \
				 INTEL_DEVID(dev) == 0x1921 || \
				 INTEL_DEVID(dev) == 0x1926)
#define IS_SKL_ULX(dev)		(INTEL_DEVID(dev) == 0x190E || \
				 INTEL_DEVID(dev) == 0x1915 || \
				 INTEL_DEVID(dev) == 0x191E)
2482
#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2483

2484 2485 2486 2487
#define SKL_REVID_A0		(0x0)
#define SKL_REVID_B0		(0x1)
#define SKL_REVID_C0		(0x2)
#define SKL_REVID_D0		(0x3)
2488
#define SKL_REVID_E0		(0x4)
I
Imre Deak 已提交
2489
#define SKL_REVID_F0		(0x5)
2490

N
Nick Hoath 已提交
2491 2492 2493 2494
#define BXT_REVID_A0		(0x0)
#define BXT_REVID_B0		(0x3)
#define BXT_REVID_C0		(0x6)

2495 2496 2497 2498 2499 2500
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2501 2502 2503 2504 2505
#define IS_GEN2(dev)	(INTEL_INFO(dev)->gen == 2)
#define IS_GEN3(dev)	(INTEL_INFO(dev)->gen == 3)
#define IS_GEN4(dev)	(INTEL_INFO(dev)->gen == 4)
#define IS_GEN5(dev)	(INTEL_INFO(dev)->gen == 5)
#define IS_GEN6(dev)	(INTEL_INFO(dev)->gen == 6)
2506
#define IS_GEN7(dev)	(INTEL_INFO(dev)->gen == 7)
B
Ben Widawsky 已提交
2507
#define IS_GEN8(dev)	(INTEL_INFO(dev)->gen == 8)
2508
#define IS_GEN9(dev)	(INTEL_INFO(dev)->gen == 9)
2509

2510 2511 2512 2513
#define RENDER_RING		(1<<RCS)
#define BSD_RING		(1<<VCS)
#define BLT_RING		(1<<BCS)
#define VEBOX_RING		(1<<VECS)
2514
#define BSD2_RING		(1<<VCS2)
2515
#define HAS_BSD(dev)		(INTEL_INFO(dev)->ring_mask & BSD_RING)
2516
#define HAS_BSD2(dev)		(INTEL_INFO(dev)->ring_mask & BSD2_RING)
2517 2518 2519 2520
#define HAS_BLT(dev)		(INTEL_INFO(dev)->ring_mask & BLT_RING)
#define HAS_VEBOX(dev)		(INTEL_INFO(dev)->ring_mask & VEBOX_RING)
#define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
#define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2521
				 __I915__(dev)->ellc_size)
2522 2523
#define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)

2524
#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
2525
#define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 8)
2526
#define USES_PPGTT(dev)		(i915.enable_ppgtt)
2527 2528
#define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev)	(i915.enable_ppgtt == 3)
2529

2530
#define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
2531 2532
#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)

2533 2534
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))
2535 2536 2537 2538 2539 2540 2541 2542
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2543

2544 2545 2546 2547 2548 2549 2550 2551 2552 2553
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
						      IS_I915GM(dev)))
#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)

#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2554
#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2555

2556
#define HAS_IPS(dev)		(IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2557

2558 2559 2560
#define HAS_DP_MST(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
				 INTEL_INFO(dev)->gen >= 9)

2561
#define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
2562
#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
2563
#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2564 2565
				 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
				 IS_SKYLAKE(dev))
2566
#define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
S
Suketu Shah 已提交
2567 2568
				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
				 IS_SKYLAKE(dev))
2569 2570
#define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
#define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
P
Paulo Zanoni 已提交
2571

2572 2573
#define HAS_CSR(dev)	(IS_SKYLAKE(dev))

2574 2575 2576
#define HAS_GUC_UCODE(dev)	(IS_GEN9(dev))
#define HAS_GUC_SCHED(dev)	(IS_GEN9(dev))

2577 2578 2579
#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
				    INTEL_INFO(dev)->gen >= 8)

2580
#define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
2581
				 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
2582

2583 2584 2585 2586 2587 2588
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2589 2590
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2591

2592
#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2593
#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2594
#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2595 2596
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
B
Ben Widawsky 已提交
2597
#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2598
#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2599

2600 2601
#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))

2602 2603 2604
/* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2605

2606
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2607
#define GEN9_FREQ_SCALER 3
2608

2609 2610
#include "i915_trace.h"

R
Rob Clark 已提交
2611
extern const struct drm_ioctl_desc i915_ioctls[];
2612 2613
extern int i915_max_ioctl;

2614 2615
extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
extern int i915_resume_switcheroo(struct drm_device *dev);
2616

2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627
/* i915_params.c */
struct i915_params {
	int modeset;
	int panel_ignore_lid;
	int semaphores;
	int lvds_channel_mode;
	int panel_use_ssc;
	int vbt_sdvo_panel_type;
	int enable_rc6;
	int enable_fbc;
	int enable_ppgtt;
2628
	int enable_execlists;
2629 2630 2631 2632
	int enable_psr;
	unsigned int preliminary_hw_support;
	int disable_power_well;
	int enable_ips;
2633
	int invert_brightness;
2634
	int enable_cmd_parser;
2635 2636 2637
	/* leave bools at the end to not create holes */
	bool enable_hangcheck;
	bool fastboot;
2638
	bool prefault_disable;
2639
	bool load_detect_test;
2640
	bool reset;
2641
	bool disable_display;
2642
	bool disable_vtd_wa;
2643 2644
	bool enable_guc_submission;
	int guc_log_level;
2645
	int use_mmio_flip;
2646
	int mmio_debug;
R
Rob Clark 已提交
2647
	bool verbose_state_checks;
2648
	bool nuclear_pageflip;
2649
	int edp_vswing;
2650 2651 2652
};
extern struct i915_params i915 __read_mostly;

L
Linus Torvalds 已提交
2653
				/* i915_dma.c */
2654
extern int i915_driver_load(struct drm_device *, unsigned long flags);
J
Jesse Barnes 已提交
2655
extern int i915_driver_unload(struct drm_device *);
2656
extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2657
extern void i915_driver_lastclose(struct drm_device * dev);
2658
extern void i915_driver_preclose(struct drm_device *dev,
2659
				 struct drm_file *file);
2660
extern void i915_driver_postclose(struct drm_device *dev,
2661
				  struct drm_file *file);
2662
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2663 2664
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2665
#endif
2666
extern int intel_gpu_reset(struct drm_device *dev);
2667
extern bool intel_has_gpu_reset(struct drm_device *dev);
2668
extern int i915_reset(struct drm_device *dev);
2669 2670 2671 2672
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2673
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2674
void i915_firmware_load_error_print(const char *fw_path, int err);
2675

2676 2677 2678 2679 2680
/* intel_hotplug.c */
void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2681
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2682

L
Linus Torvalds 已提交
2683
/* i915_irq.c */
2684
void i915_queue_hangcheck(struct drm_device *dev);
2685 2686 2687
__printf(3, 4)
void i915_handle_error(struct drm_device *dev, bool wedged,
		       const char *fmt, ...);
L
Linus Torvalds 已提交
2688

2689
extern void intel_irq_init(struct drm_i915_private *dev_priv);
2690 2691
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2692 2693

extern void intel_uncore_sanitize(struct drm_device *dev);
2694 2695
extern void intel_uncore_early_sanitize(struct drm_device *dev,
					bool restore_forcewake);
2696 2697
extern void intel_uncore_init(struct drm_device *dev);
extern void intel_uncore_check_errors(struct drm_device *dev);
2698
extern void intel_uncore_fini(struct drm_device *dev);
2699
extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2700
const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2701
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2702
				enum forcewake_domains domains);
2703
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2704
				enum forcewake_domains domains);
2705 2706 2707 2708 2709 2710 2711
/* Like above but the caller must manage the uncore.lock itself.
 * Must be used with I915_READ_FW and friends.
 */
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
2712
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2713 2714 2715 2716
static inline bool intel_vgpu_active(struct drm_device *dev)
{
	return to_i915(dev)->vgpu.active;
}
2717

2718
void
2719
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2720
		     u32 status_mask);
2721 2722

void
2723
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2724
		      u32 status_mask);
2725

2726 2727
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738
void
ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
void
ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
#define ibx_enable_display_interrupt(dev_priv, bits) \
	ibx_display_interrupt_update((dev_priv), (bits), (bits))
#define ibx_disable_display_interrupt(dev_priv, bits) \
	ibx_display_interrupt_update((dev_priv), (bits), 0)
2739

2740 2741 2742 2743 2744 2745 2746 2747 2748
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2749 2750
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2751 2752 2753 2754
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
2755
void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2756
					struct drm_i915_gem_request *req);
2757
void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2758
int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2759
				   struct drm_i915_gem_execbuffer2 *args,
2760
				   struct list_head *vmas);
2761 2762
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
2763 2764
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
2765 2766
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
2767 2768 2769 2770
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
2771 2772
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
2773 2774
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
2775 2776 2777 2778
int i915_gem_set_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_get_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2779 2780 2781
int i915_gem_init_userptr(struct drm_device *dev);
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
2782 2783
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
2784 2785
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2786
void i915_gem_load(struct drm_device *dev);
2787 2788
void *i915_gem_object_alloc(struct drm_device *dev);
void i915_gem_object_free(struct drm_i915_gem_object *obj);
2789 2790
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
2791 2792
struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
						  size_t size);
2793 2794
struct drm_i915_gem_object *i915_gem_object_create_from_data(
		struct drm_device *dev, const void *data, size_t size);
2795 2796
void i915_init_vm(struct drm_i915_private *dev_priv,
		  struct i915_address_space *vm);
2797
void i915_gem_free_object(struct drm_gem_object *obj);
B
Ben Widawsky 已提交
2798
void i915_gem_vma_destroy(struct i915_vma *vma);
2799

2800 2801 2802 2803 2804 2805 2806
/* Flags used by pin/bind&friends. */
#define PIN_MAPPABLE	(1<<0)
#define PIN_NONBLOCK	(1<<1)
#define PIN_GLOBAL	(1<<2)
#define PIN_OFFSET_BIAS	(1<<3)
#define PIN_USER	(1<<4)
#define PIN_UPDATE	(1<<5)
2807
#define PIN_OFFSET_MASK (~4095)
2808 2809 2810 2811 2812 2813 2814 2815 2816 2817
int __must_check
i915_gem_object_pin(struct drm_i915_gem_object *obj,
		    struct i915_address_space *vm,
		    uint32_t alignment,
		    uint64_t flags);
int __must_check
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
			 uint32_t alignment,
			 uint64_t flags);
2818 2819 2820

int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
		  u32 flags);
2821
int __must_check i915_vma_unbind(struct i915_vma *vma);
2822
int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2823
void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2824
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2825

2826 2827 2828
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    int *needs_clflush);

2829
int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2830 2831

static inline int __sg_page_count(struct scatterlist *sg)
2832
{
2833 2834
	return sg->length >> PAGE_SHIFT;
}
2835

2836 2837
static inline struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2838
{
2839 2840
	if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
		return NULL;
2841

2842 2843 2844 2845
	if (n < obj->get_page.last) {
		obj->get_page.sg = obj->pages->sgl;
		obj->get_page.last = 0;
	}
2846

2847 2848 2849 2850 2851
	while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
		obj->get_page.last += __sg_page_count(obj->get_page.sg++);
		if (unlikely(sg_is_chain(obj->get_page.sg)))
			obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
	}
2852

2853
	return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2854
}
2855

2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866
static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages == NULL);
	obj->pages_pin_count++;
}
static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages_pin_count == 0);
	obj->pages_pin_count--;
}

2867
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2868
int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2869 2870
			 struct intel_engine_cs *to,
			 struct drm_i915_gem_request **to_req);
B
Ben Widawsky 已提交
2871
void i915_vma_move_to_active(struct i915_vma *vma,
2872
			     struct drm_i915_gem_request *req);
2873 2874 2875
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
2876 2877
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
2878 2879 2880 2881 2882 2883 2884 2885 2886
/**
 * Returns true if seq1 is later than seq2.
 */
static inline bool
i915_seqno_passed(uint32_t seq1, uint32_t seq2)
{
	return (int32_t)(seq1 - seq2) >= 0;
}

2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898
static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
					      bool lazy_coherency)
{
	u32 seqno;

	BUG_ON(req == NULL);

	seqno = req->ring->get_seqno(req->ring, lazy_coherency);

	return i915_seqno_passed(seqno, req->seqno);
}

2899 2900
int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2901

2902
struct drm_i915_gem_request *
2903
i915_gem_find_active_request(struct intel_engine_cs *ring);
2904

2905
bool i915_gem_retire_requests(struct drm_device *dev);
2906
void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2907
int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2908
				      bool interruptible);
2909

2910 2911 2912
static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
{
	return unlikely(atomic_read(&error->reset_counter)
M
Mika Kuoppala 已提交
2913
			& (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2914 2915 2916 2917
}

static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
{
M
Mika Kuoppala 已提交
2918 2919 2920 2921 2922 2923
	return atomic_read(&error->reset_counter) & I915_WEDGED;
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
	return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2924
}
2925

2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937
static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
{
	return dev_priv->gpu_error.stop_rings == 0 ||
		dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
}

static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
{
	return dev_priv->gpu_error.stop_rings == 0 ||
		dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
}

2938
void i915_gem_reset(struct drm_device *dev);
2939
bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2940
int __must_check i915_gem_init(struct drm_device *dev);
2941
int i915_gem_init_rings(struct drm_device *dev);
2942
int __must_check i915_gem_init_hw(struct drm_device *dev);
2943
int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
2944
void i915_gem_init_swizzling(struct drm_device *dev);
J
Jesse Barnes 已提交
2945
void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2946
int __must_check i915_gpu_idle(struct drm_device *dev);
2947
int __must_check i915_gem_suspend(struct drm_device *dev);
2948
void __i915_add_request(struct drm_i915_gem_request *req,
2949 2950
			struct drm_i915_gem_object *batch_obj,
			bool flush_caches);
2951
#define i915_add_request(req) \
2952
	__i915_add_request(req, NULL, true)
2953
#define i915_add_request_no_flush(req) \
2954
	__i915_add_request(req, NULL, false)
2955
int __i915_wait_request(struct drm_i915_gem_request *req,
2956 2957 2958
			unsigned reset_counter,
			bool interruptible,
			s64 *timeout,
2959
			struct intel_rps_client *rps);
2960
int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2961
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2962
int __must_check
2963 2964 2965
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
			       bool readonly);
int __must_check
2966 2967 2968
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
				  bool write);
int __must_check
2969 2970
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
int __must_check
2971 2972
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
2973
				     struct intel_engine_cs *pipelined,
2974
				     struct drm_i915_gem_request **pipelined_request,
2975 2976 2977
				     const struct i915_ggtt_view *view);
void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
					      const struct i915_ggtt_view *view);
2978
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2979
				int align);
2980
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2981
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2982

2983 2984
uint32_t
i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2985
uint32_t
2986 2987
i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
			    int tiling_mode, bool fenced);
2988

2989 2990 2991
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

2992 2993 2994 2995 2996 2997
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

2998 2999 3000 3001 3002
u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
				  const struct i915_ggtt_view *view);
u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
			struct i915_address_space *vm);
static inline u64
3003
i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3004
{
3005
	return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3006
}
3007

3008
bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3009
bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3010
				  const struct i915_ggtt_view *view);
3011
bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3012
			struct i915_address_space *vm);
3013

3014 3015
unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
				struct i915_address_space *vm);
3016
struct i915_vma *
3017 3018 3019 3020 3021
i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
		    struct i915_address_space *vm);
struct i915_vma *
i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
			  const struct i915_ggtt_view *view);
3022

3023 3024
struct i915_vma *
i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3025 3026 3027 3028
				  struct i915_address_space *vm);
struct i915_vma *
i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
				       const struct i915_ggtt_view *view);
3029

3030 3031 3032 3033
static inline struct i915_vma *
i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
{
	return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
B
Ben Widawsky 已提交
3034
}
3035
bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3036

3037
/* Some GGTT VM helpers */
3038
#define i915_obj_to_ggtt(obj) \
3039 3040 3041 3042 3043 3044 3045 3046
	(&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
static inline bool i915_is_ggtt(struct i915_address_space *vm)
{
	struct i915_address_space *ggtt =
		&((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
	return vm == ggtt;
}

3047 3048 3049 3050 3051 3052 3053 3054 3055
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	WARN_ON(i915_is_ggtt(vm));

	return container_of(vm, struct i915_hw_ppgtt, base);
}


3056 3057
static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
{
3058
	return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3059 3060 3061 3062 3063
}

static inline unsigned long
i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
{
3064
	return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3065
}
B
Ben Widawsky 已提交
3066 3067 3068 3069

static inline int __must_check
i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
		      uint32_t alignment,
3070
		      unsigned flags)
B
Ben Widawsky 已提交
3071
{
3072 3073
	return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
				   alignment, flags | PIN_GLOBAL);
B
Ben Widawsky 已提交
3074
}
3075

3076 3077 3078 3079 3080 3081
static inline int
i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
{
	return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
}

3082 3083 3084 3085 3086 3087 3088
void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
				     const struct i915_ggtt_view *view);
static inline void
i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
{
	i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
}
3089

3090 3091 3092 3093 3094 3095 3096 3097 3098
/* i915_gem_fence.c */
int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);

bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);

void i915_gem_restore_fences(struct drm_device *dev);

3099 3100 3101 3102
void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);

3103
/* i915_gem_context.c */
3104
int __must_check i915_gem_context_init(struct drm_device *dev);
3105
void i915_gem_context_fini(struct drm_device *dev);
3106
void i915_gem_context_reset(struct drm_device *dev);
3107
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3108
int i915_gem_context_enable(struct drm_i915_gem_request *req);
3109
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3110
int i915_switch_context(struct drm_i915_gem_request *req);
3111
struct intel_context *
3112
i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3113
void i915_gem_context_free(struct kref *ctx_ref);
3114 3115
struct drm_i915_gem_object *
i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3116
static inline void i915_gem_context_reference(struct intel_context *ctx)
3117
{
3118
	kref_get(&ctx->ref);
3119 3120
}

3121
static inline void i915_gem_context_unreference(struct intel_context *ctx)
3122
{
3123
	kref_put(&ctx->ref, i915_gem_context_free);
3124 3125
}

3126
static inline bool i915_gem_context_is_default(const struct intel_context *c)
3127
{
3128
	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3129 3130
}

3131 3132 3133 3134
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file);
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
				   struct drm_file *file);
3135 3136 3137 3138
int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
3139

3140 3141 3142 3143 3144 3145
/* i915_gem_evict.c */
int __must_check i915_gem_evict_something(struct drm_device *dev,
					  struct i915_address_space *vm,
					  int min_size,
					  unsigned alignment,
					  unsigned cache_level,
3146 3147
					  unsigned long start,
					  unsigned long end,
3148
					  unsigned flags);
3149 3150
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
int i915_gem_evict_everything(struct drm_device *dev);
3151

3152
/* belongs in i915_gem_gtt.h */
3153
static inline void i915_gem_chipset_flush(struct drm_device *dev)
3154 3155 3156 3157
{
	if (INTEL_INFO(dev)->gen < 6)
		intel_gtt_chipset_flush();
}
3158

3159
/* i915_gem_stolen.c */
3160 3161 3162 3163 3164
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3165 3166
int i915_gem_init_stolen(struct drm_device *dev);
void i915_gem_cleanup_stolen(struct drm_device *dev);
3167 3168
struct drm_i915_gem_object *
i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3169 3170 3171 3172 3173
struct drm_i915_gem_object *
i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3174

3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
			      long target,
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);


3186
/* i915_gem_tiling.c */
3187
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3188
{
3189
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3190 3191 3192 3193 3194

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
		obj->tiling_mode != I915_TILING_NONE;
}

3195
/* i915_gem_debug.c */
3196 3197
#if WATCH_LISTS
int i915_verify_lists(struct drm_device *dev);
3198
#else
3199
#define i915_verify_lists(dev) 0
3200
#endif
L
Linus Torvalds 已提交
3201

3202
/* i915_debugfs.c */
3203 3204
int i915_debugfs_init(struct drm_minor *minor);
void i915_debugfs_cleanup(struct drm_minor *minor);
3205
#ifdef CONFIG_DEBUG_FS
J
Jani Nikula 已提交
3206
int i915_debugfs_connector_add(struct drm_connector *connector);
3207 3208
void intel_display_crc_init(struct drm_device *dev);
#else
3209 3210
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3211
static inline void intel_display_crc_init(struct drm_device *dev) {}
3212
#endif
3213 3214

/* i915_gpu_error.c */
3215 3216
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3217 3218
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
			    const struct i915_error_state_file_priv *error);
3219
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3220
			      struct drm_i915_private *i915,
3221 3222 3223 3224 3225 3226
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3227 3228
void i915_capture_error_state(struct drm_device *dev, bool wedge,
			      const char *error_msg);
3229 3230 3231 3232 3233 3234
void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv);
void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
void i915_destroy_error_state(struct drm_device *dev);

void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3235
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3236

3237
/* i915_cmd_parser.c */
3238
int i915_cmd_parser_get_version(void);
3239 3240 3241 3242
int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
int i915_parse_cmds(struct intel_engine_cs *ring,
3243
		    struct drm_i915_gem_object *batch_obj,
3244
		    struct drm_i915_gem_object *shadow_batch_obj,
3245
		    u32 batch_start_offset,
3246
		    u32 batch_len,
3247 3248
		    bool is_master);

3249 3250 3251
/* i915_suspend.c */
extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev);
3252

B
Ben Widawsky 已提交
3253 3254 3255 3256
/* i915_sysfs.c */
void i915_setup_sysfs(struct drm_device *dev_priv);
void i915_teardown_sysfs(struct drm_device *dev_priv);

3257 3258 3259
/* intel_i2c.c */
extern int intel_setup_gmbus(struct drm_device *dev);
extern void intel_teardown_gmbus(struct drm_device *dev);
3260 3261
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3262

3263 3264
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3265 3266
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3267
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3268 3269 3270
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3271 3272
extern void intel_i2c_reset(struct drm_device *dev);

3273
/* intel_opregion.c */
3274
#ifdef CONFIG_ACPI
3275
extern int intel_opregion_setup(struct drm_device *dev);
3276 3277
extern void intel_opregion_init(struct drm_device *dev);
extern void intel_opregion_fini(struct drm_device *dev);
3278
extern void intel_opregion_asle_intr(struct drm_device *dev);
3279 3280
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
3281 3282
extern int intel_opregion_notify_adapter(struct drm_device *dev,
					 pci_power_t state);
3283
#else
3284
static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3285 3286
static inline void intel_opregion_init(struct drm_device *dev) { return; }
static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3287
static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3288 3289 3290 3291 3292
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
3293 3294 3295 3296 3297
static inline int
intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
{
	return 0;
}
3298
#endif
3299

J
Jesse Barnes 已提交
3300 3301 3302 3303 3304 3305 3306 3307 3308
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

J
Jesse Barnes 已提交
3309
/* modesetting */
3310
extern void intel_modeset_init_hw(struct drm_device *dev);
J
Jesse Barnes 已提交
3311
extern void intel_modeset_init(struct drm_device *dev);
3312
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3313
extern void intel_modeset_cleanup(struct drm_device *dev);
3314
extern void intel_connector_unregister(struct intel_connector *);
3315
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3316
extern void intel_display_resume(struct drm_device *dev);
3317
extern void i915_redisable_vga(struct drm_device *dev);
3318
extern void i915_redisable_vga_power_on(struct drm_device *dev);
3319
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
P
Paulo Zanoni 已提交
3320
extern void intel_init_pch_refclk(struct drm_device *dev);
3321
extern void intel_set_rps(struct drm_device *dev, u8 val);
3322 3323
extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
				  bool enable);
3324 3325
extern void intel_detect_pch(struct drm_device *dev);
extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
B
Ben Widawsky 已提交
3326
extern int intel_enable_rc6(const struct drm_device *dev);
3327

3328
extern bool i915_semaphore_is_enabled(struct drm_device *dev);
B
Ben Widawsky 已提交
3329 3330
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3331 3332
int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
3333

3334 3335
/* overlay */
extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3336 3337
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3338 3339

extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3340
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3341 3342
					    struct drm_device *dev,
					    struct intel_display_error_state *error);
3343

3344 3345
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3346 3347

/* intel_sideband.c */
3348 3349
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3350
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3351 3352 3353 3354 3355 3356
u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3357 3358
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3359 3360
u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3361 3362
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3363 3364 3365 3366
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3367 3368
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3369

3370 3371
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3372

3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3386 3387 3388 3389 3390 3391
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
 * machine death. You have been warned.
 */
3392 3393
#define I915_WRITE64(reg, val)	dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3394

3395
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3396 3397 3398 3399 3400 3401 3402 3403
	u32 upper, lower, tmp;						\
	tmp = I915_READ(upper_reg);					\
	do {								\
		upper = tmp;						\
		lower = I915_READ(lower_reg);				\
		tmp = I915_READ(upper_reg);				\
	} while (upper != tmp);						\
	(u64)upper << 32 | lower; })
3404

3405 3406 3407
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418
/* These are untraced mmio-accessors that are only valid to be used inside
 * criticial sections inside IRQ handlers where forcewake is explicitly
 * controlled.
 * Think twice, and think again, before using these.
 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
 * intel_uncore_forcewake_irqunlock().
 */
#define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
#define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

3419 3420 3421 3422
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
3423

3424 3425
static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
{
3426
	if (IS_VALLEYVIEW(dev))
3427
		return VLV_VGACNTRL;
3428 3429
	else if (INTEL_INFO(dev)->gen >= 5)
		return CPU_VGACNTRL;
3430 3431 3432 3433
	else
		return VGACNTRL;
}

V
Ville Syrjälä 已提交
3434 3435 3436 3437 3438
static inline void __user *to_user_ptr(u64 address)
{
	return (void __user *)(uintptr_t)address;
}

3439 3440 3441 3442 3443 3444 3445
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3446 3447 3448 3449 3450
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

3451 3452 3453 3454 3455 3456 3457 3458
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3459 3460 3461 3462 3463 3464 3465 3466 3467
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
3468
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3469 3470 3471 3472 3473 3474 3475 3476 3477 3478

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
3479 3480 3481 3482
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
3483 3484 3485
	}
}

3486 3487 3488 3489 3490 3491 3492
static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
				      struct drm_i915_gem_request *req)
{
	if (ring->trace_irq_req == NULL && ring->irq_get(ring))
		i915_gem_request_assign(&ring->trace_irq_req, req);
}

L
Linus Torvalds 已提交
3493
#endif