igb_main.c 179.1 KB
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/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
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  Copyright(c) 2007-2009 Intel Corporation.
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  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#include <linux/module.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/vmalloc.h>
#include <linux/pagemap.h>
#include <linux/netdevice.h>
#include <linux/ipv6.h>
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#include <linux/slab.h>
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#include <net/checksum.h>
#include <net/ip6_checksum.h>
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#include <linux/net_tstamp.h>
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#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/if_vlan.h>
#include <linux/pci.h>
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#include <linux/pci-aspm.h>
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#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/if_ether.h>
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#include <linux/aer.h>
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#ifdef CONFIG_IGB_DCA
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#include <linux/dca.h>
#endif
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#include "igb.h"

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#define DRV_VERSION "2.1.0-k2"
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char igb_driver_name[] = "igb";
char igb_driver_version[] = DRV_VERSION;
static const char igb_driver_string[] =
				"Intel(R) Gigabit Ethernet Network Driver";
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static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
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static const struct e1000_info *igb_info_tbl[] = {
	[board_82575] = &e1000_82575_info,
};

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static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
	/* required last entry */
	{0, }
};

MODULE_DEVICE_TABLE(pci, igb_pci_tbl);

void igb_reset(struct igb_adapter *);
static int igb_setup_all_tx_resources(struct igb_adapter *);
static int igb_setup_all_rx_resources(struct igb_adapter *);
static void igb_free_all_tx_resources(struct igb_adapter *);
static void igb_free_all_rx_resources(struct igb_adapter *);
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static void igb_setup_mrqc(struct igb_adapter *);
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void igb_update_stats(struct igb_adapter *);
static int igb_probe(struct pci_dev *, const struct pci_device_id *);
static void __devexit igb_remove(struct pci_dev *pdev);
static int igb_sw_init(struct igb_adapter *);
static int igb_open(struct net_device *);
static int igb_close(struct net_device *);
static void igb_configure_tx(struct igb_adapter *);
static void igb_configure_rx(struct igb_adapter *);
static void igb_clean_all_tx_rings(struct igb_adapter *);
static void igb_clean_all_rx_rings(struct igb_adapter *);
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static void igb_clean_tx_ring(struct igb_ring *);
static void igb_clean_rx_ring(struct igb_ring *);
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static void igb_set_rx_mode(struct net_device *);
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static void igb_update_phy_info(unsigned long);
static void igb_watchdog(unsigned long);
static void igb_watchdog_task(struct work_struct *);
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static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
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static struct net_device_stats *igb_get_stats(struct net_device *);
static int igb_change_mtu(struct net_device *, int);
static int igb_set_mac(struct net_device *, void *);
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static void igb_set_uta(struct igb_adapter *adapter);
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static irqreturn_t igb_intr(int irq, void *);
static irqreturn_t igb_intr_msi(int irq, void *);
static irqreturn_t igb_msix_other(int irq, void *);
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static irqreturn_t igb_msix_ring(int irq, void *);
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#ifdef CONFIG_IGB_DCA
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static void igb_update_dca(struct igb_q_vector *);
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static void igb_setup_dca(struct igb_adapter *);
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#endif /* CONFIG_IGB_DCA */
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static bool igb_clean_tx_irq(struct igb_q_vector *);
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static int igb_poll(struct napi_struct *, int);
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static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int);
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static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
static void igb_tx_timeout(struct net_device *);
static void igb_reset_task(struct work_struct *);
static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
static void igb_vlan_rx_add_vid(struct net_device *, u16);
static void igb_vlan_rx_kill_vid(struct net_device *, u16);
static void igb_restore_vlan(struct igb_adapter *);
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static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
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static void igb_ping_all_vfs(struct igb_adapter *);
static void igb_msg_task(struct igb_adapter *);
static void igb_vmm_control(struct igb_adapter *);
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static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
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static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
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static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
static int igb_ndo_set_vf_vlan(struct net_device *netdev,
			       int vf, u16 vlan, u8 qos);
static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
				 struct ifla_vf_info *ivi);
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#ifdef CONFIG_PM
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static int igb_suspend(struct pci_dev *, pm_message_t);
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static int igb_resume(struct pci_dev *);
#endif
static void igb_shutdown(struct pci_dev *);
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#ifdef CONFIG_IGB_DCA
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static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
static struct notifier_block dca_notifier = {
	.notifier_call	= igb_notify_dca,
	.next		= NULL,
	.priority	= 0
};
#endif
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#ifdef CONFIG_NET_POLL_CONTROLLER
/* for netdump / net console */
static void igb_netpoll(struct net_device *);
#endif
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#ifdef CONFIG_PCI_IOV
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static unsigned int max_vfs = 0;
module_param(max_vfs, uint, 0);
MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
                 "per physical function");
#endif /* CONFIG_PCI_IOV */

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static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
		     pci_channel_state_t);
static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
static void igb_io_resume(struct pci_dev *);

static struct pci_error_handlers igb_err_handler = {
	.error_detected = igb_io_error_detected,
	.slot_reset = igb_io_slot_reset,
	.resume = igb_io_resume,
};


static struct pci_driver igb_driver = {
	.name     = igb_driver_name,
	.id_table = igb_pci_tbl,
	.probe    = igb_probe,
	.remove   = __devexit_p(igb_remove),
#ifdef CONFIG_PM
	/* Power Managment Hooks */
	.suspend  = igb_suspend,
	.resume   = igb_resume,
#endif
	.shutdown = igb_shutdown,
	.err_handler = &igb_err_handler
};

MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);

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struct igb_reg_info {
	u32 ofs;
	char *name;
};

static const struct igb_reg_info igb_reg_info_tbl[] = {

	/* General Registers */
	{E1000_CTRL, "CTRL"},
	{E1000_STATUS, "STATUS"},
	{E1000_CTRL_EXT, "CTRL_EXT"},

	/* Interrupt Registers */
	{E1000_ICR, "ICR"},

	/* RX Registers */
	{E1000_RCTL, "RCTL"},
	{E1000_RDLEN(0), "RDLEN"},
	{E1000_RDH(0), "RDH"},
	{E1000_RDT(0), "RDT"},
	{E1000_RXDCTL(0), "RXDCTL"},
	{E1000_RDBAL(0), "RDBAL"},
	{E1000_RDBAH(0), "RDBAH"},

	/* TX Registers */
	{E1000_TCTL, "TCTL"},
	{E1000_TDBAL(0), "TDBAL"},
	{E1000_TDBAH(0), "TDBAH"},
	{E1000_TDLEN(0), "TDLEN"},
	{E1000_TDH(0), "TDH"},
	{E1000_TDT(0), "TDT"},
	{E1000_TXDCTL(0), "TXDCTL"},
	{E1000_TDFH, "TDFH"},
	{E1000_TDFT, "TDFT"},
	{E1000_TDFHS, "TDFHS"},
	{E1000_TDFPC, "TDFPC"},

	/* List Terminator */
	{}
};

/*
 * igb_regdump - register printout routine
 */
static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
{
	int n = 0;
	char rname[16];
	u32 regs[8];

	switch (reginfo->ofs) {
	case E1000_RDLEN(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_RDLEN(n));
		break;
	case E1000_RDH(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_RDH(n));
		break;
	case E1000_RDT(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_RDT(n));
		break;
	case E1000_RXDCTL(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_RXDCTL(n));
		break;
	case E1000_RDBAL(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_RDBAL(n));
		break;
	case E1000_RDBAH(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_RDBAH(n));
		break;
	case E1000_TDBAL(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_RDBAL(n));
		break;
	case E1000_TDBAH(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_TDBAH(n));
		break;
	case E1000_TDLEN(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_TDLEN(n));
		break;
	case E1000_TDH(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_TDH(n));
		break;
	case E1000_TDT(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_TDT(n));
		break;
	case E1000_TXDCTL(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_TXDCTL(n));
		break;
	default:
		printk(KERN_INFO "%-15s %08x\n",
			reginfo->name, rd32(reginfo->ofs));
		return;
	}

	snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
	printk(KERN_INFO "%-15s ", rname);
	for (n = 0; n < 4; n++)
		printk(KERN_CONT "%08x ", regs[n]);
	printk(KERN_CONT "\n");
}

/*
 * igb_dump - Print registers, tx-rings and rx-rings
 */
static void igb_dump(struct igb_adapter *adapter)
{
	struct net_device *netdev = adapter->netdev;
	struct e1000_hw *hw = &adapter->hw;
	struct igb_reg_info *reginfo;
	int n = 0;
	struct igb_ring *tx_ring;
	union e1000_adv_tx_desc *tx_desc;
	struct my_u0 { u64 a; u64 b; } *u0;
	struct igb_buffer *buffer_info;
	struct igb_ring *rx_ring;
	union e1000_adv_rx_desc *rx_desc;
	u32 staterr;
	int i = 0;

	if (!netif_msg_hw(adapter))
		return;

	/* Print netdevice Info */
	if (netdev) {
		dev_info(&adapter->pdev->dev, "Net device Info\n");
		printk(KERN_INFO "Device Name     state            "
			"trans_start      last_rx\n");
		printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
		netdev->name,
		netdev->state,
		netdev->trans_start,
		netdev->last_rx);
	}

	/* Print Registers */
	dev_info(&adapter->pdev->dev, "Register Dump\n");
	printk(KERN_INFO " Register Name   Value\n");
	for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
	     reginfo->name; reginfo++) {
		igb_regdump(hw, reginfo);
	}

	/* Print TX Ring Summary */
	if (!netdev || !netif_running(netdev))
		goto exit;

	dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
	printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma  ]"
		" leng ntw timestamp\n");
	for (n = 0; n < adapter->num_tx_queues; n++) {
		tx_ring = adapter->tx_ring[n];
		buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
		printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
			   n, tx_ring->next_to_use, tx_ring->next_to_clean,
			   (u64)buffer_info->dma,
			   buffer_info->length,
			   buffer_info->next_to_watch,
			   (u64)buffer_info->time_stamp);
	}

	/* Print TX Rings */
	if (!netif_msg_tx_done(adapter))
		goto rx_ring_summary;

	dev_info(&adapter->pdev->dev, "TX Rings Dump\n");

	/* Transmit Descriptor Formats
	 *
	 * Advanced Transmit Descriptor
	 *   +--------------------------------------------------------------+
	 * 0 |         Buffer Address [63:0]                                |
	 *   +--------------------------------------------------------------+
	 * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
	 *   +--------------------------------------------------------------+
	 *   63      46 45    40 39 38 36 35 32 31   24             15       0
	 */

	for (n = 0; n < adapter->num_tx_queues; n++) {
		tx_ring = adapter->tx_ring[n];
		printk(KERN_INFO "------------------------------------\n");
		printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
		printk(KERN_INFO "------------------------------------\n");
		printk(KERN_INFO "T [desc]     [address 63:0  ] "
			"[PlPOCIStDDM Ln] [bi->dma       ] "
			"leng  ntw timestamp        bi->skb\n");

		for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
			tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
			buffer_info = &tx_ring->buffer_info[i];
			u0 = (struct my_u0 *)tx_desc;
			printk(KERN_INFO "T [0x%03X]    %016llX %016llX %016llX"
				" %04X  %3X %016llX %p", i,
				le64_to_cpu(u0->a),
				le64_to_cpu(u0->b),
				(u64)buffer_info->dma,
				buffer_info->length,
				buffer_info->next_to_watch,
				(u64)buffer_info->time_stamp,
				buffer_info->skb);
			if (i == tx_ring->next_to_use &&
				i == tx_ring->next_to_clean)
				printk(KERN_CONT " NTC/U\n");
			else if (i == tx_ring->next_to_use)
				printk(KERN_CONT " NTU\n");
			else if (i == tx_ring->next_to_clean)
				printk(KERN_CONT " NTC\n");
			else
				printk(KERN_CONT "\n");

			if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
				print_hex_dump(KERN_INFO, "",
					DUMP_PREFIX_ADDRESS,
					16, 1, phys_to_virt(buffer_info->dma),
					buffer_info->length, true);
		}
	}

	/* Print RX Rings Summary */
rx_ring_summary:
	dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
	printk(KERN_INFO "Queue [NTU] [NTC]\n");
	for (n = 0; n < adapter->num_rx_queues; n++) {
		rx_ring = adapter->rx_ring[n];
		printk(KERN_INFO " %5d %5X %5X\n", n,
			   rx_ring->next_to_use, rx_ring->next_to_clean);
	}

	/* Print RX Rings */
	if (!netif_msg_rx_status(adapter))
		goto exit;

	dev_info(&adapter->pdev->dev, "RX Rings Dump\n");

	/* Advanced Receive Descriptor (Read) Format
	 *    63                                           1        0
	 *    +-----------------------------------------------------+
	 *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
	 *    +----------------------------------------------+------+
	 *  8 |       Header Buffer Address [63:1]           |  DD  |
	 *    +-----------------------------------------------------+
	 *
	 *
	 * Advanced Receive Descriptor (Write-Back) Format
	 *
	 *   63       48 47    32 31  30      21 20 17 16   4 3     0
	 *   +------------------------------------------------------+
	 * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
	 *   | Checksum   Ident  |   |           |    | Type | Type |
	 *   +------------------------------------------------------+
	 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
	 *   +------------------------------------------------------+
	 *   63       48 47    32 31            20 19               0
	 */

	for (n = 0; n < adapter->num_rx_queues; n++) {
		rx_ring = adapter->rx_ring[n];
		printk(KERN_INFO "------------------------------------\n");
		printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
		printk(KERN_INFO "------------------------------------\n");
		printk(KERN_INFO "R  [desc]      [ PktBuf     A0] "
			"[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
			"<-- Adv Rx Read format\n");
		printk(KERN_INFO "RWB[desc]      [PcsmIpSHl PtRs] "
			"[vl er S cks ln] ---------------- [bi->skb] "
			"<-- Adv Rx Write-Back format\n");

		for (i = 0; i < rx_ring->count; i++) {
			buffer_info = &rx_ring->buffer_info[i];
			rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
			u0 = (struct my_u0 *)rx_desc;
			staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
			if (staterr & E1000_RXD_STAT_DD) {
				/* Descriptor Done */
				printk(KERN_INFO "RWB[0x%03X]     %016llX "
					"%016llX ---------------- %p", i,
					le64_to_cpu(u0->a),
					le64_to_cpu(u0->b),
					buffer_info->skb);
			} else {
				printk(KERN_INFO "R  [0x%03X]     %016llX "
					"%016llX %016llX %p", i,
					le64_to_cpu(u0->a),
					le64_to_cpu(u0->b),
					(u64)buffer_info->dma,
					buffer_info->skb);

				if (netif_msg_pktdata(adapter)) {
					print_hex_dump(KERN_INFO, "",
						DUMP_PREFIX_ADDRESS,
						16, 1,
						phys_to_virt(buffer_info->dma),
						rx_ring->rx_buffer_len, true);
					if (rx_ring->rx_buffer_len
						< IGB_RXBUFFER_1024)
						print_hex_dump(KERN_INFO, "",
						  DUMP_PREFIX_ADDRESS,
						  16, 1,
						  phys_to_virt(
						    buffer_info->page_dma +
						    buffer_info->page_offset),
						  PAGE_SIZE/2, true);
				}
			}

			if (i == rx_ring->next_to_use)
				printk(KERN_CONT " NTU\n");
			else if (i == rx_ring->next_to_clean)
				printk(KERN_CONT " NTC\n");
			else
				printk(KERN_CONT "\n");

		}
	}

exit:
	return;
}


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/**
 * igb_read_clock - read raw cycle counter (to be used by time counter)
 */
static cycle_t igb_read_clock(const struct cyclecounter *tc)
{
	struct igb_adapter *adapter =
		container_of(tc, struct igb_adapter, cycles);
	struct e1000_hw *hw = &adapter->hw;
542 543
	u64 stamp = 0;
	int shift = 0;
P
Patrick Ohly 已提交
544

545 546 547 548 549 550 551 552 553 554
	/*
	 * The timestamp latches on lowest register read. For the 82580
	 * the lowest register is SYSTIMR instead of SYSTIML.  However we never
	 * adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it.
	 */
	if (hw->mac.type == e1000_82580) {
		stamp = rd32(E1000_SYSTIMR) >> 8;
		shift = IGB_82580_TSYNC_SHIFT;
	}

555 556
	stamp |= (u64)rd32(E1000_SYSTIML) << shift;
	stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32);
P
Patrick Ohly 已提交
557 558 559
	return stamp;
}

560
/**
561
 * igb_get_hw_dev - return device
562 563
 * used by hardware layer to print debugging information
 **/
564
struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
565 566
{
	struct igb_adapter *adapter = hw->back;
567
	return adapter->netdev;
568
}
P
Patrick Ohly 已提交
569

570 571 572 573 574 575 576 577 578 579 580 581 582 583
/**
 * igb_init_module - Driver Registration Routine
 *
 * igb_init_module is the first routine called when the driver is
 * loaded. All it does is register with the PCI subsystem.
 **/
static int __init igb_init_module(void)
{
	int ret;
	printk(KERN_INFO "%s - version %s\n",
	       igb_driver_string, igb_driver_version);

	printk(KERN_INFO "%s\n", igb_copyright);

584
#ifdef CONFIG_IGB_DCA
J
Jeb Cramer 已提交
585 586
	dca_register_notify(&dca_notifier);
#endif
587
	ret = pci_register_driver(&igb_driver);
588 589 590 591 592 593 594 595 596 597 598 599 600
	return ret;
}

module_init(igb_init_module);

/**
 * igb_exit_module - Driver Exit Cleanup Routine
 *
 * igb_exit_module is called just before the driver is removed
 * from memory.
 **/
static void __exit igb_exit_module(void)
{
601
#ifdef CONFIG_IGB_DCA
J
Jeb Cramer 已提交
602 603
	dca_unregister_notify(&dca_notifier);
#endif
604 605 606 607 608
	pci_unregister_driver(&igb_driver);
}

module_exit(igb_exit_module);

609 610 611 612 613 614 615 616 617 618
#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
/**
 * igb_cache_ring_register - Descriptor ring to register mapping
 * @adapter: board private structure to initialize
 *
 * Once we know the feature-set enabled for the device, we'll cache
 * the register offset the descriptor ring is assigned to.
 **/
static void igb_cache_ring_register(struct igb_adapter *adapter)
{
619
	int i = 0, j = 0;
620
	u32 rbase_offset = adapter->vfs_allocated_count;
621 622 623 624 625 626 627 628

	switch (adapter->hw.mac.type) {
	case e1000_82576:
		/* The queues are allocated for virtualization such that VF 0
		 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
		 * In order to avoid collision we start at the first free queue
		 * and continue consuming queues in the same sequence
		 */
629
		if (adapter->vfs_allocated_count) {
630
			for (; i < adapter->rss_queues; i++)
631 632
				adapter->rx_ring[i]->reg_idx = rbase_offset +
				                               Q_IDX_82576(i);
633
		}
634
	case e1000_82575:
635
	case e1000_82580:
636
	case e1000_i350:
637
	default:
638
		for (; i < adapter->num_rx_queues; i++)
639
			adapter->rx_ring[i]->reg_idx = rbase_offset + i;
640
		for (; j < adapter->num_tx_queues; j++)
641
			adapter->tx_ring[j]->reg_idx = rbase_offset + j;
642 643 644 645
		break;
	}
}

646 647
static void igb_free_queues(struct igb_adapter *adapter)
{
648
	int i;
649

650 651 652 653 654 655 656 657
	for (i = 0; i < adapter->num_tx_queues; i++) {
		kfree(adapter->tx_ring[i]);
		adapter->tx_ring[i] = NULL;
	}
	for (i = 0; i < adapter->num_rx_queues; i++) {
		kfree(adapter->rx_ring[i]);
		adapter->rx_ring[i] = NULL;
	}
658 659 660 661
	adapter->num_rx_queues = 0;
	adapter->num_tx_queues = 0;
}

662 663 664 665 666 667 668 669 670
/**
 * igb_alloc_queues - Allocate memory for all rings
 * @adapter: board private structure to initialize
 *
 * We allocate one ring per queue at run-time since we don't know the
 * number of queues at compile-time.
 **/
static int igb_alloc_queues(struct igb_adapter *adapter)
{
671
	struct igb_ring *ring;
672 673
	int i;

674
	for (i = 0; i < adapter->num_tx_queues; i++) {
675 676 677
		ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
		if (!ring)
			goto err;
678
		ring->count = adapter->tx_ring_count;
679
		ring->queue_index = i;
680
		ring->dev = &adapter->pdev->dev;
681
		ring->netdev = adapter->netdev;
682 683 684
		/* For 82575, context index must be unique per ring. */
		if (adapter->hw.mac.type == e1000_82575)
			ring->flags = IGB_RING_FLAG_TX_CTX_IDX;
685
		adapter->tx_ring[i] = ring;
686
	}
687

688
	for (i = 0; i < adapter->num_rx_queues; i++) {
689 690 691
		ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
		if (!ring)
			goto err;
692
		ring->count = adapter->rx_ring_count;
P
PJ Waskiewicz 已提交
693
		ring->queue_index = i;
694
		ring->dev = &adapter->pdev->dev;
695
		ring->netdev = adapter->netdev;
696
		ring->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
697 698 699 700
		ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */
		/* set flag indicating ring supports SCTP checksum offload */
		if (adapter->hw.mac.type >= e1000_82576)
			ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM;
701
		adapter->rx_ring[i] = ring;
702
	}
703 704

	igb_cache_ring_register(adapter);
705

706
	return 0;
A
Alexander Duyck 已提交
707

708 709
err:
	igb_free_queues(adapter);
710

711
	return -ENOMEM;
A
Alexander Duyck 已提交
712 713
}

714
#define IGB_N0_QUEUE -1
715
static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
716 717
{
	u32 msixbm = 0;
718
	struct igb_adapter *adapter = q_vector->adapter;
719
	struct e1000_hw *hw = &adapter->hw;
A
Alexander Duyck 已提交
720
	u32 ivar, index;
721 722 723 724 725 726 727
	int rx_queue = IGB_N0_QUEUE;
	int tx_queue = IGB_N0_QUEUE;

	if (q_vector->rx_ring)
		rx_queue = q_vector->rx_ring->reg_idx;
	if (q_vector->tx_ring)
		tx_queue = q_vector->tx_ring->reg_idx;
A
Alexander Duyck 已提交
728 729 730

	switch (hw->mac.type) {
	case e1000_82575:
731 732 733 734
		/* The 82575 assigns vectors using a bitmask, which matches the
		   bitmask for the EICR/EIMS/EIMC registers.  To assign one
		   or more queues to a vector, we write the appropriate bits
		   into the MSIXBM register for that vector. */
735
		if (rx_queue > IGB_N0_QUEUE)
736
			msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
737
		if (tx_queue > IGB_N0_QUEUE)
738
			msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
739 740
		if (!adapter->msix_entries && msix_vector == 0)
			msixbm |= E1000_EIMS_OTHER;
741
		array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
742
		q_vector->eims_value = msixbm;
A
Alexander Duyck 已提交
743 744
		break;
	case e1000_82576:
745
		/* 82576 uses a table-based method for assigning vectors.
A
Alexander Duyck 已提交
746 747 748 749
		   Each queue has a single entry in the table to which we write
		   a vector number along with a "valid" bit.  Sadly, the layout
		   of the table is somewhat counterintuitive. */
		if (rx_queue > IGB_N0_QUEUE) {
750
			index = (rx_queue & 0x7);
A
Alexander Duyck 已提交
751
			ivar = array_rd32(E1000_IVAR0, index);
752
			if (rx_queue < 8) {
753 754 755
				/* vector goes into low byte of register */
				ivar = ivar & 0xFFFFFF00;
				ivar |= msix_vector | E1000_IVAR_VALID;
756 757 758 759
			} else {
				/* vector goes into third byte of register */
				ivar = ivar & 0xFF00FFFF;
				ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
A
Alexander Duyck 已提交
760 761 762 763
			}
			array_wr32(E1000_IVAR0, index, ivar);
		}
		if (tx_queue > IGB_N0_QUEUE) {
764
			index = (tx_queue & 0x7);
A
Alexander Duyck 已提交
765
			ivar = array_rd32(E1000_IVAR0, index);
766
			if (tx_queue < 8) {
767 768 769
				/* vector goes into second byte of register */
				ivar = ivar & 0xFFFF00FF;
				ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
770 771 772 773
			} else {
				/* vector goes into high byte of register */
				ivar = ivar & 0x00FFFFFF;
				ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
A
Alexander Duyck 已提交
774 775 776
			}
			array_wr32(E1000_IVAR0, index, ivar);
		}
777
		q_vector->eims_value = 1 << msix_vector;
A
Alexander Duyck 已提交
778
		break;
779
	case e1000_82580:
780
	case e1000_i350:
781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812
		/* 82580 uses the same table-based approach as 82576 but has fewer
		   entries as a result we carry over for queues greater than 4. */
		if (rx_queue > IGB_N0_QUEUE) {
			index = (rx_queue >> 1);
			ivar = array_rd32(E1000_IVAR0, index);
			if (rx_queue & 0x1) {
				/* vector goes into third byte of register */
				ivar = ivar & 0xFF00FFFF;
				ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
			} else {
				/* vector goes into low byte of register */
				ivar = ivar & 0xFFFFFF00;
				ivar |= msix_vector | E1000_IVAR_VALID;
			}
			array_wr32(E1000_IVAR0, index, ivar);
		}
		if (tx_queue > IGB_N0_QUEUE) {
			index = (tx_queue >> 1);
			ivar = array_rd32(E1000_IVAR0, index);
			if (tx_queue & 0x1) {
				/* vector goes into high byte of register */
				ivar = ivar & 0x00FFFFFF;
				ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
			} else {
				/* vector goes into second byte of register */
				ivar = ivar & 0xFFFF00FF;
				ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
			}
			array_wr32(E1000_IVAR0, index, ivar);
		}
		q_vector->eims_value = 1 << msix_vector;
		break;
A
Alexander Duyck 已提交
813 814 815 816
	default:
		BUG();
		break;
	}
817 818 819 820 821 822

	/* add q_vector eims value to global eims_enable_mask */
	adapter->eims_enable_mask |= q_vector->eims_value;

	/* configure q_vector to set itr on first interrupt */
	q_vector->set_itr = 1;
823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839
}

/**
 * igb_configure_msix - Configure MSI-X hardware
 *
 * igb_configure_msix sets up the hardware to properly
 * generate MSI-X interrupts.
 **/
static void igb_configure_msix(struct igb_adapter *adapter)
{
	u32 tmp;
	int i, vector = 0;
	struct e1000_hw *hw = &adapter->hw;

	adapter->eims_enable_mask = 0;

	/* set vector for other causes, i.e. link changes */
A
Alexander Duyck 已提交
840 841
	switch (hw->mac.type) {
	case e1000_82575:
842 843 844 845 846 847 848 849 850
		tmp = rd32(E1000_CTRL_EXT);
		/* enable MSI-X PBA support*/
		tmp |= E1000_CTRL_EXT_PBA_CLR;

		/* Auto-Mask interrupts upon ICR read. */
		tmp |= E1000_CTRL_EXT_EIAME;
		tmp |= E1000_CTRL_EXT_IRCA;

		wr32(E1000_CTRL_EXT, tmp);
851 852 853 854

		/* enable msix_other interrupt */
		array_wr32(E1000_MSIXBM(0), vector++,
		                      E1000_EIMS_OTHER);
P
PJ Waskiewicz 已提交
855
		adapter->eims_other = E1000_EIMS_OTHER;
856

A
Alexander Duyck 已提交
857 858 859
		break;

	case e1000_82576:
860
	case e1000_82580:
861
	case e1000_i350:
862 863 864 865 866 867 868 869
		/* Turn on MSI-X capability first, or our settings
		 * won't stick.  And it will take days to debug. */
		wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
		                E1000_GPIE_PBA | E1000_GPIE_EIAME |
		                E1000_GPIE_NSICR);

		/* enable msix_other interrupt */
		adapter->eims_other = 1 << vector;
A
Alexander Duyck 已提交
870 871
		tmp = (vector++ | E1000_IVAR_VALID) << 8;

872
		wr32(E1000_IVAR_MISC, tmp);
A
Alexander Duyck 已提交
873 874 875 876 877
		break;
	default:
		/* do nothing, since nothing else supports MSI-X */
		break;
	} /* switch (hw->mac.type) */
878 879 880

	adapter->eims_enable_mask |= adapter->eims_other;

881 882
	for (i = 0; i < adapter->num_q_vectors; i++)
		igb_assign_vector(adapter->q_vector[i], vector++);
883

884 885 886 887 888 889 890 891 892 893 894 895
	wrfl();
}

/**
 * igb_request_msix - Initialize MSI-X interrupts
 *
 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 * kernel.
 **/
static int igb_request_msix(struct igb_adapter *adapter)
{
	struct net_device *netdev = adapter->netdev;
896
	struct e1000_hw *hw = &adapter->hw;
897 898
	int i, err = 0, vector = 0;

899
	err = request_irq(adapter->msix_entries[vector].vector,
900
	                  igb_msix_other, 0, netdev->name, adapter);
901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918
	if (err)
		goto out;
	vector++;

	for (i = 0; i < adapter->num_q_vectors; i++) {
		struct igb_q_vector *q_vector = adapter->q_vector[i];

		q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);

		if (q_vector->rx_ring && q_vector->tx_ring)
			sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
			        q_vector->rx_ring->queue_index);
		else if (q_vector->tx_ring)
			sprintf(q_vector->name, "%s-tx-%u", netdev->name,
			        q_vector->tx_ring->queue_index);
		else if (q_vector->rx_ring)
			sprintf(q_vector->name, "%s-rx-%u", netdev->name,
			        q_vector->rx_ring->queue_index);
919
		else
920 921
			sprintf(q_vector->name, "%s-unused", netdev->name);

922
		err = request_irq(adapter->msix_entries[vector].vector,
923
		                  igb_msix_ring, 0, q_vector->name,
924
		                  q_vector);
925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941
		if (err)
			goto out;
		vector++;
	}

	igb_configure_msix(adapter);
	return 0;
out:
	return err;
}

static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
{
	if (adapter->msix_entries) {
		pci_disable_msix(adapter->pdev);
		kfree(adapter->msix_entries);
		adapter->msix_entries = NULL;
942
	} else if (adapter->flags & IGB_FLAG_HAS_MSI) {
943
		pci_disable_msi(adapter->pdev);
944
	}
945 946
}

947 948 949 950 951 952 953 954 955 956 957 958 959 960 961
/**
 * igb_free_q_vectors - Free memory allocated for interrupt vectors
 * @adapter: board private structure to initialize
 *
 * This function frees the memory allocated to the q_vectors.  In addition if
 * NAPI is enabled it will delete any references to the NAPI struct prior
 * to freeing the q_vector.
 **/
static void igb_free_q_vectors(struct igb_adapter *adapter)
{
	int v_idx;

	for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
		struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
		adapter->q_vector[v_idx] = NULL;
962 963
		if (!q_vector)
			continue;
964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981
		netif_napi_del(&q_vector->napi);
		kfree(q_vector);
	}
	adapter->num_q_vectors = 0;
}

/**
 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
 *
 * This function resets the device so that it has 0 rx queues, tx queues, and
 * MSI-X interrupts allocated.
 */
static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
{
	igb_free_queues(adapter);
	igb_free_q_vectors(adapter);
	igb_reset_interrupt_capability(adapter);
}
982 983 984 985 986 987 988 989 990 991 992 993

/**
 * igb_set_interrupt_capability - set MSI or MSI-X if supported
 *
 * Attempt to configure interrupts using the best available
 * capabilities of the hardware and kernel.
 **/
static void igb_set_interrupt_capability(struct igb_adapter *adapter)
{
	int err;
	int numvecs, i;

994
	/* Number of supported queues. */
995
	adapter->num_rx_queues = adapter->rss_queues;
996 997 998 999
	if (adapter->vfs_allocated_count)
		adapter->num_tx_queues = 1;
	else
		adapter->num_tx_queues = adapter->rss_queues;
1000

1001 1002 1003
	/* start with one vector for every rx queue */
	numvecs = adapter->num_rx_queues;

D
Daniel Mack 已提交
1004
	/* if tx handler is separate add 1 for every tx queue */
1005 1006
	if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
		numvecs += adapter->num_tx_queues;
1007 1008 1009 1010 1011 1012

	/* store the number of vectors reserved for queues */
	adapter->num_q_vectors = numvecs;

	/* add 1 vector for link status interrupts */
	numvecs++;
1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024
	adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
					GFP_KERNEL);
	if (!adapter->msix_entries)
		goto msi_only;

	for (i = 0; i < numvecs; i++)
		adapter->msix_entries[i].entry = i;

	err = pci_enable_msix(adapter->pdev,
			      adapter->msix_entries,
			      numvecs);
	if (err == 0)
1025
		goto out;
1026 1027 1028 1029 1030

	igb_reset_interrupt_capability(adapter);

	/* If we can't do MSI-X, try MSI */
msi_only:
1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045
#ifdef CONFIG_PCI_IOV
	/* disable SR-IOV for non MSI-X configurations */
	if (adapter->vf_data) {
		struct e1000_hw *hw = &adapter->hw;
		/* disable iov and allow time for transactions to clear */
		pci_disable_sriov(adapter->pdev);
		msleep(500);

		kfree(adapter->vf_data);
		adapter->vf_data = NULL;
		wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
		msleep(100);
		dev_info(&adapter->pdev->dev, "IOV Disabled\n");
	}
#endif
1046
	adapter->vfs_allocated_count = 0;
1047
	adapter->rss_queues = 1;
1048
	adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1049
	adapter->num_rx_queues = 1;
1050
	adapter->num_tx_queues = 1;
1051
	adapter->num_q_vectors = 1;
1052
	if (!pci_enable_msi(adapter->pdev))
1053
		adapter->flags |= IGB_FLAG_HAS_MSI;
1054
out:
1055
	/* Notify the stack of the (possibly) reduced Tx Queue count. */
1056
	adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
1057 1058
}

1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084
/**
 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
 * @adapter: board private structure to initialize
 *
 * We allocate one q_vector per queue interrupt.  If allocation fails we
 * return -ENOMEM.
 **/
static int igb_alloc_q_vectors(struct igb_adapter *adapter)
{
	struct igb_q_vector *q_vector;
	struct e1000_hw *hw = &adapter->hw;
	int v_idx;

	for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
		q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
		if (!q_vector)
			goto err_out;
		q_vector->adapter = adapter;
		q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
		q_vector->itr_val = IGB_START_ITR;
		netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
		adapter->q_vector[v_idx] = q_vector;
	}
	return 0;

err_out:
1085
	igb_free_q_vectors(adapter);
1086 1087 1088 1089 1090 1091
	return -ENOMEM;
}

static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
                                      int ring_idx, int v_idx)
{
1092
	struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1093

1094
	q_vector->rx_ring = adapter->rx_ring[ring_idx];
1095
	q_vector->rx_ring->q_vector = q_vector;
1096 1097 1098
	q_vector->itr_val = adapter->rx_itr_setting;
	if (q_vector->itr_val && q_vector->itr_val <= 3)
		q_vector->itr_val = IGB_START_ITR;
1099 1100 1101 1102 1103
}

static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
                                      int ring_idx, int v_idx)
{
1104
	struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1105

1106
	q_vector->tx_ring = adapter->tx_ring[ring_idx];
1107
	q_vector->tx_ring->q_vector = q_vector;
1108 1109 1110
	q_vector->itr_val = adapter->tx_itr_setting;
	if (q_vector->itr_val && q_vector->itr_val <= 3)
		q_vector->itr_val = IGB_START_ITR;
1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185
}

/**
 * igb_map_ring_to_vector - maps allocated queues to vectors
 *
 * This function maps the recently allocated queues to vectors.
 **/
static int igb_map_ring_to_vector(struct igb_adapter *adapter)
{
	int i;
	int v_idx = 0;

	if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
	    (adapter->num_q_vectors < adapter->num_tx_queues))
		return -ENOMEM;

	if (adapter->num_q_vectors >=
	    (adapter->num_rx_queues + adapter->num_tx_queues)) {
		for (i = 0; i < adapter->num_rx_queues; i++)
			igb_map_rx_ring_to_vector(adapter, i, v_idx++);
		for (i = 0; i < adapter->num_tx_queues; i++)
			igb_map_tx_ring_to_vector(adapter, i, v_idx++);
	} else {
		for (i = 0; i < adapter->num_rx_queues; i++) {
			if (i < adapter->num_tx_queues)
				igb_map_tx_ring_to_vector(adapter, i, v_idx);
			igb_map_rx_ring_to_vector(adapter, i, v_idx++);
		}
		for (; i < adapter->num_tx_queues; i++)
			igb_map_tx_ring_to_vector(adapter, i, v_idx++);
	}
	return 0;
}

/**
 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
 *
 * This function initializes the interrupts and allocates all of the queues.
 **/
static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
{
	struct pci_dev *pdev = adapter->pdev;
	int err;

	igb_set_interrupt_capability(adapter);

	err = igb_alloc_q_vectors(adapter);
	if (err) {
		dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
		goto err_alloc_q_vectors;
	}

	err = igb_alloc_queues(adapter);
	if (err) {
		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
		goto err_alloc_queues;
	}

	err = igb_map_ring_to_vector(adapter);
	if (err) {
		dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
		goto err_map_queues;
	}


	return 0;
err_map_queues:
	igb_free_queues(adapter);
err_alloc_queues:
	igb_free_q_vectors(adapter);
err_alloc_q_vectors:
	igb_reset_interrupt_capability(adapter);
	return err;
}

1186 1187 1188 1189 1190 1191 1192 1193 1194
/**
 * igb_request_irq - initialize interrupts
 *
 * Attempts to configure interrupts using the best available
 * capabilities of the hardware and kernel.
 **/
static int igb_request_irq(struct igb_adapter *adapter)
{
	struct net_device *netdev = adapter->netdev;
1195
	struct pci_dev *pdev = adapter->pdev;
1196 1197 1198 1199
	int err = 0;

	if (adapter->msix_entries) {
		err = igb_request_msix(adapter);
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1200
		if (!err)
1201 1202
			goto request_done;
		/* fall back to MSI */
1203
		igb_clear_interrupt_scheme(adapter);
1204
		if (!pci_enable_msi(adapter->pdev))
1205
			adapter->flags |= IGB_FLAG_HAS_MSI;
1206 1207
		igb_free_all_tx_resources(adapter);
		igb_free_all_rx_resources(adapter);
1208
		adapter->num_tx_queues = 1;
1209
		adapter->num_rx_queues = 1;
1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225
		adapter->num_q_vectors = 1;
		err = igb_alloc_q_vectors(adapter);
		if (err) {
			dev_err(&pdev->dev,
			        "Unable to allocate memory for vectors\n");
			goto request_done;
		}
		err = igb_alloc_queues(adapter);
		if (err) {
			dev_err(&pdev->dev,
			        "Unable to allocate memory for queues\n");
			igb_free_q_vectors(adapter);
			goto request_done;
		}
		igb_setup_all_tx_resources(adapter);
		igb_setup_all_rx_resources(adapter);
P
PJ Waskiewicz 已提交
1226
	} else {
1227
		igb_assign_vector(adapter->q_vector[0], 0);
1228
	}
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PJ Waskiewicz 已提交
1229

1230
	if (adapter->flags & IGB_FLAG_HAS_MSI) {
1231
		err = request_irq(adapter->pdev->irq, igb_intr_msi, 0,
1232
				  netdev->name, adapter);
1233 1234
		if (!err)
			goto request_done;
1235

1236 1237
		/* fall back to legacy interrupts */
		igb_reset_interrupt_capability(adapter);
1238
		adapter->flags &= ~IGB_FLAG_HAS_MSI;
1239 1240
	}

1241
	err = request_irq(adapter->pdev->irq, igb_intr, IRQF_SHARED,
1242
			  netdev->name, adapter);
1243

A
Andy Gospodarek 已提交
1244
	if (err)
1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256
		dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
			err);

request_done:
	return err;
}

static void igb_free_irq(struct igb_adapter *adapter)
{
	if (adapter->msix_entries) {
		int vector = 0, i;

1257
		free_irq(adapter->msix_entries[vector++].vector, adapter);
1258

1259 1260 1261 1262 1263 1264 1265
		for (i = 0; i < adapter->num_q_vectors; i++) {
			struct igb_q_vector *q_vector = adapter->q_vector[i];
			free_irq(adapter->msix_entries[vector++].vector,
			         q_vector);
		}
	} else {
		free_irq(adapter->pdev->irq, adapter);
1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276
	}
}

/**
 * igb_irq_disable - Mask off interrupt generation on the NIC
 * @adapter: board private structure
 **/
static void igb_irq_disable(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;

1277 1278 1279 1280 1281
	/*
	 * we need to be careful when disabling interrupts.  The VFs are also
	 * mapped into these registers and so clearing the bits can cause
	 * issues on the VF drivers so we only need to clear what we set
	 */
1282
	if (adapter->msix_entries) {
1283 1284 1285 1286 1287
		u32 regval = rd32(E1000_EIAM);
		wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
		wr32(E1000_EIMC, adapter->eims_enable_mask);
		regval = rd32(E1000_EIAC);
		wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1288
	}
P
PJ Waskiewicz 已提交
1289 1290

	wr32(E1000_IAM, 0);
1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304
	wr32(E1000_IMC, ~0);
	wrfl();
	synchronize_irq(adapter->pdev->irq);
}

/**
 * igb_irq_enable - Enable default interrupt generation settings
 * @adapter: board private structure
 **/
static void igb_irq_enable(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;

	if (adapter->msix_entries) {
1305
		u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC;
1306 1307 1308 1309
		u32 regval = rd32(E1000_EIAC);
		wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
		regval = rd32(E1000_EIAM);
		wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
P
PJ Waskiewicz 已提交
1310
		wr32(E1000_EIMS, adapter->eims_enable_mask);
1311
		if (adapter->vfs_allocated_count) {
1312
			wr32(E1000_MBVFIMR, 0xFF);
1313 1314
			ims |= E1000_IMS_VMMB;
		}
1315 1316 1317
		if (adapter->hw.mac.type == e1000_82580)
			ims |= E1000_IMS_DRSTA;

1318
		wr32(E1000_IMS, ims);
P
PJ Waskiewicz 已提交
1319
	} else {
1320 1321 1322 1323
		wr32(E1000_IMS, IMS_ENABLE_MASK |
				E1000_IMS_DRSTA);
		wr32(E1000_IAM, IMS_ENABLE_MASK |
				E1000_IMS_DRSTA);
P
PJ Waskiewicz 已提交
1324
	}
1325 1326 1327 1328
}

static void igb_update_mng_vlan(struct igb_adapter *adapter)
{
1329
	struct e1000_hw *hw = &adapter->hw;
1330 1331
	u16 vid = adapter->hw.mng_cookie.vlan_id;
	u16 old_vid = adapter->mng_vlan_id;
1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345

	if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
		/* add VID to filter table */
		igb_vfta_set(hw, vid, true);
		adapter->mng_vlan_id = vid;
	} else {
		adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
	}

	if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
	    (vid != old_vid) &&
	    !vlan_group_get_device(adapter->vlgrp, old_vid)) {
		/* remove VID from filter table */
		igb_vfta_set(hw, old_vid, false);
1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398
	}
}

/**
 * igb_release_hw_control - release control of the h/w to f/w
 * @adapter: address of board private structure
 *
 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
 * For ASF and Pass Through versions of f/w this means that the
 * driver is no longer loaded.
 *
 **/
static void igb_release_hw_control(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 ctrl_ext;

	/* Let firmware take over control of h/w */
	ctrl_ext = rd32(E1000_CTRL_EXT);
	wr32(E1000_CTRL_EXT,
			ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
}

/**
 * igb_get_hw_control - get control of the h/w from f/w
 * @adapter: address of board private structure
 *
 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
 * For ASF and Pass Through versions of f/w this means that
 * the driver is loaded.
 *
 **/
static void igb_get_hw_control(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 ctrl_ext;

	/* Let firmware know the driver has taken over */
	ctrl_ext = rd32(E1000_CTRL_EXT);
	wr32(E1000_CTRL_EXT,
			ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
}

/**
 * igb_configure - configure the hardware for RX and TX
 * @adapter: private board structure
 **/
static void igb_configure(struct igb_adapter *adapter)
{
	struct net_device *netdev = adapter->netdev;
	int i;

	igb_get_hw_control(adapter);
1399
	igb_set_rx_mode(netdev);
1400 1401 1402

	igb_restore_vlan(adapter);

1403
	igb_setup_tctl(adapter);
1404
	igb_setup_mrqc(adapter);
1405
	igb_setup_rctl(adapter);
1406 1407

	igb_configure_tx(adapter);
1408
	igb_configure_rx(adapter);
1409 1410 1411

	igb_rx_fifo_flush_82575(&adapter->hw);

1412
	/* call igb_desc_unused which always leaves
1413 1414 1415
	 * at least 1 descriptor unused to make sure
	 * next_to_use != next_to_clean */
	for (i = 0; i < adapter->num_rx_queues; i++) {
1416
		struct igb_ring *ring = adapter->rx_ring[i];
1417
		igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
1418 1419 1420
	}
}

1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443
/**
 * igb_power_up_link - Power up the phy/serdes link
 * @adapter: address of board private structure
 **/
void igb_power_up_link(struct igb_adapter *adapter)
{
	if (adapter->hw.phy.media_type == e1000_media_type_copper)
		igb_power_up_phy_copper(&adapter->hw);
	else
		igb_power_up_serdes_link_82575(&adapter->hw);
}

/**
 * igb_power_down_link - Power down the phy/serdes link
 * @adapter: address of board private structure
 */
static void igb_power_down_link(struct igb_adapter *adapter)
{
	if (adapter->hw.phy.media_type == e1000_media_type_copper)
		igb_power_down_phy_copper_82575(&adapter->hw);
	else
		igb_shutdown_serdes_link_82575(&adapter->hw);
}
1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458

/**
 * igb_up - Open the interface and prepare it to handle traffic
 * @adapter: board private structure
 **/
int igb_up(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	int i;

	/* hardware has been reset, we need to reload some things */
	igb_configure(adapter);

	clear_bit(__IGB_DOWN, &adapter->state);

1459 1460 1461 1462
	for (i = 0; i < adapter->num_q_vectors; i++) {
		struct igb_q_vector *q_vector = adapter->q_vector[i];
		napi_enable(&q_vector->napi);
	}
P
PJ Waskiewicz 已提交
1463
	if (adapter->msix_entries)
1464
		igb_configure_msix(adapter);
1465 1466
	else
		igb_assign_vector(adapter->q_vector[0], 0);
1467 1468 1469 1470 1471

	/* Clear any pending interrupts. */
	rd32(E1000_ICR);
	igb_irq_enable(adapter);

1472 1473 1474 1475 1476 1477 1478
	/* notify VFs that reset has been completed */
	if (adapter->vfs_allocated_count) {
		u32 reg_data = rd32(E1000_CTRL_EXT);
		reg_data |= E1000_CTRL_EXT_PFRSTD;
		wr32(E1000_CTRL_EXT, reg_data);
	}

1479 1480
	netif_tx_start_all_queues(adapter->netdev);

1481 1482 1483 1484
	/* start the watchdog. */
	hw->mac.get_link_status = 1;
	schedule_work(&adapter->watchdog_task);

1485 1486 1487 1488 1489 1490
	return 0;
}

void igb_down(struct igb_adapter *adapter)
{
	struct net_device *netdev = adapter->netdev;
1491
	struct e1000_hw *hw = &adapter->hw;
1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503
	u32 tctl, rctl;
	int i;

	/* signal that we're down so the interrupt handler does not
	 * reschedule our watchdog timer */
	set_bit(__IGB_DOWN, &adapter->state);

	/* disable receives in the hardware */
	rctl = rd32(E1000_RCTL);
	wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
	/* flush and sleep below */

1504
	netif_tx_stop_all_queues(netdev);
1505 1506 1507 1508 1509 1510 1511 1512 1513

	/* disable transmits in the hardware */
	tctl = rd32(E1000_TCTL);
	tctl &= ~E1000_TCTL_EN;
	wr32(E1000_TCTL, tctl);
	/* flush both disables and wait for them to finish */
	wrfl();
	msleep(10);

1514 1515 1516 1517
	for (i = 0; i < adapter->num_q_vectors; i++) {
		struct igb_q_vector *q_vector = adapter->q_vector[i];
		napi_disable(&q_vector->napi);
	}
1518 1519 1520 1521 1522 1523 1524

	igb_irq_disable(adapter);

	del_timer_sync(&adapter->watchdog_timer);
	del_timer_sync(&adapter->phy_info_timer);

	netif_carrier_off(netdev);
1525 1526 1527 1528

	/* record the stats before reset*/
	igb_update_stats(adapter);

1529 1530 1531
	adapter->link_speed = 0;
	adapter->link_duplex = 0;

1532 1533
	if (!pci_channel_offline(adapter->pdev))
		igb_reset(adapter);
1534 1535
	igb_clean_all_tx_rings(adapter);
	igb_clean_all_rx_rings(adapter);
1536 1537 1538 1539 1540
#ifdef CONFIG_IGB_DCA

	/* since we reset the hardware DCA settings were cleared */
	igb_setup_dca(adapter);
#endif
1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554
}

void igb_reinit_locked(struct igb_adapter *adapter)
{
	WARN_ON(in_interrupt());
	while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
		msleep(1);
	igb_down(adapter);
	igb_up(adapter);
	clear_bit(__IGB_RESETTING, &adapter->state);
}

void igb_reset(struct igb_adapter *adapter)
{
1555
	struct pci_dev *pdev = adapter->pdev;
1556
	struct e1000_hw *hw = &adapter->hw;
A
Alexander Duyck 已提交
1557 1558
	struct e1000_mac_info *mac = &hw->mac;
	struct e1000_fc_info *fc = &hw->fc;
1559 1560 1561 1562 1563 1564
	u32 pba = 0, tx_space, min_tx_space, min_rx_space;
	u16 hwm;

	/* Repartition Pba for greater than 9k mtu
	 * To take effect CTRL.RST is required.
	 */
1565
	switch (mac->type) {
1566
	case e1000_i350:
1567 1568 1569 1570
	case e1000_82580:
		pba = rd32(E1000_RXPBS);
		pba = igb_rxpbs_adjust_82580(pba);
		break;
1571
	case e1000_82576:
1572 1573
		pba = rd32(E1000_RXPBS);
		pba &= E1000_RXPBS_SIZE_MASK_82576;
1574 1575 1576 1577 1578
		break;
	case e1000_82575:
	default:
		pba = E1000_PBA_34K;
		break;
A
Alexander Duyck 已提交
1579
	}
1580

A
Alexander Duyck 已提交
1581 1582
	if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
	    (mac->type < e1000_82576)) {
1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599
		/* adjust PBA for jumbo frames */
		wr32(E1000_PBA, pba);

		/* To maintain wire speed transmits, the Tx FIFO should be
		 * large enough to accommodate two full transmit packets,
		 * rounded up to the next 1KB and expressed in KB.  Likewise,
		 * the Rx FIFO should be large enough to accommodate at least
		 * one full receive packet and is similarly rounded up and
		 * expressed in KB. */
		pba = rd32(E1000_PBA);
		/* upper 16 bits has Tx packet buffer allocation size in KB */
		tx_space = pba >> 16;
		/* lower 16 bits has Rx packet buffer allocation size in KB */
		pba &= 0xffff;
		/* the tx fifo also stores 16 bytes of information about the tx
		 * but don't include ethernet FCS because hardware appends it */
		min_tx_space = (adapter->max_frame_size +
1600
				sizeof(union e1000_adv_tx_desc) -
1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620
				ETH_FCS_LEN) * 2;
		min_tx_space = ALIGN(min_tx_space, 1024);
		min_tx_space >>= 10;
		/* software strips receive CRC, so leave room for it */
		min_rx_space = adapter->max_frame_size;
		min_rx_space = ALIGN(min_rx_space, 1024);
		min_rx_space >>= 10;

		/* If current Tx allocation is less than the min Tx FIFO size,
		 * and the min Tx FIFO size is less than the current Rx FIFO
		 * allocation, take space away from current Rx allocation */
		if (tx_space < min_tx_space &&
		    ((min_tx_space - tx_space) < pba)) {
			pba = pba - (min_tx_space - tx_space);

			/* if short on rx space, rx wins and must trump tx
			 * adjustment */
			if (pba < min_rx_space)
				pba = min_rx_space;
		}
A
Alexander Duyck 已提交
1621
		wr32(E1000_PBA, pba);
1622 1623 1624 1625 1626 1627 1628 1629 1630
	}

	/* flow control settings */
	/* The high water mark must be low enough to fit one full frame
	 * (or the size used for early receive) above it in the Rx FIFO.
	 * Set it to the lower of:
	 * - 90% of the Rx FIFO size, or
	 * - the full Rx FIFO size minus one full frame */
	hwm = min(((pba << 10) * 9 / 10),
A
Alexander Duyck 已提交
1631
			((pba << 10) - 2 * adapter->max_frame_size));
1632

1633 1634
	fc->high_water = hwm & 0xFFF0;	/* 16-byte granularity */
	fc->low_water = fc->high_water - 16;
1635 1636
	fc->pause_time = 0xFFFF;
	fc->send_xon = 1;
1637
	fc->current_mode = fc->requested_mode;
1638

1639 1640 1641 1642
	/* disable receive for all VFs and wait one second */
	if (adapter->vfs_allocated_count) {
		int i;
		for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1643
			adapter->vf_data[i].flags = 0;
1644 1645

		/* ping all the active vfs to let them know we are going down */
1646
		igb_ping_all_vfs(adapter);
1647 1648 1649 1650 1651 1652

		/* disable transmits and receives */
		wr32(E1000_VFRE, 0);
		wr32(E1000_VFTE, 0);
	}

1653
	/* Allow time for pending master requests to run */
1654
	hw->mac.ops.reset_hw(hw);
1655 1656
	wr32(E1000_WUC, 0);

1657
	if (hw->mac.ops.init_hw(hw))
1658
		dev_err(&pdev->dev, "Hardware Error\n");
1659

1660 1661 1662 1663 1664
	if (hw->mac.type == e1000_82580) {
		u32 reg = rd32(E1000_PCIEMISC);
		wr32(E1000_PCIEMISC,
		                reg & ~E1000_PCIEMISC_LX_DECISION);
	}
1665 1666 1667
	if (!netif_running(adapter->netdev))
		igb_power_down_link(adapter);

1668 1669 1670 1671 1672
	igb_update_mng_vlan(adapter);

	/* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
	wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);

1673
	igb_get_phy_info(hw);
1674 1675
}

S
Stephen Hemminger 已提交
1676
static const struct net_device_ops igb_netdev_ops = {
1677
	.ndo_open		= igb_open,
S
Stephen Hemminger 已提交
1678
	.ndo_stop		= igb_close,
1679
	.ndo_start_xmit		= igb_xmit_frame_adv,
S
Stephen Hemminger 已提交
1680
	.ndo_get_stats		= igb_get_stats,
1681 1682
	.ndo_set_rx_mode	= igb_set_rx_mode,
	.ndo_set_multicast_list	= igb_set_rx_mode,
S
Stephen Hemminger 已提交
1683 1684 1685 1686 1687 1688 1689 1690
	.ndo_set_mac_address	= igb_set_mac,
	.ndo_change_mtu		= igb_change_mtu,
	.ndo_do_ioctl		= igb_ioctl,
	.ndo_tx_timeout		= igb_tx_timeout,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_vlan_rx_register	= igb_vlan_rx_register,
	.ndo_vlan_rx_add_vid	= igb_vlan_rx_add_vid,
	.ndo_vlan_rx_kill_vid	= igb_vlan_rx_kill_vid,
1691 1692 1693 1694
	.ndo_set_vf_mac		= igb_ndo_set_vf_mac,
	.ndo_set_vf_vlan	= igb_ndo_set_vf_vlan,
	.ndo_set_vf_tx_rate	= igb_ndo_set_vf_bw,
	.ndo_get_vf_config	= igb_ndo_get_vf_config,
S
Stephen Hemminger 已提交
1695 1696 1697 1698 1699
#ifdef CONFIG_NET_POLL_CONTROLLER
	.ndo_poll_controller	= igb_netpoll,
#endif
};

1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716
/**
 * igb_probe - Device Initialization Routine
 * @pdev: PCI device information struct
 * @ent: entry in igb_pci_tbl
 *
 * Returns 0 on success, negative on failure
 *
 * igb_probe initializes an adapter identified by a pci_dev structure.
 * The OS initialization, configuring of the adapter private structure,
 * and a hardware reset occur.
 **/
static int __devinit igb_probe(struct pci_dev *pdev,
			       const struct pci_device_id *ent)
{
	struct net_device *netdev;
	struct igb_adapter *adapter;
	struct e1000_hw *hw;
1717 1718
	u16 eeprom_data = 0;
	static int global_quad_port_a; /* global quad port a indication */
1719 1720
	const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
	unsigned long mmio_start, mmio_len;
1721
	int err, pci_using_dac;
1722 1723 1724
	u16 eeprom_apme_mask = IGB_EEPROM_APME;
	u32 part_num;

1725
	err = pci_enable_device_mem(pdev);
1726 1727 1728 1729
	if (err)
		return err;

	pci_using_dac = 0;
1730
	err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1731
	if (!err) {
1732
		err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1733 1734 1735
		if (!err)
			pci_using_dac = 1;
	} else {
1736
		err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1737
		if (err) {
1738
			err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1739 1740 1741 1742 1743 1744 1745 1746
			if (err) {
				dev_err(&pdev->dev, "No usable DMA "
					"configuration, aborting\n");
				goto err_dma;
			}
		}
	}

1747 1748 1749
	err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
	                                   IORESOURCE_MEM),
	                                   igb_driver_name);
1750 1751 1752
	if (err)
		goto err_pci_reg;

1753
	pci_enable_pcie_error_reporting(pdev);
1754

1755
	pci_set_master(pdev);
1756
	pci_save_state(pdev);
1757 1758

	err = -ENOMEM;
1759 1760
	netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
	                           IGB_ABS_MAX_TX_QUEUES);
1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777
	if (!netdev)
		goto err_alloc_etherdev;

	SET_NETDEV_DEV(netdev, &pdev->dev);

	pci_set_drvdata(pdev, netdev);
	adapter = netdev_priv(netdev);
	adapter->netdev = netdev;
	adapter->pdev = pdev;
	hw = &adapter->hw;
	hw->back = adapter;
	adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;

	mmio_start = pci_resource_start(pdev, 0);
	mmio_len = pci_resource_len(pdev, 0);

	err = -EIO;
1778 1779
	hw->hw_addr = ioremap(mmio_start, mmio_len);
	if (!hw->hw_addr)
1780 1781
		goto err_ioremap;

S
Stephen Hemminger 已提交
1782
	netdev->netdev_ops = &igb_netdev_ops;
1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804
	igb_set_ethtool_ops(netdev);
	netdev->watchdog_timeo = 5 * HZ;

	strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);

	netdev->mem_start = mmio_start;
	netdev->mem_end = mmio_start + mmio_len;

	/* PCI config space info */
	hw->vendor_id = pdev->vendor;
	hw->device_id = pdev->device;
	hw->revision_id = pdev->revision;
	hw->subsystem_vendor_id = pdev->subsystem_vendor;
	hw->subsystem_device_id = pdev->subsystem_device;

	/* Copy the default MAC, PHY and NVM function pointers */
	memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
	memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
	memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
	/* Initialize skew-specific constants */
	err = ei->get_invariants(hw);
	if (err)
1805
		goto err_sw_init;
1806

1807
	/* setup the private structure */
1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827
	err = igb_sw_init(adapter);
	if (err)
		goto err_sw_init;

	igb_get_bus_info_pcie(hw);

	hw->phy.autoneg_wait_to_complete = false;

	/* Copper options */
	if (hw->phy.media_type == e1000_media_type_copper) {
		hw->phy.mdix = AUTO_ALL_MODES;
		hw->phy.disable_polarity_correction = false;
		hw->phy.ms_type = e1000_ms_hw_default;
	}

	if (igb_check_reset_block(hw))
		dev_info(&pdev->dev,
			"PHY reset is blocked due to SOL/IDER session.\n");

	netdev->features = NETIF_F_SG |
1828
			   NETIF_F_IP_CSUM |
1829 1830 1831 1832
			   NETIF_F_HW_VLAN_TX |
			   NETIF_F_HW_VLAN_RX |
			   NETIF_F_HW_VLAN_FILTER;

1833
	netdev->features |= NETIF_F_IPV6_CSUM;
1834 1835
	netdev->features |= NETIF_F_TSO;
	netdev->features |= NETIF_F_TSO6;
H
Herbert Xu 已提交
1836
	netdev->features |= NETIF_F_GRO;
1837

1838 1839
	netdev->vlan_features |= NETIF_F_TSO;
	netdev->vlan_features |= NETIF_F_TSO6;
1840
	netdev->vlan_features |= NETIF_F_IP_CSUM;
1841
	netdev->vlan_features |= NETIF_F_IPV6_CSUM;
1842 1843
	netdev->vlan_features |= NETIF_F_SG;

1844 1845 1846
	if (pci_using_dac)
		netdev->features |= NETIF_F_HIGHDMA;

1847
	if (hw->mac.type >= e1000_82576)
1848 1849
		netdev->features |= NETIF_F_SCTP_CSUM;

1850
	adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875

	/* before reading the NVM, reset the controller to put the device in a
	 * known good starting state */
	hw->mac.ops.reset_hw(hw);

	/* make sure the NVM is good */
	if (igb_validate_nvm_checksum(hw) < 0) {
		dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
		err = -EIO;
		goto err_eeprom;
	}

	/* copy the MAC address out of the NVM */
	if (hw->mac.ops.read_mac_addr(hw))
		dev_err(&pdev->dev, "NVM Read Error\n");

	memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
	memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);

	if (!is_valid_ether_addr(netdev->perm_addr)) {
		dev_err(&pdev->dev, "Invalid MAC Address\n");
		err = -EIO;
		goto err_eeprom;
	}

1876 1877 1878 1879
	setup_timer(&adapter->watchdog_timer, &igb_watchdog,
	            (unsigned long) adapter);
	setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
	            (unsigned long) adapter);
1880 1881 1882 1883

	INIT_WORK(&adapter->reset_task, igb_reset_task);
	INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);

1884
	/* Initialize link properties that are user-changeable */
1885 1886 1887 1888
	adapter->fc_autoneg = true;
	hw->mac.autoneg = true;
	hw->phy.autoneg_advertised = 0x2f;

1889 1890
	hw->fc.requested_mode = e1000_fc_default;
	hw->fc.current_mode = e1000_fc_default;
1891 1892 1893 1894 1895 1896 1897

	igb_validate_mdi_setting(hw);

	/* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
	 * enable the ACPI Magic Packet filter
	 */

1898
	if (hw->bus.func == 0)
A
Alexander Duyck 已提交
1899
		hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1900 1901 1902 1903
	else if (hw->mac.type == e1000_82580)
		hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
		                 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
		                 &eeprom_data);
1904 1905
	else if (hw->bus.func == 1)
		hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917

	if (eeprom_data & eeprom_apme_mask)
		adapter->eeprom_wol |= E1000_WUFC_MAG;

	/* now that we have the eeprom settings, apply the special cases where
	 * the eeprom may be wrong or the board simply won't support wake on
	 * lan on a particular port */
	switch (pdev->device) {
	case E1000_DEV_ID_82575GB_QUAD_COPPER:
		adapter->eeprom_wol = 0;
		break;
	case E1000_DEV_ID_82575EB_FIBER_SERDES:
A
Alexander Duyck 已提交
1918 1919
	case E1000_DEV_ID_82576_FIBER:
	case E1000_DEV_ID_82576_SERDES:
1920 1921 1922 1923 1924
		/* Wake events only supported on port A for dual fiber
		 * regardless of eeprom setting */
		if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
			adapter->eeprom_wol = 0;
		break;
1925
	case E1000_DEV_ID_82576_QUAD_COPPER:
1926
	case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
1927 1928 1929 1930 1931 1932 1933 1934 1935
		/* if quad port adapter, disable WoL on all but port A */
		if (global_quad_port_a != 0)
			adapter->eeprom_wol = 0;
		else
			adapter->flags |= IGB_FLAG_QUAD_PORT_A;
		/* Reset for multiple quad port adapters */
		if (++global_quad_port_a == 4)
			global_quad_port_a = 0;
		break;
1936 1937 1938 1939
	}

	/* initialize the wol settings based on the eeprom settings */
	adapter->wol = adapter->eeprom_wol;
1940
	device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953

	/* reset the hardware with the new settings */
	igb_reset(adapter);

	/* let the f/w know that the h/w is now under the control of the
	 * driver. */
	igb_get_hw_control(adapter);

	strcpy(netdev->name, "eth%d");
	err = register_netdev(netdev);
	if (err)
		goto err_register;

1954 1955 1956
	/* carrier off reporting is important to ethtool even BEFORE open */
	netif_carrier_off(netdev);

1957
#ifdef CONFIG_IGB_DCA
1958
	if (dca_add_requester(&pdev->dev) == 0) {
1959
		adapter->flags |= IGB_FLAG_DCA_ENABLED;
J
Jeb Cramer 已提交
1960 1961 1962 1963
		dev_info(&pdev->dev, "DCA enabled\n");
		igb_setup_dca(adapter);
	}

P
Patrick Ohly 已提交
1964
#endif
1965 1966
	dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
	/* print bus type/speed/width info */
J
Johannes Berg 已提交
1967
	dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1968
		 netdev->name,
1969
		 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
1970
		  (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
1971
		                                            "unknown"),
1972 1973 1974 1975
		 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
		  (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
		  (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
		   "unknown"),
J
Johannes Berg 已提交
1976
		 netdev->dev_addr);
1977 1978 1979 1980 1981 1982 1983 1984

	igb_read_part_num(hw, &part_num);
	dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
		(part_num >> 8), (part_num & 0xff));

	dev_info(&pdev->dev,
		"Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
		adapter->msix_entries ? "MSI-X" :
1985
		(adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1986 1987 1988 1989 1990 1991 1992 1993
		adapter->num_rx_queues, adapter->num_tx_queues);

	return 0;

err_register:
	igb_release_hw_control(adapter);
err_eeprom:
	if (!igb_check_reset_block(hw))
1994
		igb_reset_phy(hw);
1995 1996 1997 1998

	if (hw->flash_address)
		iounmap(hw->flash_address);
err_sw_init:
1999
	igb_clear_interrupt_scheme(adapter);
2000 2001 2002 2003
	iounmap(hw->hw_addr);
err_ioremap:
	free_netdev(netdev);
err_alloc_etherdev:
2004 2005
	pci_release_selected_regions(pdev,
	                             pci_select_bars(pdev, IORESOURCE_MEM));
2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024
err_pci_reg:
err_dma:
	pci_disable_device(pdev);
	return err;
}

/**
 * igb_remove - Device Removal Routine
 * @pdev: PCI device information struct
 *
 * igb_remove is called by the PCI subsystem to alert the driver
 * that it should release a PCI device.  The could be caused by a
 * Hot-Plug event, or because the driver is going to be removed from
 * memory.
 **/
static void __devexit igb_remove(struct pci_dev *pdev)
{
	struct net_device *netdev = pci_get_drvdata(pdev);
	struct igb_adapter *adapter = netdev_priv(netdev);
J
Jeb Cramer 已提交
2025
	struct e1000_hw *hw = &adapter->hw;
2026 2027 2028 2029 2030 2031 2032 2033 2034

	/* flush_scheduled work may reschedule our watchdog task, so
	 * explicitly disable watchdog tasks from being rescheduled  */
	set_bit(__IGB_DOWN, &adapter->state);
	del_timer_sync(&adapter->watchdog_timer);
	del_timer_sync(&adapter->phy_info_timer);

	flush_scheduled_work();

2035
#ifdef CONFIG_IGB_DCA
2036
	if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
J
Jeb Cramer 已提交
2037 2038
		dev_info(&pdev->dev, "DCA disabled\n");
		dca_remove_requester(&pdev->dev);
2039
		adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
A
Alexander Duyck 已提交
2040
		wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
J
Jeb Cramer 已提交
2041 2042 2043
	}
#endif

2044 2045 2046 2047 2048 2049
	/* Release control of h/w to f/w.  If f/w is AMT enabled, this
	 * would have already happened in close and is redundant. */
	igb_release_hw_control(adapter);

	unregister_netdev(netdev);

2050
	igb_clear_interrupt_scheme(adapter);
2051

2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065
#ifdef CONFIG_PCI_IOV
	/* reclaim resources allocated to VFs */
	if (adapter->vf_data) {
		/* disable iov and allow time for transactions to clear */
		pci_disable_sriov(pdev);
		msleep(500);

		kfree(adapter->vf_data);
		adapter->vf_data = NULL;
		wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
		msleep(100);
		dev_info(&pdev->dev, "IOV Disabled\n");
	}
#endif
2066

2067 2068 2069
	iounmap(hw->hw_addr);
	if (hw->flash_address)
		iounmap(hw->flash_address);
2070 2071
	pci_release_selected_regions(pdev,
	                             pci_select_bars(pdev, IORESOURCE_MEM));
2072 2073 2074

	free_netdev(netdev);

2075
	pci_disable_pcie_error_reporting(pdev);
2076

2077 2078 2079
	pci_disable_device(pdev);
}

2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124
/**
 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
 * @adapter: board private structure to initialize
 *
 * This function initializes the vf specific data storage and then attempts to
 * allocate the VFs.  The reason for ordering it this way is because it is much
 * mor expensive time wise to disable SR-IOV than it is to allocate and free
 * the memory for the VFs.
 **/
static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
{
#ifdef CONFIG_PCI_IOV
	struct pci_dev *pdev = adapter->pdev;

	if (adapter->vfs_allocated_count) {
		adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
		                           sizeof(struct vf_data_storage),
		                           GFP_KERNEL);
		/* if allocation failed then we do not support SR-IOV */
		if (!adapter->vf_data) {
			adapter->vfs_allocated_count = 0;
			dev_err(&pdev->dev, "Unable to allocate memory for VF "
			        "Data Storage\n");
		}
	}

	if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) {
		kfree(adapter->vf_data);
		adapter->vf_data = NULL;
#endif /* CONFIG_PCI_IOV */
		adapter->vfs_allocated_count = 0;
#ifdef CONFIG_PCI_IOV
	} else {
		unsigned char mac_addr[ETH_ALEN];
		int i;
		dev_info(&pdev->dev, "%d vfs allocated\n",
		         adapter->vfs_allocated_count);
		for (i = 0; i < adapter->vfs_allocated_count; i++) {
			random_ether_addr(mac_addr);
			igb_set_vf_mac(adapter, i, mac_addr);
		}
	}
#endif /* CONFIG_PCI_IOV */
}

2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137

/**
 * igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp
 * @adapter: board private structure to initialize
 *
 * igb_init_hw_timer initializes the function pointer and values for the hw
 * timer found in hardware.
 **/
static void igb_init_hw_timer(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;

	switch (hw->mac.type) {
2138
	case e1000_i350:
2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180
	case e1000_82580:
		memset(&adapter->cycles, 0, sizeof(adapter->cycles));
		adapter->cycles.read = igb_read_clock;
		adapter->cycles.mask = CLOCKSOURCE_MASK(64);
		adapter->cycles.mult = 1;
		/*
		 * The 82580 timesync updates the system timer every 8ns by 8ns
		 * and the value cannot be shifted.  Instead we need to shift
		 * the registers to generate a 64bit timer value.  As a result
		 * SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by
		 * 24 in order to generate a larger value for synchronization.
		 */
		adapter->cycles.shift = IGB_82580_TSYNC_SHIFT;
		/* disable system timer temporarily by setting bit 31 */
		wr32(E1000_TSAUXC, 0x80000000);
		wrfl();

		/* Set registers so that rollover occurs soon to test this. */
		wr32(E1000_SYSTIMR, 0x00000000);
		wr32(E1000_SYSTIML, 0x80000000);
		wr32(E1000_SYSTIMH, 0x000000FF);
		wrfl();

		/* enable system timer by clearing bit 31 */
		wr32(E1000_TSAUXC, 0x0);
		wrfl();

		timecounter_init(&adapter->clock,
				 &adapter->cycles,
				 ktime_to_ns(ktime_get_real()));
		/*
		 * Synchronize our NIC clock against system wall clock. NIC
		 * time stamp reading requires ~3us per sample, each sample
		 * was pretty stable even under load => only require 10
		 * samples for each offset comparison.
		 */
		memset(&adapter->compare, 0, sizeof(adapter->compare));
		adapter->compare.source = &adapter->clock;
		adapter->compare.target = ktime_get_real;
		adapter->compare.num_samples = 10;
		timecompare_update(&adapter->compare, 0);
		break;
2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231
	case e1000_82576:
		/*
		 * Initialize hardware timer: we keep it running just in case
		 * that some program needs it later on.
		 */
		memset(&adapter->cycles, 0, sizeof(adapter->cycles));
		adapter->cycles.read = igb_read_clock;
		adapter->cycles.mask = CLOCKSOURCE_MASK(64);
		adapter->cycles.mult = 1;
		/**
		 * Scale the NIC clock cycle by a large factor so that
		 * relatively small clock corrections can be added or
		 * substracted at each clock tick. The drawbacks of a large
		 * factor are a) that the clock register overflows more quickly
		 * (not such a big deal) and b) that the increment per tick has
		 * to fit into 24 bits.  As a result we need to use a shift of
		 * 19 so we can fit a value of 16 into the TIMINCA register.
		 */
		adapter->cycles.shift = IGB_82576_TSYNC_SHIFT;
		wr32(E1000_TIMINCA,
		                (1 << E1000_TIMINCA_16NS_SHIFT) |
		                (16 << IGB_82576_TSYNC_SHIFT));

		/* Set registers so that rollover occurs soon to test this. */
		wr32(E1000_SYSTIML, 0x00000000);
		wr32(E1000_SYSTIMH, 0xFF800000);
		wrfl();

		timecounter_init(&adapter->clock,
				 &adapter->cycles,
				 ktime_to_ns(ktime_get_real()));
		/*
		 * Synchronize our NIC clock against system wall clock. NIC
		 * time stamp reading requires ~3us per sample, each sample
		 * was pretty stable even under load => only require 10
		 * samples for each offset comparison.
		 */
		memset(&adapter->compare, 0, sizeof(adapter->compare));
		adapter->compare.source = &adapter->clock;
		adapter->compare.target = ktime_get_real;
		adapter->compare.num_samples = 10;
		timecompare_update(&adapter->compare, 0);
		break;
	case e1000_82575:
		/* 82575 does not support timesync */
	default:
		break;
	}

}

2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247
/**
 * igb_sw_init - Initialize general software structures (struct igb_adapter)
 * @adapter: board private structure to initialize
 *
 * igb_sw_init initializes the Adapter private data structure.
 * Fields are initialized based on PCI device information and
 * OS network device settings (MTU size).
 **/
static int __devinit igb_sw_init(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	struct net_device *netdev = adapter->netdev;
	struct pci_dev *pdev = adapter->pdev;

	pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);

2248 2249
	adapter->tx_ring_count = IGB_DEFAULT_TXD;
	adapter->rx_ring_count = IGB_DEFAULT_RXD;
2250 2251 2252
	adapter->rx_itr_setting = IGB_DEFAULT_ITR;
	adapter->tx_itr_setting = IGB_DEFAULT_ITR;

2253 2254 2255
	adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
	adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;

2256 2257
#ifdef CONFIG_PCI_IOV
	if (hw->mac.type == e1000_82576)
2258
		adapter->vfs_allocated_count = (max_vfs > 7) ? 7 : max_vfs;
2259 2260

#endif /* CONFIG_PCI_IOV */
2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271
	adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());

	/*
	 * if rss_queues > 4 or vfs are going to be allocated with rss_queues
	 * then we should combine the queues into a queue pair in order to
	 * conserve interrupts due to limited supply
	 */
	if ((adapter->rss_queues > 4) ||
	    ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6)))
		adapter->flags |= IGB_FLAG_QUEUE_PAIRS;

2272
	/* This call may decrease the number of queues */
2273
	if (igb_init_interrupt_scheme(adapter)) {
2274 2275 2276 2277
		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
		return -ENOMEM;
	}

2278
	igb_init_hw_timer(adapter);
2279 2280
	igb_probe_vfs(adapter);

2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310
	/* Explicitly disable IRQ since the NIC can be in any state. */
	igb_irq_disable(adapter);

	set_bit(__IGB_DOWN, &adapter->state);
	return 0;
}

/**
 * igb_open - Called when a network interface is made active
 * @netdev: network interface device structure
 *
 * Returns 0 on success, negative value on failure
 *
 * The open entry point is called when a network interface is made
 * active by the system (IFF_UP).  At this point all resources needed
 * for transmit and receive operations are allocated, the interrupt
 * handler is registered with the OS, the watchdog timer is started,
 * and the stack is notified that the interface is ready.
 **/
static int igb_open(struct net_device *netdev)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
	int err;
	int i;

	/* disallow open during test */
	if (test_bit(__IGB_TESTING, &adapter->state))
		return -EBUSY;

2311 2312
	netif_carrier_off(netdev);

2313 2314 2315 2316 2317 2318 2319 2320 2321 2322
	/* allocate transmit descriptors */
	err = igb_setup_all_tx_resources(adapter);
	if (err)
		goto err_setup_tx;

	/* allocate receive descriptors */
	err = igb_setup_all_rx_resources(adapter);
	if (err)
		goto err_setup_rx;

2323
	igb_power_up_link(adapter);
2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337

	/* before we allocate an interrupt, we must be ready to handle it.
	 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
	 * as soon as we call pci_request_irq, so we have to setup our
	 * clean_rx handler before we do so.  */
	igb_configure(adapter);

	err = igb_request_irq(adapter);
	if (err)
		goto err_req_irq;

	/* From here on the code is the same as igb_up() */
	clear_bit(__IGB_DOWN, &adapter->state);

2338 2339 2340 2341
	for (i = 0; i < adapter->num_q_vectors; i++) {
		struct igb_q_vector *q_vector = adapter->q_vector[i];
		napi_enable(&q_vector->napi);
	}
2342 2343 2344

	/* Clear any pending interrupts. */
	rd32(E1000_ICR);
P
PJ Waskiewicz 已提交
2345 2346 2347

	igb_irq_enable(adapter);

2348 2349 2350 2351 2352 2353 2354
	/* notify VFs that reset has been completed */
	if (adapter->vfs_allocated_count) {
		u32 reg_data = rd32(E1000_CTRL_EXT);
		reg_data |= E1000_CTRL_EXT_PFRSTD;
		wr32(E1000_CTRL_EXT, reg_data);
	}

2355 2356
	netif_tx_start_all_queues(netdev);

2357 2358 2359
	/* start the watchdog. */
	hw->mac.get_link_status = 1;
	schedule_work(&adapter->watchdog_task);
2360 2361 2362 2363 2364

	return 0;

err_req_irq:
	igb_release_hw_control(adapter);
2365
	igb_power_down_link(adapter);
2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406
	igb_free_all_rx_resources(adapter);
err_setup_rx:
	igb_free_all_tx_resources(adapter);
err_setup_tx:
	igb_reset(adapter);

	return err;
}

/**
 * igb_close - Disables a network interface
 * @netdev: network interface device structure
 *
 * Returns 0, this is not allowed to fail
 *
 * The close entry point is called when an interface is de-activated
 * by the OS.  The hardware is still under the driver's control, but
 * needs to be disabled.  A global MAC reset is issued to stop the
 * hardware, and all transmit and receive resources are freed.
 **/
static int igb_close(struct net_device *netdev)
{
	struct igb_adapter *adapter = netdev_priv(netdev);

	WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
	igb_down(adapter);

	igb_free_irq(adapter);

	igb_free_all_tx_resources(adapter);
	igb_free_all_rx_resources(adapter);

	return 0;
}

/**
 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
 * @tx_ring: tx descriptor ring (for a specific queue) to setup
 *
 * Return 0 on success, negative on failure
 **/
2407
int igb_setup_tx_resources(struct igb_ring *tx_ring)
2408
{
2409
	struct device *dev = tx_ring->dev;
2410 2411 2412 2413 2414 2415 2416 2417 2418
	int size;

	size = sizeof(struct igb_buffer) * tx_ring->count;
	tx_ring->buffer_info = vmalloc(size);
	if (!tx_ring->buffer_info)
		goto err;
	memset(tx_ring->buffer_info, 0, size);

	/* round up to nearest 4K */
2419
	tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
2420 2421
	tx_ring->size = ALIGN(tx_ring->size, 4096);

2422 2423 2424 2425
	tx_ring->desc = dma_alloc_coherent(dev,
					   tx_ring->size,
					   &tx_ring->dma,
					   GFP_KERNEL);
2426 2427 2428 2429 2430 2431 2432 2433 2434 2435

	if (!tx_ring->desc)
		goto err;

	tx_ring->next_to_use = 0;
	tx_ring->next_to_clean = 0;
	return 0;

err:
	vfree(tx_ring->buffer_info);
2436
	dev_err(dev,
2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449
		"Unable to allocate memory for the transmit descriptor ring\n");
	return -ENOMEM;
}

/**
 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
 *				  (Descriptors) for all queues
 * @adapter: board private structure
 *
 * Return 0 on success, negative on failure
 **/
static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
{
2450
	struct pci_dev *pdev = adapter->pdev;
2451 2452 2453
	int i, err = 0;

	for (i = 0; i < adapter->num_tx_queues; i++) {
2454
		err = igb_setup_tx_resources(adapter->tx_ring[i]);
2455
		if (err) {
2456
			dev_err(&pdev->dev,
2457 2458
				"Allocation for Tx Queue %u failed\n", i);
			for (i--; i >= 0; i--)
2459
				igb_free_tx_resources(adapter->tx_ring[i]);
2460 2461 2462 2463
			break;
		}
	}

2464
	for (i = 0; i < IGB_ABS_MAX_TX_QUEUES; i++) {
2465
		int r_idx = i % adapter->num_tx_queues;
2466
		adapter->multi_tx_table[i] = adapter->tx_ring[r_idx];
2467
	}
2468 2469 2470 2471
	return err;
}

/**
2472 2473
 * igb_setup_tctl - configure the transmit control registers
 * @adapter: Board private structure
2474
 **/
2475
void igb_setup_tctl(struct igb_adapter *adapter)
2476 2477 2478 2479
{
	struct e1000_hw *hw = &adapter->hw;
	u32 tctl;

2480 2481
	/* disable queue 0 which is enabled by default on 82575 and 82576 */
	wr32(E1000_TXDCTL(0), 0);
2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496

	/* Program the Transmit Control Register */
	tctl = rd32(E1000_TCTL);
	tctl &= ~E1000_TCTL_CT;
	tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
		(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);

	igb_config_collision_dist(hw);

	/* Enable transmits */
	tctl |= E1000_TCTL_EN;

	wr32(E1000_TCTL, tctl);
}

2497 2498 2499 2500 2501 2502 2503
/**
 * igb_configure_tx_ring - Configure transmit ring after Reset
 * @adapter: board private structure
 * @ring: tx ring to configure
 *
 * Configure a transmit ring after a reset.
 **/
2504 2505
void igb_configure_tx_ring(struct igb_adapter *adapter,
                           struct igb_ring *ring)
2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524
{
	struct e1000_hw *hw = &adapter->hw;
	u32 txdctl;
	u64 tdba = ring->dma;
	int reg_idx = ring->reg_idx;

	/* disable the queue */
	txdctl = rd32(E1000_TXDCTL(reg_idx));
	wr32(E1000_TXDCTL(reg_idx),
	                txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
	wrfl();
	mdelay(10);

	wr32(E1000_TDLEN(reg_idx),
	                ring->count * sizeof(union e1000_adv_tx_desc));
	wr32(E1000_TDBAL(reg_idx),
	                tdba & 0x00000000ffffffffULL);
	wr32(E1000_TDBAH(reg_idx), tdba >> 32);

2525 2526 2527 2528
	ring->head = hw->hw_addr + E1000_TDH(reg_idx);
	ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
	writel(0, ring->head);
	writel(0, ring->tail);
2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548

	txdctl |= IGB_TX_PTHRESH;
	txdctl |= IGB_TX_HTHRESH << 8;
	txdctl |= IGB_TX_WTHRESH << 16;

	txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
	wr32(E1000_TXDCTL(reg_idx), txdctl);
}

/**
 * igb_configure_tx - Configure transmit Unit after Reset
 * @adapter: board private structure
 *
 * Configure the Tx unit of the MAC after a reset.
 **/
static void igb_configure_tx(struct igb_adapter *adapter)
{
	int i;

	for (i = 0; i < adapter->num_tx_queues; i++)
2549
		igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
2550 2551
}

2552 2553 2554 2555 2556 2557
/**
 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
 * @rx_ring:    rx descriptor ring (for a specific queue) to setup
 *
 * Returns 0 on success, negative on failure
 **/
2558
int igb_setup_rx_resources(struct igb_ring *rx_ring)
2559
{
2560
	struct device *dev = rx_ring->dev;
2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574
	int size, desc_len;

	size = sizeof(struct igb_buffer) * rx_ring->count;
	rx_ring->buffer_info = vmalloc(size);
	if (!rx_ring->buffer_info)
		goto err;
	memset(rx_ring->buffer_info, 0, size);

	desc_len = sizeof(union e1000_adv_rx_desc);

	/* Round up to nearest 4K */
	rx_ring->size = rx_ring->count * desc_len;
	rx_ring->size = ALIGN(rx_ring->size, 4096);

2575 2576 2577 2578
	rx_ring->desc = dma_alloc_coherent(dev,
					   rx_ring->size,
					   &rx_ring->dma,
					   GFP_KERNEL);
2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589

	if (!rx_ring->desc)
		goto err;

	rx_ring->next_to_clean = 0;
	rx_ring->next_to_use = 0;

	return 0;

err:
	vfree(rx_ring->buffer_info);
2590
	rx_ring->buffer_info = NULL;
2591 2592
	dev_err(dev, "Unable to allocate memory for the receive descriptor"
		" ring\n");
2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604
	return -ENOMEM;
}

/**
 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
 *				  (Descriptors) for all queues
 * @adapter: board private structure
 *
 * Return 0 on success, negative on failure
 **/
static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
{
2605
	struct pci_dev *pdev = adapter->pdev;
2606 2607 2608
	int i, err = 0;

	for (i = 0; i < adapter->num_rx_queues; i++) {
2609
		err = igb_setup_rx_resources(adapter->rx_ring[i]);
2610
		if (err) {
2611
			dev_err(&pdev->dev,
2612 2613
				"Allocation for Rx Queue %u failed\n", i);
			for (i--; i >= 0; i--)
2614
				igb_free_rx_resources(adapter->rx_ring[i]);
2615 2616 2617 2618 2619 2620 2621
			break;
		}
	}

	return err;
}

2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649
/**
 * igb_setup_mrqc - configure the multiple receive queue control registers
 * @adapter: Board private structure
 **/
static void igb_setup_mrqc(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 mrqc, rxcsum;
	u32 j, num_rx_queues, shift = 0, shift2 = 0;
	union e1000_reta {
		u32 dword;
		u8  bytes[4];
	} reta;
	static const u8 rsshash[40] = {
		0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67,
		0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb,
		0xae, 0x7b, 0x30, 0xb4,	0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30,
		0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa };

	/* Fill out hash function seeds */
	for (j = 0; j < 10; j++) {
		u32 rsskey = rsshash[(j * 4)];
		rsskey |= rsshash[(j * 4) + 1] << 8;
		rsskey |= rsshash[(j * 4) + 2] << 16;
		rsskey |= rsshash[(j * 4) + 3] << 24;
		array_wr32(E1000_RSSRK(0), j, rsskey);
	}

2650
	num_rx_queues = adapter->rss_queues;
2651 2652 2653 2654

	if (adapter->vfs_allocated_count) {
		/* 82575 and 82576 supports 2 RSS queues for VMDq */
		switch (hw->mac.type) {
2655
		case e1000_i350:
2656 2657 2658 2659
		case e1000_82580:
			num_rx_queues = 1;
			shift = 0;
			break;
2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710
		case e1000_82576:
			shift = 3;
			num_rx_queues = 2;
			break;
		case e1000_82575:
			shift = 2;
			shift2 = 6;
		default:
			break;
		}
	} else {
		if (hw->mac.type == e1000_82575)
			shift = 6;
	}

	for (j = 0; j < (32 * 4); j++) {
		reta.bytes[j & 3] = (j % num_rx_queues) << shift;
		if (shift2)
			reta.bytes[j & 3] |= num_rx_queues << shift2;
		if ((j & 3) == 3)
			wr32(E1000_RETA(j >> 2), reta.dword);
	}

	/*
	 * Disable raw packet checksumming so that RSS hash is placed in
	 * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
	 * offloads as they are enabled by default
	 */
	rxcsum = rd32(E1000_RXCSUM);
	rxcsum |= E1000_RXCSUM_PCSD;

	if (adapter->hw.mac.type >= e1000_82576)
		/* Enable Receive Checksum Offload for SCTP */
		rxcsum |= E1000_RXCSUM_CRCOFL;

	/* Don't need to set TUOFL or IPOFL, they default to 1 */
	wr32(E1000_RXCSUM, rxcsum);

	/* If VMDq is enabled then we set the appropriate mode for that, else
	 * we default to RSS so that an RSS hash is calculated per packet even
	 * if we are only using one queue */
	if (adapter->vfs_allocated_count) {
		if (hw->mac.type > e1000_82575) {
			/* Set the default pool for the PF's first queue */
			u32 vtctl = rd32(E1000_VT_CTL);
			vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
				   E1000_VT_CTL_DISABLE_DEF_POOL);
			vtctl |= adapter->vfs_allocated_count <<
				E1000_VT_CTL_DEFAULT_POOL_SHIFT;
			wr32(E1000_VT_CTL, vtctl);
		}
2711
		if (adapter->rss_queues > 1)
2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731
			mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
		else
			mrqc = E1000_MRQC_ENABLE_VMDQ;
	} else {
		mrqc = E1000_MRQC_ENABLE_RSS_4Q;
	}
	igb_vmm_control(adapter);

	mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
		 E1000_MRQC_RSS_FIELD_IPV4_TCP);
	mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
		 E1000_MRQC_RSS_FIELD_IPV6_TCP);
	mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
		 E1000_MRQC_RSS_FIELD_IPV6_UDP);
	mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
		 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);

	wr32(E1000_MRQC, mrqc);
}

2732 2733 2734 2735
/**
 * igb_setup_rctl - configure the receive control registers
 * @adapter: Board private structure
 **/
2736
void igb_setup_rctl(struct igb_adapter *adapter)
2737 2738 2739 2740 2741 2742 2743
{
	struct e1000_hw *hw = &adapter->hw;
	u32 rctl;

	rctl = rd32(E1000_RCTL);

	rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2744
	rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2745

2746
	rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2747
		(hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2748

2749 2750 2751 2752
	/*
	 * enable stripping of CRC. It's unlikely this will break BMC
	 * redirection as it did with e1000. Newer features require
	 * that the HW strips the CRC.
2753
	 */
2754
	rctl |= E1000_RCTL_SECRC;
2755

2756
	/* disable store bad packets and clear size bits. */
2757
	rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2758

A
Alexander Duyck 已提交
2759 2760
	/* enable LPE to prevent packets larger than max_frame_size */
	rctl |= E1000_RCTL_LPE;
2761

2762 2763
	/* disable queue 0 to prevent tail write w/o re-config */
	wr32(E1000_RXDCTL(0), 0);
2764

2765 2766 2767 2768 2769 2770 2771 2772 2773
	/* Attention!!!  For SR-IOV PF driver operations you must enable
	 * queue drop for all VF and PF queues to prevent head of line blocking
	 * if an un-trusted VF does not provide descriptors to hardware.
	 */
	if (adapter->vfs_allocated_count) {
		/* set all queue drop enable bits */
		wr32(E1000_QDE, ALL_QUEUES);
	}

2774 2775 2776
	wr32(E1000_RCTL, rctl);
}

2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796
static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
                                   int vfn)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 vmolr;

	/* if it isn't the PF check to see if VFs are enabled and
	 * increase the size to support vlan tags */
	if (vfn < adapter->vfs_allocated_count &&
	    adapter->vf_data[vfn].vlans_enabled)
		size += VLAN_TAG_SIZE;

	vmolr = rd32(E1000_VMOLR(vfn));
	vmolr &= ~E1000_VMOLR_RLPML_MASK;
	vmolr |= size | E1000_VMOLR_LPE;
	wr32(E1000_VMOLR(vfn), vmolr);

	return 0;
}

2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815
/**
 * igb_rlpml_set - set maximum receive packet size
 * @adapter: board private structure
 *
 * Configure maximum receivable packet size.
 **/
static void igb_rlpml_set(struct igb_adapter *adapter)
{
	u32 max_frame_size = adapter->max_frame_size;
	struct e1000_hw *hw = &adapter->hw;
	u16 pf_id = adapter->vfs_allocated_count;

	if (adapter->vlgrp)
		max_frame_size += VLAN_TAG_SIZE;

	/* if vfs are enabled we set RLPML to the largest possible request
	 * size and set the VMOLR RLPML to the size we need */
	if (pf_id) {
		igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2816
		max_frame_size = MAX_JUMBO_FRAME_SIZE;
2817 2818 2819 2820 2821
	}

	wr32(E1000_RLPML, max_frame_size);
}

2822 2823
static inline void igb_set_vmolr(struct igb_adapter *adapter,
				 int vfn, bool aupe)
2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835
{
	struct e1000_hw *hw = &adapter->hw;
	u32 vmolr;

	/*
	 * This register exists only on 82576 and newer so if we are older then
	 * we should exit and do nothing
	 */
	if (hw->mac.type < e1000_82576)
		return;

	vmolr = rd32(E1000_VMOLR(vfn));
2836 2837 2838 2839 2840
	vmolr |= E1000_VMOLR_STRVLAN;      /* Strip vlan tags */
	if (aupe)
		vmolr |= E1000_VMOLR_AUPE;        /* Accept untagged packets */
	else
		vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
2841 2842 2843 2844

	/* clear all bits that might not be set */
	vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);

2845
	if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856
		vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
	/*
	 * for VMDq only allow the VFs and pool 0 to accept broadcast and
	 * multicast packets
	 */
	if (vfn <= adapter->vfs_allocated_count)
		vmolr |= E1000_VMOLR_BAM;	   /* Accept broadcast */

	wr32(E1000_VMOLR(vfn), vmolr);
}

2857 2858 2859 2860 2861 2862 2863
/**
 * igb_configure_rx_ring - Configure a receive ring after Reset
 * @adapter: board private structure
 * @ring: receive ring to be configured
 *
 * Configure the Rx unit of the MAC after a reset.
 **/
2864 2865
void igb_configure_rx_ring(struct igb_adapter *adapter,
                           struct igb_ring *ring)
2866 2867 2868 2869
{
	struct e1000_hw *hw = &adapter->hw;
	u64 rdba = ring->dma;
	int reg_idx = ring->reg_idx;
2870
	u32 srrctl, rxdctl;
2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884

	/* disable the queue */
	rxdctl = rd32(E1000_RXDCTL(reg_idx));
	wr32(E1000_RXDCTL(reg_idx),
	                rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);

	/* Set DMA base address registers */
	wr32(E1000_RDBAL(reg_idx),
	     rdba & 0x00000000ffffffffULL);
	wr32(E1000_RDBAH(reg_idx), rdba >> 32);
	wr32(E1000_RDLEN(reg_idx),
	               ring->count * sizeof(union e1000_adv_rx_desc));

	/* initialize head and tail */
2885 2886 2887 2888
	ring->head = hw->hw_addr + E1000_RDH(reg_idx);
	ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
	writel(0, ring->head);
	writel(0, ring->tail);
2889

2890
	/* set descriptor configuration */
2891 2892
	if (ring->rx_buffer_len < IGB_RXBUFFER_1024) {
		srrctl = ALIGN(ring->rx_buffer_len, 64) <<
2893 2894 2895 2896 2897 2898 2899 2900 2901 2902
		         E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
		srrctl |= IGB_RXBUFFER_16384 >>
		          E1000_SRRCTL_BSIZEPKT_SHIFT;
#else
		srrctl |= (PAGE_SIZE / 2) >>
		          E1000_SRRCTL_BSIZEPKT_SHIFT;
#endif
		srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
	} else {
2903
		srrctl = ALIGN(ring->rx_buffer_len, 1024) >>
2904 2905 2906
		         E1000_SRRCTL_BSIZEPKT_SHIFT;
		srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
	}
N
Nick Nunley 已提交
2907 2908
	if (hw->mac.type == e1000_82580)
		srrctl |= E1000_SRRCTL_TIMESTAMP;
2909 2910 2911
	/* Only set Drop Enable if we are supporting multiple queues */
	if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
		srrctl |= E1000_SRRCTL_DROP_EN;
2912 2913 2914

	wr32(E1000_SRRCTL(reg_idx), srrctl);

2915
	/* set filtering for VMDQ pools */
2916
	igb_set_vmolr(adapter, reg_idx & 0x7, true);
2917

2918 2919 2920 2921 2922 2923 2924 2925 2926 2927
	/* enable receive descriptor fetching */
	rxdctl = rd32(E1000_RXDCTL(reg_idx));
	rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
	rxdctl &= 0xFFF00000;
	rxdctl |= IGB_RX_PTHRESH;
	rxdctl |= IGB_RX_HTHRESH << 8;
	rxdctl |= IGB_RX_WTHRESH << 16;
	wr32(E1000_RXDCTL(reg_idx), rxdctl);
}

2928 2929 2930 2931 2932 2933 2934 2935
/**
 * igb_configure_rx - Configure receive Unit after Reset
 * @adapter: board private structure
 *
 * Configure the Rx unit of the MAC after a reset.
 **/
static void igb_configure_rx(struct igb_adapter *adapter)
{
2936
	int i;
2937

2938 2939 2940
	/* set UTA to appropriate mode */
	igb_set_uta(adapter);

2941 2942 2943 2944
	/* set the correct pool for the PF default MAC address in entry 0 */
	igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
	                 adapter->vfs_allocated_count);

2945 2946 2947
	/* Setup the HW Rx Head and Tail Descriptor Pointers and
	 * the Base and Length of the Rx Descriptor Ring */
	for (i = 0; i < adapter->num_rx_queues; i++)
2948
		igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
2949 2950 2951 2952 2953 2954 2955 2956
}

/**
 * igb_free_tx_resources - Free Tx Resources per Queue
 * @tx_ring: Tx descriptor ring for a specific queue
 *
 * Free all transmit software resources
 **/
2957
void igb_free_tx_resources(struct igb_ring *tx_ring)
2958
{
2959
	igb_clean_tx_ring(tx_ring);
2960 2961 2962 2963

	vfree(tx_ring->buffer_info);
	tx_ring->buffer_info = NULL;

2964 2965 2966 2967
	/* if not set, then don't free */
	if (!tx_ring->desc)
		return;

2968 2969
	dma_free_coherent(tx_ring->dev, tx_ring->size,
			  tx_ring->desc, tx_ring->dma);
2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984

	tx_ring->desc = NULL;
}

/**
 * igb_free_all_tx_resources - Free Tx Resources for All Queues
 * @adapter: board private structure
 *
 * Free all transmit software resources
 **/
static void igb_free_all_tx_resources(struct igb_adapter *adapter)
{
	int i;

	for (i = 0; i < adapter->num_tx_queues; i++)
2985
		igb_free_tx_resources(adapter->tx_ring[i]);
2986 2987
}

2988 2989
void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring,
				    struct igb_buffer *buffer_info)
2990
{
2991 2992
	if (buffer_info->dma) {
		if (buffer_info->mapped_as_page)
2993
			dma_unmap_page(tx_ring->dev,
2994 2995
					buffer_info->dma,
					buffer_info->length,
2996
					DMA_TO_DEVICE);
2997
		else
2998
			dma_unmap_single(tx_ring->dev,
2999 3000
					buffer_info->dma,
					buffer_info->length,
3001
					DMA_TO_DEVICE);
3002 3003
		buffer_info->dma = 0;
	}
3004 3005 3006 3007 3008
	if (buffer_info->skb) {
		dev_kfree_skb_any(buffer_info->skb);
		buffer_info->skb = NULL;
	}
	buffer_info->time_stamp = 0;
3009 3010 3011
	buffer_info->length = 0;
	buffer_info->next_to_watch = 0;
	buffer_info->mapped_as_page = false;
3012 3013 3014 3015 3016 3017
}

/**
 * igb_clean_tx_ring - Free Tx Buffers
 * @tx_ring: ring to be cleaned
 **/
3018
static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029
{
	struct igb_buffer *buffer_info;
	unsigned long size;
	unsigned int i;

	if (!tx_ring->buffer_info)
		return;
	/* Free all the Tx ring sk_buffs */

	for (i = 0; i < tx_ring->count; i++) {
		buffer_info = &tx_ring->buffer_info[i];
3030
		igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051
	}

	size = sizeof(struct igb_buffer) * tx_ring->count;
	memset(tx_ring->buffer_info, 0, size);

	/* Zero out the descriptor ring */
	memset(tx_ring->desc, 0, tx_ring->size);

	tx_ring->next_to_use = 0;
	tx_ring->next_to_clean = 0;
}

/**
 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
 * @adapter: board private structure
 **/
static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
{
	int i;

	for (i = 0; i < adapter->num_tx_queues; i++)
3052
		igb_clean_tx_ring(adapter->tx_ring[i]);
3053 3054 3055 3056 3057 3058 3059 3060
}

/**
 * igb_free_rx_resources - Free Rx Resources
 * @rx_ring: ring to clean the resources from
 *
 * Free all receive software resources
 **/
3061
void igb_free_rx_resources(struct igb_ring *rx_ring)
3062
{
3063
	igb_clean_rx_ring(rx_ring);
3064 3065 3066 3067

	vfree(rx_ring->buffer_info);
	rx_ring->buffer_info = NULL;

3068 3069 3070 3071
	/* if not set, then don't free */
	if (!rx_ring->desc)
		return;

3072 3073
	dma_free_coherent(rx_ring->dev, rx_ring->size,
			  rx_ring->desc, rx_ring->dma);
3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088

	rx_ring->desc = NULL;
}

/**
 * igb_free_all_rx_resources - Free Rx Resources for All Queues
 * @adapter: board private structure
 *
 * Free all receive software resources
 **/
static void igb_free_all_rx_resources(struct igb_adapter *adapter)
{
	int i;

	for (i = 0; i < adapter->num_rx_queues; i++)
3089
		igb_free_rx_resources(adapter->rx_ring[i]);
3090 3091 3092 3093 3094 3095
}

/**
 * igb_clean_rx_ring - Free Rx Buffers per Queue
 * @rx_ring: ring to free buffers from
 **/
3096
static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3097 3098 3099 3100 3101 3102 3103
{
	struct igb_buffer *buffer_info;
	unsigned long size;
	unsigned int i;

	if (!rx_ring->buffer_info)
		return;
3104

3105 3106 3107 3108
	/* Free all the Rx ring sk_buffs */
	for (i = 0; i < rx_ring->count; i++) {
		buffer_info = &rx_ring->buffer_info[i];
		if (buffer_info->dma) {
3109
			dma_unmap_single(rx_ring->dev,
3110
			                 buffer_info->dma,
3111
					 rx_ring->rx_buffer_len,
3112
					 DMA_FROM_DEVICE);
3113 3114 3115 3116 3117 3118 3119
			buffer_info->dma = 0;
		}

		if (buffer_info->skb) {
			dev_kfree_skb(buffer_info->skb);
			buffer_info->skb = NULL;
		}
A
Alexander Duyck 已提交
3120
		if (buffer_info->page_dma) {
3121
			dma_unmap_page(rx_ring->dev,
3122
			               buffer_info->page_dma,
A
Alexander Duyck 已提交
3123
				       PAGE_SIZE / 2,
3124
				       DMA_FROM_DEVICE);
A
Alexander Duyck 已提交
3125 3126
			buffer_info->page_dma = 0;
		}
3127 3128 3129
		if (buffer_info->page) {
			put_page(buffer_info->page);
			buffer_info->page = NULL;
3130
			buffer_info->page_offset = 0;
3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152
		}
	}

	size = sizeof(struct igb_buffer) * rx_ring->count;
	memset(rx_ring->buffer_info, 0, size);

	/* Zero out the descriptor ring */
	memset(rx_ring->desc, 0, rx_ring->size);

	rx_ring->next_to_clean = 0;
	rx_ring->next_to_use = 0;
}

/**
 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
 * @adapter: board private structure
 **/
static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
{
	int i;

	for (i = 0; i < adapter->num_rx_queues; i++)
3153
		igb_clean_rx_ring(adapter->rx_ring[i]);
3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165
}

/**
 * igb_set_mac - Change the Ethernet Address of the NIC
 * @netdev: network interface device structure
 * @p: pointer to an address structure
 *
 * Returns 0 on success, negative on failure
 **/
static int igb_set_mac(struct net_device *netdev, void *p)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
3166
	struct e1000_hw *hw = &adapter->hw;
3167 3168 3169 3170 3171 3172
	struct sockaddr *addr = p;

	if (!is_valid_ether_addr(addr->sa_data))
		return -EADDRNOTAVAIL;

	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3173
	memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3174

3175 3176 3177
	/* set the correct pool for the new PF MAC address in entry 0 */
	igb_rar_set_qsel(adapter, hw->mac.addr, 0,
	                 adapter->vfs_allocated_count);
3178

3179 3180 3181 3182
	return 0;
}

/**
3183
 * igb_write_mc_addr_list - write multicast addresses to MTA
3184 3185
 * @netdev: network interface device structure
 *
3186 3187 3188 3189
 * Writes multicast address list to the MTA hash table.
 * Returns: -ENOMEM on failure
 *                0 on no addresses written
 *                X on writing X addresses to MTA
3190
 **/
3191
static int igb_write_mc_addr_list(struct net_device *netdev)
3192 3193 3194
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
3195
	struct netdev_hw_addr *ha;
3196
	u8  *mta_list;
3197 3198
	int i;

3199
	if (netdev_mc_empty(netdev)) {
3200 3201 3202 3203 3204
		/* nothing to program, so clear mc list */
		igb_update_mc_addr_list(hw, NULL, 0);
		igb_restore_vf_multicasts(adapter);
		return 0;
	}
3205

3206
	mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3207 3208
	if (!mta_list)
		return -ENOMEM;
3209

3210
	/* The shared function expects a packed array of only addresses. */
3211
	i = 0;
3212 3213
	netdev_for_each_mc_addr(ha, netdev)
		memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3214 3215 3216 3217

	igb_update_mc_addr_list(hw, mta_list, i);
	kfree(mta_list);

3218
	return netdev_mc_count(netdev);
3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238
}

/**
 * igb_write_uc_addr_list - write unicast addresses to RAR table
 * @netdev: network interface device structure
 *
 * Writes unicast address list to the RAR table.
 * Returns: -ENOMEM on failure/insufficient address space
 *                0 on no addresses written
 *                X on writing X addresses to the RAR table
 **/
static int igb_write_uc_addr_list(struct net_device *netdev)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
	unsigned int vfn = adapter->vfs_allocated_count;
	unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
	int count = 0;

	/* return ENOMEM indicating insufficient memory for addresses */
3239
	if (netdev_uc_count(netdev) > rar_entries)
3240
		return -ENOMEM;
3241

3242
	if (!netdev_uc_empty(netdev) && rar_entries) {
3243
		struct netdev_hw_addr *ha;
3244 3245

		netdev_for_each_uc_addr(ha, netdev) {
3246 3247
			if (!rar_entries)
				break;
3248 3249
			igb_rar_set_qsel(adapter, ha->addr,
			                 rar_entries--,
3250 3251
			                 vfn);
			count++;
3252 3253 3254 3255 3256 3257 3258 3259 3260
		}
	}
	/* write the addresses in reverse order to avoid write combining */
	for (; rar_entries > 0 ; rar_entries--) {
		wr32(E1000_RAH(rar_entries), 0);
		wr32(E1000_RAL(rar_entries), 0);
	}
	wrfl();

3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318
	return count;
}

/**
 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
 * @netdev: network interface device structure
 *
 * The set_rx_mode entry point is called whenever the unicast or multicast
 * address lists or the network interface flags are updated.  This routine is
 * responsible for configuring the hardware for proper unicast, multicast,
 * promiscuous mode, and all-multi behavior.
 **/
static void igb_set_rx_mode(struct net_device *netdev)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
	unsigned int vfn = adapter->vfs_allocated_count;
	u32 rctl, vmolr = 0;
	int count;

	/* Check for Promiscuous and All Multicast modes */
	rctl = rd32(E1000_RCTL);

	/* clear the effected bits */
	rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);

	if (netdev->flags & IFF_PROMISC) {
		rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
		vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
	} else {
		if (netdev->flags & IFF_ALLMULTI) {
			rctl |= E1000_RCTL_MPE;
			vmolr |= E1000_VMOLR_MPME;
		} else {
			/*
			 * Write addresses to the MTA, if the attempt fails
			 * then we should just turn on promiscous mode so
			 * that we can at least receive multicast traffic
			 */
			count = igb_write_mc_addr_list(netdev);
			if (count < 0) {
				rctl |= E1000_RCTL_MPE;
				vmolr |= E1000_VMOLR_MPME;
			} else if (count) {
				vmolr |= E1000_VMOLR_ROMPE;
			}
		}
		/*
		 * Write addresses to available RAR registers, if there is not
		 * sufficient space to store all the addresses then enable
		 * unicast promiscous mode
		 */
		count = igb_write_uc_addr_list(netdev);
		if (count < 0) {
			rctl |= E1000_RCTL_UPE;
			vmolr |= E1000_VMOLR_ROPE;
		}
		rctl |= E1000_RCTL_VFE;
3319
	}
3320
	wr32(E1000_RCTL, rctl);
3321

3322 3323 3324 3325 3326 3327 3328
	/*
	 * In order to support SR-IOV and eventually VMDq it is necessary to set
	 * the VMOLR to enable the appropriate modes.  Without this workaround
	 * we will have issues with VLAN tag stripping not being done for frames
	 * that are only arriving because we are the default pool
	 */
	if (hw->mac.type < e1000_82576)
3329
		return;
3330

3331 3332 3333
	vmolr |= rd32(E1000_VMOLR(vfn)) &
	         ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
	wr32(E1000_VMOLR(vfn), vmolr);
3334
	igb_restore_vf_multicasts(adapter);
3335 3336 3337 3338 3339 3340 3341
}

/* Need to wait a few seconds after link up to get diagnostic information from
 * the phy */
static void igb_update_phy_info(unsigned long data)
{
	struct igb_adapter *adapter = (struct igb_adapter *) data;
3342
	igb_get_phy_info(&adapter->hw);
3343 3344
}

A
Alexander Duyck 已提交
3345 3346 3347 3348
/**
 * igb_has_link - check shared code for link and determine up/down
 * @adapter: pointer to driver private info
 **/
3349
bool igb_has_link(struct igb_adapter *adapter)
A
Alexander Duyck 已提交
3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380
{
	struct e1000_hw *hw = &adapter->hw;
	bool link_active = false;
	s32 ret_val = 0;

	/* get_link_status is set on LSC (link status) interrupt or
	 * rx sequence error interrupt.  get_link_status will stay
	 * false until the e1000_check_for_link establishes link
	 * for copper adapters ONLY
	 */
	switch (hw->phy.media_type) {
	case e1000_media_type_copper:
		if (hw->mac.get_link_status) {
			ret_val = hw->mac.ops.check_for_link(hw);
			link_active = !hw->mac.get_link_status;
		} else {
			link_active = true;
		}
		break;
	case e1000_media_type_internal_serdes:
		ret_val = hw->mac.ops.check_for_link(hw);
		link_active = hw->mac.serdes_has_link;
		break;
	default:
	case e1000_media_type_unknown:
		break;
	}

	return link_active;
}

3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394
/**
 * igb_watchdog - Timer Call-back
 * @data: pointer to adapter cast into an unsigned long
 **/
static void igb_watchdog(unsigned long data)
{
	struct igb_adapter *adapter = (struct igb_adapter *)data;
	/* Do the rest outside of interrupt context */
	schedule_work(&adapter->watchdog_task);
}

static void igb_watchdog_task(struct work_struct *work)
{
	struct igb_adapter *adapter = container_of(work,
3395 3396
	                                           struct igb_adapter,
                                                   watchdog_task);
3397 3398 3399
	struct e1000_hw *hw = &adapter->hw;
	struct net_device *netdev = adapter->netdev;
	u32 link;
3400
	int i;
3401

A
Alexander Duyck 已提交
3402
	link = igb_has_link(adapter);
3403 3404 3405
	if (link) {
		if (!netif_carrier_ok(netdev)) {
			u32 ctrl;
3406 3407 3408
			hw->mac.ops.get_speed_and_duplex(hw,
			                                 &adapter->link_speed,
			                                 &adapter->link_duplex);
3409 3410

			ctrl = rd32(E1000_CTRL);
3411 3412
			/* Links status message must follow this format */
			printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
3413
				 "Flow Control: %s\n",
3414 3415 3416
			       netdev->name,
			       adapter->link_speed,
			       adapter->link_duplex == FULL_DUPLEX ?
3417
				 "Full Duplex" : "Half Duplex",
3418 3419 3420 3421
			       ((ctrl & E1000_CTRL_TFCE) &&
			        (ctrl & E1000_CTRL_RFCE)) ? "RX/TX" :
			       ((ctrl & E1000_CTRL_RFCE) ?  "RX" :
			       ((ctrl & E1000_CTRL_TFCE) ?  "TX" : "None")));
3422

3423
			/* adjust timeout factor according to speed/duplex */
3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435
			adapter->tx_timeout_factor = 1;
			switch (adapter->link_speed) {
			case SPEED_10:
				adapter->tx_timeout_factor = 14;
				break;
			case SPEED_100:
				/* maybe add some timeout factor ? */
				break;
			}

			netif_carrier_on(netdev);

3436 3437
			igb_ping_all_vfs(adapter);

3438
			/* link state has changed, schedule phy info update */
3439 3440 3441 3442 3443 3444 3445 3446
			if (!test_bit(__IGB_DOWN, &adapter->state))
				mod_timer(&adapter->phy_info_timer,
					  round_jiffies(jiffies + 2 * HZ));
		}
	} else {
		if (netif_carrier_ok(netdev)) {
			adapter->link_speed = 0;
			adapter->link_duplex = 0;
3447 3448 3449
			/* Links status message must follow this format */
			printk(KERN_INFO "igb: %s NIC Link is Down\n",
			       netdev->name);
3450
			netif_carrier_off(netdev);
3451

3452 3453
			igb_ping_all_vfs(adapter);

3454
			/* link state has changed, schedule phy info update */
3455 3456 3457 3458 3459 3460 3461 3462
			if (!test_bit(__IGB_DOWN, &adapter->state))
				mod_timer(&adapter->phy_info_timer,
					  round_jiffies(jiffies + 2 * HZ));
		}
	}

	igb_update_stats(adapter);

3463
	for (i = 0; i < adapter->num_tx_queues; i++) {
3464
		struct igb_ring *tx_ring = adapter->tx_ring[i];
3465
		if (!netif_carrier_ok(netdev)) {
3466 3467 3468 3469
			/* We've lost link, so the controller stops DMA,
			 * but we've got queued Tx work that's never going
			 * to get done, so reset controller to flush Tx.
			 * (Do the reset outside of interrupt context). */
3470 3471 3472 3473 3474 3475
			if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
				adapter->tx_timeout_count++;
				schedule_work(&adapter->reset_task);
				/* return immediately since reset is imminent */
				return;
			}
3476 3477
		}

3478 3479 3480
		/* Force detection of hung controller every watchdog period */
		tx_ring->detect_tx_hung = true;
	}
3481

3482
	/* Cause software interrupt to ensure rx ring is cleaned */
3483
	if (adapter->msix_entries) {
3484 3485 3486 3487 3488
		u32 eics = 0;
		for (i = 0; i < adapter->num_q_vectors; i++) {
			struct igb_q_vector *q_vector = adapter->q_vector[i];
			eics |= q_vector->eims_value;
		}
3489 3490 3491 3492
		wr32(E1000_EICS, eics);
	} else {
		wr32(E1000_ICS, E1000_ICS_RXDMT0);
	}
3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506

	/* Reset the timer */
	if (!test_bit(__IGB_DOWN, &adapter->state))
		mod_timer(&adapter->watchdog_timer,
			  round_jiffies(jiffies + 2 * HZ));
}

enum latency_range {
	lowest_latency = 0,
	low_latency = 1,
	bulk_latency = 2,
	latency_invalid = 255
};

3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520
/**
 * igb_update_ring_itr - update the dynamic ITR value based on packet size
 *
 *      Stores a new ITR value based on strictly on packet size.  This
 *      algorithm is less sophisticated than that used in igb_update_itr,
 *      due to the difficulty of synchronizing statistics across multiple
 *      receive rings.  The divisors and thresholds used by this fuction
 *      were determined based on theoretical maximum wire speed and testing
 *      data, in order to minimize response time while increasing bulk
 *      throughput.
 *      This functionality is controlled by the InterruptThrottleRate module
 *      parameter (see igb_param.c)
 *      NOTE:  This function is called only when operating in a multiqueue
 *             receive environment.
3521
 * @q_vector: pointer to q_vector
3522
 **/
3523
static void igb_update_ring_itr(struct igb_q_vector *q_vector)
3524
{
3525
	int new_val = q_vector->itr_val;
3526
	int avg_wire_size = 0;
3527
	struct igb_adapter *adapter = q_vector->adapter;
3528

3529 3530 3531 3532
	/* For non-gigabit speeds, just fix the interrupt rate at 4000
	 * ints/sec - ITR timer value of 120 ticks.
	 */
	if (adapter->link_speed != SPEED_1000) {
3533
		new_val = 976;
3534
		goto set_itr_val;
3535
	}
3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551

	if (q_vector->rx_ring && q_vector->rx_ring->total_packets) {
		struct igb_ring *ring = q_vector->rx_ring;
		avg_wire_size = ring->total_bytes / ring->total_packets;
	}

	if (q_vector->tx_ring && q_vector->tx_ring->total_packets) {
		struct igb_ring *ring = q_vector->tx_ring;
		avg_wire_size = max_t(u32, avg_wire_size,
		                      (ring->total_bytes /
		                       ring->total_packets));
	}

	/* if avg_wire_size isn't set no work was done */
	if (!avg_wire_size)
		goto clear_counts;
3552

3553 3554 3555 3556 3557
	/* Add 24 bytes to size to account for CRC, preamble, and gap */
	avg_wire_size += 24;

	/* Don't starve jumbo frames */
	avg_wire_size = min(avg_wire_size, 3000);
3558

3559 3560 3561 3562 3563
	/* Give a little boost to mid-size frames */
	if ((avg_wire_size > 300) && (avg_wire_size < 1200))
		new_val = avg_wire_size / 3;
	else
		new_val = avg_wire_size / 2;
3564

3565 3566 3567 3568
	/* when in itr mode 3 do not exceed 20K ints/sec */
	if (adapter->rx_itr_setting == 3 && new_val < 196)
		new_val = 196;

3569
set_itr_val:
3570 3571 3572
	if (new_val != q_vector->itr_val) {
		q_vector->itr_val = new_val;
		q_vector->set_itr = 1;
3573
	}
3574
clear_counts:
3575 3576 3577 3578 3579 3580 3581 3582
	if (q_vector->rx_ring) {
		q_vector->rx_ring->total_bytes = 0;
		q_vector->rx_ring->total_packets = 0;
	}
	if (q_vector->tx_ring) {
		q_vector->tx_ring->total_bytes = 0;
		q_vector->tx_ring->total_packets = 0;
	}
3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598
}

/**
 * igb_update_itr - update the dynamic ITR value based on statistics
 *      Stores a new ITR value based on packets and byte
 *      counts during the last interrupt.  The advantage of per interrupt
 *      computation is faster updates and more accurate ITR for the current
 *      traffic pattern.  Constants in this function were computed
 *      based on theoretical maximum wire speed and thresholds were set based
 *      on testing data as well as attempting to minimize response time
 *      while increasing bulk throughput.
 *      this functionality is controlled by the InterruptThrottleRate module
 *      parameter (see igb_param.c)
 *      NOTE:  These calculations are only valid when operating in a single-
 *             queue environment.
 * @adapter: pointer to adapter
3599
 * @itr_setting: current q_vector->itr_val
3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638
 * @packets: the number of packets during this measurement interval
 * @bytes: the number of bytes during this measurement interval
 **/
static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
				   int packets, int bytes)
{
	unsigned int retval = itr_setting;

	if (packets == 0)
		goto update_itr_done;

	switch (itr_setting) {
	case lowest_latency:
		/* handle TSO and jumbo frames */
		if (bytes/packets > 8000)
			retval = bulk_latency;
		else if ((packets < 5) && (bytes > 512))
			retval = low_latency;
		break;
	case low_latency:  /* 50 usec aka 20000 ints/s */
		if (bytes > 10000) {
			/* this if handles the TSO accounting */
			if (bytes/packets > 8000) {
				retval = bulk_latency;
			} else if ((packets < 10) || ((bytes/packets) > 1200)) {
				retval = bulk_latency;
			} else if ((packets > 35)) {
				retval = lowest_latency;
			}
		} else if (bytes/packets > 2000) {
			retval = bulk_latency;
		} else if (packets <= 2 && bytes < 512) {
			retval = lowest_latency;
		}
		break;
	case bulk_latency: /* 250 usec aka 4000 ints/s */
		if (bytes > 25000) {
			if (packets > 35)
				retval = low_latency;
3639
		} else if (bytes < 1500) {
3640 3641 3642 3643 3644 3645 3646 3647 3648
			retval = low_latency;
		}
		break;
	}

update_itr_done:
	return retval;
}

3649
static void igb_set_itr(struct igb_adapter *adapter)
3650
{
3651
	struct igb_q_vector *q_vector = adapter->q_vector[0];
3652
	u16 current_itr;
3653
	u32 new_itr = q_vector->itr_val;
3654 3655 3656 3657 3658 3659 3660 3661 3662 3663

	/* for non-gigabit speeds, just fix the interrupt rate at 4000 */
	if (adapter->link_speed != SPEED_1000) {
		current_itr = 0;
		new_itr = 4000;
		goto set_itr_now;
	}

	adapter->rx_itr = igb_update_itr(adapter,
				    adapter->rx_itr,
3664 3665
				    q_vector->rx_ring->total_packets,
				    q_vector->rx_ring->total_bytes);
3666

3667 3668
	adapter->tx_itr = igb_update_itr(adapter,
				    adapter->tx_itr,
3669 3670
				    q_vector->tx_ring->total_packets,
				    q_vector->tx_ring->total_bytes);
3671
	current_itr = max(adapter->rx_itr, adapter->tx_itr);
3672

3673
	/* conservative mode (itr 3) eliminates the lowest_latency setting */
3674
	if (adapter->rx_itr_setting == 3 && current_itr == lowest_latency)
3675 3676
		current_itr = low_latency;

3677 3678 3679
	switch (current_itr) {
	/* counts and packets in update_itr are dependent on these numbers */
	case lowest_latency:
3680
		new_itr = 56;  /* aka 70,000 ints/sec */
3681 3682
		break;
	case low_latency:
3683
		new_itr = 196; /* aka 20,000 ints/sec */
3684 3685
		break;
	case bulk_latency:
3686
		new_itr = 980; /* aka 4,000 ints/sec */
3687 3688 3689 3690 3691 3692
		break;
	default:
		break;
	}

set_itr_now:
3693 3694 3695 3696
	q_vector->rx_ring->total_bytes = 0;
	q_vector->rx_ring->total_packets = 0;
	q_vector->tx_ring->total_bytes = 0;
	q_vector->tx_ring->total_packets = 0;
3697

3698
	if (new_itr != q_vector->itr_val) {
3699 3700 3701
		/* this attempts to bias the interrupt rate towards Bulk
		 * by adding intermediate steps when interrupt rate is
		 * increasing */
3702 3703 3704 3705
		new_itr = new_itr > q_vector->itr_val ?
		             max((new_itr * q_vector->itr_val) /
		                 (new_itr + (q_vector->itr_val >> 2)),
		                 new_itr) :
3706 3707 3708 3709 3710 3711 3712
			     new_itr;
		/* Don't write the value here; it resets the adapter's
		 * internal timer, and causes us to delay far longer than
		 * we should between interrupts.  Instead, we write the ITR
		 * value at the beginning of the next interrupt so the timing
		 * ends up being correct.
		 */
3713 3714
		q_vector->itr_val = new_itr;
		q_vector->set_itr = 1;
3715 3716 3717 3718 3719 3720 3721
	}
}

#define IGB_TX_FLAGS_CSUM		0x00000001
#define IGB_TX_FLAGS_VLAN		0x00000002
#define IGB_TX_FLAGS_TSO		0x00000004
#define IGB_TX_FLAGS_IPV4		0x00000008
A
Alexander Duyck 已提交
3722 3723 3724
#define IGB_TX_FLAGS_TSTAMP		0x00000010
#define IGB_TX_FLAGS_VLAN_MASK		0xffff0000
#define IGB_TX_FLAGS_VLAN_SHIFT		        16
3725

3726
static inline int igb_tso_adv(struct igb_ring *tx_ring,
3727 3728 3729 3730 3731 3732 3733
			      struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
{
	struct e1000_adv_tx_context_desc *context_desc;
	unsigned int i;
	int err;
	struct igb_buffer *buffer_info;
	u32 info = 0, tu_cmd = 0;
N
Nick Nunley 已提交
3734 3735
	u32 mss_l4len_idx;
	u8 l4len;
3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753

	if (skb_header_cloned(skb)) {
		err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
		if (err)
			return err;
	}

	l4len = tcp_hdrlen(skb);
	*hdr_len += l4len;

	if (skb->protocol == htons(ETH_P_IP)) {
		struct iphdr *iph = ip_hdr(skb);
		iph->tot_len = 0;
		iph->check = 0;
		tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
							 iph->daddr, 0,
							 IPPROTO_TCP,
							 0);
3754
	} else if (skb_is_gso_v6(skb)) {
3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786
		ipv6_hdr(skb)->payload_len = 0;
		tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
						       &ipv6_hdr(skb)->daddr,
						       0, IPPROTO_TCP, 0);
	}

	i = tx_ring->next_to_use;

	buffer_info = &tx_ring->buffer_info[i];
	context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
	/* VLAN MACLEN IPLEN */
	if (tx_flags & IGB_TX_FLAGS_VLAN)
		info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
	info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
	*hdr_len += skb_network_offset(skb);
	info |= skb_network_header_len(skb);
	*hdr_len += skb_network_header_len(skb);
	context_desc->vlan_macip_lens = cpu_to_le32(info);

	/* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
	tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);

	if (skb->protocol == htons(ETH_P_IP))
		tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
	tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;

	context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);

	/* MSS L4LEN IDX */
	mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
	mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);

3787
	/* For 82575, context index must be unique per ring. */
3788 3789
	if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
		mss_l4len_idx |= tx_ring->reg_idx << 4;
3790 3791 3792 3793 3794

	context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
	context_desc->seqnum_seed = 0;

	buffer_info->time_stamp = jiffies;
A
Alexander Duyck 已提交
3795
	buffer_info->next_to_watch = i;
3796 3797 3798 3799 3800 3801 3802 3803 3804 3805
	buffer_info->dma = 0;
	i++;
	if (i == tx_ring->count)
		i = 0;

	tx_ring->next_to_use = i;

	return true;
}

3806 3807
static inline bool igb_tx_csum_adv(struct igb_ring *tx_ring,
				   struct sk_buff *skb, u32 tx_flags)
3808 3809
{
	struct e1000_adv_tx_context_desc *context_desc;
3810
	struct device *dev = tx_ring->dev;
3811 3812
	struct igb_buffer *buffer_info;
	u32 info = 0, tu_cmd = 0;
3813
	unsigned int i;
3814 3815 3816 3817 3818 3819 3820 3821 3822

	if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
	    (tx_flags & IGB_TX_FLAGS_VLAN)) {
		i = tx_ring->next_to_use;
		buffer_info = &tx_ring->buffer_info[i];
		context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);

		if (tx_flags & IGB_TX_FLAGS_VLAN)
			info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
A
Alexander Duyck 已提交
3823

3824 3825 3826 3827 3828 3829 3830 3831 3832
		info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
		if (skb->ip_summed == CHECKSUM_PARTIAL)
			info |= skb_network_header_len(skb);

		context_desc->vlan_macip_lens = cpu_to_le32(info);

		tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);

		if (skb->ip_summed == CHECKSUM_PARTIAL) {
3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844
			__be16 protocol;

			if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
				const struct vlan_ethhdr *vhdr =
				          (const struct vlan_ethhdr*)skb->data;

				protocol = vhdr->h_vlan_encapsulated_proto;
			} else {
				protocol = skb->protocol;
			}

			switch (protocol) {
3845
			case cpu_to_be16(ETH_P_IP):
3846
				tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3847 3848
				if (ip_hdr(skb)->protocol == IPPROTO_TCP)
					tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3849 3850
				else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
					tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3851
				break;
3852
			case cpu_to_be16(ETH_P_IPV6):
3853 3854 3855
				/* XXX what about other V6 headers?? */
				if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
					tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3856 3857
				else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
					tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3858 3859 3860
				break;
			default:
				if (unlikely(net_ratelimit()))
3861
					dev_warn(dev,
3862 3863 3864 3865
					    "partial checksum but proto=%x!\n",
					    skb->protocol);
				break;
			}
3866 3867 3868 3869
		}

		context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
		context_desc->seqnum_seed = 0;
3870
		if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
3871
			context_desc->mss_l4len_idx =
3872
				cpu_to_le32(tx_ring->reg_idx << 4);
3873 3874

		buffer_info->time_stamp = jiffies;
A
Alexander Duyck 已提交
3875
		buffer_info->next_to_watch = i;
3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890
		buffer_info->dma = 0;

		i++;
		if (i == tx_ring->count)
			i = 0;
		tx_ring->next_to_use = i;

		return true;
	}
	return false;
}

#define IGB_MAX_TXD_PWR	16
#define IGB_MAX_DATA_PER_TXD	(1<<IGB_MAX_TXD_PWR)

3891
static inline int igb_tx_map_adv(struct igb_ring *tx_ring, struct sk_buff *skb,
A
Alexander Duyck 已提交
3892
				 unsigned int first)
3893 3894
{
	struct igb_buffer *buffer_info;
3895
	struct device *dev = tx_ring->dev;
3896
	unsigned int hlen = skb_headlen(skb);
3897 3898
	unsigned int count = 0, i;
	unsigned int f;
3899
	u16 gso_segs = skb_shinfo(skb)->gso_segs ?: 1;
3900 3901 3902 3903

	i = tx_ring->next_to_use;

	buffer_info = &tx_ring->buffer_info[i];
3904 3905
	BUG_ON(hlen >= IGB_MAX_DATA_PER_TXD);
	buffer_info->length = hlen;
3906 3907
	/* set time_stamp *before* dma to help avoid a possible race */
	buffer_info->time_stamp = jiffies;
A
Alexander Duyck 已提交
3908
	buffer_info->next_to_watch = i;
3909
	buffer_info->dma = dma_map_single(dev, skb->data, hlen,
3910 3911
					  DMA_TO_DEVICE);
	if (dma_mapping_error(dev, buffer_info->dma))
3912
		goto dma_error;
3913 3914

	for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3915 3916
		struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[f];
		unsigned int len = frag->size;
3917

3918
		count++;
3919 3920 3921 3922
		i++;
		if (i == tx_ring->count)
			i = 0;

3923 3924 3925 3926
		buffer_info = &tx_ring->buffer_info[i];
		BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
		buffer_info->length = len;
		buffer_info->time_stamp = jiffies;
A
Alexander Duyck 已提交
3927
		buffer_info->next_to_watch = i;
3928
		buffer_info->mapped_as_page = true;
3929
		buffer_info->dma = dma_map_page(dev,
3930 3931 3932
						frag->page,
						frag->page_offset,
						len,
3933 3934
						DMA_TO_DEVICE);
		if (dma_mapping_error(dev, buffer_info->dma))
3935 3936
			goto dma_error;

3937 3938 3939
	}

	tx_ring->buffer_info[i].skb = skb;
3940 3941 3942 3943
	tx_ring->buffer_info[i].shtx = skb_shinfo(skb)->tx_flags;
	/* multiply data chunks by size of headers */
	tx_ring->buffer_info[i].bytecount = ((gso_segs - 1) * hlen) + skb->len;
	tx_ring->buffer_info[i].gso_segs = gso_segs;
A
Alexander Duyck 已提交
3944
	tx_ring->buffer_info[first].next_to_watch = i;
3945

A
Alexander Duyck 已提交
3946
	return ++count;
3947 3948

dma_error:
3949
	dev_err(dev, "TX DMA map failed\n");
3950 3951 3952 3953 3954 3955 3956 3957 3958

	/* clear timestamp and dma mappings for failed buffer_info mapping */
	buffer_info->dma = 0;
	buffer_info->time_stamp = 0;
	buffer_info->length = 0;
	buffer_info->next_to_watch = 0;
	buffer_info->mapped_as_page = false;

	/* clear timestamp and dma mappings for remaining portion of packet */
3959 3960 3961
	while (count--) {
		if (i == 0)
			i = tx_ring->count;
3962 3963 3964 3965 3966 3967
		i--;
		buffer_info = &tx_ring->buffer_info[i];
		igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
	}

	return 0;
3968 3969
}

3970
static inline void igb_tx_queue_adv(struct igb_ring *tx_ring,
N
Nick Nunley 已提交
3971
				    u32 tx_flags, int count, u32 paylen,
3972 3973
				    u8 hdr_len)
{
A
Alexander Duyck 已提交
3974
	union e1000_adv_tx_desc *tx_desc;
3975 3976
	struct igb_buffer *buffer_info;
	u32 olinfo_status = 0, cmd_type_len;
A
Alexander Duyck 已提交
3977
	unsigned int i = tx_ring->next_to_use;
3978 3979 3980 3981 3982 3983 3984

	cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
			E1000_ADVTXD_DCMD_DEXT);

	if (tx_flags & IGB_TX_FLAGS_VLAN)
		cmd_type_len |= E1000_ADVTXD_DCMD_VLE;

3985 3986 3987
	if (tx_flags & IGB_TX_FLAGS_TSTAMP)
		cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;

3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001
	if (tx_flags & IGB_TX_FLAGS_TSO) {
		cmd_type_len |= E1000_ADVTXD_DCMD_TSE;

		/* insert tcp checksum */
		olinfo_status |= E1000_TXD_POPTS_TXSM << 8;

		/* insert ip checksum */
		if (tx_flags & IGB_TX_FLAGS_IPV4)
			olinfo_status |= E1000_TXD_POPTS_IXSM << 8;

	} else if (tx_flags & IGB_TX_FLAGS_CSUM) {
		olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
	}

4002 4003 4004
	if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) &&
	    (tx_flags & (IGB_TX_FLAGS_CSUM |
	                 IGB_TX_FLAGS_TSO |
4005
			 IGB_TX_FLAGS_VLAN)))
4006
		olinfo_status |= tx_ring->reg_idx << 4;
4007 4008 4009

	olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);

A
Alexander Duyck 已提交
4010
	do {
4011 4012 4013 4014 4015 4016
		buffer_info = &tx_ring->buffer_info[i];
		tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
		tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
		tx_desc->read.cmd_type_len =
			cpu_to_le32(cmd_type_len | buffer_info->length);
		tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
A
Alexander Duyck 已提交
4017
		count--;
4018 4019 4020
		i++;
		if (i == tx_ring->count)
			i = 0;
A
Alexander Duyck 已提交
4021
	} while (count > 0);
4022

4023
	tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD);
4024 4025 4026 4027 4028 4029 4030
	/* Force memory writes to complete before letting h/w
	 * know there are new descriptors to fetch.  (Only
	 * applicable for weak-ordered memory model archs,
	 * such as IA-64). */
	wmb();

	tx_ring->next_to_use = i;
4031
	writel(i, tx_ring->tail);
4032 4033 4034 4035 4036
	/* we need this if more than one processor can write to our tail
	 * at a time, it syncronizes IO on IA64/Altix systems */
	mmiowb();
}

4037
static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
4038
{
4039 4040
	struct net_device *netdev = tx_ring->netdev;

4041 4042
	netif_stop_subqueue(netdev, tx_ring->queue_index);

4043 4044 4045 4046 4047 4048 4049
	/* Herbert's original patch had:
	 *  smp_mb__after_netif_stop_queue();
	 * but since that doesn't exist yet, just open code it. */
	smp_mb();

	/* We need to check again in a case another CPU has just
	 * made room available. */
4050
	if (igb_desc_unused(tx_ring) < size)
4051 4052 4053
		return -EBUSY;

	/* A reprieve! */
4054
	netif_wake_subqueue(netdev, tx_ring->queue_index);
4055
	tx_ring->tx_stats.restart_queue++;
4056 4057 4058
	return 0;
}

N
Nick Nunley 已提交
4059
static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
4060
{
4061
	if (igb_desc_unused(tx_ring) >= size)
4062
		return 0;
4063
	return __igb_maybe_stop_tx(tx_ring, size);
4064 4065
}

4066 4067
netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
				    struct igb_ring *tx_ring)
4068
{
4069
	struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
A
Alexander Duyck 已提交
4070
	int tso = 0, count;
N
Nick Nunley 已提交
4071 4072 4073
	u32 tx_flags = 0;
	u16 first;
	u8 hdr_len = 0;
4074
	union skb_shared_tx *shtx = skb_tx(skb);
4075 4076 4077 4078 4079 4080

	/* need: 1 descriptor per page,
	 *       + 2 desc gap to keep tail from touching head,
	 *       + 1 desc for skb->data,
	 *       + 1 desc for context descriptor,
	 * otherwise try next time */
4081
	if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
4082 4083 4084
		/* this is a hard error */
		return NETDEV_TX_BUSY;
	}
4085 4086 4087 4088 4089

	if (unlikely(shtx->hardware)) {
		shtx->in_progress = 1;
		tx_flags |= IGB_TX_FLAGS_TSTAMP;
	}
4090

A
Alexander Duyck 已提交
4091
	if (vlan_tx_tag_present(skb) && adapter->vlgrp) {
4092 4093 4094 4095
		tx_flags |= IGB_TX_FLAGS_VLAN;
		tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
	}

4096 4097 4098
	if (skb->protocol == htons(ETH_P_IP))
		tx_flags |= IGB_TX_FLAGS_IPV4;

A
Alexander Duyck 已提交
4099
	first = tx_ring->next_to_use;
4100 4101
	if (skb_is_gso(skb)) {
		tso = igb_tso_adv(tx_ring, skb, tx_flags, &hdr_len);
A
Alexander Duyck 已提交
4102

4103 4104 4105 4106
		if (tso < 0) {
			dev_kfree_skb_any(skb);
			return NETDEV_TX_OK;
		}
4107 4108 4109 4110
	}

	if (tso)
		tx_flags |= IGB_TX_FLAGS_TSO;
4111
	else if (igb_tx_csum_adv(tx_ring, skb, tx_flags) &&
4112 4113
	         (skb->ip_summed == CHECKSUM_PARTIAL))
		tx_flags |= IGB_TX_FLAGS_CSUM;
4114

4115
	/*
A
Alexander Duyck 已提交
4116
	 * count reflects descriptors mapped, if 0 or less then mapping error
4117 4118
	 * has occured and we need to rewind the descriptor queue
	 */
4119
	count = igb_tx_map_adv(tx_ring, skb, first);
4120
	if (!count) {
4121 4122 4123
		dev_kfree_skb_any(skb);
		tx_ring->buffer_info[first].time_stamp = 0;
		tx_ring->next_to_use = first;
4124
		return NETDEV_TX_OK;
4125
	}
4126

4127 4128 4129
	igb_tx_queue_adv(tx_ring, tx_flags, count, skb->len, hdr_len);

	/* Make sure there is space in the ring for the next send. */
4130
	igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
4131

4132 4133 4134
	return NETDEV_TX_OK;
}

4135 4136
static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
				      struct net_device *netdev)
4137 4138
{
	struct igb_adapter *adapter = netdev_priv(netdev);
4139 4140
	struct igb_ring *tx_ring;
	int r_idx = 0;
4141 4142 4143 4144 4145 4146 4147 4148 4149 4150 4151

	if (test_bit(__IGB_DOWN, &adapter->state)) {
		dev_kfree_skb_any(skb);
		return NETDEV_TX_OK;
	}

	if (skb->len <= 0) {
		dev_kfree_skb_any(skb);
		return NETDEV_TX_OK;
	}

4152
	r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
4153
	tx_ring = adapter->multi_tx_table[r_idx];
4154 4155 4156 4157 4158

	/* This goes back to the question of how to logically map a tx queue
	 * to a flow.  Right now, performance is impacted slightly negatively
	 * if using multiple tx queues.  If the stack breaks away from a
	 * single qdisc implementation, we can look at this again. */
4159
	return igb_xmit_frame_ring_adv(skb, tx_ring);
4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172
}

/**
 * igb_tx_timeout - Respond to a Tx Hang
 * @netdev: network interface device structure
 **/
static void igb_tx_timeout(struct net_device *netdev)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;

	/* Do the reset outside of interrupt context */
	adapter->tx_timeout_count++;
4173

4174 4175 4176
	if (hw->mac.type == e1000_82580)
		hw->dev_spec._82575.global_device_reset = true;

4177
	schedule_work(&adapter->reset_task);
4178 4179
	wr32(E1000_EICS,
	     (adapter->eims_enable_mask & ~adapter->eims_other));
4180 4181 4182 4183 4184 4185 4186
}

static void igb_reset_task(struct work_struct *work)
{
	struct igb_adapter *adapter;
	adapter = container_of(work, struct igb_adapter, reset_task);

4187 4188
	igb_dump(adapter);
	netdev_err(adapter->netdev, "Reset adapter\n");
4189 4190 4191 4192 4193 4194 4195 4196 4197 4198
	igb_reinit_locked(adapter);
}

/**
 * igb_get_stats - Get System Network Statistics
 * @netdev: network interface device structure
 *
 * Returns the address of the device statistics structure.
 * The statistics are actually updated from the timer callback.
 **/
4199
static struct net_device_stats *igb_get_stats(struct net_device *netdev)
4200 4201
{
	/* only return the current stats */
4202
	return &netdev->stats;
4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214
}

/**
 * igb_change_mtu - Change the Maximum Transfer Unit
 * @netdev: network interface device structure
 * @new_mtu: new value for maximum frame size
 *
 * Returns 0 on success, negative on failure
 **/
static int igb_change_mtu(struct net_device *netdev, int new_mtu)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
4215
	struct pci_dev *pdev = adapter->pdev;
4216
	int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4217
	u32 rx_buffer_len, i;
4218

4219
	if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
4220
		dev_err(&pdev->dev, "Invalid MTU setting\n");
4221 4222 4223 4224
		return -EINVAL;
	}

	if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
4225
		dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
4226 4227 4228 4229 4230
		return -EINVAL;
	}

	while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
		msleep(1);
4231

4232 4233
	/* igb_down has a dependency on max_frame_size */
	adapter->max_frame_size = max_frame;
4234

4235 4236 4237 4238 4239 4240
	/* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
	 * means we reserve 2 more, this pushes us to allocate from the next
	 * larger slab size.
	 * i.e. RXBUFFER_2048 --> size-4096 slab
	 */

N
Nick Nunley 已提交
4241 4242 4243
	if (adapter->hw.mac.type == e1000_82580)
		max_frame += IGB_TS_HDR_LEN;

4244
	if (max_frame <= IGB_RXBUFFER_1024)
4245
		rx_buffer_len = IGB_RXBUFFER_1024;
A
Alexander Duyck 已提交
4246
	else if (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE)
4247
		rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
A
Alexander Duyck 已提交
4248
	else
4249 4250
		rx_buffer_len = IGB_RXBUFFER_128;

N
Nick Nunley 已提交
4251 4252 4253 4254 4255 4256 4257 4258
	if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN + IGB_TS_HDR_LEN) ||
	     (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE + IGB_TS_HDR_LEN))
		rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE + IGB_TS_HDR_LEN;

	if ((adapter->hw.mac.type == e1000_82580) &&
	    (rx_buffer_len == IGB_RXBUFFER_128))
		rx_buffer_len += IGB_RXBUFFER_64;

4259 4260
	if (netif_running(netdev))
		igb_down(adapter);
4261

4262
	dev_info(&pdev->dev, "changing MTU from %d to %d\n",
4263 4264 4265
		 netdev->mtu, new_mtu);
	netdev->mtu = new_mtu;

4266
	for (i = 0; i < adapter->num_rx_queues; i++)
4267
		adapter->rx_ring[i]->rx_buffer_len = rx_buffer_len;
4268

4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285
	if (netif_running(netdev))
		igb_up(adapter);
	else
		igb_reset(adapter);

	clear_bit(__IGB_RESETTING, &adapter->state);

	return 0;
}

/**
 * igb_update_stats - Update the board statistics counters
 * @adapter: board private structure
 **/

void igb_update_stats(struct igb_adapter *adapter)
{
4286
	struct net_device_stats *net_stats = igb_get_stats(adapter->netdev);
4287 4288
	struct e1000_hw *hw = &adapter->hw;
	struct pci_dev *pdev = adapter->pdev;
4289
	u32 reg, mpc;
4290
	u16 phy_tmp;
4291 4292
	int i;
	u64 bytes, packets;
4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304

#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF

	/*
	 * Prevent stats update while adapter is being reset, or if the pci
	 * connection is down.
	 */
	if (adapter->link_speed == 0)
		return;
	if (pci_channel_offline(pdev))
		return;

4305 4306 4307 4308
	bytes = 0;
	packets = 0;
	for (i = 0; i < adapter->num_rx_queues; i++) {
		u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF;
4309 4310
		struct igb_ring *ring = adapter->rx_ring[i];
		ring->rx_stats.drops += rqdpc_tmp;
4311
		net_stats->rx_fifo_errors += rqdpc_tmp;
4312 4313
		bytes += ring->rx_stats.bytes;
		packets += ring->rx_stats.packets;
4314 4315
	}

4316 4317
	net_stats->rx_bytes = bytes;
	net_stats->rx_packets = packets;
4318 4319 4320 4321

	bytes = 0;
	packets = 0;
	for (i = 0; i < adapter->num_tx_queues; i++) {
4322 4323 4324
		struct igb_ring *ring = adapter->tx_ring[i];
		bytes += ring->tx_stats.bytes;
		packets += ring->tx_stats.packets;
4325
	}
4326 4327
	net_stats->tx_bytes = bytes;
	net_stats->tx_packets = packets;
4328 4329

	/* read stats registers */
4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346
	adapter->stats.crcerrs += rd32(E1000_CRCERRS);
	adapter->stats.gprc += rd32(E1000_GPRC);
	adapter->stats.gorc += rd32(E1000_GORCL);
	rd32(E1000_GORCH); /* clear GORCL */
	adapter->stats.bprc += rd32(E1000_BPRC);
	adapter->stats.mprc += rd32(E1000_MPRC);
	adapter->stats.roc += rd32(E1000_ROC);

	adapter->stats.prc64 += rd32(E1000_PRC64);
	adapter->stats.prc127 += rd32(E1000_PRC127);
	adapter->stats.prc255 += rd32(E1000_PRC255);
	adapter->stats.prc511 += rd32(E1000_PRC511);
	adapter->stats.prc1023 += rd32(E1000_PRC1023);
	adapter->stats.prc1522 += rd32(E1000_PRC1522);
	adapter->stats.symerrs += rd32(E1000_SYMERRS);
	adapter->stats.sec += rd32(E1000_SEC);

4347 4348 4349
	mpc = rd32(E1000_MPC);
	adapter->stats.mpc += mpc;
	net_stats->rx_fifo_errors += mpc;
4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363
	adapter->stats.scc += rd32(E1000_SCC);
	adapter->stats.ecol += rd32(E1000_ECOL);
	adapter->stats.mcc += rd32(E1000_MCC);
	adapter->stats.latecol += rd32(E1000_LATECOL);
	adapter->stats.dc += rd32(E1000_DC);
	adapter->stats.rlec += rd32(E1000_RLEC);
	adapter->stats.xonrxc += rd32(E1000_XONRXC);
	adapter->stats.xontxc += rd32(E1000_XONTXC);
	adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
	adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
	adapter->stats.fcruc += rd32(E1000_FCRUC);
	adapter->stats.gptc += rd32(E1000_GPTC);
	adapter->stats.gotc += rd32(E1000_GOTCL);
	rd32(E1000_GOTCH); /* clear GOTCL */
4364
	adapter->stats.rnbc += rd32(E1000_RNBC);
4365 4366 4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381
	adapter->stats.ruc += rd32(E1000_RUC);
	adapter->stats.rfc += rd32(E1000_RFC);
	adapter->stats.rjc += rd32(E1000_RJC);
	adapter->stats.tor += rd32(E1000_TORH);
	adapter->stats.tot += rd32(E1000_TOTH);
	adapter->stats.tpr += rd32(E1000_TPR);

	adapter->stats.ptc64 += rd32(E1000_PTC64);
	adapter->stats.ptc127 += rd32(E1000_PTC127);
	adapter->stats.ptc255 += rd32(E1000_PTC255);
	adapter->stats.ptc511 += rd32(E1000_PTC511);
	adapter->stats.ptc1023 += rd32(E1000_PTC1023);
	adapter->stats.ptc1522 += rd32(E1000_PTC1522);

	adapter->stats.mptc += rd32(E1000_MPTC);
	adapter->stats.bptc += rd32(E1000_BPTC);

4382 4383
	adapter->stats.tpt += rd32(E1000_TPT);
	adapter->stats.colc += rd32(E1000_COLC);
4384 4385

	adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
4386 4387 4388 4389 4390 4391 4392
	/* read internal phy specific stats */
	reg = rd32(E1000_CTRL_EXT);
	if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
		adapter->stats.rxerrc += rd32(E1000_RXERRC);
		adapter->stats.tncrs += rd32(E1000_TNCRS);
	}

4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406
	adapter->stats.tsctc += rd32(E1000_TSCTC);
	adapter->stats.tsctfc += rd32(E1000_TSCTFC);

	adapter->stats.iac += rd32(E1000_IAC);
	adapter->stats.icrxoc += rd32(E1000_ICRXOC);
	adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
	adapter->stats.icrxatc += rd32(E1000_ICRXATC);
	adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
	adapter->stats.ictxatc += rd32(E1000_ICTXATC);
	adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
	adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
	adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);

	/* Fill out the OS statistics structure */
4407 4408
	net_stats->multicast = adapter->stats.mprc;
	net_stats->collisions = adapter->stats.colc;
4409 4410 4411 4412

	/* Rx Errors */

	/* RLEC on some newer hardware can be incorrect so build
4413
	 * our own version based on RUC and ROC */
4414
	net_stats->rx_errors = adapter->stats.rxerrc +
4415 4416 4417
		adapter->stats.crcerrs + adapter->stats.algnerrc +
		adapter->stats.ruc + adapter->stats.roc +
		adapter->stats.cexterr;
4418 4419 4420 4421 4422
	net_stats->rx_length_errors = adapter->stats.ruc +
				      adapter->stats.roc;
	net_stats->rx_crc_errors = adapter->stats.crcerrs;
	net_stats->rx_frame_errors = adapter->stats.algnerrc;
	net_stats->rx_missed_errors = adapter->stats.mpc;
4423 4424

	/* Tx Errors */
4425 4426 4427 4428 4429
	net_stats->tx_errors = adapter->stats.ecol +
			       adapter->stats.latecol;
	net_stats->tx_aborted_errors = adapter->stats.ecol;
	net_stats->tx_window_errors = adapter->stats.latecol;
	net_stats->tx_carrier_errors = adapter->stats.tncrs;
4430 4431 4432 4433 4434 4435

	/* Tx Dropped needs to be maintained elsewhere */

	/* Phy Stats */
	if (hw->phy.media_type == e1000_media_type_copper) {
		if ((adapter->link_speed == SPEED_1000) &&
4436
		   (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449
			phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
			adapter->phy_stats.idle_errors += phy_tmp;
		}
	}

	/* Management Stats */
	adapter->stats.mgptc += rd32(E1000_MGTPTC);
	adapter->stats.mgprc += rd32(E1000_MGTPRC);
	adapter->stats.mgpdc += rd32(E1000_MGTPDC);
}

static irqreturn_t igb_msix_other(int irq, void *data)
{
4450
	struct igb_adapter *adapter = data;
4451
	struct e1000_hw *hw = &adapter->hw;
P
PJ Waskiewicz 已提交
4452 4453
	u32 icr = rd32(E1000_ICR);
	/* reading ICR causes bit 31 of EICR to be cleared */
4454

4455 4456 4457
	if (icr & E1000_ICR_DRSTA)
		schedule_work(&adapter->reset_task);

4458
	if (icr & E1000_ICR_DOUTSYNC) {
4459 4460 4461
		/* HW is reporting DMA is out of sync */
		adapter->stats.doosync++;
	}
4462

4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473
	/* Check for a mailbox event */
	if (icr & E1000_ICR_VMMB)
		igb_msg_task(adapter);

	if (icr & E1000_ICR_LSC) {
		hw->mac.get_link_status = 1;
		/* guard against interrupt when we're going down */
		if (!test_bit(__IGB_DOWN, &adapter->state))
			mod_timer(&adapter->watchdog_timer, jiffies + 1);
	}

4474 4475 4476 4477 4478 4479
	if (adapter->vfs_allocated_count)
		wr32(E1000_IMS, E1000_IMS_LSC |
				E1000_IMS_VMMB |
				E1000_IMS_DOUTSYNC);
	else
		wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
P
PJ Waskiewicz 已提交
4480
	wr32(E1000_EIMS, adapter->eims_other);
4481 4482 4483 4484

	return IRQ_HANDLED;
}

4485
static void igb_write_itr(struct igb_q_vector *q_vector)
4486
{
4487
	struct igb_adapter *adapter = q_vector->adapter;
4488
	u32 itr_val = q_vector->itr_val & 0x7FFC;
4489

4490 4491
	if (!q_vector->set_itr)
		return;
4492

4493 4494
	if (!itr_val)
		itr_val = 0x4;
4495

4496 4497
	if (adapter->hw.mac.type == e1000_82575)
		itr_val |= itr_val << 16;
4498
	else
4499
		itr_val |= 0x8000000;
4500

4501 4502
	writel(itr_val, q_vector->itr_register);
	q_vector->set_itr = 0;
4503 4504
}

4505
static irqreturn_t igb_msix_ring(int irq, void *data)
4506
{
4507
	struct igb_q_vector *q_vector = data;
4508

4509 4510
	/* Write the ITR value calculated from the previous interrupt. */
	igb_write_itr(q_vector);
4511

4512
	napi_schedule(&q_vector->napi);
P
PJ Waskiewicz 已提交
4513

4514
	return IRQ_HANDLED;
J
Jeb Cramer 已提交
4515 4516
}

4517
#ifdef CONFIG_IGB_DCA
4518
static void igb_update_dca(struct igb_q_vector *q_vector)
J
Jeb Cramer 已提交
4519
{
4520
	struct igb_adapter *adapter = q_vector->adapter;
J
Jeb Cramer 已提交
4521 4522 4523
	struct e1000_hw *hw = &adapter->hw;
	int cpu = get_cpu();

4524 4525 4526 4527 4528 4529 4530 4531 4532
	if (q_vector->cpu == cpu)
		goto out_no_update;

	if (q_vector->tx_ring) {
		int q = q_vector->tx_ring->reg_idx;
		u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
		if (hw->mac.type == e1000_82575) {
			dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
			dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
A
Alexander Duyck 已提交
4533
		} else {
4534 4535 4536 4537 4538 4539 4540 4541 4542 4543 4544
			dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
			dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
			              E1000_DCA_TXCTRL_CPUID_SHIFT;
		}
		dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
		wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
	}
	if (q_vector->rx_ring) {
		int q = q_vector->rx_ring->reg_idx;
		u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
		if (hw->mac.type == e1000_82575) {
A
Alexander Duyck 已提交
4545
			dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
M
Maciej Sosnowski 已提交
4546
			dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
4547 4548 4549 4550
		} else {
			dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
			dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
			              E1000_DCA_RXCTRL_CPUID_SHIFT;
A
Alexander Duyck 已提交
4551
		}
J
Jeb Cramer 已提交
4552 4553 4554 4555 4556
		dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
		dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
		dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
		wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
	}
4557 4558
	q_vector->cpu = cpu;
out_no_update:
J
Jeb Cramer 已提交
4559 4560 4561 4562 4563
	put_cpu();
}

static void igb_setup_dca(struct igb_adapter *adapter)
{
4564
	struct e1000_hw *hw = &adapter->hw;
J
Jeb Cramer 已提交
4565 4566
	int i;

4567
	if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
J
Jeb Cramer 已提交
4568 4569
		return;

4570 4571 4572
	/* Always use CB2 mode, difference is masked in the CB driver. */
	wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);

4573
	for (i = 0; i < adapter->num_q_vectors; i++) {
4574 4575
		adapter->q_vector[i]->cpu = -1;
		igb_update_dca(adapter->q_vector[i]);
J
Jeb Cramer 已提交
4576 4577 4578 4579 4580 4581 4582
	}
}

static int __igb_notify_dca(struct device *dev, void *data)
{
	struct net_device *netdev = dev_get_drvdata(dev);
	struct igb_adapter *adapter = netdev_priv(netdev);
4583
	struct pci_dev *pdev = adapter->pdev;
J
Jeb Cramer 已提交
4584 4585 4586 4587 4588 4589
	struct e1000_hw *hw = &adapter->hw;
	unsigned long event = *(unsigned long *)data;

	switch (event) {
	case DCA_PROVIDER_ADD:
		/* if already enabled, don't do it again */
4590
		if (adapter->flags & IGB_FLAG_DCA_ENABLED)
J
Jeb Cramer 已提交
4591 4592
			break;
		if (dca_add_requester(dev) == 0) {
4593
			adapter->flags |= IGB_FLAG_DCA_ENABLED;
4594
			dev_info(&pdev->dev, "DCA enabled\n");
J
Jeb Cramer 已提交
4595 4596 4597 4598 4599
			igb_setup_dca(adapter);
			break;
		}
		/* Fall Through since DCA is disabled. */
	case DCA_PROVIDER_REMOVE:
4600
		if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
J
Jeb Cramer 已提交
4601
			/* without this a class_device is left
4602
			 * hanging around in the sysfs model */
J
Jeb Cramer 已提交
4603
			dca_remove_requester(dev);
4604
			dev_info(&pdev->dev, "DCA disabled\n");
4605
			adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
A
Alexander Duyck 已提交
4606
			wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
J
Jeb Cramer 已提交
4607 4608 4609
		}
		break;
	}
4610

J
Jeb Cramer 已提交
4611
	return 0;
4612 4613
}

J
Jeb Cramer 已提交
4614 4615 4616 4617 4618 4619 4620 4621 4622 4623
static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
                          void *p)
{
	int ret_val;

	ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
	                                 __igb_notify_dca);

	return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
}
4624
#endif /* CONFIG_IGB_DCA */
4625

4626 4627 4628 4629 4630 4631 4632 4633
static void igb_ping_all_vfs(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 ping;
	int i;

	for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
		ping = E1000_PF_CONTROL_MSG;
4634
		if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4635 4636 4637 4638 4639
			ping |= E1000_VT_MSGTYPE_CTS;
		igb_write_mbx(hw, &ping, 1, i);
	}
}

4640 4641 4642 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675 4676 4677 4678
static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 vmolr = rd32(E1000_VMOLR(vf));
	struct vf_data_storage *vf_data = &adapter->vf_data[vf];

	vf_data->flags |= ~(IGB_VF_FLAG_UNI_PROMISC |
	                    IGB_VF_FLAG_MULTI_PROMISC);
	vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);

	if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
		vmolr |= E1000_VMOLR_MPME;
		*msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
	} else {
		/*
		 * if we have hashes and we are clearing a multicast promisc
		 * flag we need to write the hashes to the MTA as this step
		 * was previously skipped
		 */
		if (vf_data->num_vf_mc_hashes > 30) {
			vmolr |= E1000_VMOLR_MPME;
		} else if (vf_data->num_vf_mc_hashes) {
			int j;
			vmolr |= E1000_VMOLR_ROMPE;
			for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
				igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
		}
	}

	wr32(E1000_VMOLR(vf), vmolr);

	/* there are flags left unprocessed, likely not supported */
	if (*msgbuf & E1000_VT_MSGINFO_MASK)
		return -EINVAL;

	return 0;

}

4679 4680 4681 4682 4683 4684 4685 4686
static int igb_set_vf_multicasts(struct igb_adapter *adapter,
				  u32 *msgbuf, u32 vf)
{
	int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
	u16 *hash_list = (u16 *)&msgbuf[1];
	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
	int i;

4687
	/* salt away the number of multicast addresses assigned
4688 4689 4690 4691 4692
	 * to this VF for later use to restore when the PF multi cast
	 * list changes
	 */
	vf_data->num_vf_mc_hashes = n;

4693 4694 4695 4696 4697
	/* only up to 30 hash values supported */
	if (n > 30)
		n = 30;

	/* store the hashes for later use */
4698
	for (i = 0; i < n; i++)
4699
		vf_data->vf_mc_hashes[i] = hash_list[i];
4700 4701

	/* Flush and reset the mta with the new values */
4702
	igb_set_rx_mode(adapter->netdev);
4703 4704 4705 4706 4707 4708 4709 4710 4711 4712 4713

	return 0;
}

static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	struct vf_data_storage *vf_data;
	int i, j;

	for (i = 0; i < adapter->vfs_allocated_count; i++) {
4714 4715 4716
		u32 vmolr = rd32(E1000_VMOLR(i));
		vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);

4717
		vf_data = &adapter->vf_data[i];
4718 4719 4720 4721 4722 4723 4724 4725 4726 4727

		if ((vf_data->num_vf_mc_hashes > 30) ||
		    (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
			vmolr |= E1000_VMOLR_MPME;
		} else if (vf_data->num_vf_mc_hashes) {
			vmolr |= E1000_VMOLR_ROMPE;
			for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
				igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
		}
		wr32(E1000_VMOLR(i), vmolr);
4728 4729 4730 4731 4732 4733 4734 4735 4736 4737 4738 4739 4740 4741 4742 4743 4744 4745 4746 4747 4748 4749 4750 4751 4752 4753 4754 4755
	}
}

static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 pool_mask, reg, vid;
	int i;

	pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);

	/* Find the vlan filter for this id */
	for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
		reg = rd32(E1000_VLVF(i));

		/* remove the vf from the pool */
		reg &= ~pool_mask;

		/* if pool is empty then remove entry from vfta */
		if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
		    (reg & E1000_VLVF_VLANID_ENABLE)) {
			reg = 0;
			vid = reg & E1000_VLVF_VLANID_MASK;
			igb_vfta_set(hw, vid, false);
		}

		wr32(E1000_VLVF(i), reg);
	}
4756 4757

	adapter->vf_data[vf].vlans_enabled = 0;
4758 4759 4760 4761 4762 4763 4764
}

static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 reg, i;

4765 4766 4767 4768 4769
	/* The vlvf table only exists on 82576 hardware and newer */
	if (hw->mac.type < e1000_82576)
		return -1;

	/* we only need to do this if VMDq is enabled */
4770 4771 4772 4773 4774 4775 4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788 4789 4790 4791 4792 4793 4794 4795 4796 4797 4798
	if (!adapter->vfs_allocated_count)
		return -1;

	/* Find the vlan filter for this id */
	for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
		reg = rd32(E1000_VLVF(i));
		if ((reg & E1000_VLVF_VLANID_ENABLE) &&
		    vid == (reg & E1000_VLVF_VLANID_MASK))
			break;
	}

	if (add) {
		if (i == E1000_VLVF_ARRAY_SIZE) {
			/* Did not find a matching VLAN ID entry that was
			 * enabled.  Search for a free filter entry, i.e.
			 * one without the enable bit set
			 */
			for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
				reg = rd32(E1000_VLVF(i));
				if (!(reg & E1000_VLVF_VLANID_ENABLE))
					break;
			}
		}
		if (i < E1000_VLVF_ARRAY_SIZE) {
			/* Found an enabled/available entry */
			reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);

			/* if !enabled we need to set this up in vfta */
			if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
4799 4800
				/* add VID to filter table */
				igb_vfta_set(hw, vid, true);
4801 4802
				reg |= E1000_VLVF_VLANID_ENABLE;
			}
A
Alexander Duyck 已提交
4803 4804
			reg &= ~E1000_VLVF_VLANID_MASK;
			reg |= vid;
4805
			wr32(E1000_VLVF(i), reg);
4806 4807 4808 4809 4810 4811 4812 4813 4814 4815 4816 4817 4818 4819 4820

			/* do not modify RLPML for PF devices */
			if (vf >= adapter->vfs_allocated_count)
				return 0;

			if (!adapter->vf_data[vf].vlans_enabled) {
				u32 size;
				reg = rd32(E1000_VMOLR(vf));
				size = reg & E1000_VMOLR_RLPML_MASK;
				size += 4;
				reg &= ~E1000_VMOLR_RLPML_MASK;
				reg |= size;
				wr32(E1000_VMOLR(vf), reg);
			}

4821
			adapter->vf_data[vf].vlans_enabled++;
4822 4823 4824 4825 4826 4827 4828 4829 4830 4831 4832 4833
			return 0;
		}
	} else {
		if (i < E1000_VLVF_ARRAY_SIZE) {
			/* remove vf from the pool */
			reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
			/* if pool is empty then remove entry from vfta */
			if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
				reg = 0;
				igb_vfta_set(hw, vid, false);
			}
			wr32(E1000_VLVF(i), reg);
4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848

			/* do not modify RLPML for PF devices */
			if (vf >= adapter->vfs_allocated_count)
				return 0;

			adapter->vf_data[vf].vlans_enabled--;
			if (!adapter->vf_data[vf].vlans_enabled) {
				u32 size;
				reg = rd32(E1000_VMOLR(vf));
				size = reg & E1000_VMOLR_RLPML_MASK;
				size -= 4;
				reg &= ~E1000_VMOLR_RLPML_MASK;
				reg |= size;
				wr32(E1000_VMOLR(vf), reg);
			}
4849 4850
		}
	}
4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899
	return 0;
}

static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
{
	struct e1000_hw *hw = &adapter->hw;

	if (vid)
		wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
	else
		wr32(E1000_VMVIR(vf), 0);
}

static int igb_ndo_set_vf_vlan(struct net_device *netdev,
			       int vf, u16 vlan, u8 qos)
{
	int err = 0;
	struct igb_adapter *adapter = netdev_priv(netdev);

	if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
		return -EINVAL;
	if (vlan || qos) {
		err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
		if (err)
			goto out;
		igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
		igb_set_vmolr(adapter, vf, !vlan);
		adapter->vf_data[vf].pf_vlan = vlan;
		adapter->vf_data[vf].pf_qos = qos;
		dev_info(&adapter->pdev->dev,
			 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
		if (test_bit(__IGB_DOWN, &adapter->state)) {
			dev_warn(&adapter->pdev->dev,
				 "The VF VLAN has been set,"
				 " but the PF device is not up.\n");
			dev_warn(&adapter->pdev->dev,
				 "Bring the PF device up before"
				 " attempting to use the VF device.\n");
		}
	} else {
		igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
				   false, vf);
		igb_set_vmvir(adapter, vlan, vf);
		igb_set_vmolr(adapter, vf, true);
		adapter->vf_data[vf].pf_vlan = 0;
		adapter->vf_data[vf].pf_qos = 0;
       }
out:
       return err;
4900 4901 4902 4903 4904 4905 4906 4907 4908 4909
}

static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
{
	int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
	int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);

	return igb_vlvf_set(adapter, vid, add, vf);
}

4910
static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4911
{
4912 4913
	/* clear flags */
	adapter->vf_data[vf].flags &= ~(IGB_VF_FLAG_PF_SET_MAC);
4914
	adapter->vf_data[vf].last_nack = jiffies;
4915 4916

	/* reset offloads to defaults */
4917
	igb_set_vmolr(adapter, vf, true);
4918 4919 4920

	/* reset vlans for device */
	igb_clear_vf_vfta(adapter, vf);
4921 4922 4923 4924 4925 4926
	if (adapter->vf_data[vf].pf_vlan)
		igb_ndo_set_vf_vlan(adapter->netdev, vf,
				    adapter->vf_data[vf].pf_vlan,
				    adapter->vf_data[vf].pf_qos);
	else
		igb_clear_vf_vfta(adapter, vf);
4927 4928 4929 4930 4931

	/* reset multicast table array for vf */
	adapter->vf_data[vf].num_vf_mc_hashes = 0;

	/* Flush and reset the mta with the new values */
4932
	igb_set_rx_mode(adapter->netdev);
4933 4934
}

4935 4936 4937 4938 4939
static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
{
	unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;

	/* generate a new mac address as we were hotplug removed/added */
4940 4941
	if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
		random_ether_addr(vf_mac);
4942 4943 4944 4945 4946 4947

	/* process remaining reset events */
	igb_vf_reset(adapter, vf);
}

static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4948 4949 4950
{
	struct e1000_hw *hw = &adapter->hw;
	unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4951
	int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4952 4953 4954 4955
	u32 reg, msgbuf[3];
	u8 *addr = (u8 *)(&msgbuf[1]);

	/* process all the same items cleared in a function level reset */
4956
	igb_vf_reset(adapter, vf);
4957 4958

	/* set vf mac address */
4959
	igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4960 4961 4962 4963 4964 4965 4966

	/* enable transmit and receive for vf */
	reg = rd32(E1000_VFTE);
	wr32(E1000_VFTE, reg | (1 << vf));
	reg = rd32(E1000_VFRE);
	wr32(E1000_VFRE, reg | (1 << vf));

4967
	adapter->vf_data[vf].flags = IGB_VF_FLAG_CTS;
4968 4969 4970 4971 4972 4973 4974 4975 4976

	/* reply to reset with ack and vf mac address */
	msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
	memcpy(addr, vf_mac, 6);
	igb_write_mbx(hw, msgbuf, 3, vf);
}

static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
{
G
Greg Rose 已提交
4977 4978 4979 4980
	/*
	 * The VF MAC Address is stored in a packed array of bytes
	 * starting at the second 32 bit word of the msg array
	 */
4981 4982
	unsigned char *addr = (char *)&msg[1];
	int err = -1;
4983

4984 4985
	if (is_valid_ether_addr(addr))
		err = igb_set_vf_mac(adapter, vf, addr);
4986

4987
	return err;
4988 4989 4990 4991 4992
}

static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
{
	struct e1000_hw *hw = &adapter->hw;
4993
	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4994 4995 4996
	u32 msg = E1000_VT_MSGTYPE_NACK;

	/* if device isn't clear to send it shouldn't be reading either */
4997 4998
	if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
	    time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4999
		igb_write_mbx(hw, &msg, 1, vf);
5000
		vf_data->last_nack = jiffies;
5001 5002 5003
	}
}

5004
static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
5005
{
5006 5007
	struct pci_dev *pdev = adapter->pdev;
	u32 msgbuf[E1000_VFMAILBOX_SIZE];
5008
	struct e1000_hw *hw = &adapter->hw;
5009
	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5010 5011
	s32 retval;

5012
	retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
5013

5014 5015
	if (retval) {
		/* if receive failed revoke VF CTS stats and restart init */
5016
		dev_err(&pdev->dev, "Error receiving message from VF\n");
5017 5018 5019 5020 5021
		vf_data->flags &= ~IGB_VF_FLAG_CTS;
		if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
			return;
		goto out;
	}
5022 5023 5024

	/* this is a message we already processed, do nothing */
	if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
5025
		return;
5026 5027 5028 5029 5030 5031 5032 5033

	/*
	 * until the vf completes a reset it should not be
	 * allowed to start any configuration.
	 */

	if (msgbuf[0] == E1000_VF_RESET) {
		igb_vf_reset_msg(adapter, vf);
5034
		return;
5035 5036
	}

5037
	if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
5038 5039 5040 5041
		if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
			return;
		retval = -1;
		goto out;
5042 5043 5044 5045 5046 5047
	}

	switch ((msgbuf[0] & 0xFFFF)) {
	case E1000_VF_SET_MAC_ADDR:
		retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
		break;
5048 5049 5050
	case E1000_VF_SET_PROMISC:
		retval = igb_set_vf_promisc(adapter, msgbuf, vf);
		break;
5051 5052 5053 5054 5055 5056 5057
	case E1000_VF_SET_MULTICAST:
		retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
		break;
	case E1000_VF_SET_LPE:
		retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
		break;
	case E1000_VF_SET_VLAN:
5058 5059 5060 5061
		if (adapter->vf_data[vf].pf_vlan)
			retval = -1;
		else
			retval = igb_set_vf_vlan(adapter, msgbuf, vf);
5062 5063
		break;
	default:
5064
		dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
5065 5066 5067 5068
		retval = -1;
		break;
	}

5069 5070
	msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
out:
5071 5072 5073 5074 5075 5076 5077
	/* notify the VF of the results of what it sent us */
	if (retval)
		msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
	else
		msgbuf[0] |= E1000_VT_MSGTYPE_ACK;

	igb_write_mbx(hw, msgbuf, 1, vf);
5078
}
5079

5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097
static void igb_msg_task(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 vf;

	for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
		/* process any reset requests */
		if (!igb_check_for_rst(hw, vf))
			igb_vf_reset_event(adapter, vf);

		/* process any messages pending */
		if (!igb_check_for_msg(hw, vf))
			igb_rcv_msg_from_vf(adapter, vf);

		/* process any acks */
		if (!igb_check_for_ack(hw, vf))
			igb_rcv_ack_from_vf(adapter, vf);
	}
5098 5099
}

5100 5101 5102 5103 5104 5105 5106 5107 5108 5109 5110 5111 5112 5113 5114 5115 5116 5117 5118 5119 5120 5121 5122 5123 5124 5125 5126
/**
 *  igb_set_uta - Set unicast filter table address
 *  @adapter: board private structure
 *
 *  The unicast table address is a register array of 32-bit registers.
 *  The table is meant to be used in a way similar to how the MTA is used
 *  however due to certain limitations in the hardware it is necessary to
 *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
 *  enable bit to allow vlan tag stripping when promiscous mode is enabled
 **/
static void igb_set_uta(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	int i;

	/* The UTA table only exists on 82576 hardware and newer */
	if (hw->mac.type < e1000_82576)
		return;

	/* we only need to do this if VMDq is enabled */
	if (!adapter->vfs_allocated_count)
		return;

	for (i = 0; i < hw->mac.uta_reg_count; i++)
		array_wr32(E1000_UTA, i, ~0);
}

5127 5128 5129 5130 5131 5132 5133
/**
 * igb_intr_msi - Interrupt Handler
 * @irq: interrupt number
 * @data: pointer to a network interface device structure
 **/
static irqreturn_t igb_intr_msi(int irq, void *data)
{
5134 5135
	struct igb_adapter *adapter = data;
	struct igb_q_vector *q_vector = adapter->q_vector[0];
5136 5137 5138 5139
	struct e1000_hw *hw = &adapter->hw;
	/* read ICR disables interrupts using IAM */
	u32 icr = rd32(E1000_ICR);

5140
	igb_write_itr(q_vector);
5141

5142 5143 5144
	if (icr & E1000_ICR_DRSTA)
		schedule_work(&adapter->reset_task);

5145
	if (icr & E1000_ICR_DOUTSYNC) {
5146 5147 5148 5149
		/* HW is reporting DMA is out of sync */
		adapter->stats.doosync++;
	}

5150 5151 5152 5153 5154 5155
	if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
		hw->mac.get_link_status = 1;
		if (!test_bit(__IGB_DOWN, &adapter->state))
			mod_timer(&adapter->watchdog_timer, jiffies + 1);
	}

5156
	napi_schedule(&q_vector->napi);
5157 5158 5159 5160 5161

	return IRQ_HANDLED;
}

/**
5162
 * igb_intr - Legacy Interrupt Handler
5163 5164 5165 5166 5167
 * @irq: interrupt number
 * @data: pointer to a network interface device structure
 **/
static irqreturn_t igb_intr(int irq, void *data)
{
5168 5169
	struct igb_adapter *adapter = data;
	struct igb_q_vector *q_vector = adapter->q_vector[0];
5170 5171 5172 5173 5174 5175 5176
	struct e1000_hw *hw = &adapter->hw;
	/* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
	 * need for the IMC write */
	u32 icr = rd32(E1000_ICR);
	if (!icr)
		return IRQ_NONE;  /* Not our interrupt */

5177
	igb_write_itr(q_vector);
5178 5179 5180 5181 5182 5183

	/* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
	 * not set, then the adapter didn't send an interrupt */
	if (!(icr & E1000_ICR_INT_ASSERTED))
		return IRQ_NONE;

5184 5185 5186
	if (icr & E1000_ICR_DRSTA)
		schedule_work(&adapter->reset_task);

5187
	if (icr & E1000_ICR_DOUTSYNC) {
5188 5189 5190 5191
		/* HW is reporting DMA is out of sync */
		adapter->stats.doosync++;
	}

5192 5193 5194 5195 5196 5197 5198
	if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
		hw->mac.get_link_status = 1;
		/* guard against interrupt when we're going down */
		if (!test_bit(__IGB_DOWN, &adapter->state))
			mod_timer(&adapter->watchdog_timer, jiffies + 1);
	}

5199
	napi_schedule(&q_vector->napi);
5200 5201 5202 5203

	return IRQ_HANDLED;
}

5204
static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
5205
{
5206
	struct igb_adapter *adapter = q_vector->adapter;
5207
	struct e1000_hw *hw = &adapter->hw;
5208

5209 5210
	if ((q_vector->rx_ring && (adapter->rx_itr_setting & 3)) ||
	    (!q_vector->rx_ring && (adapter->tx_itr_setting & 3))) {
5211
		if (!adapter->msix_entries)
5212
			igb_set_itr(adapter);
5213
		else
5214
			igb_update_ring_itr(q_vector);
5215 5216
	}

5217 5218
	if (!test_bit(__IGB_DOWN, &adapter->state)) {
		if (adapter->msix_entries)
5219
			wr32(E1000_EIMS, q_vector->eims_value);
5220 5221 5222
		else
			igb_irq_enable(adapter);
	}
5223 5224
}

5225 5226 5227 5228 5229 5230
/**
 * igb_poll - NAPI Rx polling callback
 * @napi: napi polling structure
 * @budget: count of how many packets we should handle
 **/
static int igb_poll(struct napi_struct *napi, int budget)
5231
{
5232 5233 5234 5235
	struct igb_q_vector *q_vector = container_of(napi,
	                                             struct igb_q_vector,
	                                             napi);
	int tx_clean_complete = 1, work_done = 0;
5236

5237
#ifdef CONFIG_IGB_DCA
5238 5239
	if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
		igb_update_dca(q_vector);
J
Jeb Cramer 已提交
5240
#endif
5241 5242
	if (q_vector->tx_ring)
		tx_clean_complete = igb_clean_tx_irq(q_vector);
5243

5244 5245 5246 5247 5248
	if (q_vector->rx_ring)
		igb_clean_rx_irq_adv(q_vector, &work_done, budget);

	if (!tx_clean_complete)
		work_done = budget;
5249

5250
	/* If not enough Rx work done, exit the polling mode */
5251
	if (work_done < budget) {
5252
		napi_complete(napi);
5253
		igb_ring_irq_enable(q_vector);
5254 5255
	}

5256
	return work_done;
5257
}
A
Al Viro 已提交
5258

5259
/**
5260
 * igb_systim_to_hwtstamp - convert system time value to hw timestamp
5261
 * @adapter: board private structure
5262 5263 5264 5265 5266 5267 5268 5269 5270 5271 5272 5273
 * @shhwtstamps: timestamp structure to update
 * @regval: unsigned 64bit system time value.
 *
 * We need to convert the system time value stored in the RX/TXSTMP registers
 * into a hwtstamp which can be used by the upper level timestamping functions
 */
static void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
                                   struct skb_shared_hwtstamps *shhwtstamps,
                                   u64 regval)
{
	u64 ns;

5274 5275 5276 5277 5278 5279 5280
	/*
	 * The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to
	 * 24 to match clock shift we setup earlier.
	 */
	if (adapter->hw.mac.type == e1000_82580)
		regval <<= IGB_82580_TSYNC_SHIFT;

5281 5282 5283 5284 5285 5286 5287 5288 5289 5290
	ns = timecounter_cyc2time(&adapter->clock, regval);
	timecompare_update(&adapter->compare, ns);
	memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
	shhwtstamps->hwtstamp = ns_to_ktime(ns);
	shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns);
}

/**
 * igb_tx_hwtstamp - utility function which checks for TX time stamp
 * @q_vector: pointer to q_vector containing needed info
5291
 * @buffer: pointer to igb_buffer structure
5292 5293 5294 5295 5296
 *
 * If we were asked to do hardware stamping and such a time stamp is
 * available, then it must have been for this skb here because we only
 * allow only one such packet into the queue.
 */
5297
static void igb_tx_hwtstamp(struct igb_q_vector *q_vector, struct igb_buffer *buffer_info)
5298
{
5299
	struct igb_adapter *adapter = q_vector->adapter;
5300
	struct e1000_hw *hw = &adapter->hw;
5301 5302
	struct skb_shared_hwtstamps shhwtstamps;
	u64 regval;
5303

5304
	/* if skb does not support hw timestamp or TX stamp not valid exit */
5305
	if (likely(!buffer_info->shtx.hardware) ||
5306 5307 5308 5309 5310 5311 5312
	    !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID))
		return;

	regval = rd32(E1000_TXSTMPL);
	regval |= (u64)rd32(E1000_TXSTMPH) << 32;

	igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
5313
	skb_tstamp_tx(buffer_info->skb, &shhwtstamps);
5314 5315
}

5316 5317
/**
 * igb_clean_tx_irq - Reclaim resources after transmit completes
5318
 * @q_vector: pointer to q_vector containing needed info
5319 5320
 * returns true if ring is completely cleaned
 **/
5321
static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
5322
{
5323 5324
	struct igb_adapter *adapter = q_vector->adapter;
	struct igb_ring *tx_ring = q_vector->tx_ring;
5325
	struct net_device *netdev = tx_ring->netdev;
A
Alexander Duyck 已提交
5326
	struct e1000_hw *hw = &adapter->hw;
5327
	struct igb_buffer *buffer_info;
A
Alexander Duyck 已提交
5328
	union e1000_adv_tx_desc *tx_desc, *eop_desc;
5329
	unsigned int total_bytes = 0, total_packets = 0;
A
Alexander Duyck 已提交
5330 5331
	unsigned int i, eop, count = 0;
	bool cleaned = false;
5332 5333

	i = tx_ring->next_to_clean;
A
Alexander Duyck 已提交
5334 5335 5336 5337 5338 5339 5340
	eop = tx_ring->buffer_info[i].next_to_watch;
	eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);

	while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
	       (count < tx_ring->count)) {
		for (cleaned = false; !cleaned; count++) {
			tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
5341
			buffer_info = &tx_ring->buffer_info[i];
A
Alexander Duyck 已提交
5342
			cleaned = (i == eop);
5343

5344 5345
			if (buffer_info->skb) {
				total_bytes += buffer_info->bytecount;
5346
				/* gso_segs is currently only valid for tcp */
5347 5348
				total_packets += buffer_info->gso_segs;
				igb_tx_hwtstamp(q_vector, buffer_info);
5349 5350
			}

5351
			igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
A
Alexander Duyck 已提交
5352
			tx_desc->wb.status = 0;
5353 5354 5355 5356 5357

			i++;
			if (i == tx_ring->count)
				i = 0;
		}
A
Alexander Duyck 已提交
5358 5359 5360 5361
		eop = tx_ring->buffer_info[i].next_to_watch;
		eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
	}

5362 5363
	tx_ring->next_to_clean = i;

5364
	if (unlikely(count &&
5365
		     netif_carrier_ok(netdev) &&
5366
		     igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
5367 5368 5369 5370
		/* Make sure that anybody stopping the queue after this
		 * sees the new next_to_clean.
		 */
		smp_mb();
5371 5372 5373
		if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
		    !(test_bit(__IGB_DOWN, &adapter->state))) {
			netif_wake_subqueue(netdev, tx_ring->queue_index);
5374
			tx_ring->tx_stats.restart_queue++;
5375
		}
5376 5377 5378 5379 5380 5381 5382 5383
	}

	if (tx_ring->detect_tx_hung) {
		/* Detect a transmit hang in hardware, this serializes the
		 * check with the clearing of time_stamp and movement of i */
		tx_ring->detect_tx_hung = false;
		if (tx_ring->buffer_info[i].time_stamp &&
		    time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
5384 5385
			       (adapter->tx_timeout_factor * HZ)) &&
		    !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
5386 5387

			/* detected Tx unit hang */
5388
			dev_err(tx_ring->dev,
5389
				"Detected Tx Unit Hang\n"
A
Alexander Duyck 已提交
5390
				"  Tx Queue             <%d>\n"
5391 5392 5393 5394 5395 5396
				"  TDH                  <%x>\n"
				"  TDT                  <%x>\n"
				"  next_to_use          <%x>\n"
				"  next_to_clean        <%x>\n"
				"buffer_info[next_to_clean]\n"
				"  time_stamp           <%lx>\n"
A
Alexander Duyck 已提交
5397
				"  next_to_watch        <%x>\n"
5398 5399
				"  jiffies              <%lx>\n"
				"  desc.status          <%x>\n",
A
Alexander Duyck 已提交
5400
				tx_ring->queue_index,
5401 5402
				readl(tx_ring->head),
				readl(tx_ring->tail),
5403 5404
				tx_ring->next_to_use,
				tx_ring->next_to_clean,
5405
				tx_ring->buffer_info[eop].time_stamp,
A
Alexander Duyck 已提交
5406
				eop,
5407
				jiffies,
A
Alexander Duyck 已提交
5408
				eop_desc->wb.status);
5409
			netif_stop_subqueue(netdev, tx_ring->queue_index);
5410 5411 5412 5413
		}
	}
	tx_ring->total_bytes += total_bytes;
	tx_ring->total_packets += total_packets;
5414 5415
	tx_ring->tx_stats.bytes += total_bytes;
	tx_ring->tx_stats.packets += total_packets;
A
Alexander Duyck 已提交
5416
	return (count < tx_ring->count);
5417 5418 5419 5420
}

/**
 * igb_receive_skb - helper function to handle rx indications
5421 5422 5423
 * @q_vector: structure containing interrupt and ring information
 * @skb: packet to send up
 * @vlan_tag: vlan tag for packet
5424
 **/
5425 5426 5427 5428 5429 5430
static void igb_receive_skb(struct igb_q_vector *q_vector,
                            struct sk_buff *skb,
                            u16 vlan_tag)
{
	struct igb_adapter *adapter = q_vector->adapter;

5431
	if (vlan_tag && adapter->vlgrp)
5432 5433
		vlan_gro_receive(&q_vector->napi, adapter->vlgrp,
		                 vlan_tag, skb);
5434
	else
5435
		napi_gro_receive(&q_vector->napi, skb);
5436 5437
}

5438
static inline void igb_rx_checksum_adv(struct igb_ring *ring,
5439 5440 5441 5442 5443
				       u32 status_err, struct sk_buff *skb)
{
	skb->ip_summed = CHECKSUM_NONE;

	/* Ignore Checksum bit is set or checksum is disabled through ethtool */
5444 5445
	if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) ||
	     (status_err & E1000_RXD_STAT_IXSM))
5446
		return;
5447

5448 5449 5450
	/* TCP/UDP checksum error bit is set */
	if (status_err &
	    (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
5451 5452 5453 5454 5455
		/*
		 * work around errata with sctp packets where the TCPE aka
		 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
		 * packets, (aka let the stack check the crc32c)
		 */
5456 5457
		if ((skb->len == 60) &&
		    (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM))
5458
			ring->rx_stats.csum_err++;
5459

5460 5461 5462 5463 5464 5465 5466
		/* let the stack verify checksum errors */
		return;
	}
	/* It must be a TCP or UDP packet with a valid checksum */
	if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
		skb->ip_summed = CHECKSUM_UNNECESSARY;

5467
	dev_dbg(ring->dev, "cksum success: bits %08X\n", status_err);
5468 5469
}

N
Nick Nunley 已提交
5470
static void igb_rx_hwtstamp(struct igb_q_vector *q_vector, u32 staterr,
5471 5472 5473 5474 5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487
                                   struct sk_buff *skb)
{
	struct igb_adapter *adapter = q_vector->adapter;
	struct e1000_hw *hw = &adapter->hw;
	u64 regval;

	/*
	 * If this bit is set, then the RX registers contain the time stamp. No
	 * other packet will be time stamped until we read these registers, so
	 * read the registers to make them available again. Because only one
	 * packet can be time stamped at a time, we know that the register
	 * values must belong to this one here and therefore we don't need to
	 * compare any of the additional attributes stored for it.
	 *
	 * If nothing went wrong, then it should have a skb_shared_tx that we
	 * can turn into a skb_shared_hwtstamps.
	 */
N
Nick Nunley 已提交
5488 5489 5490 5491 5492 5493 5494 5495
	if (staterr & E1000_RXDADV_STAT_TSIP) {
		u32 *stamp = (u32 *)skb->data;
		regval = le32_to_cpu(*(stamp + 2));
		regval |= (u64)le32_to_cpu(*(stamp + 3)) << 32;
		skb_pull(skb, IGB_TS_HDR_LEN);
	} else {
		if(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
			return;
5496

N
Nick Nunley 已提交
5497 5498 5499
		regval = rd32(E1000_RXSTMPL);
		regval |= (u64)rd32(E1000_RXSTMPH) << 32;
	}
5500 5501 5502

	igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
}
5503
static inline u16 igb_get_hlen(struct igb_ring *rx_ring,
5504 5505 5506 5507 5508 5509 5510 5511
                               union e1000_adv_rx_desc *rx_desc)
{
	/* HW will not DMA in data larger than the given buffer, even if it
	 * parses the (NFS, of course) header to be larger.  In that case, it
	 * fills the header buffer and spills the rest into the page.
	 */
	u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
	           E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
5512 5513
	if (hlen > rx_ring->rx_buffer_len)
		hlen = rx_ring->rx_buffer_len;
5514 5515 5516
	return hlen;
}

5517 5518
static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector,
                                 int *work_done, int budget)
5519
{
5520
	struct igb_ring *rx_ring = q_vector->rx_ring;
5521
	struct net_device *netdev = rx_ring->netdev;
5522
	struct device *dev = rx_ring->dev;
5523 5524 5525 5526 5527
	union e1000_adv_rx_desc *rx_desc , *next_rxd;
	struct igb_buffer *buffer_info , *next_buffer;
	struct sk_buff *skb;
	bool cleaned = false;
	int cleaned_count = 0;
5528
	int current_node = numa_node_id();
5529
	unsigned int total_bytes = 0, total_packets = 0;
5530
	unsigned int i;
5531 5532
	u32 staterr;
	u16 length;
5533
	u16 vlan_tag;
5534 5535

	i = rx_ring->next_to_clean;
5536
	buffer_info = &rx_ring->buffer_info[i];
5537 5538 5539 5540 5541 5542 5543 5544
	rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
	staterr = le32_to_cpu(rx_desc->wb.upper.status_error);

	while (staterr & E1000_RXD_STAT_DD) {
		if (*work_done >= budget)
			break;
		(*work_done)++;

5545 5546 5547 5548 5549 5550 5551
		skb = buffer_info->skb;
		prefetch(skb->data - NET_IP_ALIGN);
		buffer_info->skb = NULL;

		i++;
		if (i == rx_ring->count)
			i = 0;
5552

5553 5554 5555
		next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
		prefetch(next_rxd);
		next_buffer = &rx_ring->buffer_info[i];
5556 5557 5558 5559 5560

		length = le16_to_cpu(rx_desc->wb.upper.length);
		cleaned = true;
		cleaned_count++;

5561
		if (buffer_info->dma) {
5562
			dma_unmap_single(dev, buffer_info->dma,
5563
					 rx_ring->rx_buffer_len,
5564
					 DMA_FROM_DEVICE);
J
Jesse Brandeburg 已提交
5565
			buffer_info->dma = 0;
5566
			if (rx_ring->rx_buffer_len >= IGB_RXBUFFER_1024) {
A
Alexander Duyck 已提交
5567 5568 5569
				skb_put(skb, length);
				goto send_up;
			}
5570
			skb_put(skb, igb_get_hlen(rx_ring, rx_desc));
5571 5572 5573
		}

		if (length) {
5574 5575
			dma_unmap_page(dev, buffer_info->page_dma,
				       PAGE_SIZE / 2, DMA_FROM_DEVICE);
5576
			buffer_info->page_dma = 0;
5577

K
Koki Sanagi 已提交
5578
			skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
5579 5580 5581 5582
						buffer_info->page,
						buffer_info->page_offset,
						length);

5583 5584
			if ((page_count(buffer_info->page) != 1) ||
			    (page_to_nid(buffer_info->page) != current_node))
5585 5586 5587
				buffer_info->page = NULL;
			else
				get_page(buffer_info->page);
5588 5589 5590

			skb->len += length;
			skb->data_len += length;
5591
			skb->truesize += length;
5592 5593
		}

5594
		if (!(staterr & E1000_RXD_STAT_EOP)) {
5595 5596 5597 5598
			buffer_info->skb = next_buffer->skb;
			buffer_info->dma = next_buffer->dma;
			next_buffer->skb = skb;
			next_buffer->dma = 0;
5599 5600
			goto next_desc;
		}
5601
send_up:
5602 5603 5604 5605 5606
		if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
			dev_kfree_skb_irq(skb);
			goto next_desc;
		}

N
Nick Nunley 已提交
5607 5608
		if (staterr & (E1000_RXDADV_STAT_TSIP | E1000_RXDADV_STAT_TS))
			igb_rx_hwtstamp(q_vector, staterr, skb);
5609 5610 5611
		total_bytes += skb->len;
		total_packets++;

5612
		igb_rx_checksum_adv(rx_ring, staterr, skb);
5613 5614

		skb->protocol = eth_type_trans(skb, netdev);
5615 5616 5617 5618
		skb_record_rx_queue(skb, rx_ring->queue_index);

		vlan_tag = ((staterr & E1000_RXD_STAT_VP) ?
		            le16_to_cpu(rx_desc->wb.upper.vlan) : 0);
5619

5620
		igb_receive_skb(q_vector, skb, vlan_tag);
5621 5622 5623 5624 5625 5626

next_desc:
		rx_desc->wb.upper.status_error = 0;

		/* return some buffers to hardware, one at a time is too slow */
		if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
5627
			igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
5628 5629 5630 5631 5632 5633 5634 5635
			cleaned_count = 0;
		}

		/* use prefetched values */
		rx_desc = next_rxd;
		buffer_info = next_buffer;
		staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
	}
5636

5637
	rx_ring->next_to_clean = i;
5638
	cleaned_count = igb_desc_unused(rx_ring);
5639 5640

	if (cleaned_count)
5641
		igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
5642 5643 5644 5645 5646 5647 5648 5649 5650 5651 5652 5653

	rx_ring->total_packets += total_packets;
	rx_ring->total_bytes += total_bytes;
	rx_ring->rx_stats.packets += total_packets;
	rx_ring->rx_stats.bytes += total_bytes;
	return cleaned;
}

/**
 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
 * @adapter: address of board private structure
 **/
5654
void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, int cleaned_count)
5655
{
5656
	struct net_device *netdev = rx_ring->netdev;
5657 5658 5659 5660
	union e1000_adv_rx_desc *rx_desc;
	struct igb_buffer *buffer_info;
	struct sk_buff *skb;
	unsigned int i;
5661
	int bufsz;
5662 5663 5664 5665

	i = rx_ring->next_to_use;
	buffer_info = &rx_ring->buffer_info[i];

5666
	bufsz = rx_ring->rx_buffer_len;
5667

5668 5669 5670
	while (cleaned_count--) {
		rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);

A
Alexander Duyck 已提交
5671
		if ((bufsz < IGB_RXBUFFER_1024) && !buffer_info->page_dma) {
5672
			if (!buffer_info->page) {
5673
				buffer_info->page = netdev_alloc_page(netdev);
5674
				if (!buffer_info->page) {
5675
					rx_ring->rx_stats.alloc_failed++;
5676 5677 5678 5679 5680
					goto no_buffers;
				}
				buffer_info->page_offset = 0;
			} else {
				buffer_info->page_offset ^= PAGE_SIZE / 2;
5681 5682
			}
			buffer_info->page_dma =
5683
				dma_map_page(rx_ring->dev, buffer_info->page,
5684 5685
					     buffer_info->page_offset,
					     PAGE_SIZE / 2,
5686 5687 5688
					     DMA_FROM_DEVICE);
			if (dma_mapping_error(rx_ring->dev,
					      buffer_info->page_dma)) {
5689 5690 5691 5692
				buffer_info->page_dma = 0;
				rx_ring->rx_stats.alloc_failed++;
				goto no_buffers;
			}
5693 5694
		}

5695 5696
		skb = buffer_info->skb;
		if (!skb) {
5697
			skb = netdev_alloc_skb_ip_align(netdev, bufsz);
5698
			if (!skb) {
5699
				rx_ring->rx_stats.alloc_failed++;
5700 5701 5702 5703
				goto no_buffers;
			}

			buffer_info->skb = skb;
5704 5705
		}
		if (!buffer_info->dma) {
5706
			buffer_info->dma = dma_map_single(rx_ring->dev,
5707
			                                  skb->data,
5708
							  bufsz,
5709 5710 5711
							  DMA_FROM_DEVICE);
			if (dma_mapping_error(rx_ring->dev,
					      buffer_info->dma)) {
5712 5713 5714 5715
				buffer_info->dma = 0;
				rx_ring->rx_stats.alloc_failed++;
				goto no_buffers;
			}
5716 5717 5718
		}
		/* Refresh the desc even if buffer_addrs didn't change because
		 * each write-back erases this info. */
A
Alexander Duyck 已提交
5719
		if (bufsz < IGB_RXBUFFER_1024) {
5720 5721 5722 5723
			rx_desc->read.pkt_addr =
			     cpu_to_le64(buffer_info->page_dma);
			rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
		} else {
5724
			rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma);
5725 5726 5727 5728 5729 5730 5731 5732 5733 5734 5735 5736 5737 5738 5739 5740 5741 5742 5743 5744 5745 5746
			rx_desc->read.hdr_addr = 0;
		}

		i++;
		if (i == rx_ring->count)
			i = 0;
		buffer_info = &rx_ring->buffer_info[i];
	}

no_buffers:
	if (rx_ring->next_to_use != i) {
		rx_ring->next_to_use = i;
		if (i == 0)
			i = (rx_ring->count - 1);
		else
			i--;

		/* Force memory writes to complete before letting h/w
		 * know there are new descriptors to fetch.  (Only
		 * applicable for weak-ordered memory model archs,
		 * such as IA-64). */
		wmb();
5747
		writel(i, rx_ring->tail);
5748 5749 5750 5751 5752 5753 5754 5755 5756 5757 5758 5759 5760 5761 5762 5763 5764 5765 5766 5767 5768 5769
	}
}

/**
 * igb_mii_ioctl -
 * @netdev:
 * @ifreq:
 * @cmd:
 **/
static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct mii_ioctl_data *data = if_mii(ifr);

	if (adapter->hw.phy.media_type != e1000_media_type_copper)
		return -EOPNOTSUPP;

	switch (cmd) {
	case SIOCGMIIPHY:
		data->phy_id = adapter->hw.phy.addr;
		break;
	case SIOCGMIIREG:
5770 5771
		if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
		                     &data->val_out))
5772 5773 5774 5775 5776 5777 5778 5779 5780
			return -EIO;
		break;
	case SIOCSMIIREG:
	default:
		return -EOPNOTSUPP;
	}
	return 0;
}

5781 5782 5783 5784 5785 5786
/**
 * igb_hwtstamp_ioctl - control hardware time stamping
 * @netdev:
 * @ifreq:
 * @cmd:
 *
5787 5788 5789 5790 5791 5792 5793 5794 5795 5796 5797 5798
 * Outgoing time stamping can be enabled and disabled. Play nice and
 * disable it when requested, although it shouldn't case any overhead
 * when no packet needs it. At most one packet in the queue may be
 * marked for time stamping, otherwise it would be impossible to tell
 * for sure to which packet the hardware time stamp belongs.
 *
 * Incoming time stamping has to be configured via the hardware
 * filters. Not all combinations are supported, in particular event
 * type has to be specified. Matching the kind of event packet is
 * not supported, with the exception of "all V2 events regardless of
 * level 2 or 4".
 *
5799 5800 5801 5802
 **/
static int igb_hwtstamp_ioctl(struct net_device *netdev,
			      struct ifreq *ifr, int cmd)
{
5803 5804
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
5805
	struct hwtstamp_config config;
5806 5807
	u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
	u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
5808
	u32 tsync_rx_cfg = 0;
5809 5810
	bool is_l4 = false;
	bool is_l2 = false;
5811
	u32 regval;
5812 5813 5814 5815 5816 5817 5818 5819

	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
		return -EFAULT;

	/* reserved for future extensions */
	if (config.flags)
		return -EINVAL;

5820 5821
	switch (config.tx_type) {
	case HWTSTAMP_TX_OFF:
5822
		tsync_tx_ctl = 0;
5823 5824 5825 5826 5827 5828 5829 5830
	case HWTSTAMP_TX_ON:
		break;
	default:
		return -ERANGE;
	}

	switch (config.rx_filter) {
	case HWTSTAMP_FILTER_NONE:
5831
		tsync_rx_ctl = 0;
5832 5833 5834 5835 5836 5837 5838 5839 5840 5841
		break;
	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
	case HWTSTAMP_FILTER_ALL:
		/*
		 * register TSYNCRXCFG must be set, therefore it is not
		 * possible to time stamp both Sync and Delay_Req messages
		 * => fall back to time stamping all packets
		 */
5842
		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
5843 5844 5845
		config.rx_filter = HWTSTAMP_FILTER_ALL;
		break;
	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5846
		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
5847
		tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
5848
		is_l4 = true;
5849 5850
		break;
	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5851
		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
5852
		tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
5853
		is_l4 = true;
5854 5855 5856
		break;
	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5857
		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5858
		tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
5859 5860
		is_l2 = true;
		is_l4 = true;
5861 5862 5863 5864
		config.rx_filter = HWTSTAMP_FILTER_SOME;
		break;
	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5865
		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5866
		tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
5867 5868
		is_l2 = true;
		is_l4 = true;
5869 5870 5871 5872 5873
		config.rx_filter = HWTSTAMP_FILTER_SOME;
		break;
	case HWTSTAMP_FILTER_PTP_V2_EVENT:
	case HWTSTAMP_FILTER_PTP_V2_SYNC:
	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5874
		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
5875
		config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
5876
		is_l2 = true;
5877 5878 5879 5880 5881
		break;
	default:
		return -ERANGE;
	}

5882 5883 5884 5885 5886 5887
	if (hw->mac.type == e1000_82575) {
		if (tsync_rx_ctl | tsync_tx_ctl)
			return -EINVAL;
		return 0;
	}

N
Nick Nunley 已提交
5888 5889 5890 5891 5892 5893 5894 5895 5896 5897
	/*
	 * Per-packet timestamping only works if all packets are
	 * timestamped, so enable timestamping in all packets as
	 * long as one rx filter was configured.
	 */
	if ((hw->mac.type == e1000_82580) && tsync_rx_ctl) {
		tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
	}

5898 5899
	/* enable/disable TX */
	regval = rd32(E1000_TSYNCTXCTL);
5900 5901
	regval &= ~E1000_TSYNCTXCTL_ENABLED;
	regval |= tsync_tx_ctl;
5902 5903
	wr32(E1000_TSYNCTXCTL, regval);

5904
	/* enable/disable RX */
5905
	regval = rd32(E1000_TSYNCRXCTL);
5906 5907
	regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
	regval |= tsync_rx_ctl;
5908 5909
	wr32(E1000_TSYNCRXCTL, regval);

5910 5911
	/* define which PTP packets are time stamped */
	wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
5912

5913 5914 5915 5916 5917 5918 5919 5920 5921 5922 5923 5924 5925 5926 5927 5928 5929 5930 5931 5932 5933 5934 5935 5936 5937 5938 5939 5940 5941 5942
	/* define ethertype filter for timestamped packets */
	if (is_l2)
		wr32(E1000_ETQF(3),
		                (E1000_ETQF_FILTER_ENABLE | /* enable filter */
		                 E1000_ETQF_1588 | /* enable timestamping */
		                 ETH_P_1588));     /* 1588 eth protocol type */
	else
		wr32(E1000_ETQF(3), 0);

#define PTP_PORT 319
	/* L4 Queue Filter[3]: filter by destination port and protocol */
	if (is_l4) {
		u32 ftqf = (IPPROTO_UDP /* UDP */
			| E1000_FTQF_VF_BP /* VF not compared */
			| E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
			| E1000_FTQF_MASK); /* mask all inputs */
		ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */

		wr32(E1000_IMIR(3), htons(PTP_PORT));
		wr32(E1000_IMIREXT(3),
		     (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
		if (hw->mac.type == e1000_82576) {
			/* enable source port check */
			wr32(E1000_SPQF(3), htons(PTP_PORT));
			ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
		}
		wr32(E1000_FTQF(3), ftqf);
	} else {
		wr32(E1000_FTQF(3), E1000_FTQF_MASK);
	}
5943 5944 5945 5946 5947 5948 5949
	wrfl();

	adapter->hwtstamp_config = config;

	/* clear TX/RX time stamp registers, just to be sure */
	regval = rd32(E1000_TXSTMPH);
	regval = rd32(E1000_RXSTMPH);
5950

5951 5952
	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
		-EFAULT : 0;
5953 5954
}

5955 5956 5957 5958 5959 5960 5961 5962 5963 5964 5965 5966 5967
/**
 * igb_ioctl -
 * @netdev:
 * @ifreq:
 * @cmd:
 **/
static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
{
	switch (cmd) {
	case SIOCGMIIPHY:
	case SIOCGMIIREG:
	case SIOCSMIIREG:
		return igb_mii_ioctl(netdev, ifr, cmd);
5968 5969
	case SIOCSHWTSTAMP:
		return igb_hwtstamp_ioctl(netdev, ifr, cmd);
5970 5971 5972 5973 5974
	default:
		return -EOPNOTSUPP;
	}
}

5975 5976 5977 5978 5979 5980 5981 5982 5983 5984 5985 5986 5987 5988 5989 5990 5991 5992 5993 5994 5995 5996 5997 5998 5999 6000 6001 6002
s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
{
	struct igb_adapter *adapter = hw->back;
	u16 cap_offset;

	cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
	if (!cap_offset)
		return -E1000_ERR_CONFIG;

	pci_read_config_word(adapter->pdev, cap_offset + reg, value);

	return 0;
}

s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
{
	struct igb_adapter *adapter = hw->back;
	u16 cap_offset;

	cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
	if (!cap_offset)
		return -E1000_ERR_CONFIG;

	pci_write_config_word(adapter->pdev, cap_offset + reg, *value);

	return 0;
}

6003 6004 6005 6006 6007 6008 6009 6010 6011 6012 6013 6014 6015 6016 6017 6018
static void igb_vlan_rx_register(struct net_device *netdev,
				 struct vlan_group *grp)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
	u32 ctrl, rctl;

	igb_irq_disable(adapter);
	adapter->vlgrp = grp;

	if (grp) {
		/* enable VLAN tag insert/strip */
		ctrl = rd32(E1000_CTRL);
		ctrl |= E1000_CTRL_VME;
		wr32(E1000_CTRL, ctrl);

6019
		/* Disable CFI check */
6020 6021 6022 6023 6024 6025 6026 6027 6028 6029
		rctl = rd32(E1000_RCTL);
		rctl &= ~E1000_RCTL_CFIEN;
		wr32(E1000_RCTL, rctl);
	} else {
		/* disable VLAN tag insert/strip */
		ctrl = rd32(E1000_CTRL);
		ctrl &= ~E1000_CTRL_VME;
		wr32(E1000_CTRL, ctrl);
	}

6030 6031
	igb_rlpml_set(adapter);

6032 6033 6034 6035 6036 6037 6038 6039
	if (!test_bit(__IGB_DOWN, &adapter->state))
		igb_irq_enable(adapter);
}

static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
6040
	int pf_id = adapter->vfs_allocated_count;
6041

6042 6043
	/* attempt to add filter to vlvf array */
	igb_vlvf_set(adapter, vid, true, pf_id);
6044

6045 6046
	/* add the filter since PF can receive vlans w/o entry in vlvf */
	igb_vfta_set(hw, vid, true);
6047 6048 6049 6050 6051 6052
}

static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
6053
	int pf_id = adapter->vfs_allocated_count;
6054
	s32 err;
6055 6056 6057 6058 6059 6060 6061

	igb_irq_disable(adapter);
	vlan_group_set_device(adapter->vlgrp, vid, NULL);

	if (!test_bit(__IGB_DOWN, &adapter->state))
		igb_irq_enable(adapter);

6062 6063
	/* remove vlan from VLVF table array */
	err = igb_vlvf_set(adapter, vid, false, pf_id);
6064

6065 6066
	/* if vid was not present in VLVF just remove it from table */
	if (err)
6067
		igb_vfta_set(hw, vid, false);
6068 6069 6070 6071 6072 6073 6074 6075 6076 6077 6078 6079 6080 6081 6082 6083 6084 6085
}

static void igb_restore_vlan(struct igb_adapter *adapter)
{
	igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);

	if (adapter->vlgrp) {
		u16 vid;
		for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
			if (!vlan_group_get_device(adapter->vlgrp, vid))
				continue;
			igb_vlan_rx_add_vid(adapter->netdev, vid);
		}
	}
}

int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
{
6086
	struct pci_dev *pdev = adapter->pdev;
6087 6088 6089 6090 6091 6092 6093 6094 6095 6096 6097 6098 6099 6100 6101 6102 6103 6104 6105 6106 6107 6108 6109
	struct e1000_mac_info *mac = &adapter->hw.mac;

	mac->autoneg = 0;

	switch (spddplx) {
	case SPEED_10 + DUPLEX_HALF:
		mac->forced_speed_duplex = ADVERTISE_10_HALF;
		break;
	case SPEED_10 + DUPLEX_FULL:
		mac->forced_speed_duplex = ADVERTISE_10_FULL;
		break;
	case SPEED_100 + DUPLEX_HALF:
		mac->forced_speed_duplex = ADVERTISE_100_HALF;
		break;
	case SPEED_100 + DUPLEX_FULL:
		mac->forced_speed_duplex = ADVERTISE_100_FULL;
		break;
	case SPEED_1000 + DUPLEX_FULL:
		mac->autoneg = 1;
		adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
		break;
	case SPEED_1000 + DUPLEX_HALF: /* not supported */
	default:
6110
		dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6111 6112 6113 6114 6115
		return -EINVAL;
	}
	return 0;
}

6116
static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
6117 6118 6119 6120
{
	struct net_device *netdev = pci_get_drvdata(pdev);
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
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6121
	u32 ctrl, rctl, status;
6122 6123 6124 6125 6126 6127 6128
	u32 wufc = adapter->wol;
#ifdef CONFIG_PM
	int retval = 0;
#endif

	netif_device_detach(netdev);

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6129 6130 6131
	if (netif_running(netdev))
		igb_close(netdev);

6132
	igb_clear_interrupt_scheme(adapter);
6133 6134 6135 6136 6137 6138 6139 6140 6141 6142 6143 6144 6145

#ifdef CONFIG_PM
	retval = pci_save_state(pdev);
	if (retval)
		return retval;
#endif

	status = rd32(E1000_STATUS);
	if (status & E1000_STATUS_LU)
		wufc &= ~E1000_WUFC_LNKC;

	if (wufc) {
		igb_setup_rctl(adapter);
6146
		igb_set_rx_mode(netdev);
6147 6148 6149 6150 6151 6152 6153 6154 6155 6156 6157 6158 6159 6160 6161 6162 6163

		/* turn on all-multi mode if wake on multicast is enabled */
		if (wufc & E1000_WUFC_MC) {
			rctl = rd32(E1000_RCTL);
			rctl |= E1000_RCTL_MPE;
			wr32(E1000_RCTL, rctl);
		}

		ctrl = rd32(E1000_CTRL);
		/* advertise wake from D3Cold */
		#define E1000_CTRL_ADVD3WUC 0x00100000
		/* phy power management enable */
		#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
		ctrl |= E1000_CTRL_ADVD3WUC;
		wr32(E1000_CTRL, ctrl);

		/* Allow time for pending master requests to run */
6164
		igb_disable_pcie_master(hw);
6165 6166 6167 6168 6169 6170 6171 6172

		wr32(E1000_WUC, E1000_WUC_PME_EN);
		wr32(E1000_WUFC, wufc);
	} else {
		wr32(E1000_WUC, 0);
		wr32(E1000_WUFC, 0);
	}

6173 6174
	*enable_wake = wufc || adapter->en_mng_pt;
	if (!*enable_wake)
6175 6176 6177
		igb_power_down_link(adapter);
	else
		igb_power_up_link(adapter);
6178 6179 6180 6181 6182 6183 6184 6185 6186 6187 6188

	/* Release control of h/w to f/w.  If f/w is AMT enabled, this
	 * would have already happened in close and is redundant. */
	igb_release_hw_control(adapter);

	pci_disable_device(pdev);

	return 0;
}

#ifdef CONFIG_PM
6189 6190 6191 6192 6193 6194 6195 6196 6197 6198 6199 6200 6201 6202 6203 6204 6205 6206 6207
static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
{
	int retval;
	bool wake;

	retval = __igb_shutdown(pdev, &wake);
	if (retval)
		return retval;

	if (wake) {
		pci_prepare_to_sleep(pdev);
	} else {
		pci_wake_from_d3(pdev, false);
		pci_set_power_state(pdev, PCI_D3hot);
	}

	return 0;
}

6208 6209 6210 6211 6212 6213 6214 6215 6216
static int igb_resume(struct pci_dev *pdev)
{
	struct net_device *netdev = pci_get_drvdata(pdev);
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
	u32 err;

	pci_set_power_state(pdev, PCI_D0);
	pci_restore_state(pdev);
6217
	pci_save_state(pdev);
T
Taku Izumi 已提交
6218

6219
	err = pci_enable_device_mem(pdev);
6220 6221 6222 6223 6224 6225 6226 6227 6228 6229
	if (err) {
		dev_err(&pdev->dev,
			"igb: Cannot enable PCI device from suspend\n");
		return err;
	}
	pci_set_master(pdev);

	pci_enable_wake(pdev, PCI_D3hot, 0);
	pci_enable_wake(pdev, PCI_D3cold, 0);

6230
	if (igb_init_interrupt_scheme(adapter)) {
A
Alexander Duyck 已提交
6231 6232
		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
		return -ENOMEM;
6233 6234 6235
	}

	igb_reset(adapter);
6236 6237 6238 6239 6240

	/* let the f/w know that the h/w is now under the control of the
	 * driver. */
	igb_get_hw_control(adapter);

6241 6242
	wr32(E1000_WUS, ~0);

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6243 6244 6245 6246 6247
	if (netif_running(netdev)) {
		err = igb_open(netdev);
		if (err)
			return err;
	}
6248 6249 6250 6251 6252 6253 6254 6255 6256

	netif_device_attach(netdev);

	return 0;
}
#endif

static void igb_shutdown(struct pci_dev *pdev)
{
6257 6258 6259 6260 6261 6262 6263 6264
	bool wake;

	__igb_shutdown(pdev, &wake);

	if (system_state == SYSTEM_POWER_OFF) {
		pci_wake_from_d3(pdev, wake);
		pci_set_power_state(pdev, PCI_D3hot);
	}
6265 6266 6267 6268 6269 6270 6271 6272 6273 6274 6275
}

#ifdef CONFIG_NET_POLL_CONTROLLER
/*
 * Polling 'interrupt' - used by things like netconsole to send skbs
 * without having to re-enable interrupts. It's not called while
 * the interrupt routine is executing.
 */
static void igb_netpoll(struct net_device *netdev)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
6276
	struct e1000_hw *hw = &adapter->hw;
6277 6278
	int i;

6279
	if (!adapter->msix_entries) {
6280
		struct igb_q_vector *q_vector = adapter->q_vector[0];
6281
		igb_irq_disable(adapter);
6282
		napi_schedule(&q_vector->napi);
6283 6284
		return;
	}
6285

6286 6287 6288 6289
	for (i = 0; i < adapter->num_q_vectors; i++) {
		struct igb_q_vector *q_vector = adapter->q_vector[i];
		wr32(E1000_EIMC, q_vector->eims_value);
		napi_schedule(&q_vector->napi);
6290
	}
6291 6292 6293 6294 6295 6296 6297 6298 6299 6300 6301 6302 6303 6304 6305 6306 6307 6308 6309
}
#endif /* CONFIG_NET_POLL_CONTROLLER */

/**
 * igb_io_error_detected - called when PCI error is detected
 * @pdev: Pointer to PCI device
 * @state: The current pci connection state
 *
 * This function is called after a PCI bus error affecting
 * this device has been detected.
 */
static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
					      pci_channel_state_t state)
{
	struct net_device *netdev = pci_get_drvdata(pdev);
	struct igb_adapter *adapter = netdev_priv(netdev);

	netif_device_detach(netdev);

6310 6311 6312
	if (state == pci_channel_io_perm_failure)
		return PCI_ERS_RESULT_DISCONNECT;

6313 6314 6315 6316 6317 6318 6319 6320 6321 6322 6323 6324 6325 6326 6327 6328 6329 6330 6331 6332
	if (netif_running(netdev))
		igb_down(adapter);
	pci_disable_device(pdev);

	/* Request a slot slot reset. */
	return PCI_ERS_RESULT_NEED_RESET;
}

/**
 * igb_io_slot_reset - called after the pci bus has been reset.
 * @pdev: Pointer to PCI device
 *
 * Restart the card from scratch, as if from a cold-boot. Implementation
 * resembles the first-half of the igb_resume routine.
 */
static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
{
	struct net_device *netdev = pci_get_drvdata(pdev);
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
6333
	pci_ers_result_t result;
T
Taku Izumi 已提交
6334
	int err;
6335

6336
	if (pci_enable_device_mem(pdev)) {
6337 6338
		dev_err(&pdev->dev,
			"Cannot re-enable PCI device after reset.\n");
6339 6340 6341 6342
		result = PCI_ERS_RESULT_DISCONNECT;
	} else {
		pci_set_master(pdev);
		pci_restore_state(pdev);
6343
		pci_save_state(pdev);
6344

6345 6346
		pci_enable_wake(pdev, PCI_D3hot, 0);
		pci_enable_wake(pdev, PCI_D3cold, 0);
6347

6348 6349 6350 6351
		igb_reset(adapter);
		wr32(E1000_WUS, ~0);
		result = PCI_ERS_RESULT_RECOVERED;
	}
6352

6353 6354 6355 6356 6357 6358
	err = pci_cleanup_aer_uncorrect_error_status(pdev);
	if (err) {
		dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
		        "failed 0x%0x\n", err);
		/* non-fatal, continue */
	}
6359 6360

	return result;
6361 6362 6363 6364 6365 6366 6367 6368 6369 6370 6371 6372 6373 6374 6375 6376 6377 6378 6379 6380 6381 6382 6383 6384 6385 6386 6387 6388 6389
}

/**
 * igb_io_resume - called when traffic can start flowing again.
 * @pdev: Pointer to PCI device
 *
 * This callback is called when the error recovery driver tells us that
 * its OK to resume normal operation. Implementation resembles the
 * second-half of the igb_resume routine.
 */
static void igb_io_resume(struct pci_dev *pdev)
{
	struct net_device *netdev = pci_get_drvdata(pdev);
	struct igb_adapter *adapter = netdev_priv(netdev);

	if (netif_running(netdev)) {
		if (igb_up(adapter)) {
			dev_err(&pdev->dev, "igb_up failed after reset\n");
			return;
		}
	}

	netif_device_attach(netdev);

	/* let the f/w know that the h/w is now under the control of the
	 * driver. */
	igb_get_hw_control(adapter);
}

6390 6391 6392 6393 6394 6395 6396 6397 6398 6399 6400 6401 6402 6403 6404 6405 6406 6407 6408 6409 6410 6411 6412 6413 6414 6415 6416
static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
                             u8 qsel)
{
	u32 rar_low, rar_high;
	struct e1000_hw *hw = &adapter->hw;

	/* HW expects these in little endian so we reverse the byte order
	 * from network order (big endian) to little endian
	 */
	rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
	          ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));

	/* Indicate to hardware the Address is Valid. */
	rar_high |= E1000_RAH_AV;

	if (hw->mac.type == e1000_82575)
		rar_high |= E1000_RAH_POOL_1 * qsel;
	else
		rar_high |= E1000_RAH_POOL_1 << qsel;

	wr32(E1000_RAL(index), rar_low);
	wrfl();
	wr32(E1000_RAH(index), rar_high);
	wrfl();
}

6417 6418 6419 6420
static int igb_set_vf_mac(struct igb_adapter *adapter,
                          int vf, unsigned char *mac_addr)
{
	struct e1000_hw *hw = &adapter->hw;
6421 6422 6423
	/* VF MAC addresses start at end of receive addresses and moves
	 * torwards the first, as a result a collision should not be possible */
	int rar_entry = hw->mac.rar_entry_count - (vf + 1);
6424

6425
	memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
6426

6427
	igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
6428 6429 6430 6431

	return 0;
}

6432 6433 6434 6435 6436 6437 6438 6439 6440 6441 6442 6443 6444 6445 6446 6447 6448 6449 6450 6451 6452 6453 6454 6455 6456 6457 6458 6459 6460 6461 6462 6463 6464 6465 6466 6467 6468
static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
		return -EINVAL;
	adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
	dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
	dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
				      " change effective.");
	if (test_bit(__IGB_DOWN, &adapter->state)) {
		dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
			 " but the PF device is not up.\n");
		dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
			 " attempting to use the VF device.\n");
	}
	return igb_set_vf_mac(adapter, vf, mac);
}

static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
{
	return -EOPNOTSUPP;
}

static int igb_ndo_get_vf_config(struct net_device *netdev,
				 int vf, struct ifla_vf_info *ivi)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	if (vf >= adapter->vfs_allocated_count)
		return -EINVAL;
	ivi->vf = vf;
	memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
	ivi->tx_rate = 0;
	ivi->vlan = adapter->vf_data[vf].pf_vlan;
	ivi->qos = adapter->vf_data[vf].pf_qos;
	return 0;
}

6469 6470 6471
static void igb_vmm_control(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
6472
	u32 reg;
6473

6474 6475 6476 6477
	switch (hw->mac.type) {
	case e1000_82575:
	default:
		/* replication is not supported for 82575 */
6478
		return;
6479 6480 6481 6482 6483 6484 6485 6486 6487 6488
	case e1000_82576:
		/* notify HW that the MAC is adding vlan tags */
		reg = rd32(E1000_DTXCTL);
		reg |= E1000_DTXCTL_VLAN_ADDED;
		wr32(E1000_DTXCTL, reg);
	case e1000_82580:
		/* enable replication vlan tag stripping */
		reg = rd32(E1000_RPLOLR);
		reg |= E1000_RPLOLR_STRVLAN;
		wr32(E1000_RPLOLR, reg);
6489 6490
	case e1000_i350:
		/* none of the above registers are supported by i350 */
6491 6492
		break;
	}
6493

6494 6495 6496 6497 6498 6499 6500
	if (adapter->vfs_allocated_count) {
		igb_vmdq_set_loopback_pf(hw, true);
		igb_vmdq_set_replication_pf(hw, true);
	} else {
		igb_vmdq_set_loopback_pf(hw, false);
		igb_vmdq_set_replication_pf(hw, false);
	}
6501 6502
}

6503
/* igb_main.c */