io_apic.c 94.0 KB
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/*
 *	Intel IO-APIC support for multi-Pentium hosts.
 *
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 *	Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
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 *
 *	Many thanks to Stig Venaas for trying out countless experimental
 *	patches and reporting/debugging problems patiently!
 *
 *	(c) 1999, Multiple IO-APIC support, developed by
 *	Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
 *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
 *	further tested and cleaned up by Zach Brown <zab@redhat.com>
 *	and Ingo Molnar <mingo@redhat.com>
 *
 *	Fixes
 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
 *					thanks to Eric Gilmore
 *					and Rolf G. Tews
 *					for testing these extensively
 *	Paul Diefenbaugh	:	Added full ACPI support
 */

#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/mc146818rtc.h>
#include <linux/compiler.h>
#include <linux/acpi.h>
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#include <linux/module.h>
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#include <linux/syscore_ops.h>
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#include <linux/msi.h>
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#include <linux/htirq.h>
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#include <linux/freezer.h>
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#include <linux/kthread.h>
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#include <linux/jiffies.h>	/* time_after() */
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#include <linux/slab.h>
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#ifdef CONFIG_ACPI
#include <acpi/acpi_bus.h>
#endif
#include <linux/bootmem.h>
#include <linux/dmar.h>
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#include <linux/hpet.h>
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#include <asm/idle.h>
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#include <asm/io.h>
#include <asm/smp.h>
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#include <asm/cpu.h>
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#include <asm/desc.h>
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#include <asm/proto.h>
#include <asm/acpi.h>
#include <asm/dma.h>
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#include <asm/timer.h>
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#include <asm/i8259.h>
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#include <asm/msidef.h>
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#include <asm/hypertransport.h>
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#include <asm/setup.h>
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#include <asm/irq_remapping.h>
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#include <asm/hpet.h>
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#include <asm/hw_irq.h>
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#include <asm/apic.h>
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#define __apicdebuginit(type) static type __init
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#define for_each_irq_pin(entry, head) \
	for (entry = head; entry; entry = entry->next)
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/*
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 *      Is the SiS APIC rmw bug present ?
 *      -1 = don't know, 0 = no, 1 = yes
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 */
int sis_apic_bug = -1;

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static DEFINE_RAW_SPINLOCK(ioapic_lock);
static DEFINE_RAW_SPINLOCK(vector_lock);
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static struct ioapic {
	/*
	 * # of IRQ routing registers
	 */
	int nr_registers;
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	/*
	 * Saved state during suspend/resume, or while enabling intr-remap.
	 */
	struct IO_APIC_route_entry *saved_registers;
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	/* I/O APIC config */
	struct mpc_ioapic mp_config;
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	/* IO APIC gsi routing info */
	struct mp_ioapic_gsi  gsi_config;
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	DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
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} ioapics[MAX_IO_APICS];
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#define mpc_ioapic_ver(ioapic_idx)	ioapics[ioapic_idx].mp_config.apicver
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int mpc_ioapic_id(int ioapic_idx)
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{
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	return ioapics[ioapic_idx].mp_config.apicid;
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}

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unsigned int mpc_ioapic_addr(int ioapic_idx)
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{
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	return ioapics[ioapic_idx].mp_config.apicaddr;
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}

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struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
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{
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	return &ioapics[ioapic_idx].gsi_config;
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}
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int nr_ioapics;
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/* The one past the highest gsi number used */
u32 gsi_top;
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/* MP IRQ source entries */
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struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
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/* # of MP IRQ source entries */
int mp_irq_entries;

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/* GSI interrupts */
static int nr_irqs_gsi = NR_IRQS_LEGACY;

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#ifdef CONFIG_EISA
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int mp_bus_id_to_type[MAX_MP_BUSSES];
#endif

DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);

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int skip_ioapic_setup;

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/**
 * disable_ioapic_support() - disables ioapic support at runtime
 */
void disable_ioapic_support(void)
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{
#ifdef CONFIG_PCI
	noioapicquirk = 1;
	noioapicreroute = -1;
#endif
	skip_ioapic_setup = 1;
}

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static int __init parse_noapic(char *str)
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{
	/* disable IO-APIC */
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	disable_ioapic_support();
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	return 0;
}
early_param("noapic", parse_noapic);
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static int io_apic_setup_irq_pin(unsigned int irq, int node,
				 struct io_apic_irq_attr *attr);
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/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
void mp_save_irq(struct mpc_intsrc *m)
{
	int i;

	apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
		" IRQ %02x, APIC ID %x, APIC INT %02x\n",
		m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
		m->srcbusirq, m->dstapic, m->dstirq);

	for (i = 0; i < mp_irq_entries; i++) {
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		if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
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			return;
	}

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	memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
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	if (++mp_irq_entries == MAX_IRQ_SOURCES)
		panic("Max # of irq sources exceeded!!\n");
}

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struct irq_pin_list {
	int apic, pin;
	struct irq_pin_list *next;
};

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static struct irq_pin_list *alloc_irq_pin_list(int node)
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{
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	return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
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}

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/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
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static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
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int __init arch_early_irq_init(void)
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{
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	struct irq_cfg *cfg;
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	int count, node, i;
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	if (!legacy_pic->nr_legacy_irqs)
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		io_apic_irqs = ~0UL;

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	for (i = 0; i < nr_ioapics; i++) {
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		ioapics[i].saved_registers =
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			kzalloc(sizeof(struct IO_APIC_route_entry) *
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				ioapics[i].nr_registers, GFP_KERNEL);
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		if (!ioapics[i].saved_registers)
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			pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
	}

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	cfg = irq_cfgx;
	count = ARRAY_SIZE(irq_cfgx);
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	node = cpu_to_node(0);
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	/* Make sure the legacy interrupts are marked in the bitmap */
	irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);

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	for (i = 0; i < count; i++) {
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		irq_set_chip_data(i, &cfg[i]);
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		zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
		zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
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		/*
		 * For legacy IRQ's, start with assigning irq0 to irq15 to
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		 * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's.
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		 */
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		if (i < legacy_pic->nr_legacy_irqs) {
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			cfg[i].vector = IRQ0_VECTOR + i;
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			cpumask_setall(cfg[i].domain);
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		}
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	}
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	return 0;
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}
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static struct irq_cfg *irq_cfg(unsigned int irq)
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{
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	return irq_get_chip_data(irq);
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}
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static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
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{
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	struct irq_cfg *cfg;
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	cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
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	if (!cfg)
		return NULL;
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	if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
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		goto out_cfg;
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	if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
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		goto out_domain;
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	return cfg;
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out_domain:
	free_cpumask_var(cfg->domain);
out_cfg:
	kfree(cfg);
	return NULL;
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}

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static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
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{
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	if (!cfg)
		return;
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	irq_set_chip_data(at, NULL);
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	free_cpumask_var(cfg->domain);
	free_cpumask_var(cfg->old_domain);
	kfree(cfg);
}

static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
{
	int res = irq_alloc_desc_at(at, node);
	struct irq_cfg *cfg;

	if (res < 0) {
		if (res != -EEXIST)
			return NULL;
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		cfg = irq_get_chip_data(at);
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		if (cfg)
			return cfg;
	}

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	cfg = alloc_irq_cfg(at, node);
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	if (cfg)
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		irq_set_chip_data(at, cfg);
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	else
		irq_free_desc(at);
	return cfg;
}

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static int alloc_irqs_from(unsigned int from, unsigned int count, int node)
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{
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	return irq_alloc_descs_from(from, count, node);
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}

static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
{
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	free_irq_cfg(at, cfg);
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	irq_free_desc(at);
}

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struct io_apic {
	unsigned int index;
	unsigned int unused[3];
	unsigned int data;
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	unsigned int unused2[11];
	unsigned int eoi;
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};

static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
{
	return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
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		+ (mpc_ioapic_addr(idx) & ~PAGE_MASK);
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}

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void io_apic_eoi(unsigned int apic, unsigned int vector)
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{
	struct io_apic __iomem *io_apic = io_apic_base(apic);
	writel(vector, &io_apic->eoi);
}

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unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
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{
	struct io_apic __iomem *io_apic = io_apic_base(apic);
	writel(reg, &io_apic->index);
	return readl(&io_apic->data);
}

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void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
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{
	struct io_apic __iomem *io_apic = io_apic_base(apic);
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	writel(reg, &io_apic->index);
	writel(value, &io_apic->data);
}

/*
 * Re-write a value: to be used for read-modify-write
 * cycles where the read already set up the index register.
 *
 * Older SiS APIC requires we rewrite the index register
 */
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void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
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{
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	struct io_apic __iomem *io_apic = io_apic_base(apic);
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	if (sis_apic_bug)
		writel(reg, &io_apic->index);
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	writel(value, &io_apic->data);
}

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union entry_union {
	struct { u32 w1, w2; };
	struct IO_APIC_route_entry entry;
};

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static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
{
	union entry_union eu;

	eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
	eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
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	return eu.entry;
}

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static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
{
	union entry_union eu;
	unsigned long flags;
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	raw_spin_lock_irqsave(&ioapic_lock, flags);
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	eu.entry = __ioapic_read_entry(apic, pin);
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	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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	return eu.entry;
}

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/*
 * When we write a new IO APIC routing entry, we need to write the high
 * word first! If the mask bit in the low word is clear, we will enable
 * the interrupt, and we need to make sure the entry is fully populated
 * before that happens.
 */
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static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
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{
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	union entry_union eu = {{0, 0}};

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	eu.entry = e;
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	io_apic_write(apic, 0x11 + 2*pin, eu.w2);
	io_apic_write(apic, 0x10 + 2*pin, eu.w1);
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}

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static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
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{
	unsigned long flags;
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	raw_spin_lock_irqsave(&ioapic_lock, flags);
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	__ioapic_write_entry(apic, pin, e);
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	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}

/*
 * When we mask an IO APIC routing entry, we need to write the low
 * word first, in order to set the mask bit before we change the
 * high bits!
 */
static void ioapic_mask_entry(int apic, int pin)
{
	unsigned long flags;
	union entry_union eu = { .entry.mask = 1 };

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	raw_spin_lock_irqsave(&ioapic_lock, flags);
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	io_apic_write(apic, 0x10 + 2*pin, eu.w1);
	io_apic_write(apic, 0x11 + 2*pin, eu.w2);
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	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}

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/*
 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 * shared ISA-space IRQs, so we have to support them. We are super
 * fast in the common case, and fast for shared ISA-space IRQs.
 */
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static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
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{
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	struct irq_pin_list **last, *entry;
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	/* don't allow duplicates */
	last = &cfg->irq_2_pin;
	for_each_irq_pin(entry, cfg->irq_2_pin) {
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		if (entry->apic == apic && entry->pin == pin)
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			return 0;
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		last = &entry->next;
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	}
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	entry = alloc_irq_pin_list(node);
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	if (!entry) {
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		pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
		       node, apic, pin);
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		return -ENOMEM;
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	}
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	entry->apic = apic;
	entry->pin = pin;
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	*last = entry;
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	return 0;
}

static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
{
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	if (__add_pin_to_irq_node(cfg, node, apic, pin))
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		panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
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}

/*
 * Reroute an IRQ to a different pin.
 */
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static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
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					   int oldapic, int oldpin,
					   int newapic, int newpin)
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{
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	struct irq_pin_list *entry;
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	for_each_irq_pin(entry, cfg->irq_2_pin) {
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		if (entry->apic == oldapic && entry->pin == oldpin) {
			entry->apic = newapic;
			entry->pin = newpin;
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			/* every one is different, right? */
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			return;
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		}
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	}
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	/* old apic/pin didn't exist, so just add new ones */
	add_pin_to_irq_node(cfg, node, newapic, newpin);
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}

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static void __io_apic_modify_irq(struct irq_pin_list *entry,
				 int mask_and, int mask_or,
				 void (*final)(struct irq_pin_list *entry))
{
	unsigned int reg, pin;

	pin = entry->pin;
	reg = io_apic_read(entry->apic, 0x10 + pin * 2);
	reg &= mask_and;
	reg |= mask_or;
	io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
	if (final)
		final(entry);
}

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static void io_apic_modify_irq(struct irq_cfg *cfg,
			       int mask_and, int mask_or,
			       void (*final)(struct irq_pin_list *entry))
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{
	struct irq_pin_list *entry;
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	for_each_irq_pin(entry, cfg->irq_2_pin)
		__io_apic_modify_irq(entry, mask_and, mask_or, final);
}

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static void io_apic_sync(struct irq_pin_list *entry)
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{
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	/*
	 * Synchronize the IO-APIC and the CPU by doing
	 * a dummy read from the IO-APIC
	 */
	struct io_apic __iomem *io_apic;
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	io_apic = io_apic_base(entry->apic);
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	readl(&io_apic->data);
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}

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static void mask_ioapic(struct irq_cfg *cfg)
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{
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	unsigned long flags;

	raw_spin_lock_irqsave(&ioapic_lock, flags);
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	io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
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	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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static void mask_ioapic_irq(struct irq_data *data)
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{
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	mask_ioapic(data->chip_data);
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}
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static void __unmask_ioapic(struct irq_cfg *cfg)
{
	io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
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}

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static void unmask_ioapic(struct irq_cfg *cfg)
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{
	unsigned long flags;

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	raw_spin_lock_irqsave(&ioapic_lock, flags);
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	__unmask_ioapic(cfg);
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	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}

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static void unmask_ioapic_irq(struct irq_data *data)
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{
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	unmask_ioapic(data->chip_data);
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}

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/*
 * IO-APIC versions below 0x20 don't support EOI register.
 * For the record, here is the information about various versions:
 *     0Xh     82489DX
 *     1Xh     I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
 *     2Xh     I/O(x)APIC which is PCI 2.2 Compliant
 *     30h-FFh Reserved
 *
 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
 * version as 0x2. This is an error with documentation and these ICH chips
 * use io-apic's of version 0x20.
 *
 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
 * Otherwise, we simulate the EOI message manually by changing the trigger
 * mode to edge and then back to level, with RTE being masked during this.
 */
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void native_eoi_ioapic_pin(int apic, int pin, int vector)
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{
	if (mpc_ioapic_ver(apic) >= 0x20) {
563
		io_apic_eoi(apic, vector);
564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583
	} else {
		struct IO_APIC_route_entry entry, entry1;

		entry = entry1 = __ioapic_read_entry(apic, pin);

		/*
		 * Mask the entry and change the trigger mode to edge.
		 */
		entry1.mask = 1;
		entry1.trigger = IOAPIC_EDGE;

		__ioapic_write_entry(apic, pin, entry1);

		/*
		 * Restore the previous level triggered entry.
		 */
		__ioapic_write_entry(apic, pin, entry);
	}
}

584
void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
585 586 587 588 589 590
{
	struct irq_pin_list *entry;
	unsigned long flags;

	raw_spin_lock_irqsave(&ioapic_lock, flags);
	for_each_irq_pin(entry, cfg->irq_2_pin)
591 592
		x86_io_apic_ops.eoi_ioapic_pin(entry->apic, entry->pin,
					       cfg->vector);
593 594 595
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
}

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static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
{
	struct IO_APIC_route_entry entry;
599

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	/* Check delivery_mode to be sure we're not clearing an SMI pin */
601
	entry = ioapic_read_entry(apic, pin);
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	if (entry.delivery_mode == dest_SMI)
		return;
604

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	/*
606 607 608 609 610 611 612 613 614 615
	 * Make sure the entry is masked and re-read the contents to check
	 * if it is a level triggered pin and if the remote-IRR is set.
	 */
	if (!entry.mask) {
		entry.mask = 1;
		ioapic_write_entry(apic, pin, entry);
		entry = ioapic_read_entry(apic, pin);
	}

	if (entry.irr) {
616 617
		unsigned long flags;

618 619 620 621 622 623 624 625 626 627
		/*
		 * Make sure the trigger mode is set to level. Explicit EOI
		 * doesn't clear the remote-IRR if the trigger mode is not
		 * set to level.
		 */
		if (!entry.trigger) {
			entry.trigger = IOAPIC_LEVEL;
			ioapic_write_entry(apic, pin, entry);
		}

628
		raw_spin_lock_irqsave(&ioapic_lock, flags);
629
		x86_io_apic_ops.eoi_ioapic_pin(apic, pin, entry.vector);
630
		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
631 632 633 634 635
	}

	/*
	 * Clear the rest of the bits in the IO-APIC RTE except for the mask
	 * bit.
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	 */
637
	ioapic_mask_entry(apic, pin);
638 639
	entry = ioapic_read_entry(apic, pin);
	if (entry.irr)
640
		pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
641
		       mpc_ioapic_id(apic), pin);
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}

644
static void clear_IO_APIC (void)
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{
	int apic, pin;

	for (apic = 0; apic < nr_ioapics; apic++)
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		for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
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			clear_IO_APIC_pin(apic, pin);
}

653
#ifdef CONFIG_X86_32
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/*
 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 * specific CPU-side IRQs.
 */

#define MAX_PIRQS 8
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static int pirq_entries[MAX_PIRQS] = {
	[0 ... MAX_PIRQS - 1] = -1
};
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static int __init ioapic_pirq_setup(char *str)
{
	int i, max;
	int ints[MAX_PIRQS+1];

	get_options(str, ARRAY_SIZE(ints), ints);

	apic_printk(APIC_VERBOSE, KERN_INFO
			"PIRQ redirection, working around broken MP-BIOS.\n");
	max = MAX_PIRQS;
	if (ints[0] < MAX_PIRQS)
		max = ints[0];

	for (i = 0; i < max; i++) {
		apic_printk(APIC_VERBOSE, KERN_DEBUG
				"... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
		/*
		 * PIRQs are mapped upside down, usually.
		 */
		pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
	}
	return 1;
}

__setup("pirq=", ioapic_pirq_setup);
689 690 691
#endif /* CONFIG_X86_32 */

/*
692
 * Saves all the IO-APIC RTE's
693
 */
694
int save_ioapic_entries(void)
695 696
{
	int apic, pin;
697
	int err = 0;
698 699

	for (apic = 0; apic < nr_ioapics; apic++) {
700
		if (!ioapics[apic].saved_registers) {
701 702 703
			err = -ENOMEM;
			continue;
		}
704

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		for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
706
			ioapics[apic].saved_registers[pin] =
707
				ioapic_read_entry(apic, pin);
708
	}
709

710
	return err;
711 712
}

713 714 715
/*
 * Mask all IO APIC entries.
 */
716
void mask_ioapic_entries(void)
717 718 719 720
{
	int apic, pin;

	for (apic = 0; apic < nr_ioapics; apic++) {
721
		if (!ioapics[apic].saved_registers)
722
			continue;
723

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		for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
725 726
			struct IO_APIC_route_entry entry;

727
			entry = ioapics[apic].saved_registers[pin];
728 729 730 731 732 733 734 735
			if (!entry.mask) {
				entry.mask = 1;
				ioapic_write_entry(apic, pin, entry);
			}
		}
	}
}

736
/*
737
 * Restore IO APIC entries which was saved in the ioapic structure.
738
 */
739
int restore_ioapic_entries(void)
740 741 742
{
	int apic, pin;

743
	for (apic = 0; apic < nr_ioapics; apic++) {
744
		if (!ioapics[apic].saved_registers)
745
			continue;
746

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		for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
748
			ioapic_write_entry(apic, pin,
749
					   ioapics[apic].saved_registers[pin]);
750
	}
751
	return 0;
752 753
}

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/*
 * Find the IRQ entry number of a certain pin.
 */
757
static int find_irq_entry(int ioapic_idx, int pin, int type)
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{
	int i;

	for (i = 0; i < mp_irq_entries; i++)
762
		if (mp_irqs[i].irqtype == type &&
763
		    (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
764 765
		     mp_irqs[i].dstapic == MP_APIC_ALL) &&
		    mp_irqs[i].dstirq == pin)
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			return i;

	return -1;
}

/*
 * Find the pin to which IRQ[irq] (ISA) is connected
 */
774
static int __init find_isa_irq_pin(int irq, int type)
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{
	int i;

	for (i = 0; i < mp_irq_entries; i++) {
779
		int lbus = mp_irqs[i].srcbus;
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		if (test_bit(lbus, mp_bus_not_pci) &&
782 783
		    (mp_irqs[i].irqtype == type) &&
		    (mp_irqs[i].srcbusirq == irq))
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784

785
			return mp_irqs[i].dstirq;
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	}
	return -1;
}

790 791 792 793 794
static int __init find_isa_irq_apic(int irq, int type)
{
	int i;

	for (i = 0; i < mp_irq_entries; i++) {
795
		int lbus = mp_irqs[i].srcbus;
796

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		if (test_bit(lbus, mp_bus_not_pci) &&
798 799
		    (mp_irqs[i].irqtype == type) &&
		    (mp_irqs[i].srcbusirq == irq))
800 801
			break;
	}
802

803
	if (i < mp_irq_entries) {
804 805 806 807 808
		int ioapic_idx;

		for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
			if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
				return ioapic_idx;
809 810 811 812 813
	}

	return -1;
}

814
#ifdef CONFIG_EISA
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/*
 * EISA Edge/Level control register, ELCR
 */
static int EISA_ELCR(unsigned int irq)
{
820
	if (irq < legacy_pic->nr_legacy_irqs) {
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		unsigned int port = 0x4d0 + (irq >> 3);
		return (inb(port) >> (irq & 7)) & 1;
	}
	apic_printk(APIC_VERBOSE, KERN_INFO
			"Broken MPtable reports ISA irq %d\n", irq);
	return 0;
}
828

829
#endif
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/* ISA interrupts are always polarity zero edge triggered,
 * when listed as conforming in the MP table. */

#define default_ISA_trigger(idx)	(0)
#define default_ISA_polarity(idx)	(0)

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/* EISA interrupts are always polarity zero and can be edge or level
 * trigger depending on the ELCR value.  If an interrupt is listed as
 * EISA conforming in the MP table, that means its trigger type must
 * be read in from the ELCR */

842
#define default_EISA_trigger(idx)	(EISA_ELCR(mp_irqs[idx].srcbusirq))
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#define default_EISA_polarity(idx)	default_ISA_polarity(idx)
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/* PCI interrupts are always polarity one level triggered,
 * when listed as conforming in the MP table. */

#define default_PCI_trigger(idx)	(1)
#define default_PCI_polarity(idx)	(1)

851
static int irq_polarity(int idx)
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{
853
	int bus = mp_irqs[idx].srcbus;
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	int polarity;

	/*
	 * Determine IRQ line polarity (high active or low active):
	 */
859
	switch (mp_irqs[idx].irqflag & 3)
860
	{
861 862 863 864 865 866 867 868 869 870 871 872 873
		case 0: /* conforms, ie. bus-type dependent polarity */
			if (test_bit(bus, mp_bus_not_pci))
				polarity = default_ISA_polarity(idx);
			else
				polarity = default_PCI_polarity(idx);
			break;
		case 1: /* high active */
		{
			polarity = 0;
			break;
		}
		case 2: /* reserved */
		{
874
			pr_warn("broken BIOS!!\n");
875 876 877 878 879 880 881 882 883 884
			polarity = 1;
			break;
		}
		case 3: /* low active */
		{
			polarity = 1;
			break;
		}
		default: /* invalid */
		{
885
			pr_warn("broken BIOS!!\n");
886 887 888
			polarity = 1;
			break;
		}
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	}
	return polarity;
}

893
static int irq_trigger(int idx)
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894
{
895
	int bus = mp_irqs[idx].srcbus;
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	int trigger;

	/*
	 * Determine IRQ trigger mode (edge or level sensitive):
	 */
901
	switch ((mp_irqs[idx].irqflag>>2) & 3)
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	{
903 904 905 906 907
		case 0: /* conforms, ie. bus-type dependent */
			if (test_bit(bus, mp_bus_not_pci))
				trigger = default_ISA_trigger(idx);
			else
				trigger = default_PCI_trigger(idx);
908
#ifdef CONFIG_EISA
909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926
			switch (mp_bus_id_to_type[bus]) {
				case MP_BUS_ISA: /* ISA pin */
				{
					/* set before the switch */
					break;
				}
				case MP_BUS_EISA: /* EISA pin */
				{
					trigger = default_EISA_trigger(idx);
					break;
				}
				case MP_BUS_PCI: /* PCI pin */
				{
					/* set before the switch */
					break;
				}
				default:
				{
927
					pr_warn("broken BIOS!!\n");
928 929 930 931 932
					trigger = 1;
					break;
				}
			}
#endif
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933
			break;
934
		case 1: /* edge */
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935
		{
936
			trigger = 0;
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937 938
			break;
		}
939
		case 2: /* reserved */
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940
		{
941
			pr_warn("broken BIOS!!\n");
942
			trigger = 1;
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943 944
			break;
		}
945
		case 3: /* level */
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946
		{
947
			trigger = 1;
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948 949
			break;
		}
950
		default: /* invalid */
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951
		{
952
			pr_warn("broken BIOS!!\n");
953
			trigger = 0;
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			break;
		}
	}
	return trigger;
}

static int pin_2_irq(int idx, int apic, int pin)
{
962
	int irq;
963
	int bus = mp_irqs[idx].srcbus;
964
	struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);
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	/*
	 * Debugging check, we are in big trouble if this message pops up!
	 */
969
	if (mp_irqs[idx].dstirq != pin)
970
		pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
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971

972
	if (test_bit(bus, mp_bus_not_pci)) {
973
		irq = mp_irqs[idx].srcbusirq;
974
	} else {
975
		u32 gsi = gsi_cfg->gsi_base + pin;
976 977 978 979

		if (gsi >= NR_IRQS_LEGACY)
			irq = gsi;
		else
980
			irq = gsi_top + gsi;
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981 982
	}

983
#ifdef CONFIG_X86_32
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	/*
	 * PCI IRQ command line redirection. Yes, limits are hardcoded.
	 */
	if ((pin >= 16) && (pin <= 23)) {
		if (pirq_entries[pin-16] != -1) {
			if (!pirq_entries[pin-16]) {
				apic_printk(APIC_VERBOSE, KERN_DEBUG
						"disabling PIRQ%d\n", pin-16);
			} else {
				irq = pirq_entries[pin-16];
				apic_printk(APIC_VERBOSE, KERN_DEBUG
						"using PIRQ%d -> IRQ %d\n",
						pin-16, irq);
			}
		}
	}
1000 1001
#endif

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	return irq;
}

1005 1006 1007 1008 1009
/*
 * Find a specific PCI IRQ entry.
 * Not an __init, possibly needed by modules
 */
int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1010
				struct io_apic_irq_attr *irq_attr)
1011
{
1012
	int ioapic_idx, i, best_guess = -1;
1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024

	apic_printk(APIC_DEBUG,
		    "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
		    bus, slot, pin);
	if (test_bit(bus, mp_bus_not_pci)) {
		apic_printk(APIC_VERBOSE,
			    "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
		return -1;
	}
	for (i = 0; i < mp_irq_entries; i++) {
		int lbus = mp_irqs[i].srcbus;

1025 1026
		for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
			if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1027 1028 1029 1030 1031 1032 1033
			    mp_irqs[i].dstapic == MP_APIC_ALL)
				break;

		if (!test_bit(lbus, mp_bus_not_pci) &&
		    !mp_irqs[i].irqtype &&
		    (bus == lbus) &&
		    (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1034
			int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq);
1035

1036
			if (!(ioapic_idx || IO_APIC_IRQ(irq)))
1037 1038 1039
				continue;

			if (pin == (mp_irqs[i].srcbusirq & 3)) {
1040
				set_io_apic_irq_attr(irq_attr, ioapic_idx,
1041 1042 1043
						     mp_irqs[i].dstirq,
						     irq_trigger(i),
						     irq_polarity(i));
1044 1045 1046 1047 1048 1049 1050
				return irq;
			}
			/*
			 * Use the first all-but-pin matching entry as a
			 * best-guess fuzzy result for broken mptables.
			 */
			if (best_guess < 0) {
1051
				set_io_apic_irq_attr(irq_attr, ioapic_idx,
1052 1053 1054
						     mp_irqs[i].dstirq,
						     irq_trigger(i),
						     irq_polarity(i));
1055 1056 1057 1058 1059 1060 1061 1062
				best_guess = irq;
			}
		}
	}
	return best_guess;
}
EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);

1063 1064 1065 1066 1067
void lock_vector_lock(void)
{
	/* Used to the online set of cpus does not change
	 * during assign_irq_vector.
	 */
1068
	raw_spin_lock(&vector_lock);
1069
}
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1071
void unlock_vector_lock(void)
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1072
{
1073
	raw_spin_unlock(&vector_lock);
1074
}
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1076 1077
static int
__assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1078
{
1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089
	/*
	 * NOTE! The local APIC isn't very good at handling
	 * multiple interrupts at the same interrupt level.
	 * As the interrupt level is determined by taking the
	 * vector number and shifting that right by 4, we
	 * want to spread these out a bit so that they don't
	 * all fall in the same interrupt level.
	 *
	 * Also, we've got to be careful not to trash gate
	 * 0x80, because int 0x80 is hm, kind of importantish. ;)
	 */
1090
	static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1091
	static int current_offset = VECTOR_OFFSET_START % 16;
1092 1093
	int cpu, err;
	cpumask_var_t tmp_mask;
1094

1095
	if (cfg->move_in_progress)
1096
		return -EBUSY;
1097

1098 1099
	if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
		return -ENOMEM;
1100

1101
	/* Only try and allocate irqs on cpus that are present */
1102
	err = -ENOSPC;
1103 1104 1105
	cpumask_clear(cfg->old_domain);
	cpu = cpumask_first_and(mask, cpu_online_mask);
	while (cpu < nr_cpu_ids) {
1106
		int new_cpu, vector, offset;
1107

1108
		apic->vector_allocation_domain(cpu, tmp_mask, mask);
1109

1110
		if (cpumask_subset(tmp_mask, cfg->domain)) {
1111 1112 1113 1114 1115 1116 1117 1118 1119
			err = 0;
			if (cpumask_equal(tmp_mask, cfg->domain))
				break;
			/*
			 * New cpumask using the vector is a proper subset of
			 * the current in use mask. So cleanup the vector
			 * allocation for the members that are not used anymore.
			 */
			cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask);
1120 1121
			cfg->move_in_progress =
			   cpumask_intersects(cfg->old_domain, cpu_online_mask);
1122 1123
			cpumask_and(cfg->domain, cfg->domain, tmp_mask);
			break;
1124
		}
1125

1126 1127
		vector = current_vector;
		offset = current_offset;
1128
next:
1129
		vector += 16;
1130
		if (vector >= first_system_vector) {
1131
			offset = (offset + 1) % 16;
1132
			vector = FIRST_EXTERNAL_VECTOR + offset;
1133
		}
1134 1135

		if (unlikely(current_vector == vector)) {
1136 1137 1138
			cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask);
			cpumask_andnot(tmp_mask, mask, cfg->old_domain);
			cpu = cpumask_first_and(tmp_mask, cpu_online_mask);
1139
			continue;
1140
		}
1141 1142

		if (test_bit(vector, used_vectors))
1143
			goto next;
1144

1145
		for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1146 1147 1148 1149 1150
			if (per_cpu(vector_irq, new_cpu)[vector] != -1)
				goto next;
		/* Found one! */
		current_vector = vector;
		current_offset = offset;
1151
		if (cfg->vector) {
1152
			cpumask_copy(cfg->old_domain, cfg->domain);
1153 1154
			cfg->move_in_progress =
			   cpumask_intersects(cfg->old_domain, cpu_online_mask);
1155
		}
1156
		for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1157 1158
			per_cpu(vector_irq, new_cpu)[vector] = irq;
		cfg->vector = vector;
1159 1160 1161
		cpumask_copy(cfg->domain, tmp_mask);
		err = 0;
		break;
1162
	}
1163 1164
	free_cpumask_var(tmp_mask);
	return err;
1165 1166
}

1167
int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1168 1169
{
	int err;
1170 1171
	unsigned long flags;

1172
	raw_spin_lock_irqsave(&vector_lock, flags);
Y
Yinghai Lu 已提交
1173
	err = __assign_irq_vector(irq, cfg, mask);
1174
	raw_spin_unlock_irqrestore(&vector_lock, flags);
1175 1176 1177
	return err;
}

Y
Yinghai Lu 已提交
1178
static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1179 1180 1181 1182 1183 1184
{
	int cpu, vector;

	BUG_ON(!cfg->vector);

	vector = cfg->vector;
1185
	for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1186 1187 1188
		per_cpu(vector_irq, cpu)[vector] = -1;

	cfg->vector = 0;
1189
	cpumask_clear(cfg->domain);
1190 1191 1192

	if (likely(!cfg->move_in_progress))
		return;
1193
	for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1194 1195 1196 1197 1198 1199 1200 1201 1202
		for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
								vector++) {
			if (per_cpu(vector_irq, cpu)[vector] != irq)
				continue;
			per_cpu(vector_irq, cpu)[vector] = -1;
			break;
		}
	}
	cfg->move_in_progress = 0;
1203 1204 1205 1206 1207 1208 1209 1210
}

void __setup_vector_irq(int cpu)
{
	/* Initialize vector_irq on a new cpu */
	int irq, vector;
	struct irq_cfg *cfg;

1211 1212 1213 1214 1215
	/*
	 * vector_lock will make sure that we don't run into irq vector
	 * assignments that might be happening on another cpu in parallel,
	 * while we setup our initial vector to irq mappings.
	 */
1216
	raw_spin_lock(&vector_lock);
1217
	/* Mark the inuse vectors */
T
Thomas Gleixner 已提交
1218
	for_each_active_irq(irq) {
1219
		cfg = irq_get_chip_data(irq);
T
Thomas Gleixner 已提交
1220 1221
		if (!cfg)
			continue;
1222

1223
		if (!cpumask_test_cpu(cpu, cfg->domain))
1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234
			continue;
		vector = cfg->vector;
		per_cpu(vector_irq, cpu)[vector] = irq;
	}
	/* Mark the free vectors */
	for (vector = 0; vector < NR_VECTORS; ++vector) {
		irq = per_cpu(vector_irq, cpu)[vector];
		if (irq < 0)
			continue;

		cfg = irq_cfg(irq);
1235
		if (!cpumask_test_cpu(cpu, cfg->domain))
1236
			per_cpu(vector_irq, cpu)[vector] = -1;
1237
	}
1238
	raw_spin_unlock(&vector_lock);
L
Linus Torvalds 已提交
1239
}
1240

1241
static struct irq_chip ioapic_chip;
L
Linus Torvalds 已提交
1242

1243
#ifdef CONFIG_X86_32
1244 1245
static inline int IO_APIC_irq_trigger(int irq)
{
T
Thomas Gleixner 已提交
1246
	int apic, idx, pin;
1247

T
Thomas Gleixner 已提交
1248
	for (apic = 0; apic < nr_ioapics; apic++) {
S
Suresh Siddha 已提交
1249
		for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
T
Thomas Gleixner 已提交
1250 1251 1252 1253 1254 1255
			idx = find_irq_entry(apic, pin, mp_INT);
			if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
				return irq_trigger(idx);
		}
	}
	/*
1256 1257
         * nonexistent IRQs are edge default
         */
T
Thomas Gleixner 已提交
1258
	return 0;
1259
}
1260 1261 1262
#else
static inline int IO_APIC_irq_trigger(int irq)
{
1263
	return 1;
1264 1265
}
#endif
1266

1267 1268
static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
				 unsigned long trigger)
L
Linus Torvalds 已提交
1269
{
1270 1271 1272
	struct irq_chip *chip = &ioapic_chip;
	irq_flow_handler_t hdl;
	bool fasteoi;
Y
Yinghai Lu 已提交
1273

1274
	if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1275
	    trigger == IOAPIC_LEVEL) {
1276
		irq_set_status_flags(irq, IRQ_LEVEL);
1277 1278
		fasteoi = true;
	} else {
1279
		irq_clear_status_flags(irq, IRQ_LEVEL);
1280 1281
		fasteoi = false;
	}
1282

1283
	if (setup_remapped_irq(irq, cfg, chip))
1284
		fasteoi = trigger != 0;
1285

1286 1287 1288
	hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
	irq_set_chip_and_handler_name(irq, chip, hdl,
				      fasteoi ? "fasteoi" : "edge");
L
Linus Torvalds 已提交
1289 1290
}

1291 1292 1293
int native_setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
			      unsigned int destination, int vector,
			      struct io_apic_irq_attr *attr)
1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306
{
	memset(entry, 0, sizeof(*entry));

	entry->delivery_mode = apic->irq_delivery_mode;
	entry->dest_mode     = apic->irq_dest_mode;
	entry->dest	     = destination;
	entry->vector	     = vector;
	entry->mask	     = 0;			/* enable IRQ */
	entry->trigger	     = attr->trigger;
	entry->polarity	     = attr->polarity;

	/*
	 * Mask level triggered irqs.
1307 1308
	 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
	 */
1309
	if (attr->trigger)
1310
		entry->mask = 1;
1311

1312 1313 1314
	return 0;
}

1315 1316
static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
				struct io_apic_irq_attr *attr)
1317
{
L
Linus Torvalds 已提交
1318
	struct IO_APIC_route_entry entry;
1319
	unsigned int dest;
1320 1321 1322

	if (!IO_APIC_IRQ(irq))
		return;
1323

1324
	if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1325 1326
		return;

1327 1328 1329 1330 1331 1332 1333 1334
	if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(),
					 &dest)) {
		pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n",
			mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
		__clear_irq_vector(irq, cfg);

		return;
	}
1335 1336 1337

	apic_printk(APIC_VERBOSE,KERN_DEBUG
		    "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1338
		    "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1339 1340
		    attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
		    cfg->vector, irq, attr->trigger, attr->polarity, dest);
1341

1342 1343
	if (x86_io_apic_ops.setup_entry(irq, &entry, dest, cfg->vector, attr)) {
		pr_warn("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
1344
			mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
Y
Yinghai Lu 已提交
1345
		__clear_irq_vector(irq, cfg);
1346

1347 1348 1349
		return;
	}

1350
	ioapic_register_intr(irq, cfg, attr->trigger);
1351
	if (irq < legacy_pic->nr_legacy_irqs)
1352
		legacy_pic->mask(irq);
1353

1354
	ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
1355 1356
}

1357
static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin)
1358 1359 1360 1361 1362
{
	if (idx != -1)
		return false;

	apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1363
		    mpc_ioapic_id(ioapic_idx), pin);
1364 1365 1366
	return true;
}

1367
static void __init __io_apic_setup_irqs(unsigned int ioapic_idx)
1368
{
1369
	int idx, node = cpu_to_node(0);
1370
	struct io_apic_irq_attr attr;
1371
	unsigned int pin, irq;
L
Linus Torvalds 已提交
1372

1373 1374 1375
	for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) {
		idx = find_irq_entry(ioapic_idx, pin, mp_INT);
		if (io_apic_pin_not_connected(idx, ioapic_idx, pin))
1376
			continue;
1377

1378
		irq = pin_2_irq(idx, ioapic_idx, pin);
1379

1380
		if ((ioapic_idx > 0) && (irq > 16))
E
Eric W. Biederman 已提交
1381 1382
			continue;

1383 1384 1385 1386 1387
		/*
		 * Skip the timer IRQ if there's a quirk handler
		 * installed and if it returns 1:
		 */
		if (apic->multi_timer_check &&
1388
		    apic->multi_timer_check(ioapic_idx, irq))
1389
			continue;
1390

1391
		set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1392
				     irq_polarity(idx));
1393

1394
		io_apic_setup_irq_pin(irq, node, &attr);
L
Linus Torvalds 已提交
1395 1396 1397
	}
}

1398 1399
static void __init setup_IO_APIC_irqs(void)
{
1400
	unsigned int ioapic_idx;
1401 1402 1403

	apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");

1404 1405
	for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
		__io_apic_setup_irqs(ioapic_idx);
1406 1407
}

Y
Yinghai Lu 已提交
1408 1409 1410 1411 1412 1413 1414
/*
 * for the gsit that is not in first ioapic
 * but could not use acpi_register_gsi()
 * like some special sci in IBM x3330
 */
void setup_IO_APIC_irq_extra(u32 gsi)
{
1415
	int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0);
1416
	struct io_apic_irq_attr attr;
Y
Yinghai Lu 已提交
1417 1418 1419 1420

	/*
	 * Convert 'gsi' to 'ioapic.pin'.
	 */
1421 1422
	ioapic_idx = mp_find_ioapic(gsi);
	if (ioapic_idx < 0)
Y
Yinghai Lu 已提交
1423 1424
		return;

1425 1426
	pin = mp_find_ioapic_pin(ioapic_idx, gsi);
	idx = find_irq_entry(ioapic_idx, pin, mp_INT);
Y
Yinghai Lu 已提交
1427 1428 1429
	if (idx == -1)
		return;

1430
	irq = pin_2_irq(idx, ioapic_idx, pin);
1431 1432

	/* Only handle the non legacy irqs on secondary ioapics */
1433
	if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY)
Y
Yinghai Lu 已提交
1434
		return;
1435

1436
	set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1437 1438
			     irq_polarity(idx));

1439
	io_apic_setup_irq_pin_once(irq, node, &attr);
Y
Yinghai Lu 已提交
1440 1441
}

L
Linus Torvalds 已提交
1442
/*
1443
 * Set up the timer pin, possibly with the 8259A-master behind.
L
Linus Torvalds 已提交
1444
 */
1445
static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
1446
					unsigned int pin, int vector)
L
Linus Torvalds 已提交
1447 1448
{
	struct IO_APIC_route_entry entry;
1449
	unsigned int dest;
L
Linus Torvalds 已提交
1450

1451
	memset(&entry, 0, sizeof(entry));
L
Linus Torvalds 已提交
1452 1453 1454 1455 1456

	/*
	 * We use logical delivery to get the timer IRQ
	 * to the first CPU.
	 */
1457 1458
	if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(),
						  apic->target_cpus(), &dest)))
1459 1460
		dest = BAD_APICID;

1461
	entry.dest_mode = apic->irq_dest_mode;
Y
Yinghai Lu 已提交
1462
	entry.mask = 0;			/* don't mask IRQ for edge */
1463
	entry.dest = dest;
1464
	entry.delivery_mode = apic->irq_delivery_mode;
L
Linus Torvalds 已提交
1465 1466 1467 1468 1469 1470
	entry.polarity = 0;
	entry.trigger = 0;
	entry.vector = vector;

	/*
	 * The timer IRQ doesn't have to know that behind the
1471
	 * scene we may have a 8259A-master in AEOI mode ...
L
Linus Torvalds 已提交
1472
	 */
1473 1474
	irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
				      "edge");
L
Linus Torvalds 已提交
1475 1476 1477 1478

	/*
	 * Add it to the IO-APIC irq-routing table:
	 */
1479
	ioapic_write_entry(ioapic_idx, pin, entry);
L
Linus Torvalds 已提交
1480 1481
}

1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508
void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
{
	int i;

	pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n");

	for (i = 0; i <= nr_entries; i++) {
		struct IO_APIC_route_entry entry;

		entry = ioapic_read_entry(apic, i);

		pr_debug(" %02x %02X  ", i, entry.dest);
		pr_cont("%1d    %1d    %1d   %1d   %1d    "
			"%1d    %1d    %02X\n",
			entry.mask,
			entry.trigger,
			entry.irr,
			entry.polarity,
			entry.delivery_status,
			entry.dest_mode,
			entry.delivery_mode,
			entry.vector);
	}
}

void intel_ir_io_apic_print_entries(unsigned int apic,
				    unsigned int nr_entries)
L
Linus Torvalds 已提交
1509
{
1510
	int i;
1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536

	pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n");

	for (i = 0; i <= nr_entries; i++) {
		struct IR_IO_APIC_route_entry *ir_entry;
		struct IO_APIC_route_entry entry;

		entry = ioapic_read_entry(apic, i);

		ir_entry = (struct IR_IO_APIC_route_entry *)&entry;

		pr_debug(" %02x %04X ", i, ir_entry->index);
		pr_cont("%1d   %1d    %1d    %1d   %1d   "
			"%1d    %1d     %X    %02X\n",
			ir_entry->format,
			ir_entry->mask,
			ir_entry->trigger,
			ir_entry->irr,
			ir_entry->polarity,
			ir_entry->delivery_status,
			ir_entry->index2,
			ir_entry->zero,
			ir_entry->vector);
	}
}

1537 1538 1539 1540 1541
void ioapic_zap_locks(void)
{
	raw_spin_lock_init(&ioapic_lock);
}

1542 1543
__apicdebuginit(void) print_IO_APIC(int ioapic_idx)
{
L
Linus Torvalds 已提交
1544 1545 1546 1547 1548 1549
	union IO_APIC_reg_00 reg_00;
	union IO_APIC_reg_01 reg_01;
	union IO_APIC_reg_02 reg_02;
	union IO_APIC_reg_03 reg_03;
	unsigned long flags;

1550
	raw_spin_lock_irqsave(&ioapic_lock, flags);
1551 1552
	reg_00.raw = io_apic_read(ioapic_idx, 0);
	reg_01.raw = io_apic_read(ioapic_idx, 1);
L
Linus Torvalds 已提交
1553
	if (reg_01.bits.version >= 0x10)
1554
		reg_02.raw = io_apic_read(ioapic_idx, 2);
T
Thomas Gleixner 已提交
1555
	if (reg_01.bits.version >= 0x20)
1556
		reg_03.raw = io_apic_read(ioapic_idx, 3);
1557
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
L
Linus Torvalds 已提交
1558

1559
	printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
L
Linus Torvalds 已提交
1560 1561 1562 1563 1564
	printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
	printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
	printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
	printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);

1565
	printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1566 1567
	printk(KERN_DEBUG ".......     : max redirection entries: %02X\n",
		reg_01.bits.entries);
L
Linus Torvalds 已提交
1568 1569

	printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1570 1571
	printk(KERN_DEBUG ".......     : IO APIC version: %02X\n",
		reg_01.bits.version);
L
Linus Torvalds 已提交
1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595

	/*
	 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
	 * but the value of reg_02 is read as the previous read register
	 * value, so ignore it if reg_02 == reg_01.
	 */
	if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
		printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
		printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
	}

	/*
	 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
	 * or reg_03, but the value of reg_0[23] is read as the previous read
	 * register value, so ignore it if reg_03 == reg_0[12].
	 */
	if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
	    reg_03.raw != reg_01.raw) {
		printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
		printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
	}

	printk(KERN_DEBUG ".... IRQ redirection table:\n");

1596
	x86_io_apic_ops.print_entries(ioapic_idx, reg_01.bits.entries);
1597 1598 1599 1600
}

__apicdebuginit(void) print_IO_APICs(void)
{
1601
	int ioapic_idx;
1602 1603
	struct irq_cfg *cfg;
	unsigned int irq;
1604
	struct irq_chip *chip;
1605 1606

	printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1607
	for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1608
		printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1609 1610
		       mpc_ioapic_id(ioapic_idx),
		       ioapics[ioapic_idx].nr_registers);
1611 1612 1613 1614 1615 1616 1617

	/*
	 * We are a bit conservative about what we expect.  We have to
	 * know about every hardware change ASAP.
	 */
	printk(KERN_INFO "testing the IO APIC.......................\n");

1618 1619
	for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
		print_IO_APIC(ioapic_idx);
1620

L
Linus Torvalds 已提交
1621
	printk(KERN_DEBUG "IRQ to pin mappings:\n");
T
Thomas Gleixner 已提交
1622
	for_each_active_irq(irq) {
1623 1624
		struct irq_pin_list *entry;

1625 1626 1627 1628
		chip = irq_get_chip(irq);
		if (chip != &ioapic_chip)
			continue;

1629
		cfg = irq_get_chip_data(irq);
1630 1631
		if (!cfg)
			continue;
1632
		entry = cfg->irq_2_pin;
1633
		if (!entry)
L
Linus Torvalds 已提交
1634
			continue;
1635
		printk(KERN_DEBUG "IRQ%d ", irq);
1636
		for_each_irq_pin(entry, cfg->irq_2_pin)
1637 1638
			pr_cont("-> %d:%d", entry->apic, entry->pin);
		pr_cont("\n");
L
Linus Torvalds 已提交
1639 1640 1641 1642 1643
	}

	printk(KERN_INFO ".................................... done.\n");
}

1644
__apicdebuginit(void) print_APIC_field(int base)
L
Linus Torvalds 已提交
1645
{
1646
	int i;
L
Linus Torvalds 已提交
1647

1648 1649 1650
	printk(KERN_DEBUG);

	for (i = 0; i < 8; i++)
1651
		pr_cont("%08x", apic_read(base + i*0x10));
1652

1653
	pr_cont("\n");
L
Linus Torvalds 已提交
1654 1655
}

1656
__apicdebuginit(void) print_local_APIC(void *dummy)
L
Linus Torvalds 已提交
1657
{
1658
	unsigned int i, v, ver, maxlvt;
1659
	u64 icr;
L
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1660

1661
	printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
L
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1662
		smp_processor_id(), hard_smp_processor_id());
1663
	v = apic_read(APIC_ID);
1664
	printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, read_apic_id());
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1665 1666 1667
	v = apic_read(APIC_LVR);
	printk(KERN_INFO "... APIC VERSION: %08x\n", v);
	ver = GET_APIC_VERSION(v);
1668
	maxlvt = lapic_get_maxlvt();
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1669 1670 1671 1672

	v = apic_read(APIC_TASKPRI);
	printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);

1673
	if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1674 1675 1676 1677 1678
		if (!APIC_XAPIC(ver)) {
			v = apic_read(APIC_ARBPRI);
			printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
			       v & APIC_ARBPRI_MASK);
		}
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1679 1680 1681 1682
		v = apic_read(APIC_PROCPRI);
		printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
	}

1683 1684 1685 1686 1687 1688 1689 1690 1691
	/*
	 * Remote read supported only in the 82489DX and local APIC for
	 * Pentium processors.
	 */
	if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
		v = apic_read(APIC_RRR);
		printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
	}

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1692 1693
	v = apic_read(APIC_LDR);
	printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1694 1695 1696 1697
	if (!x2apic_enabled()) {
		v = apic_read(APIC_DFR);
		printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
	}
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1698 1699 1700 1701
	v = apic_read(APIC_SPIV);
	printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);

	printk(KERN_DEBUG "... APIC ISR field:\n");
1702
	print_APIC_field(APIC_ISR);
L
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1703
	printk(KERN_DEBUG "... APIC TMR field:\n");
1704
	print_APIC_field(APIC_TMR);
L
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1705
	printk(KERN_DEBUG "... APIC IRR field:\n");
1706
	print_APIC_field(APIC_IRR);
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1707

1708 1709
	if (APIC_INTEGRATED(ver)) {             /* !82489DX */
		if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
L
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1710
			apic_write(APIC_ESR, 0);
1711

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1712 1713 1714 1715
		v = apic_read(APIC_ESR);
		printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
	}

1716
	icr = apic_icr_read();
1717 1718
	printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
	printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
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1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742

	v = apic_read(APIC_LVTT);
	printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);

	if (maxlvt > 3) {                       /* PC is LVT#4. */
		v = apic_read(APIC_LVTPC);
		printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
	}
	v = apic_read(APIC_LVT0);
	printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
	v = apic_read(APIC_LVT1);
	printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);

	if (maxlvt > 2) {			/* ERR is LVT#3. */
		v = apic_read(APIC_LVTERR);
		printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
	}

	v = apic_read(APIC_TMICT);
	printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
	v = apic_read(APIC_TMCCT);
	printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
	v = apic_read(APIC_TDCR);
	printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754

	if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
		v = apic_read(APIC_EFEAT);
		maxlvt = (v >> 16) & 0xff;
		printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
		v = apic_read(APIC_ECTRL);
		printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
		for (i = 0; i < maxlvt; i++) {
			v = apic_read(APIC_EILVTn(i));
			printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
		}
	}
1755
	pr_cont("\n");
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}

1758
__apicdebuginit(void) print_local_APICs(int maxcpu)
L
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1759
{
1760 1761
	int cpu;

1762 1763 1764
	if (!maxcpu)
		return;

1765
	preempt_disable();
1766 1767 1768
	for_each_online_cpu(cpu) {
		if (cpu >= maxcpu)
			break;
1769
		smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1770
	}
1771
	preempt_enable();
L
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1772 1773
}

1774
__apicdebuginit(void) print_PIC(void)
L
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1775 1776 1777 1778
{
	unsigned int v;
	unsigned long flags;

1779
	if (!legacy_pic->nr_legacy_irqs)
L
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1780 1781 1782 1783
		return;

	printk(KERN_DEBUG "\nprinting PIC contents\n");

1784
	raw_spin_lock_irqsave(&i8259A_lock, flags);
L
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1785 1786 1787 1788 1789 1790 1791

	v = inb(0xa1) << 8 | inb(0x21);
	printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);

	v = inb(0xa0) << 8 | inb(0x20);
	printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);

1792 1793
	outb(0x0b,0xa0);
	outb(0x0b,0x20);
L
Linus Torvalds 已提交
1794
	v = inb(0xa0) << 8 | inb(0x20);
1795 1796
	outb(0x0a,0xa0);
	outb(0x0a,0x20);
L
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1797

1798
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
L
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1799 1800 1801 1802 1803 1804 1805

	printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);

	v = inb(0x4d1) << 8 | inb(0x4d0);
	printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
}

1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823
static int __initdata show_lapic = 1;
static __init int setup_show_lapic(char *arg)
{
	int num = -1;

	if (strcmp(arg, "all") == 0) {
		show_lapic = CONFIG_NR_CPUS;
	} else {
		get_option(&arg, &num);
		if (num >= 0)
			show_lapic = num;
	}

	return 1;
}
__setup("show_lapic=", setup_show_lapic);

__apicdebuginit(int) print_ICs(void)
1824
{
1825 1826 1827
	if (apic_verbosity == APIC_QUIET)
		return 0;

1828
	print_PIC();
1829 1830

	/* don't print out if apic is not there */
1831
	if (!cpu_has_apic && !apic_from_smp_config())
1832 1833
		return 0;

1834
	print_local_APICs(show_lapic);
1835
	print_IO_APICs();
1836 1837 1838 1839

	return 0;
}

1840
late_initcall(print_ICs);
1841

L
Linus Torvalds 已提交
1842

Y
Yinghai Lu 已提交
1843 1844 1845
/* Where if anywhere is the i8259 connect in external int mode */
static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };

1846
void __init enable_IO_APIC(void)
L
Linus Torvalds 已提交
1847
{
1848
	int i8259_apic, i8259_pin;
1849
	int apic;
1850

1851
	if (!legacy_pic->nr_legacy_irqs)
1852 1853
		return;

1854
	for(apic = 0; apic < nr_ioapics; apic++) {
1855 1856
		int pin;
		/* See if any of the pins is in ExtINT mode */
S
Suresh Siddha 已提交
1857
		for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1858
			struct IO_APIC_route_entry entry;
1859
			entry = ioapic_read_entry(apic, pin);
1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889

			/* If the interrupt line is enabled and in ExtInt mode
			 * I have found the pin where the i8259 is connected.
			 */
			if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
				ioapic_i8259.apic = apic;
				ioapic_i8259.pin  = pin;
				goto found_i8259;
			}
		}
	}
 found_i8259:
	/* Look to see what if the MP table has reported the ExtINT */
	/* If we could not find the appropriate pin by looking at the ioapic
	 * the i8259 probably is not connected the ioapic but give the
	 * mptable a chance anyway.
	 */
	i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
	i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
	/* Trust the MP table if nothing is setup in the hardware */
	if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
		printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
		ioapic_i8259.pin  = i8259_pin;
		ioapic_i8259.apic = i8259_apic;
	}
	/* Complain if the MP table and the hardware disagree */
	if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
		(i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
	{
		printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
L
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1890 1891 1892 1893 1894 1895 1896 1897
	}

	/*
	 * Do not trust the IO-APIC being empty at bootup
	 */
	clear_IO_APIC();
}

1898
void native_disable_io_apic(void)
L
Linus Torvalds 已提交
1899
{
1900
	/*
1901
	 * If the i8259 is routed through an IOAPIC
1902
	 * Put that IOAPIC in virtual wire mode
1903
	 * so legacy interrupts can be delivered.
1904
	 */
1905
	if (ioapic_i8259.pin != -1) {
1906 1907 1908 1909 1910 1911 1912 1913 1914
		struct IO_APIC_route_entry entry;

		memset(&entry, 0, sizeof(entry));
		entry.mask            = 0; /* Enabled */
		entry.trigger         = 0; /* Edge */
		entry.irr             = 0;
		entry.polarity        = 0; /* High */
		entry.delivery_status = 0;
		entry.dest_mode       = 0; /* Physical */
1915
		entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1916
		entry.vector          = 0;
1917
		entry.dest            = read_apic_id();
1918 1919 1920 1921

		/*
		 * Add it to the IO-APIC irq-routing table:
		 */
1922
		ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1923
	}
1924

1925 1926 1927 1928 1929 1930 1931 1932 1933 1934
	if (cpu_has_apic || apic_from_smp_config())
		disconnect_bsp_APIC(ioapic_i8259.pin != -1);

}

/*
 * Not an __init, needed by the reboot code
 */
void disable_IO_APIC(void)
{
1935
	/*
1936
	 * Clear the IO-APIC before rebooting:
1937
	 */
1938 1939 1940 1941 1942 1943
	clear_IO_APIC();

	if (!legacy_pic->nr_legacy_irqs)
		return;

	x86_io_apic_ops.disable();
L
Linus Torvalds 已提交
1944 1945
}

1946
#ifdef CONFIG_X86_32
L
Linus Torvalds 已提交
1947 1948 1949 1950 1951 1952
/*
 * function to set the IO-APIC physical IDs based on the
 * values stored in the MPC table.
 *
 * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
 */
1953
void __init setup_ioapic_ids_from_mpc_nocheck(void)
L
Linus Torvalds 已提交
1954 1955 1956
{
	union IO_APIC_reg_00 reg_00;
	physid_mask_t phys_id_present_map;
1957
	int ioapic_idx;
L
Linus Torvalds 已提交
1958 1959 1960 1961 1962 1963 1964 1965
	int i;
	unsigned char old_id;
	unsigned long flags;

	/*
	 * This is broken; anything with a real cpu count has to
	 * circumvent this idiocy regardless.
	 */
1966
	apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
L
Linus Torvalds 已提交
1967 1968 1969 1970

	/*
	 * Set the IOAPIC ID to the value stored in the MPC table.
	 */
1971
	for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
L
Linus Torvalds 已提交
1972
		/* Read the register 0 value */
1973
		raw_spin_lock_irqsave(&ioapic_lock, flags);
1974
		reg_00.raw = io_apic_read(ioapic_idx, 0);
1975
		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1976

1977
		old_id = mpc_ioapic_id(ioapic_idx);
L
Linus Torvalds 已提交
1978

1979
		if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
L
Linus Torvalds 已提交
1980
			printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1981
				ioapic_idx, mpc_ioapic_id(ioapic_idx));
L
Linus Torvalds 已提交
1982 1983
			printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
				reg_00.bits.ID);
1984
			ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
L
Linus Torvalds 已提交
1985 1986 1987 1988 1989 1990 1991
		}

		/*
		 * Sanity check, is the ID really free? Every APIC in a
		 * system must have a unique ID or we get lots of nice
		 * 'stuck on smp_invalidate_needed IPI wait' messages.
		 */
1992
		if (apic->check_apicid_used(&phys_id_present_map,
1993
					    mpc_ioapic_id(ioapic_idx))) {
L
Linus Torvalds 已提交
1994
			printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1995
				ioapic_idx, mpc_ioapic_id(ioapic_idx));
L
Linus Torvalds 已提交
1996 1997 1998 1999 2000 2001 2002 2003
			for (i = 0; i < get_physical_broadcast(); i++)
				if (!physid_isset(i, phys_id_present_map))
					break;
			if (i >= get_physical_broadcast())
				panic("Max APIC ID exceeded!\n");
			printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
				i);
			physid_set(i, phys_id_present_map);
2004
			ioapics[ioapic_idx].mp_config.apicid = i;
L
Linus Torvalds 已提交
2005 2006
		} else {
			physid_mask_t tmp;
2007
			apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
2008
						    &tmp);
L
Linus Torvalds 已提交
2009 2010
			apic_printk(APIC_VERBOSE, "Setting %d in the "
					"phys_id_present_map\n",
2011
					mpc_ioapic_id(ioapic_idx));
L
Linus Torvalds 已提交
2012 2013 2014 2015 2016 2017 2018
			physids_or(phys_id_present_map, phys_id_present_map, tmp);
		}

		/*
		 * We need to adjust the IRQ routing table
		 * if the ID changed.
		 */
2019
		if (old_id != mpc_ioapic_id(ioapic_idx))
L
Linus Torvalds 已提交
2020
			for (i = 0; i < mp_irq_entries; i++)
2021 2022
				if (mp_irqs[i].dstapic == old_id)
					mp_irqs[i].dstapic
2023
						= mpc_ioapic_id(ioapic_idx);
L
Linus Torvalds 已提交
2024 2025

		/*
2026 2027
		 * Update the ID register according to the right value
		 * from the MPC table if they are different.
2028
		 */
2029
		if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
2030 2031
			continue;

L
Linus Torvalds 已提交
2032 2033
		apic_printk(APIC_VERBOSE, KERN_INFO
			"...changing IO-APIC physical APIC ID to %d ...",
2034
			mpc_ioapic_id(ioapic_idx));
L
Linus Torvalds 已提交
2035

2036
		reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2037
		raw_spin_lock_irqsave(&ioapic_lock, flags);
2038
		io_apic_write(ioapic_idx, 0, reg_00.raw);
2039
		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
L
Linus Torvalds 已提交
2040 2041 2042 2043

		/*
		 * Sanity check
		 */
2044
		raw_spin_lock_irqsave(&ioapic_lock, flags);
2045
		reg_00.raw = io_apic_read(ioapic_idx, 0);
2046
		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2047
		if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
2048
			pr_cont("could not set ID!\n");
L
Linus Torvalds 已提交
2049 2050 2051 2052
		else
			apic_printk(APIC_VERBOSE, " ok.\n");
	}
}
2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067

void __init setup_ioapic_ids_from_mpc(void)
{

	if (acpi_ioapic)
		return;
	/*
	 * Don't check I/O APIC IDs for xAPIC systems.  They have
	 * no meaning without the serial APIC bus.
	 */
	if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
		|| APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
		return;
	setup_ioapic_ids_from_mpc_nocheck();
}
2068
#endif
L
Linus Torvalds 已提交
2069

2070
int no_timer_check __initdata;
2071 2072 2073 2074 2075 2076 2077 2078

static int __init notimercheck(char *s)
{
	no_timer_check = 1;
	return 1;
}
__setup("no_timer_check", notimercheck);

L
Linus Torvalds 已提交
2079 2080 2081 2082 2083 2084 2085 2086
/*
 * There is a nasty bug in some older SMP boards, their mptable lies
 * about the timer IRQ. We do the following to work around the situation:
 *
 *	- timer IRQ defaults to IO-APIC IRQ
 *	- if this function detects that timer IRQs are defunct, then we fall
 *	  back to ISA timer IRQs
 */
2087
static int __init timer_irq_works(void)
L
Linus Torvalds 已提交
2088 2089
{
	unsigned long t1 = jiffies;
2090
	unsigned long flags;
L
Linus Torvalds 已提交
2091

2092 2093 2094
	if (no_timer_check)
		return 1;

2095
	local_save_flags(flags);
L
Linus Torvalds 已提交
2096 2097 2098
	local_irq_enable();
	/* Let ten ticks pass... */
	mdelay((10 * 1000) / HZ);
2099
	local_irq_restore(flags);
L
Linus Torvalds 已提交
2100 2101 2102 2103 2104 2105 2106 2107

	/*
	 * Expect a few ticks at least, to be sure some possible
	 * glue logic does not lock up after one or two first
	 * ticks in a non-ExtINT mode.  Also the local APIC
	 * might have cached one ExtINT interrupt.  Finally, at
	 * least one tick may be lost due to delays.
	 */
2108 2109

	/* jiffies wrap? */
2110
	if (time_after(jiffies, t1 + 4))
L
Linus Torvalds 已提交
2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136
		return 1;
	return 0;
}

/*
 * In the SMP+IOAPIC case it might happen that there are an unspecified
 * number of pending IRQ events unhandled. These cases are very rare,
 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
 * better to do it this way as thus we do not have to be aware of
 * 'pending' interrupts in the IRQ path, except at this point.
 */
/*
 * Edge triggered needs to resend any interrupt
 * that was delayed but this is now handled in the device
 * independent code.
 */

/*
 * Starting up a edge-triggered IO-APIC interrupt is
 * nasty - we need to make sure that we get the edge.
 * If it is already asserted for some reason, we need
 * return 1 to indicate that is was pending.
 *
 * This is not complete - we should be able to fake
 * an edge even if it isn't on the 8259A...
 */
2137

2138
static unsigned int startup_ioapic_irq(struct irq_data *data)
L
Linus Torvalds 已提交
2139
{
2140
	int was_pending = 0, irq = data->irq;
L
Linus Torvalds 已提交
2141 2142
	unsigned long flags;

2143
	raw_spin_lock_irqsave(&ioapic_lock, flags);
2144
	if (irq < legacy_pic->nr_legacy_irqs) {
2145
		legacy_pic->mask(irq);
2146
		if (legacy_pic->irq_pending(irq))
L
Linus Torvalds 已提交
2147 2148
			was_pending = 1;
	}
2149
	__unmask_ioapic(data->chip_data);
2150
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
L
Linus Torvalds 已提交
2151 2152 2153 2154

	return was_pending;
}

2155
static int ioapic_retrigger_irq(struct irq_data *data)
L
Linus Torvalds 已提交
2156
{
2157
	struct irq_cfg *cfg = data->chip_data;
2158
	unsigned long flags;
2159
	int cpu;
2160

2161
	raw_spin_lock_irqsave(&vector_lock, flags);
2162 2163
	cpu = cpumask_first_and(cfg->domain, cpu_online_mask);
	apic->send_IPI_mask(cpumask_of(cpu), cfg->vector);
2164
	raw_spin_unlock_irqrestore(&vector_lock, flags);
2165 2166 2167

	return 1;
}
2168

2169 2170 2171 2172 2173 2174 2175 2176
/*
 * Level and edge triggered IO-APIC interrupts need different handling,
 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
 * handled with the level-triggered descriptor, but that one has slightly
 * more overhead. Level-triggered interrupts cannot be handled with the
 * edge-triggered handler, without risking IRQ storms and other ugly
 * races.
 */
2177

2178
#ifdef CONFIG_SMP
2179
void send_cleanup_vector(struct irq_cfg *cfg)
2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194
{
	cpumask_var_t cleanup_mask;

	if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
		unsigned int i;
		for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
			apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
	} else {
		cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
		apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
		free_cpumask_var(cleanup_mask);
	}
	cfg->move_in_progress = 0;
}

2195 2196 2197
asmlinkage void smp_irq_move_cleanup_interrupt(void)
{
	unsigned vector, me;
2198

2199 2200
	ack_APIC_irq();
	irq_enter();
2201
	exit_idle();
2202 2203 2204 2205

	me = smp_processor_id();
	for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
		unsigned int irq;
2206
		unsigned int irr;
2207 2208
		struct irq_desc *desc;
		struct irq_cfg *cfg;
T
Tejun Heo 已提交
2209
		irq = __this_cpu_read(vector_irq[vector]);
2210

2211 2212 2213
		if (irq == -1)
			continue;

2214 2215 2216 2217 2218
		desc = irq_to_desc(irq);
		if (!desc)
			continue;

		cfg = irq_cfg(irq);
2219 2220 2221
		if (!cfg)
			continue;

2222
		raw_spin_lock(&desc->lock);
2223

2224 2225 2226 2227 2228 2229 2230
		/*
		 * Check if the irq migration is in progress. If so, we
		 * haven't received the cleanup request yet for this irq.
		 */
		if (cfg->move_in_progress)
			goto unlock;

2231
		if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2232 2233
			goto unlock;

2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245
		irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
		/*
		 * Check if the vector that needs to be cleanedup is
		 * registered at the cpu's IRR. If so, then this is not
		 * the best time to clean it up. Lets clean it up in the
		 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
		 * to myself.
		 */
		if (irr  & (1 << (vector % 32))) {
			apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
			goto unlock;
		}
T
Tejun Heo 已提交
2246
		__this_cpu_write(vector_irq[vector], -1);
2247
unlock:
2248
		raw_spin_unlock(&desc->lock);
2249 2250 2251 2252 2253
	}

	irq_exit();
}

T
Thomas Gleixner 已提交
2254
static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2255
{
2256
	unsigned me;
2257

2258
	if (likely(!cfg->move_in_progress))
2259 2260 2261
		return;

	me = smp_processor_id();
2262

2263
	if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2264
		send_cleanup_vector(cfg);
2265
}
2266

T
Thomas Gleixner 已提交
2267
static void irq_complete_move(struct irq_cfg *cfg)
2268
{
T
Thomas Gleixner 已提交
2269
	__irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2270 2271 2272 2273
}

void irq_force_complete_move(int irq)
{
2274
	struct irq_cfg *cfg = irq_get_chip_data(irq);
2275

2276 2277 2278
	if (!cfg)
		return;

T
Thomas Gleixner 已提交
2279
	__irq_complete_move(cfg, cfg->vector);
2280
}
2281
#else
T
Thomas Gleixner 已提交
2282
static inline void irq_complete_move(struct irq_cfg *cfg) { }
2283
#endif
Y
Yinghai Lu 已提交
2284

2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295
static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
{
	int apic, pin;
	struct irq_pin_list *entry;
	u8 vector = cfg->vector;

	for_each_irq_pin(entry, cfg->irq_2_pin) {
		unsigned int reg;

		apic = entry->apic;
		pin = entry->pin;
2296 2297

		io_apic_write(apic, 0x11 + pin*2, dest);
2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338
		reg = io_apic_read(apic, 0x10 + pin*2);
		reg &= ~IO_APIC_REDIR_VECTOR_MASK;
		reg |= vector;
		io_apic_modify(apic, 0x10 + pin*2, reg);
	}
}

/*
 * Either sets data->affinity to a valid value, and returns
 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
 * leaves data->affinity untouched.
 */
int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
			  unsigned int *dest_id)
{
	struct irq_cfg *cfg = data->chip_data;
	unsigned int irq = data->irq;
	int err;

	if (!config_enabled(CONFIG_SMP))
		return -1;

	if (!cpumask_intersects(mask, cpu_online_mask))
		return -EINVAL;

	err = assign_irq_vector(irq, cfg, mask);
	if (err)
		return err;

	err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id);
	if (err) {
		if (assign_irq_vector(irq, cfg, data->affinity))
			pr_err("Failed to recover vector for irq %d\n", irq);
		return err;
	}

	cpumask_copy(data->affinity, mask);

	return 0;
}

2339 2340 2341 2342

int native_ioapic_set_affinity(struct irq_data *data,
			       const struct cpumask *mask,
			       bool force)
2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362
{
	unsigned int dest, irq = data->irq;
	unsigned long flags;
	int ret;

	if (!config_enabled(CONFIG_SMP))
		return -1;

	raw_spin_lock_irqsave(&ioapic_lock, flags);
	ret = __ioapic_set_affinity(data, mask, &dest);
	if (!ret) {
		/* Only the high 8 bits are valid. */
		dest = SET_APIC_LOGICAL_ID(dest);
		__target_IO_APIC_irq(irq, dest, data->chip_data);
		ret = IRQ_SET_MASK_OK_NOCOPY;
	}
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
	return ret;
}

2363
static void ack_apic_edge(struct irq_data *data)
2364
{
2365
	irq_complete_move(data->chip_data);
2366
	irq_move_irq(data);
2367 2368 2369
	ack_APIC_irq();
}

Y
Yinghai Lu 已提交
2370 2371
atomic_t irq_mis_count;

2372
#ifdef CONFIG_GENERIC_PENDING_IRQ
2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395
static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
{
	struct irq_pin_list *entry;
	unsigned long flags;

	raw_spin_lock_irqsave(&ioapic_lock, flags);
	for_each_irq_pin(entry, cfg->irq_2_pin) {
		unsigned int reg;
		int pin;

		pin = entry->pin;
		reg = io_apic_read(entry->apic, 0x10 + pin*2);
		/* Is the remote IRR bit set? */
		if (reg & IO_APIC_REDIR_REMOTE_IRR) {
			raw_spin_unlock_irqrestore(&ioapic_lock, flags);
			return true;
		}
	}
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);

	return false;
}

2396 2397
static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
{
2398
	/* If we are moving the irq we need to mask it */
2399
	if (unlikely(irqd_is_setaffinity_pending(data))) {
T
Thomas Gleixner 已提交
2400
		mask_ioapic(cfg);
2401
		return true;
2402
	}
2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449
	return false;
}

static inline void ioapic_irqd_unmask(struct irq_data *data,
				      struct irq_cfg *cfg, bool masked)
{
	if (unlikely(masked)) {
		/* Only migrate the irq if the ack has been received.
		 *
		 * On rare occasions the broadcast level triggered ack gets
		 * delayed going to ioapics, and if we reprogram the
		 * vector while Remote IRR is still set the irq will never
		 * fire again.
		 *
		 * To prevent this scenario we read the Remote IRR bit
		 * of the ioapic.  This has two effects.
		 * - On any sane system the read of the ioapic will
		 *   flush writes (and acks) going to the ioapic from
		 *   this cpu.
		 * - We get to see if the ACK has actually been delivered.
		 *
		 * Based on failed experiments of reprogramming the
		 * ioapic entry from outside of irq context starting
		 * with masking the ioapic entry and then polling until
		 * Remote IRR was clear before reprogramming the
		 * ioapic I don't trust the Remote IRR bit to be
		 * completey accurate.
		 *
		 * However there appears to be no other way to plug
		 * this race, so if the Remote IRR bit is not
		 * accurate and is causing problems then it is a hardware bug
		 * and you can go talk to the chipset vendor about it.
		 */
		if (!io_apic_level_ack_pending(cfg))
			irq_move_masked_irq(data);
		unmask_ioapic(cfg);
	}
}
#else
static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
{
	return false;
}
static inline void ioapic_irqd_unmask(struct irq_data *data,
				      struct irq_cfg *cfg, bool masked)
{
}
2450 2451
#endif

2452 2453 2454 2455 2456 2457 2458 2459 2460 2461
static void ack_apic_level(struct irq_data *data)
{
	struct irq_cfg *cfg = data->chip_data;
	int i, irq = data->irq;
	unsigned long v;
	bool masked;

	irq_complete_move(cfg);
	masked = ioapic_irqd_mask(data, cfg);

Y
Yinghai Lu 已提交
2462
	/*
2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479
	 * It appears there is an erratum which affects at least version 0x11
	 * of I/O APIC (that's the 82093AA and cores integrated into various
	 * chipsets).  Under certain conditions a level-triggered interrupt is
	 * erroneously delivered as edge-triggered one but the respective IRR
	 * bit gets set nevertheless.  As a result the I/O unit expects an EOI
	 * message but it will never arrive and further interrupts are blocked
	 * from the source.  The exact reason is so far unknown, but the
	 * phenomenon was observed when two consecutive interrupt requests
	 * from a given source get delivered to the same CPU and the source is
	 * temporarily disabled in between.
	 *
	 * A workaround is to simulate an EOI message manually.  We achieve it
	 * by setting the trigger mode to edge and then to level when the edge
	 * trigger mode gets detected in the TMR of a local APIC for a
	 * level-triggered interrupt.  We mask the source for the time of the
	 * operation to prevent an edge-triggered interrupt escaping meanwhile.
	 * The idea is from Manfred Spraul.  --macro
2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492
	 *
	 * Also in the case when cpu goes offline, fixup_irqs() will forward
	 * any unhandled interrupt on the offlined cpu to the new cpu
	 * destination that is handling the corresponding interrupt. This
	 * interrupt forwarding is done via IPI's. Hence, in this case also
	 * level-triggered io-apic interrupt will be seen as an edge
	 * interrupt in the IRR. And we can't rely on the cpu's EOI
	 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
	 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
	 * supporting EOI register, we do an explicit EOI to clear the
	 * remote IRR and on IO-APIC's which don't have an EOI register,
	 * we use the above logic (mask+edge followed by unmask+level) from
	 * Manfred Spraul to clear the remote IRR.
2493
	 */
Y
Yinghai Lu 已提交
2494
	i = cfg->vector;
Y
Yinghai Lu 已提交
2495 2496
	v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));

2497 2498 2499 2500 2501 2502
	/*
	 * We must acknowledge the irq before we move it or the acknowledge will
	 * not propagate properly.
	 */
	ack_APIC_irq();

2503 2504 2505 2506 2507 2508 2509
	/*
	 * Tail end of clearing remote IRR bit (either by delivering the EOI
	 * message via io-apic EOI register write or simulating it using
	 * mask+edge followed by unnask+level logic) manually when the
	 * level triggered interrupt is seen as the edge triggered interrupt
	 * at the cpu.
	 */
2510 2511 2512
	if (!(v & (1 << (i & 0x1f)))) {
		atomic_inc(&irq_mis_count);

T
Thomas Gleixner 已提交
2513
		eoi_ioapic_irq(irq, cfg);
2514 2515
	}

2516
	ioapic_irqd_unmask(data, cfg, masked);
Y
Yinghai Lu 已提交
2517
}
2518

2519
static struct irq_chip ioapic_chip __read_mostly = {
2520 2521 2522 2523 2524 2525
	.name			= "IO-APIC",
	.irq_startup		= startup_ioapic_irq,
	.irq_mask		= mask_ioapic_irq,
	.irq_unmask		= unmask_ioapic_irq,
	.irq_ack		= ack_apic_edge,
	.irq_eoi		= ack_apic_level,
2526
	.irq_set_affinity	= native_ioapic_set_affinity,
2527
	.irq_retrigger		= ioapic_retrigger_irq,
L
Linus Torvalds 已提交
2528 2529 2530 2531
};

static inline void init_IO_APIC_traps(void)
{
2532
	struct irq_cfg *cfg;
T
Thomas Gleixner 已提交
2533
	unsigned int irq;
L
Linus Torvalds 已提交
2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545

	/*
	 * NOTE! The local APIC isn't very good at handling
	 * multiple interrupts at the same interrupt level.
	 * As the interrupt level is determined by taking the
	 * vector number and shifting that right by 4, we
	 * want to spread these out a bit so that they don't
	 * all fall in the same interrupt level.
	 *
	 * Also, we've got to be careful not to trash gate
	 * 0x80, because int 0x80 is hm, kind of importantish. ;)
	 */
T
Thomas Gleixner 已提交
2546
	for_each_active_irq(irq) {
2547
		cfg = irq_get_chip_data(irq);
2548
		if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
L
Linus Torvalds 已提交
2549 2550 2551 2552 2553
			/*
			 * Hmm.. We don't have an entry for this,
			 * so default to an old-fashioned 8259
			 * interrupt if we can..
			 */
2554 2555
			if (irq < legacy_pic->nr_legacy_irqs)
				legacy_pic->make_irq(irq);
2556
			else
L
Linus Torvalds 已提交
2557
				/* Strange. Oh, well.. */
2558
				irq_set_chip(irq, &no_irq_chip);
L
Linus Torvalds 已提交
2559 2560 2561 2562
		}
	}
}

2563 2564 2565
/*
 * The local APIC irq-chip implementation:
 */
L
Linus Torvalds 已提交
2566

2567
static void mask_lapic_irq(struct irq_data *data)
L
Linus Torvalds 已提交
2568 2569 2570 2571
{
	unsigned long v;

	v = apic_read(APIC_LVT0);
2572
	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
L
Linus Torvalds 已提交
2573 2574
}

2575
static void unmask_lapic_irq(struct irq_data *data)
L
Linus Torvalds 已提交
2576
{
2577
	unsigned long v;
L
Linus Torvalds 已提交
2578

2579
	v = apic_read(APIC_LVT0);
2580
	apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2581
}
L
Linus Torvalds 已提交
2582

2583
static void ack_lapic_irq(struct irq_data *data)
2584 2585 2586 2587
{
	ack_APIC_irq();
}

2588
static struct irq_chip lapic_chip __read_mostly = {
2589
	.name		= "local-APIC",
2590 2591 2592
	.irq_mask	= mask_lapic_irq,
	.irq_unmask	= unmask_lapic_irq,
	.irq_ack	= ack_lapic_irq,
L
Linus Torvalds 已提交
2593 2594
};

2595
static void lapic_register_intr(int irq)
2596
{
2597
	irq_clear_status_flags(irq, IRQ_LEVEL);
2598
	irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2599 2600 2601
				      "edge");
}

L
Linus Torvalds 已提交
2602 2603 2604 2605 2606 2607 2608
/*
 * This looks a bit hackish but it's about the only one way of sending
 * a few INTA cycles to 8259As and any associated glue logic.  ICR does
 * not support the ExtINT mode, unfortunately.  We need to send these
 * cycles as some i82489DX-based boards have glue logic that keeps the
 * 8259A interrupt line asserted until INTA.  --macro
 */
2609
static inline void __init unlock_ExtINT_logic(void)
L
Linus Torvalds 已提交
2610
{
2611
	int apic, pin, i;
L
Linus Torvalds 已提交
2612 2613 2614
	struct IO_APIC_route_entry entry0, entry1;
	unsigned char save_control, save_freq_select;

2615
	pin  = find_isa_irq_pin(8, mp_INT);
2616 2617 2618 2619
	if (pin == -1) {
		WARN_ON_ONCE(1);
		return;
	}
2620
	apic = find_isa_irq_apic(8, mp_INT);
2621 2622
	if (apic == -1) {
		WARN_ON_ONCE(1);
L
Linus Torvalds 已提交
2623
		return;
2624
	}
L
Linus Torvalds 已提交
2625

2626
	entry0 = ioapic_read_entry(apic, pin);
2627
	clear_IO_APIC_pin(apic, pin);
L
Linus Torvalds 已提交
2628 2629 2630 2631 2632

	memset(&entry1, 0, sizeof(entry1));

	entry1.dest_mode = 0;			/* physical delivery */
	entry1.mask = 0;			/* unmask IRQ now */
2633
	entry1.dest = hard_smp_processor_id();
L
Linus Torvalds 已提交
2634 2635 2636 2637 2638
	entry1.delivery_mode = dest_ExtINT;
	entry1.polarity = entry0.polarity;
	entry1.trigger = 0;
	entry1.vector = 0;

2639
	ioapic_write_entry(apic, pin, entry1);
L
Linus Torvalds 已提交
2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655

	save_control = CMOS_READ(RTC_CONTROL);
	save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
	CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
		   RTC_FREQ_SELECT);
	CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);

	i = 100;
	while (i-- > 0) {
		mdelay(10);
		if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
			i -= 10;
	}

	CMOS_WRITE(save_control, RTC_CONTROL);
	CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2656
	clear_IO_APIC_pin(apic, pin);
L
Linus Torvalds 已提交
2657

2658
	ioapic_write_entry(apic, pin, entry0);
L
Linus Torvalds 已提交
2659 2660
}

Y
Yinghai Lu 已提交
2661
static int disable_timer_pin_1 __initdata;
2662
/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2663
static int __init disable_timer_pin_setup(char *arg)
Y
Yinghai Lu 已提交
2664 2665 2666 2667
{
	disable_timer_pin_1 = 1;
	return 0;
}
2668
early_param("disable_timer_pin_1", disable_timer_pin_setup);
Y
Yinghai Lu 已提交
2669 2670 2671

int timer_through_8259 __initdata;

L
Linus Torvalds 已提交
2672 2673 2674 2675 2676
/*
 * This code may look a bit paranoid, but it's supposed to cooperate with
 * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
 * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
 * fanatically on his truly buggy board.
2677 2678
 *
 * FIXME: really need to revamp this for all platforms.
L
Linus Torvalds 已提交
2679
 */
2680
static inline void __init check_timer(void)
L
Linus Torvalds 已提交
2681
{
2682
	struct irq_cfg *cfg = irq_get_chip_data(0);
2683
	int node = cpu_to_node(0);
2684
	int apic1, pin1, apic2, pin2;
2685
	unsigned long flags;
2686
	int no_pin1 = 0;
2687 2688

	local_irq_save(flags);
2689

L
Linus Torvalds 已提交
2690 2691 2692
	/*
	 * get/set the timer IRQ vector:
	 */
2693
	legacy_pic->mask(0);
2694
	assign_irq_vector(0, cfg, apic->target_cpus());
L
Linus Torvalds 已提交
2695 2696

	/*
2697 2698 2699 2700 2701 2702 2703
	 * As IRQ0 is to be enabled in the 8259A, the virtual
	 * wire has to be disabled in the local APIC.  Also
	 * timer interrupts need to be acknowledged manually in
	 * the 8259A for the i82489DX when using the NMI
	 * watchdog as that APIC treats NMIs as level-triggered.
	 * The AEOI mode will finish them in the 8259A
	 * automatically.
L
Linus Torvalds 已提交
2704
	 */
2705
	apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2706
	legacy_pic->init(1);
L
Linus Torvalds 已提交
2707

2708 2709 2710 2711
	pin1  = find_isa_irq_pin(0, mp_INT);
	apic1 = find_isa_irq_apic(0, mp_INT);
	pin2  = ioapic_i8259.pin;
	apic2 = ioapic_i8259.apic;
L
Linus Torvalds 已提交
2712

2713 2714
	apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
		    "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2715
		    cfg->vector, apic1, pin1, apic2, pin2);
L
Linus Torvalds 已提交
2716

2717 2718 2719 2720 2721 2722 2723 2724
	/*
	 * Some BIOS writers are clueless and report the ExtINTA
	 * I/O APIC input from the cascaded 8259A as the timer
	 * interrupt input.  So just in case, if only one pin
	 * was found above, try it both directly and through the
	 * 8259A.
	 */
	if (pin1 == -1) {
2725
		panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2726 2727 2728 2729 2730 2731 2732 2733
		pin1 = pin2;
		apic1 = apic2;
		no_pin1 = 1;
	} else if (pin2 == -1) {
		pin2 = pin1;
		apic2 = apic1;
	}

L
Linus Torvalds 已提交
2734 2735 2736 2737
	if (pin1 != -1) {
		/*
		 * Ok, does IRQ0 through the IOAPIC work?
		 */
2738
		if (no_pin1) {
2739
			add_pin_to_irq_node(cfg, node, apic1, pin1);
2740
			setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
Y
Yinghai Lu 已提交
2741
		} else {
2742
			/* for edge trigger, setup_ioapic_irq already
Y
Yinghai Lu 已提交
2743 2744 2745 2746 2747 2748 2749
			 * leave it unmasked.
			 * so only need to unmask if it is level-trigger
			 * do we really have level trigger timer?
			 */
			int idx;
			idx = find_irq_entry(apic1, pin1, mp_INT);
			if (idx != -1 && irq_trigger(idx))
T
Thomas Gleixner 已提交
2750
				unmask_ioapic(cfg);
2751
		}
L
Linus Torvalds 已提交
2752
		if (timer_irq_works()) {
2753 2754
			if (disable_timer_pin_1 > 0)
				clear_IO_APIC_pin(0, pin1);
2755
			goto out;
L
Linus Torvalds 已提交
2756
		}
2757
		panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
Y
Yinghai Lu 已提交
2758
		local_irq_disable();
2759
		clear_IO_APIC_pin(apic1, pin1);
2760
		if (!no_pin1)
2761 2762
			apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
				    "8254 timer not connected to IO-APIC\n");
L
Linus Torvalds 已提交
2763

2764 2765 2766 2767
		apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
			    "(IRQ0) through the 8259A ...\n");
		apic_printk(APIC_QUIET, KERN_INFO
			    "..... (found apic %d pin %d) ...\n", apic2, pin2);
L
Linus Torvalds 已提交
2768 2769 2770
		/*
		 * legacy devices should be connected to IO APIC #0
		 */
2771
		replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2772
		setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2773
		legacy_pic->unmask(0);
L
Linus Torvalds 已提交
2774
		if (timer_irq_works()) {
2775
			apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2776
			timer_through_8259 = 1;
2777
			goto out;
L
Linus Torvalds 已提交
2778 2779 2780 2781
		}
		/*
		 * Cleanup, just in case ...
		 */
Y
Yinghai Lu 已提交
2782
		local_irq_disable();
2783
		legacy_pic->mask(0);
2784
		clear_IO_APIC_pin(apic2, pin2);
2785
		apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
L
Linus Torvalds 已提交
2786 2787
	}

2788 2789
	apic_printk(APIC_QUIET, KERN_INFO
		    "...trying to set up timer as Virtual Wire IRQ...\n");
L
Linus Torvalds 已提交
2790

2791
	lapic_register_intr(0);
2792
	apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);	/* Fixed mode */
2793
	legacy_pic->unmask(0);
L
Linus Torvalds 已提交
2794 2795

	if (timer_irq_works()) {
2796
		apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2797
		goto out;
L
Linus Torvalds 已提交
2798
	}
Y
Yinghai Lu 已提交
2799
	local_irq_disable();
2800
	legacy_pic->mask(0);
2801
	apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2802
	apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
L
Linus Torvalds 已提交
2803

2804 2805
	apic_printk(APIC_QUIET, KERN_INFO
		    "...trying to set up timer as ExtINT IRQ...\n");
L
Linus Torvalds 已提交
2806

2807 2808
	legacy_pic->init(0);
	legacy_pic->make_irq(0);
2809
	apic_write(APIC_LVT0, APIC_DM_EXTINT);
L
Linus Torvalds 已提交
2810 2811 2812 2813

	unlock_ExtINT_logic();

	if (timer_irq_works()) {
2814
		apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2815
		goto out;
L
Linus Torvalds 已提交
2816
	}
Y
Yinghai Lu 已提交
2817
	local_irq_disable();
2818
	apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2819 2820 2821 2822
	if (x2apic_preenabled)
		apic_printk(APIC_QUIET, KERN_INFO
			    "Perhaps problem with the pre-enabled x2apic mode\n"
			    "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
L
Linus Torvalds 已提交
2823
	panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2824
		"report.  Then try booting with the 'noapic' option.\n");
2825 2826
out:
	local_irq_restore(flags);
L
Linus Torvalds 已提交
2827 2828 2829
}

/*
2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844
 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
 * to devices.  However there may be an I/O APIC pin available for
 * this interrupt regardless.  The pin may be left unconnected, but
 * typically it will be reused as an ExtINT cascade interrupt for
 * the master 8259A.  In the MPS case such a pin will normally be
 * reported as an ExtINT interrupt in the MP table.  With ACPI
 * there is no provision for ExtINT interrupts, and in the absence
 * of an override it would be treated as an ordinary ISA I/O APIC
 * interrupt, that is edge-triggered and unmasked by default.  We
 * used to do this, but it caused problems on some systems because
 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
 * the same ExtINT cascade interrupt to drive the local APIC of the
 * bootstrap processor.  Therefore we refrain from routing IRQ2 to
 * the I/O APIC in all cases now.  No actual device should request
 * it anyway.  --macro
L
Linus Torvalds 已提交
2845
 */
2846
#define PIC_IRQS	(1UL << PIC_CASCADE_IR)
L
Linus Torvalds 已提交
2847 2848 2849

void __init setup_IO_APIC(void)
{
2850 2851 2852 2853

	/*
	 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
	 */
2854
	io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
L
Linus Torvalds 已提交
2855

2856
	apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
T
Thomas Gleixner 已提交
2857
	/*
2858 2859
         * Set up IO-APIC IRQ routing.
         */
2860 2861
	x86_init.mpparse.setup_ioapic_ids();

L
Linus Torvalds 已提交
2862 2863 2864
	sync_Arb_IDs();
	setup_IO_APIC_irqs();
	init_IO_APIC_traps();
2865
	if (legacy_pic->nr_legacy_irqs)
2866
		check_timer();
L
Linus Torvalds 已提交
2867 2868 2869
}

/*
L
Lucas De Marchi 已提交
2870
 *      Called after all the initialization is done. If we didn't find any
2871
 *      APIC bugs then we can allow the modify fast path
L
Linus Torvalds 已提交
2872
 */
2873

L
Linus Torvalds 已提交
2874 2875
static int __init io_apic_bug_finalize(void)
{
T
Thomas Gleixner 已提交
2876 2877 2878
	if (sis_apic_bug == -1)
		sis_apic_bug = 0;
	return 0;
L
Linus Torvalds 已提交
2879 2880 2881 2882
}

late_initcall(io_apic_bug_finalize);

2883
static void resume_ioapic_id(int ioapic_idx)
L
Linus Torvalds 已提交
2884 2885 2886
{
	unsigned long flags;
	union IO_APIC_reg_00 reg_00;
2887

2888
	raw_spin_lock_irqsave(&ioapic_lock, flags);
2889 2890 2891 2892
	reg_00.raw = io_apic_read(ioapic_idx, 0);
	if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
		reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
		io_apic_write(ioapic_idx, 0, reg_00.raw);
L
Linus Torvalds 已提交
2893
	}
2894
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2895
}
L
Linus Torvalds 已提交
2896

2897 2898
static void ioapic_resume(void)
{
2899
	int ioapic_idx;
2900

2901 2902
	for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--)
		resume_ioapic_id(ioapic_idx);
2903 2904

	restore_ioapic_entries();
L
Linus Torvalds 已提交
2905 2906
}

2907
static struct syscore_ops ioapic_syscore_ops = {
2908
	.suspend = save_ioapic_entries,
L
Linus Torvalds 已提交
2909 2910 2911
	.resume = ioapic_resume,
};

2912
static int __init ioapic_init_ops(void)
L
Linus Torvalds 已提交
2913
{
2914 2915
	register_syscore_ops(&ioapic_syscore_ops);

L
Linus Torvalds 已提交
2916 2917 2918
	return 0;
}

2919
device_initcall(ioapic_init_ops);
L
Linus Torvalds 已提交
2920

2921
/*
2922
 * Dynamic irq allocate and deallocation
2923
 */
2924
unsigned int __create_irqs(unsigned int from, unsigned int count, int node)
2925
{
2926
	struct irq_cfg **cfg;
2927
	unsigned long flags;
2928
	int irq, i;
2929

2930 2931
	if (from < nr_irqs_gsi)
		from = nr_irqs_gsi;
2932

2933 2934
	cfg = kzalloc_node(count * sizeof(cfg[0]), GFP_KERNEL, node);
	if (!cfg)
2935
		return 0;
2936 2937 2938 2939 2940 2941 2942 2943 2944

	irq = alloc_irqs_from(from, count, node);
	if (irq < 0)
		goto out_cfgs;

	for (i = 0; i < count; i++) {
		cfg[i] = alloc_irq_cfg(irq + i, node);
		if (!cfg[i])
			goto out_irqs;
2945
	}
2946

2947
	raw_spin_lock_irqsave(&vector_lock, flags);
2948 2949 2950
	for (i = 0; i < count; i++)
		if (__assign_irq_vector(irq + i, cfg[i], apic->target_cpus()))
			goto out_vecs;
2951
	raw_spin_unlock_irqrestore(&vector_lock, flags);
2952

2953 2954 2955
	for (i = 0; i < count; i++) {
		irq_set_chip_data(irq + i, cfg[i]);
		irq_clear_status_flags(irq + i, IRQ_NOREQUEST);
2956
	}
2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975

	kfree(cfg);
	return irq;

out_vecs:
	for (i--; i >= 0; i--)
		__clear_irq_vector(irq + i, cfg[i]);
	raw_spin_unlock_irqrestore(&vector_lock, flags);
out_irqs:
	for (i = 0; i < count; i++)
		free_irq_at(irq + i, cfg[i]);
out_cfgs:
	kfree(cfg);
	return 0;
}

unsigned int create_irq_nr(unsigned int from, int node)
{
	return __create_irqs(from, 1, node);
2976 2977
}

Y
Yinghai Lu 已提交
2978 2979
int create_irq(void)
{
2980
	int node = cpu_to_node(0);
2981
	unsigned int irq_want;
2982 2983
	int irq;

2984
	irq_want = nr_irqs_gsi;
2985
	irq = create_irq_nr(irq_want, node);
2986 2987 2988 2989 2990

	if (irq == 0)
		irq = -1;

	return irq;
Y
Yinghai Lu 已提交
2991 2992
}

2993 2994
void destroy_irq(unsigned int irq)
{
2995
	struct irq_cfg *cfg = irq_get_chip_data(irq);
2996 2997
	unsigned long flags;

2998
	irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
2999

3000 3001
	free_remapped_irq(irq);

3002
	raw_spin_lock_irqsave(&vector_lock, flags);
3003
	__clear_irq_vector(irq, cfg);
3004
	raw_spin_unlock_irqrestore(&vector_lock, flags);
3005
	free_irq_at(irq, cfg);
3006 3007
}

3008
void destroy_irqs(unsigned int irq, unsigned int count)
3009 3010 3011 3012 3013 3014 3015
{
	unsigned int i;

	for (i = 0; i < count; i++)
		destroy_irq(irq + i);
}

3016
/*
S
Simon Arlott 已提交
3017
 * MSI message composition
3018
 */
3019 3020 3021
void native_compose_msi_msg(struct pci_dev *pdev,
			    unsigned int irq, unsigned int dest,
			    struct msi_msg *msg, u8 hpet_id)
3022
{
3023
	struct irq_cfg *cfg = irq_cfg(irq);
3024

3025
	msg->address_hi = MSI_ADDR_BASE_HI;
3026

3027
	if (x2apic_enabled())
3028
		msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest);
3029

3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046
	msg->address_lo =
		MSI_ADDR_BASE_LO |
		((apic->irq_dest_mode == 0) ?
			MSI_ADDR_DEST_MODE_PHYSICAL:
			MSI_ADDR_DEST_MODE_LOGICAL) |
		((apic->irq_delivery_mode != dest_LowestPrio) ?
			MSI_ADDR_REDIRECTION_CPU:
			MSI_ADDR_REDIRECTION_LOWPRI) |
		MSI_ADDR_DEST_ID(dest);

	msg->data =
		MSI_DATA_TRIGGER_EDGE |
		MSI_DATA_LEVEL_ASSERT |
		((apic->irq_delivery_mode != dest_LowestPrio) ?
			MSI_DATA_DELIVERY_FIXED:
			MSI_DATA_DELIVERY_LOWPRI) |
		MSI_DATA_VECTOR(cfg->vector);
3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070
}

#ifdef CONFIG_PCI_MSI
static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
			   struct msi_msg *msg, u8 hpet_id)
{
	struct irq_cfg *cfg;
	int err;
	unsigned dest;

	if (disable_apic)
		return -ENXIO;

	cfg = irq_cfg(irq);
	err = assign_irq_vector(irq, cfg, apic->target_cpus());
	if (err)
		return err;

	err = apic->cpu_mask_to_apicid_and(cfg->domain,
					   apic->target_cpus(), &dest);
	if (err)
		return err;

	x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id);
3071

3072
	return 0;
3073 3074
}

3075 3076
static int
msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3077
{
3078
	struct irq_cfg *cfg = data->chip_data;
3079 3080 3081
	struct msi_msg msg;
	unsigned int dest;

3082
	if (__ioapic_set_affinity(data, mask, &dest))
3083
		return -1;
3084

3085
	__get_cached_msi_msg(data->msi_desc, &msg);
3086 3087

	msg.data &= ~MSI_DATA_VECTOR_MASK;
3088
	msg.data |= MSI_DATA_VECTOR(cfg->vector);
3089 3090 3091
	msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
	msg.address_lo |= MSI_ADDR_DEST_ID(dest);

3092
	__write_msi_msg(data->msi_desc, &msg);
3093

3094
	return IRQ_SET_MASK_OK_NOCOPY;
3095 3096
}

3097 3098 3099 3100 3101
/*
 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
 * which implement the MSI or MSI-X Capability Structure.
 */
static struct irq_chip msi_chip = {
3102 3103 3104 3105 3106 3107
	.name			= "PCI-MSI",
	.irq_unmask		= unmask_msi_irq,
	.irq_mask		= mask_msi_irq,
	.irq_ack		= ack_apic_edge,
	.irq_set_affinity	= msi_set_affinity,
	.irq_retrigger		= ioapic_retrigger_irq,
3108 3109
};

3110 3111
int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
		  unsigned int irq_base, unsigned int irq_offset)
3112
{
3113
	struct irq_chip *chip = &msi_chip;
3114
	struct msi_msg msg;
3115
	unsigned int irq = irq_base + irq_offset;
3116
	int ret;
3117

3118
	ret = msi_compose_msg(dev, irq, &msg, -1);
3119 3120 3121
	if (ret < 0)
		return ret;

3122 3123 3124 3125 3126 3127 3128 3129
	irq_set_msi_desc_off(irq_base, irq_offset, msidesc);

	/*
	 * MSI-X message is written per-IRQ, the offset is always 0.
	 * MSI message denotes a contiguous group of IRQs, written for 0th IRQ.
	 */
	if (!irq_offset)
		write_msi_msg(irq, &msg);
3130

3131
	setup_remapped_irq(irq, irq_get_chip_data(irq), chip);
3132 3133

	irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3134

Y
Yinghai Lu 已提交
3135 3136
	dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);

3137 3138 3139
	return 0;
}

3140
int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3141
{
3142
	unsigned int irq, irq_want;
3143
	struct msi_desc *msidesc;
3144 3145 3146 3147 3148
	int node, ret;

	/* Multiple MSI vectors only supported with interrupt remapping */
	if (type == PCI_CAP_ID_MSI && nvec > 1)
		return 1;
3149

3150
	node = dev_to_node(&dev->dev);
3151
	irq_want = nr_irqs_gsi;
3152
	list_for_each_entry(msidesc, &dev->msi_list, list) {
3153
		irq = create_irq_nr(irq_want, node);
3154
		if (irq == 0)
3155
			return -ENOSPC;
3156

Y
Yinghai Lu 已提交
3157
		irq_want = irq + 1;
3158

3159
		ret = setup_msi_irq(dev, msidesc, irq, 0);
3160 3161 3162 3163
		if (ret < 0)
			goto error;
	}
	return 0;
3164 3165

error:
3166 3167
	destroy_irq(irq);
	return ret;
3168 3169
}

S
Stefano Stabellini 已提交
3170
void native_teardown_msi_irq(unsigned int irq)
3171
{
3172
	destroy_irq(irq);
3173 3174
}

3175
#ifdef CONFIG_DMAR_TABLE
3176 3177 3178
static int
dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
		      bool force)
3179
{
3180 3181
	struct irq_cfg *cfg = data->chip_data;
	unsigned int dest, irq = data->irq;
3182 3183
	struct msi_msg msg;

3184
	if (__ioapic_set_affinity(data, mask, &dest))
3185
		return -1;
3186 3187 3188 3189 3190 3191 3192

	dmar_msi_read(irq, &msg);

	msg.data &= ~MSI_DATA_VECTOR_MASK;
	msg.data |= MSI_DATA_VECTOR(cfg->vector);
	msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
	msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3193
	msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3194 3195

	dmar_msi_write(irq, &msg);
3196

3197
	return IRQ_SET_MASK_OK_NOCOPY;
3198
}
Y
Yinghai Lu 已提交
3199

3200
static struct irq_chip dmar_msi_type = {
3201 3202 3203 3204 3205 3206
	.name			= "DMAR_MSI",
	.irq_unmask		= dmar_msi_unmask,
	.irq_mask		= dmar_msi_mask,
	.irq_ack		= ack_apic_edge,
	.irq_set_affinity	= dmar_msi_set_affinity,
	.irq_retrigger		= ioapic_retrigger_irq,
3207 3208 3209 3210 3211 3212
};

int arch_setup_dmar_msi(unsigned int irq)
{
	int ret;
	struct msi_msg msg;
3213

3214
	ret = msi_compose_msg(NULL, irq, &msg, -1);
3215 3216 3217
	if (ret < 0)
		return ret;
	dmar_msi_write(irq, &msg);
3218 3219
	irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
				      "edge");
3220 3221 3222 3223
	return 0;
}
#endif

3224 3225
#ifdef CONFIG_HPET_TIMER

3226 3227
static int hpet_msi_set_affinity(struct irq_data *data,
				 const struct cpumask *mask, bool force)
3228
{
3229
	struct irq_cfg *cfg = data->chip_data;
3230 3231 3232
	struct msi_msg msg;
	unsigned int dest;

3233
	if (__ioapic_set_affinity(data, mask, &dest))
3234
		return -1;
3235

3236
	hpet_msi_read(data->handler_data, &msg);
3237 3238 3239 3240 3241 3242

	msg.data &= ~MSI_DATA_VECTOR_MASK;
	msg.data |= MSI_DATA_VECTOR(cfg->vector);
	msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
	msg.address_lo |= MSI_ADDR_DEST_ID(dest);

3243
	hpet_msi_write(data->handler_data, &msg);
3244

3245
	return IRQ_SET_MASK_OK_NOCOPY;
3246
}
Y
Yinghai Lu 已提交
3247

3248
static struct irq_chip hpet_msi_type = {
3249
	.name = "HPET_MSI",
3250 3251
	.irq_unmask = hpet_msi_unmask,
	.irq_mask = hpet_msi_mask,
3252
	.irq_ack = ack_apic_edge,
3253
	.irq_set_affinity = hpet_msi_set_affinity,
3254
	.irq_retrigger = ioapic_retrigger_irq,
3255 3256
};

3257
int default_setup_hpet_msi(unsigned int irq, unsigned int id)
3258
{
3259
	struct irq_chip *chip = &hpet_msi_type;
3260
	struct msi_msg msg;
3261
	int ret;
3262

3263
	ret = msi_compose_msg(NULL, irq, &msg, id);
3264 3265 3266
	if (ret < 0)
		return ret;

3267
	hpet_msi_write(irq_get_handler_data(irq), &msg);
3268
	irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3269
	setup_remapped_irq(irq, irq_get_chip_data(irq), chip);
Y
Yinghai Lu 已提交
3270

3271
	irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3272 3273 3274 3275
	return 0;
}
#endif

3276
#endif /* CONFIG_PCI_MSI */
3277 3278 3279 3280 3281
/*
 * Hypertransport interrupt support
 */
#ifdef CONFIG_HT_IRQ

3282
static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3283
{
3284 3285
	struct ht_irq_msg msg;
	fetch_ht_irq_msg(irq, &msg);
3286

3287
	msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3288
	msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3289

3290
	msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3291
	msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3292

3293
	write_ht_irq_msg(irq, &msg);
3294 3295
}

3296 3297
static int
ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3298
{
3299
	struct irq_cfg *cfg = data->chip_data;
3300 3301
	unsigned int dest;

3302
	if (__ioapic_set_affinity(data, mask, &dest))
3303
		return -1;
3304

3305
	target_ht_irq(data->irq, dest, cfg->vector);
3306
	return IRQ_SET_MASK_OK_NOCOPY;
3307
}
Y
Yinghai Lu 已提交
3308

3309
static struct irq_chip ht_irq_chip = {
3310 3311 3312 3313 3314 3315
	.name			= "PCI-HT",
	.irq_mask		= mask_ht_irq,
	.irq_unmask		= unmask_ht_irq,
	.irq_ack		= ack_apic_edge,
	.irq_set_affinity	= ht_set_affinity,
	.irq_retrigger		= ioapic_retrigger_irq,
3316 3317 3318 3319
};

int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
{
3320
	struct irq_cfg *cfg;
3321 3322
	struct ht_irq_msg msg;
	unsigned dest;
3323
	int err;
3324

J
Jan Beulich 已提交
3325 3326 3327
	if (disable_apic)
		return -ENXIO;

Y
Yinghai Lu 已提交
3328
	cfg = irq_cfg(irq);
3329
	err = assign_irq_vector(irq, cfg, apic->target_cpus());
3330 3331
	if (err)
		return err;
3332

3333 3334 3335 3336
	err = apic->cpu_mask_to_apicid_and(cfg->domain,
					   apic->target_cpus(), &dest);
	if (err)
		return err;
3337

3338
	msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3339

3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351
	msg.address_lo =
		HT_IRQ_LOW_BASE |
		HT_IRQ_LOW_DEST_ID(dest) |
		HT_IRQ_LOW_VECTOR(cfg->vector) |
		((apic->irq_dest_mode == 0) ?
			HT_IRQ_LOW_DM_PHYSICAL :
			HT_IRQ_LOW_DM_LOGICAL) |
		HT_IRQ_LOW_RQEOI_EDGE |
		((apic->irq_delivery_mode != dest_LowestPrio) ?
			HT_IRQ_LOW_MT_FIXED :
			HT_IRQ_LOW_MT_ARBITRATED) |
		HT_IRQ_LOW_IRQ_MASKED;
3352

3353
	write_ht_irq_msg(irq, &msg);
3354

3355 3356
	irq_set_chip_and_handler_name(irq, &ht_irq_chip,
				      handle_edge_irq, "edge");
3357

3358
	dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
Y
Yinghai Lu 已提交
3359

3360
	return 0;
3361 3362 3363
}
#endif /* CONFIG_HT_IRQ */

3364
static int
3365 3366 3367 3368 3369 3370 3371 3372 3373
io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
{
	struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
	int ret;

	if (!cfg)
		return -EINVAL;
	ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
	if (!ret)
3374
		setup_ioapic_irq(irq, cfg, attr);
3375 3376 3377
	return ret;
}

3378 3379
int io_apic_setup_irq_pin_once(unsigned int irq, int node,
			       struct io_apic_irq_attr *attr)
3380
{
3381
	unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin;
3382
	int ret;
3383
	struct IO_APIC_route_entry orig_entry;
3384 3385

	/* Avoid redundant programming */
3386
	if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) {
3387 3388 3389 3390 3391
		pr_debug("Pin %d-%d already programmed\n", mpc_ioapic_id(ioapic_idx), pin);
		orig_entry = ioapic_read_entry(attr->ioapic, pin);
		if (attr->trigger == orig_entry.trigger && attr->polarity == orig_entry.polarity)
			return 0;
		return -EBUSY;
3392 3393 3394
	}
	ret = io_apic_setup_irq_pin(irq, node, attr);
	if (!ret)
3395
		set_bit(pin, ioapics[ioapic_idx].pin_programmed);
3396 3397 3398
	return ret;
}

3399
static int __init io_apic_get_redir_entries(int ioapic)
3400 3401 3402 3403
{
	union IO_APIC_reg_01	reg_01;
	unsigned long flags;

3404
	raw_spin_lock_irqsave(&ioapic_lock, flags);
3405
	reg_01.raw = io_apic_read(ioapic, 1);
3406
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3407

3408 3409 3410 3411 3412
	/* The register returns the maximum index redir index
	 * supported, which is one less than the total number of redir
	 * entries.
	 */
	return reg_01.bits.entries + 1;
3413 3414
}

3415
static void __init probe_nr_irqs_gsi(void)
3416
{
3417
	int nr;
3418

3419
	nr = gsi_top + NR_IRQS_LEGACY;
3420
	if (nr > nr_irqs_gsi)
3421
		nr_irqs_gsi = nr;
3422 3423

	printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3424 3425
}

3426 3427 3428 3429 3430
int get_nr_irqs_gsi(void)
{
	return nr_irqs_gsi;
}

Y
Yinghai Lu 已提交
3431 3432 3433 3434
int __init arch_probe_nr_irqs(void)
{
	int nr;

Y
Yinghai Lu 已提交
3435 3436
	if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
		nr_irqs = NR_VECTORS * nr_cpu_ids;
Y
Yinghai Lu 已提交
3437

Y
Yinghai Lu 已提交
3438 3439 3440 3441 3442 3443 3444 3445
	nr = nr_irqs_gsi + 8 * nr_cpu_ids;
#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
	/*
	 * for MSI and HT dyn irq
	 */
	nr += nr_irqs_gsi * 16;
#endif
	if (nr < nr_irqs)
Y
Yinghai Lu 已提交
3446 3447
		nr_irqs = nr;

3448
	return NR_IRQS_LEGACY;
Y
Yinghai Lu 已提交
3449 3450
}

3451 3452
int io_apic_set_pci_routing(struct device *dev, int irq,
			    struct io_apic_irq_attr *irq_attr)
3453 3454 3455 3456 3457
{
	int node;

	if (!IO_APIC_IRQ(irq)) {
		apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3458
			    irq_attr->ioapic);
3459 3460 3461
		return -EINVAL;
	}

3462
	node = dev ? dev_to_node(dev) : cpu_to_node(0);
3463

3464
	return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3465 3466
}

3467
#ifdef CONFIG_X86_32
3468
static int __init io_apic_get_unique_id(int ioapic, int apic_id)
L
Linus Torvalds 已提交
3469 3470 3471 3472 3473 3474 3475 3476
{
	union IO_APIC_reg_00 reg_00;
	static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
	physid_mask_t tmp;
	unsigned long flags;
	int i = 0;

	/*
3477 3478
	 * The P4 platform supports up to 256 APIC IDs on two separate APIC
	 * buses (one for LAPICs, one for IOAPICs), where predecessors only
L
Linus Torvalds 已提交
3479
	 * supports up to 16 on one shared APIC bus.
3480
	 *
L
Linus Torvalds 已提交
3481 3482 3483 3484 3485
	 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
	 *      advantage of new APIC bus architecture.
	 */

	if (physids_empty(apic_id_map))
3486
		apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
L
Linus Torvalds 已提交
3487

3488
	raw_spin_lock_irqsave(&ioapic_lock, flags);
L
Linus Torvalds 已提交
3489
	reg_00.raw = io_apic_read(ioapic, 0);
3490
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
L
Linus Torvalds 已提交
3491 3492 3493 3494 3495 3496 3497 3498

	if (apic_id >= get_physical_broadcast()) {
		printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
			"%d\n", ioapic, apic_id, reg_00.bits.ID);
		apic_id = reg_00.bits.ID;
	}

	/*
3499
	 * Every APIC in a system must have a unique ID or we get lots of nice
L
Linus Torvalds 已提交
3500 3501
	 * 'stuck on smp_invalidate_needed IPI wait' messages.
	 */
3502
	if (apic->check_apicid_used(&apic_id_map, apic_id)) {
L
Linus Torvalds 已提交
3503 3504

		for (i = 0; i < get_physical_broadcast(); i++) {
3505
			if (!apic->check_apicid_used(&apic_id_map, i))
L
Linus Torvalds 已提交
3506 3507 3508 3509 3510 3511 3512 3513 3514 3515
				break;
		}

		if (i == get_physical_broadcast())
			panic("Max apic_id exceeded!\n");

		printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
			"trying %d\n", ioapic, apic_id, i);

		apic_id = i;
3516
	}
L
Linus Torvalds 已提交
3517

3518
	apic->apicid_to_cpu_present(apic_id, &tmp);
L
Linus Torvalds 已提交
3519 3520 3521 3522 3523
	physids_or(apic_id_map, apic_id_map, tmp);

	if (reg_00.bits.ID != apic_id) {
		reg_00.bits.ID = apic_id;

3524
		raw_spin_lock_irqsave(&ioapic_lock, flags);
L
Linus Torvalds 已提交
3525 3526
		io_apic_write(ioapic, 0, reg_00.raw);
		reg_00.raw = io_apic_read(ioapic, 0);
3527
		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
L
Linus Torvalds 已提交
3528 3529

		/* Sanity check */
3530
		if (reg_00.bits.ID != apic_id) {
3531 3532
			pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
			       ioapic);
3533 3534
			return -1;
		}
L
Linus Torvalds 已提交
3535 3536 3537 3538 3539 3540 3541
	}

	apic_printk(APIC_VERBOSE, KERN_INFO
			"IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);

	return apic_id;
}
3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558

static u8 __init io_apic_unique_id(u8 id)
{
	if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
	    !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
		return io_apic_get_unique_id(nr_ioapics, id);
	else
		return id;
}
#else
static u8 __init io_apic_unique_id(u8 id)
{
	int i;
	DECLARE_BITMAP(used, 256);

	bitmap_zero(used, 256);
	for (i = 0; i < nr_ioapics; i++) {
3559
		__set_bit(mpc_ioapic_id(i), used);
3560 3561 3562 3563 3564
	}
	if (!test_bit(id, used))
		return id;
	return find_first_zero_bit(used, 256);
}
3565
#endif
L
Linus Torvalds 已提交
3566

3567
static int __init io_apic_get_version(int ioapic)
L
Linus Torvalds 已提交
3568 3569 3570 3571
{
	union IO_APIC_reg_01	reg_01;
	unsigned long flags;

3572
	raw_spin_lock_irqsave(&ioapic_lock, flags);
L
Linus Torvalds 已提交
3573
	reg_01.raw = io_apic_read(ioapic, 1);
3574
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
L
Linus Torvalds 已提交
3575 3576 3577 3578

	return reg_01.bits.version;
}

3579
int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3580
{
3581
	int ioapic, pin, idx;
3582 3583 3584 3585

	if (skip_ioapic_setup)
		return -1;

3586 3587
	ioapic = mp_find_ioapic(gsi);
	if (ioapic < 0)
3588 3589
		return -1;

3590 3591 3592 3593 3594 3595
	pin = mp_find_ioapic_pin(ioapic, gsi);
	if (pin < 0)
		return -1;

	idx = find_irq_entry(ioapic, pin, mp_INT);
	if (idx < 0)
3596 3597
		return -1;

3598 3599
	*trigger = irq_trigger(idx);
	*polarity = irq_polarity(idx);
3600 3601 3602
	return 0;
}

3603 3604 3605
/*
 * This function currently is only a helper for the i386 smp boot process where
 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3606
 * so mask in all cases should simply be apic->target_cpus()
3607 3608 3609 3610
 */
#ifdef CONFIG_SMP
void __init setup_ioapic_dest(void)
{
E
Eric W. Biederman 已提交
3611
	int pin, ioapic, irq, irq_entry;
3612
	const struct cpumask *mask;
3613
	struct irq_data *idata;
3614 3615 3616 3617

	if (skip_ioapic_setup == 1)
		return;

E
Eric W. Biederman 已提交
3618
	for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
S
Suresh Siddha 已提交
3619
	for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
3620 3621 3622 3623
		irq_entry = find_irq_entry(ioapic, pin, mp_INT);
		if (irq_entry == -1)
			continue;
		irq = pin_2_irq(irq_entry, ioapic, pin);
3624

E
Eric W. Biederman 已提交
3625 3626 3627
		if ((ioapic > 0) && (irq > 16))
			continue;

3628
		idata = irq_get_irq_data(irq);
3629

3630 3631 3632
		/*
		 * Honour affinities which have been set in early boot
		 */
3633 3634
		if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
			mask = idata->affinity;
3635 3636
		else
			mask = apic->target_cpus();
3637

3638
		x86_io_apic_ops.set_affinity(idata, mask, false);
3639
	}
3640

3641 3642 3643
}
#endif

3644 3645 3646 3647
#define IOAPIC_RESOURCE_NAME_SIZE 11

static struct resource *ioapic_resources;

3648
static struct resource * __init ioapic_setup_resources(int nr_ioapics)
3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663
{
	unsigned long n;
	struct resource *res;
	char *mem;
	int i;

	if (nr_ioapics <= 0)
		return NULL;

	n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
	n *= nr_ioapics;

	mem = alloc_bootmem(n);
	res = (void *)mem;

3664
	mem += sizeof(struct resource) * nr_ioapics;
3665

3666 3667 3668
	for (i = 0; i < nr_ioapics; i++) {
		res[i].name = mem;
		res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3669
		snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3670
		mem += IOAPIC_RESOURCE_NAME_SIZE;
3671 3672 3673 3674 3675 3676 3677
	}

	ioapic_resources = res;

	return res;
}

3678
void __init native_io_apic_init_mappings(void)
3679 3680
{
	unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3681
	struct resource *ioapic_res;
T
Thomas Gleixner 已提交
3682
	int i;
3683

3684
	ioapic_res = ioapic_setup_resources(nr_ioapics);
3685 3686
	for (i = 0; i < nr_ioapics; i++) {
		if (smp_found_config) {
3687
			ioapic_phys = mpc_ioapic_addr(i);
3688
#ifdef CONFIG_X86_32
T
Thomas Gleixner 已提交
3689 3690 3691 3692 3693 3694 3695 3696 3697
			if (!ioapic_phys) {
				printk(KERN_ERR
				       "WARNING: bogus zero IO-APIC "
				       "address found in MPTABLE, "
				       "disabling IO/APIC support!\n");
				smp_found_config = 0;
				skip_ioapic_setup = 1;
				goto fake_ioapic_page;
			}
3698
#endif
3699
		} else {
3700
#ifdef CONFIG_X86_32
3701
fake_ioapic_page:
3702
#endif
3703
			ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3704 3705 3706
			ioapic_phys = __pa(ioapic_phys);
		}
		set_fixmap_nocache(idx, ioapic_phys);
3707 3708 3709
		apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
			__fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
			ioapic_phys);
3710
		idx++;
3711

3712
		ioapic_res->start = ioapic_phys;
3713
		ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3714
		ioapic_res++;
3715
	}
3716 3717

	probe_nr_irqs_gsi();
3718 3719
}

3720
void __init ioapic_insert_resources(void)
3721 3722 3723 3724 3725
{
	int i;
	struct resource *r = ioapic_resources;

	if (!r) {
3726
		if (nr_ioapics > 0)
3727 3728
			printk(KERN_ERR
				"IO APIC resources couldn't be allocated.\n");
3729
		return;
3730 3731 3732 3733 3734 3735 3736
	}

	for (i = 0; i < nr_ioapics; i++) {
		insert_resource(&iomem_resource, r);
		r++;
	}
}
3737

3738
int mp_find_ioapic(u32 gsi)
3739 3740 3741
{
	int i = 0;

3742 3743 3744
	if (nr_ioapics == 0)
		return -1;

3745 3746
	/* Find the IOAPIC that manages this GSI. */
	for (i = 0; i < nr_ioapics; i++) {
3747 3748 3749
		struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
		if ((gsi >= gsi_cfg->gsi_base)
		    && (gsi <= gsi_cfg->gsi_end))
3750 3751
			return i;
	}
3752

3753 3754 3755 3756
	printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
	return -1;
}

3757
int mp_find_ioapic_pin(int ioapic, u32 gsi)
3758
{
3759 3760
	struct mp_ioapic_gsi *gsi_cfg;

3761 3762
	if (WARN_ON(ioapic == -1))
		return -1;
3763 3764 3765

	gsi_cfg = mp_ioapic_gsi_routing(ioapic);
	if (WARN_ON(gsi > gsi_cfg->gsi_end))
3766 3767
		return -1;

3768
	return gsi - gsi_cfg->gsi_base;
3769 3770
}

3771
static __init int bad_ioapic(unsigned long address)
3772 3773
{
	if (nr_ioapics >= MAX_IO_APICS) {
3774 3775
		pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
			MAX_IO_APICS, nr_ioapics);
3776 3777 3778
		return 1;
	}
	if (!address) {
3779
		pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n");
3780 3781
		return 1;
	}
3782 3783 3784
	return 0;
}

3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803
static __init int bad_ioapic_register(int idx)
{
	union IO_APIC_reg_00 reg_00;
	union IO_APIC_reg_01 reg_01;
	union IO_APIC_reg_02 reg_02;

	reg_00.raw = io_apic_read(idx, 0);
	reg_01.raw = io_apic_read(idx, 1);
	reg_02.raw = io_apic_read(idx, 2);

	if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
		pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
			mpc_ioapic_addr(idx));
		return 1;
	}

	return 0;
}

3804 3805 3806
void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
{
	int idx = 0;
3807
	int entries;
3808
	struct mp_ioapic_gsi *gsi_cfg;
3809 3810 3811 3812 3813 3814

	if (bad_ioapic(address))
		return;

	idx = nr_ioapics;

3815 3816 3817
	ioapics[idx].mp_config.type = MP_IOAPIC;
	ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
	ioapics[idx].mp_config.apicaddr = address;
3818 3819

	set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
3820 3821 3822 3823 3824 3825

	if (bad_ioapic_register(idx)) {
		clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
		return;
	}

3826 3827
	ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
	ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
3828 3829 3830 3831 3832

	/*
	 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
	 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
	 */
3833
	entries = io_apic_get_redir_entries(idx);
3834 3835 3836
	gsi_cfg = mp_ioapic_gsi_routing(idx);
	gsi_cfg->gsi_base = gsi_base;
	gsi_cfg->gsi_end = gsi_base + entries - 1;
3837 3838 3839 3840

	/*
	 * The number of IO-APIC IRQ registers (== #pins):
	 */
S
Suresh Siddha 已提交
3841
	ioapics[idx].nr_registers = entries;
3842

3843 3844
	if (gsi_cfg->gsi_end >= gsi_top)
		gsi_top = gsi_cfg->gsi_end + 1;
3845

3846 3847 3848 3849
	pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
		idx, mpc_ioapic_id(idx),
		mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
		gsi_cfg->gsi_base, gsi_cfg->gsi_end);
3850 3851 3852

	nr_ioapics++;
}
3853 3854 3855 3856

/* Enable IOAPIC early just for system timer */
void __init pre_init_apic_IRQ0(void)
{
3857
	struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
3858 3859 3860

	printk(KERN_INFO "Early APIC setup for system timer0\n");
#ifndef CONFIG_SMP
3861 3862
	physid_set_mask_of_physid(boot_cpu_physical_apicid,
					 &phys_cpu_present_map);
3863 3864 3865
#endif
	setup_local_APIC();

3866
	io_apic_setup_irq_pin(0, 0, &attr);
3867 3868
	irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
				      "edge");
3869
}