intel_display.c 233.9 KB
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/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */

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#include <linux/dmi.h>
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#include <linux/module.h>
#include <linux/input.h>
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#include <linux/i2c.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/vgaarb.h>
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#include <drm/drm_edid.h>
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#include "drmP.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"
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#include "i915_trace.h"
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#include "drm_dp_helper.h"
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#include "drm_crtc_helper.h"
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#include <linux/dma_remapping.h>
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#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))

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bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
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static void intel_increase_pllclock(struct drm_crtc *crtc);
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static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
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typedef struct {
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	/* given values */
	int n;
	int m1, m2;
	int p1, p2;
	/* derived values */
	int	dot;
	int	vco;
	int	m;
	int	p;
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} intel_clock_t;

typedef struct {
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	int	min, max;
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} intel_range_t;

typedef struct {
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	int	dot_limit;
	int	p2_slow, p2_fast;
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} intel_p2_t;

#define INTEL_P2_NUM		      2
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typedef struct intel_limit intel_limit_t;
struct intel_limit {
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	intel_range_t   dot, vco, n, m, m1, m2, p, p1;
	intel_p2_t	    p2;
	bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
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			int, int, intel_clock_t *, intel_clock_t *);
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};
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/* FDI */
#define IRONLAKE_FDI_FREQ		2700000 /* in kHz for mode->clock */

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static bool
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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		    int target, int refclk, intel_clock_t *match_clock,
		    intel_clock_t *best_clock);
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static bool
intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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			int target, int refclk, intel_clock_t *match_clock,
			intel_clock_t *best_clock);
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static bool
intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
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		      int target, int refclk, intel_clock_t *match_clock,
		      intel_clock_t *best_clock);
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static bool
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intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
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			   int target, int refclk, intel_clock_t *match_clock,
			   intel_clock_t *best_clock);
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static bool
intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
			int target, int refclk, intel_clock_t *match_clock,
			intel_clock_t *best_clock);

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static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_device *dev)
{
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	if (IS_GEN5(dev)) {
		struct drm_i915_private *dev_priv = dev->dev_private;
		return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
	} else
		return 27;
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}

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static const intel_limit_t intel_limits_i8xx_dvo = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 930000, .max = 1400000 },
	.n = { .min = 3, .max = 16 },
	.m = { .min = 96, .max = 140 },
	.m1 = { .min = 18, .max = 26 },
	.m2 = { .min = 6, .max = 16 },
	.p = { .min = 4, .max = 128 },
	.p1 = { .min = 2, .max = 33 },
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	.p2 = { .dot_limit = 165000,
		.p2_slow = 4, .p2_fast = 2 },
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	.find_pll = intel_find_best_PLL,
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};

static const intel_limit_t intel_limits_i8xx_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 930000, .max = 1400000 },
	.n = { .min = 3, .max = 16 },
	.m = { .min = 96, .max = 140 },
	.m1 = { .min = 18, .max = 26 },
	.m2 = { .min = 6, .max = 16 },
	.p = { .min = 4, .max = 128 },
	.p1 = { .min = 1, .max = 6 },
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	.p2 = { .dot_limit = 165000,
		.p2_slow = 14, .p2_fast = 7 },
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	.find_pll = intel_find_best_PLL,
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};
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static const intel_limit_t intel_limits_i9xx_sdvo = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1400000, .max = 2800000 },
	.n = { .min = 1, .max = 6 },
	.m = { .min = 70, .max = 120 },
	.m1 = { .min = 10, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 200000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_find_best_PLL,
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};

static const intel_limit_t intel_limits_i9xx_lvds = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1400000, .max = 2800000 },
	.n = { .min = 1, .max = 6 },
	.m = { .min = 70, .max = 120 },
	.m1 = { .min = 10, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 7, .max = 98 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 112000,
		.p2_slow = 14, .p2_fast = 7 },
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	.find_pll = intel_find_best_PLL,
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};

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static const intel_limit_t intel_limits_g4x_sdvo = {
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	.dot = { .min = 25000, .max = 270000 },
	.vco = { .min = 1750000, .max = 3500000},
	.n = { .min = 1, .max = 4 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 10, .max = 30 },
	.p1 = { .min = 1, .max = 3},
	.p2 = { .dot_limit = 270000,
		.p2_slow = 10,
		.p2_fast = 10
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	},
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_hdmi = {
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	.dot = { .min = 22000, .max = 400000 },
	.vco = { .min = 1750000, .max = 3500000},
	.n = { .min = 1, .max = 4 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 16, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8},
	.p2 = { .dot_limit = 165000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
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	.dot = { .min = 20000, .max = 115000 },
	.vco = { .min = 1750000, .max = 3500000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 28, .max = 112 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 0,
		.p2_slow = 14, .p2_fast = 14
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	},
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
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	.dot = { .min = 80000, .max = 224000 },
	.vco = { .min = 1750000, .max = 3500000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 14, .max = 42 },
	.p1 = { .min = 2, .max = 6 },
	.p2 = { .dot_limit = 0,
		.p2_slow = 7, .p2_fast = 7
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	},
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	.find_pll = intel_g4x_find_best_PLL,
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};

static const intel_limit_t intel_limits_g4x_display_port = {
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	.dot = { .min = 161670, .max = 227000 },
	.vco = { .min = 1750000, .max = 3500000},
	.n = { .min = 1, .max = 2 },
	.m = { .min = 97, .max = 108 },
	.m1 = { .min = 0x10, .max = 0x12 },
	.m2 = { .min = 0x05, .max = 0x06 },
	.p = { .min = 10, .max = 20 },
	.p1 = { .min = 1, .max = 2},
	.p2 = { .dot_limit = 0,
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		.p2_slow = 10, .p2_fast = 10 },
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	.find_pll = intel_find_pll_g4x_dp,
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};

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static const intel_limit_t intel_limits_pineview_sdvo = {
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	.dot = { .min = 20000, .max = 400000},
	.vco = { .min = 1700000, .max = 3500000 },
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	/* Pineview's Ncounter is a ring counter */
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	.n = { .min = 3, .max = 6 },
	.m = { .min = 2, .max = 256 },
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	/* Pineview only has one combined m divider, which we treat as m2. */
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	.m1 = { .min = 0, .max = 0 },
	.m2 = { .min = 0, .max = 254 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 200000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_find_best_PLL,
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};

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static const intel_limit_t intel_limits_pineview_lvds = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1700000, .max = 3500000 },
	.n = { .min = 3, .max = 6 },
	.m = { .min = 2, .max = 256 },
	.m1 = { .min = 0, .max = 0 },
	.m2 = { .min = 0, .max = 254 },
	.p = { .min = 7, .max = 112 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 112000,
		.p2_slow = 14, .p2_fast = 14 },
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	.find_pll = intel_find_best_PLL,
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};

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/* Ironlake / Sandybridge
 *
 * We calculate clock using (register_value + 2) for N/M1/M2, so here
 * the range value for them is (actual_value - 2).
 */
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static const intel_limit_t intel_limits_ironlake_dac = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 5 },
	.m = { .min = 79, .max = 127 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 10, .p2_fast = 5 },
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	.find_pll = intel_g4x_find_best_PLL,
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};

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static const intel_limit_t intel_limits_ironlake_single_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 118 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 28, .max = 112 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 14, .p2_fast = 14 },
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	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_dual_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 127 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 14, .max = 56 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 7, .p2_fast = 7 },
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	.find_pll = intel_g4x_find_best_PLL,
};

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/* LVDS 100mhz refclk limits. */
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static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 2 },
	.m = { .min = 79, .max = 126 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 28, .max = 112 },
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	.p1 = { .min = 2, .max = 8 },
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	.p2 = { .dot_limit = 225000,
		.p2_slow = 14, .p2_fast = 14 },
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	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 126 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 14, .max = 42 },
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	.p1 = { .min = 2, .max = 6 },
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	.p2 = { .dot_limit = 225000,
		.p2_slow = 7, .p2_fast = 7 },
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	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_display_port = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000},
	.n = { .min = 1, .max = 2 },
	.m = { .min = 81, .max = 90 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 10, .max = 20 },
	.p1 = { .min = 1, .max = 2},
	.p2 = { .dot_limit = 0,
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		.p2_slow = 10, .p2_fast = 10 },
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	.find_pll = intel_find_pll_ironlake_dp,
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};

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static const intel_limit_t intel_limits_vlv_dac = {
	.dot = { .min = 25000, .max = 270000 },
	.vco = { .min = 4000000, .max = 6000000 },
	.n = { .min = 1, .max = 7 },
	.m = { .min = 22, .max = 450 }, /* guess */
	.m1 = { .min = 2, .max = 3 },
	.m2 = { .min = 11, .max = 156 },
	.p = { .min = 10, .max = 30 },
	.p1 = { .min = 2, .max = 3 },
	.p2 = { .dot_limit = 270000,
		.p2_slow = 2, .p2_fast = 20 },
	.find_pll = intel_vlv_find_best_pll,
};

static const intel_limit_t intel_limits_vlv_hdmi = {
	.dot = { .min = 20000, .max = 165000 },
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	.vco = { .min = 4000000, .max = 5994000},
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	.n = { .min = 1, .max = 7 },
	.m = { .min = 60, .max = 300 }, /* guess */
	.m1 = { .min = 2, .max = 3 },
	.m2 = { .min = 11, .max = 156 },
	.p = { .min = 10, .max = 30 },
	.p1 = { .min = 2, .max = 3 },
	.p2 = { .dot_limit = 270000,
		.p2_slow = 2, .p2_fast = 20 },
	.find_pll = intel_vlv_find_best_pll,
};

static const intel_limit_t intel_limits_vlv_dp = {
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	.dot = { .min = 25000, .max = 270000 },
	.vco = { .min = 4000000, .max = 6000000 },
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	.n = { .min = 1, .max = 7 },
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	.m = { .min = 22, .max = 450 },
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	.m1 = { .min = 2, .max = 3 },
	.m2 = { .min = 11, .max = 156 },
	.p = { .min = 10, .max = 30 },
	.p1 = { .min = 2, .max = 3 },
	.p2 = { .dot_limit = 270000,
		.p2_slow = 2, .p2_fast = 20 },
	.find_pll = intel_vlv_find_best_pll,
};

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Jesse Barnes 已提交
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u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
{
	unsigned long flags;
	u32 val = 0;

	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
		DRM_ERROR("DPIO idle wait timed out\n");
		goto out_unlock;
	}

	I915_WRITE(DPIO_REG, reg);
	I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
		   DPIO_BYTE);
	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
		DRM_ERROR("DPIO read wait timed out\n");
		goto out_unlock;
	}
	val = I915_READ(DPIO_DATA);

out_unlock:
	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
	return val;
}

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static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
			     u32 val)
{
	unsigned long flags;

	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
		DRM_ERROR("DPIO idle wait timed out\n");
		goto out_unlock;
	}

	I915_WRITE(DPIO_DATA, val);
	I915_WRITE(DPIO_REG, reg);
	I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
		   DPIO_BYTE);
	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
		DRM_ERROR("DPIO write wait timed out\n");

out_unlock:
       spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
}

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Jesse Barnes 已提交
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static void vlv_init_dpio(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* Reset the DPIO config */
	I915_WRITE(DPIO_CTL, 0);
	POSTING_READ(DPIO_CTL);
	I915_WRITE(DPIO_CTL, 1);
	POSTING_READ(DPIO_CTL);
}

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static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
{
	DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
	return 1;
}

static const struct dmi_system_id intel_dual_link_lvds[] = {
	{
		.callback = intel_dual_link_lvds_callback,
		.ident = "Apple MacBook Pro (Core i5/i7 Series)",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
			DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
		},
	},
	{ }	/* terminating entry */
};

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static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
			      unsigned int reg)
{
	unsigned int val;

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	/* use the module option value if specified */
	if (i915_lvds_channel_mode > 0)
		return i915_lvds_channel_mode == 2;

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	if (dmi_check_system(intel_dual_link_lvds))
		return true;

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	if (dev_priv->lvds_val)
		val = dev_priv->lvds_val;
	else {
		/* BIOS should set the proper LVDS register value at boot, but
		 * in reality, it doesn't set the value when the lid is closed;
		 * we need to check "the value to be set" in VBT when LVDS
		 * register is uninitialized.
		 */
		val = I915_READ(reg);
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		if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
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			val = dev_priv->bios_lvds_val;
		dev_priv->lvds_val = val;
	}
	return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
}

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static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
						int refclk)
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{
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	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	const intel_limit_t *limit;
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	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
521
		if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
522
			/* LVDS dual channel */
523
			if (refclk == 100000)
524 525 526 527
				limit = &intel_limits_ironlake_dual_lvds_100m;
			else
				limit = &intel_limits_ironlake_dual_lvds;
		} else {
528
			if (refclk == 100000)
529 530 531 532 533
				limit = &intel_limits_ironlake_single_lvds_100m;
			else
				limit = &intel_limits_ironlake_single_lvds;
		}
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
534 535
			HAS_eDP)
		limit = &intel_limits_ironlake_display_port;
536
	else
537
		limit = &intel_limits_ironlake_dac;
538 539 540 541

	return limit;
}

542 543 544 545 546 547 548
static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	const intel_limit_t *limit;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
549
		if (is_dual_link_lvds(dev_priv, LVDS))
550
			/* LVDS with dual channel */
551
			limit = &intel_limits_g4x_dual_channel_lvds;
552 553
		else
			/* LVDS with dual channel */
554
			limit = &intel_limits_g4x_single_channel_lvds;
555 556
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
		   intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
557
		limit = &intel_limits_g4x_hdmi;
558
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
559
		limit = &intel_limits_g4x_sdvo;
560
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
561
		limit = &intel_limits_g4x_display_port;
562
	} else /* The option is for other outputs */
563
		limit = &intel_limits_i9xx_sdvo;
564 565 566 567

	return limit;
}

568
static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
569 570 571 572
{
	struct drm_device *dev = crtc->dev;
	const intel_limit_t *limit;

573
	if (HAS_PCH_SPLIT(dev))
574
		limit = intel_ironlake_limit(crtc, refclk);
575
	else if (IS_G4X(dev)) {
576
		limit = intel_g4x_limit(crtc);
577
	} else if (IS_PINEVIEW(dev)) {
578
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
579
			limit = &intel_limits_pineview_lvds;
580
		else
581
			limit = &intel_limits_pineview_sdvo;
582 583 584 585 586 587 588
	} else if (IS_VALLEYVIEW(dev)) {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
			limit = &intel_limits_vlv_dac;
		else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
			limit = &intel_limits_vlv_hdmi;
		else
			limit = &intel_limits_vlv_dp;
589 590 591 592 593
	} else if (!IS_GEN2(dev)) {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
			limit = &intel_limits_i9xx_lvds;
		else
			limit = &intel_limits_i9xx_sdvo;
594 595
	} else {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
596
			limit = &intel_limits_i8xx_lvds;
597
		else
598
			limit = &intel_limits_i8xx_dvo;
599 600 601 602
	}
	return limit;
}

603 604
/* m1 is reserved as 0 in Pineview, n is a ring counter */
static void pineview_clock(int refclk, intel_clock_t *clock)
605
{
606 607 608 609 610 611 612 613
	clock->m = clock->m2 + 2;
	clock->p = clock->p1 * clock->p2;
	clock->vco = refclk * clock->m / clock->n;
	clock->dot = clock->vco / clock->p;
}

static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
{
614 615
	if (IS_PINEVIEW(dev)) {
		pineview_clock(refclk, clock);
616 617
		return;
	}
618 619 620 621 622 623 624 625 626
	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
	clock->p = clock->p1 * clock->p2;
	clock->vco = refclk * clock->m / (clock->n + 2);
	clock->dot = clock->vco / clock->p;
}

/**
 * Returns whether any output on the specified pipe is of the specified type
 */
627
bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
628
{
629 630 631
	struct drm_device *dev = crtc->dev;
	struct intel_encoder *encoder;

632 633
	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->type == type)
634 635 636
			return true;

	return false;
637 638
}

639
#define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
640 641 642 643 644
/**
 * Returns whether the given set of divisors are valid for a given refclk with
 * the given connectors.
 */

645 646 647
static bool intel_PLL_is_valid(struct drm_device *dev,
			       const intel_limit_t *limit,
			       const intel_clock_t *clock)
648 649
{
	if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
650
		INTELPllInvalid("p1 out of range\n");
651
	if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
652
		INTELPllInvalid("p out of range\n");
653
	if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
654
		INTELPllInvalid("m2 out of range\n");
655
	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
656
		INTELPllInvalid("m1 out of range\n");
657
	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
658
		INTELPllInvalid("m1 <= m2\n");
659
	if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
660
		INTELPllInvalid("m out of range\n");
661
	if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
662
		INTELPllInvalid("n out of range\n");
663
	if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664
		INTELPllInvalid("vco out of range\n");
665 666 667 668
	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
	 * connector, etc., rather than just a single range.
	 */
	if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
669
		INTELPllInvalid("dot out of range\n");
670 671 672 673

	return true;
}

674 675
static bool
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
676 677
		    int target, int refclk, intel_clock_t *match_clock,
		    intel_clock_t *best_clock)
678

679 680 681 682 683 684
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	intel_clock_t clock;
	int err = target;

685
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
686
	    (I915_READ(LVDS)) != 0) {
687 688 689 690 691 692
		/*
		 * For LVDS, if the panel is on, just rely on its current
		 * settings for dual-channel.  We haven't figured out how to
		 * reliably set up different single/dual channel state, if we
		 * even can.
		 */
693
		if (is_dual_link_lvds(dev_priv, LVDS))
694 695 696 697 698 699 700 701 702 703
			clock.p2 = limit->p2.p2_fast;
		else
			clock.p2 = limit->p2.p2_slow;
	} else {
		if (target < limit->p2.dot_limit)
			clock.p2 = limit->p2.p2_slow;
		else
			clock.p2 = limit->p2.p2_fast;
	}

704
	memset(best_clock, 0, sizeof(*best_clock));
705

706 707 708 709
	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
	     clock.m1++) {
		for (clock.m2 = limit->m2.min;
		     clock.m2 <= limit->m2.max; clock.m2++) {
710 711
			/* m1 is always 0 in Pineview */
			if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
712 713 714 715 716
				break;
			for (clock.n = limit->n.min;
			     clock.n <= limit->n.max; clock.n++) {
				for (clock.p1 = limit->p1.min;
					clock.p1 <= limit->p1.max; clock.p1++) {
717 718
					int this_err;

719
					intel_clock(dev, refclk, &clock);
720 721
					if (!intel_PLL_is_valid(dev, limit,
								&clock))
722
						continue;
723 724 725
					if (match_clock &&
					    clock.p != match_clock->p)
						continue;
726 727 728 729 730 731 732 733 734 735 736 737 738 739

					this_err = abs(clock.dot - target);
					if (this_err < err) {
						*best_clock = clock;
						err = this_err;
					}
				}
			}
		}
	}

	return (err != target);
}

740 741
static bool
intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 743
			int target, int refclk, intel_clock_t *match_clock,
			intel_clock_t *best_clock)
744 745 746 747 748 749
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	intel_clock_t clock;
	int max_n;
	bool found;
750 751
	/* approximately equals target * 0.00585 */
	int err_most = (target >> 8) + (target >> 9);
752 753 754
	found = false;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
755 756
		int lvds_reg;

757
		if (HAS_PCH_SPLIT(dev))
758 759 760 761
			lvds_reg = PCH_LVDS;
		else
			lvds_reg = LVDS;
		if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
762 763 764 765 766 767 768 769 770 771 772 773 774
		    LVDS_CLKB_POWER_UP)
			clock.p2 = limit->p2.p2_fast;
		else
			clock.p2 = limit->p2.p2_slow;
	} else {
		if (target < limit->p2.dot_limit)
			clock.p2 = limit->p2.p2_slow;
		else
			clock.p2 = limit->p2.p2_fast;
	}

	memset(best_clock, 0, sizeof(*best_clock));
	max_n = limit->n.max;
775
	/* based on hardware requirement, prefer smaller n to precision */
776
	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
777
		/* based on hardware requirement, prefere larger m1,m2 */
778 779 780 781 782 783 784 785
		for (clock.m1 = limit->m1.max;
		     clock.m1 >= limit->m1.min; clock.m1--) {
			for (clock.m2 = limit->m2.max;
			     clock.m2 >= limit->m2.min; clock.m2--) {
				for (clock.p1 = limit->p1.max;
				     clock.p1 >= limit->p1.min; clock.p1--) {
					int this_err;

786
					intel_clock(dev, refclk, &clock);
787 788
					if (!intel_PLL_is_valid(dev, limit,
								&clock))
789
						continue;
790 791 792
					if (match_clock &&
					    clock.p != match_clock->p)
						continue;
793 794

					this_err = abs(clock.dot - target);
795 796 797 798 799 800 801 802 803 804
					if (this_err < err_most) {
						*best_clock = clock;
						err_most = this_err;
						max_n = clock.n;
						found = true;
					}
				}
			}
		}
	}
805 806 807
	return found;
}

808
static bool
809
intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
810 811
			   int target, int refclk, intel_clock_t *match_clock,
			   intel_clock_t *best_clock)
812 813 814
{
	struct drm_device *dev = crtc->dev;
	intel_clock_t clock;
815

816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833
	if (target < 200000) {
		clock.n = 1;
		clock.p1 = 2;
		clock.p2 = 10;
		clock.m1 = 12;
		clock.m2 = 9;
	} else {
		clock.n = 2;
		clock.p1 = 1;
		clock.p2 = 10;
		clock.m1 = 14;
		clock.m2 = 8;
	}
	intel_clock(dev, refclk, &clock);
	memcpy(best_clock, &clock, sizeof(intel_clock_t));
	return true;
}

834 835 836
/* DisplayPort has only two frequencies, 162MHz and 270MHz */
static bool
intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 838
		      int target, int refclk, intel_clock_t *match_clock,
		      intel_clock_t *best_clock)
839
{
840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859
	intel_clock_t clock;
	if (target < 200000) {
		clock.p1 = 2;
		clock.p2 = 10;
		clock.n = 2;
		clock.m1 = 23;
		clock.m2 = 8;
	} else {
		clock.p1 = 1;
		clock.p2 = 10;
		clock.n = 1;
		clock.m1 = 14;
		clock.m2 = 2;
	}
	clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
	clock.p = (clock.p1 * clock.p2);
	clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
	clock.vco = 0;
	memcpy(best_clock, &clock, sizeof(intel_clock_t));
	return true;
860
}
861 862 863 864 865 866 867 868 869 870 871
static bool
intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
			int target, int refclk, intel_clock_t *match_clock,
			intel_clock_t *best_clock)
{
	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
	u32 m, n, fastclk;
	u32 updrate, minupdate, fracbits, p;
	unsigned long bestppm, ppm, absppm;
	int dotclk, flag;

872
	flag = 0;
873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928
	dotclk = target * 1000;
	bestppm = 1000000;
	ppm = absppm = 0;
	fastclk = dotclk / (2*100);
	updrate = 0;
	minupdate = 19200;
	fracbits = 1;
	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
	bestm1 = bestm2 = bestp1 = bestp2 = 0;

	/* based on hardware requirement, prefer smaller n to precision */
	for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
		updrate = refclk / n;
		for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
			for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
				if (p2 > 10)
					p2 = p2 - 1;
				p = p1 * p2;
				/* based on hardware requirement, prefer bigger m1,m2 values */
				for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
					m2 = (((2*(fastclk * p * n / m1 )) +
					       refclk) / (2*refclk));
					m = m1 * m2;
					vco = updrate * m;
					if (vco >= limit->vco.min && vco < limit->vco.max) {
						ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
						absppm = (ppm > 0) ? ppm : (-ppm);
						if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
							bestppm = 0;
							flag = 1;
						}
						if (absppm < bestppm - 10) {
							bestppm = absppm;
							flag = 1;
						}
						if (flag) {
							bestn = n;
							bestm1 = m1;
							bestm2 = m2;
							bestp1 = p1;
							bestp2 = p2;
							flag = 0;
						}
					}
				}
			}
		}
	}
	best_clock->n = bestn;
	best_clock->m1 = bestm1;
	best_clock->m2 = bestm2;
	best_clock->p1 = bestp1;
	best_clock->p2 = bestp2;

	return true;
}
929

930 931 932 933 934 935 936 937 938 939 940
static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 frame, frame_reg = PIPEFRAME(pipe);

	frame = I915_READ(frame_reg);

	if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
		DRM_DEBUG_KMS("vblank wait timed out\n");
}

941 942 943 944 945 946 947 948 949
/**
 * intel_wait_for_vblank - wait for vblank on a given pipe
 * @dev: drm device
 * @pipe: pipe to wait for
 *
 * Wait for vblank to occur on a given pipe.  Needed for various bits of
 * mode setting code.
 */
void intel_wait_for_vblank(struct drm_device *dev, int pipe)
950
{
951
	struct drm_i915_private *dev_priv = dev->dev_private;
952
	int pipestat_reg = PIPESTAT(pipe);
953

954 955 956 957 958
	if (INTEL_INFO(dev)->gen >= 5) {
		ironlake_wait_for_vblank(dev, pipe);
		return;
	}

959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974
	/* Clear existing vblank status. Note this will clear any other
	 * sticky status fields as well.
	 *
	 * This races with i915_driver_irq_handler() with the result
	 * that either function could miss a vblank event.  Here it is not
	 * fatal, as we will either wait upon the next vblank interrupt or
	 * timeout.  Generally speaking intel_wait_for_vblank() is only
	 * called during modeset at which time the GPU should be idle and
	 * should *not* be performing page flips and thus not waiting on
	 * vblanks...
	 * Currently, the result of us stealing a vblank from the irq
	 * handler is that a single frame will be skipped during swapbuffers.
	 */
	I915_WRITE(pipestat_reg,
		   I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);

975
	/* Wait for vblank interrupt bit to set */
976 977 978
	if (wait_for(I915_READ(pipestat_reg) &
		     PIPE_VBLANK_INTERRUPT_STATUS,
		     50))
979 980 981
		DRM_DEBUG_KMS("vblank wait timed out\n");
}

982 983
/*
 * intel_wait_for_pipe_off - wait for pipe to turn off
984 985 986 987 988 989 990
 * @dev: drm device
 * @pipe: pipe to wait for
 *
 * After disabling a pipe, we can't wait for vblank in the usual way,
 * spinning on the vblank interrupt status bit, since we won't actually
 * see an interrupt when the pipe is disabled.
 *
991 992 993 994 995 996
 * On Gen4 and above:
 *   wait for the pipe register state bit to turn off
 *
 * Otherwise:
 *   wait for the display line value to settle (it usually
 *   ends up stopping at the start of the next frame).
997
 *
998
 */
999
void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 1001
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1002 1003

	if (INTEL_INFO(dev)->gen >= 4) {
1004
		int reg = PIPECONF(pipe);
1005 1006

		/* Wait for the Pipe State to go off */
1007 1008
		if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
			     100))
1009
			WARN(1, "pipe_off wait timed out\n");
1010
	} else {
1011
		u32 last_line, line_mask;
1012
		int reg = PIPEDSL(pipe);
1013 1014
		unsigned long timeout = jiffies + msecs_to_jiffies(100);

1015 1016 1017 1018 1019
		if (IS_GEN2(dev))
			line_mask = DSL_LINEMASK_GEN2;
		else
			line_mask = DSL_LINEMASK_GEN3;

1020 1021
		/* Wait for the display line to settle */
		do {
1022
			last_line = I915_READ(reg) & line_mask;
1023
			mdelay(5);
1024
		} while (((I915_READ(reg) & line_mask) != last_line) &&
1025 1026
			 time_after(timeout, jiffies));
		if (time_after(jiffies, timeout))
1027
			WARN(1, "pipe_off wait timed out\n");
1028
	}
1029 1030
}

1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053
static const char *state_string(bool enabled)
{
	return enabled ? "on" : "off";
}

/* Only for pre-ILK configs */
static void assert_pll(struct drm_i915_private *dev_priv,
		       enum pipe pipe, bool state)
{
	int reg;
	u32 val;
	bool cur_state;

	reg = DPLL(pipe);
	val = I915_READ(reg);
	cur_state = !!(val & DPLL_VCO_ENABLE);
	WARN(cur_state != state,
	     "PLL state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
#define assert_pll_disabled(d, p) assert_pll(d, p, false)

1054 1055
/* For ILK+ */
static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056 1057 1058
			   struct intel_pch_pll *pll,
			   struct intel_crtc *crtc,
			   bool state)
1059 1060 1061 1062
{
	u32 val;
	bool cur_state;

1063 1064 1065 1066 1067
	if (HAS_PCH_LPT(dev_priv->dev)) {
		DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
		return;
	}

1068 1069
	if (WARN (!pll,
		  "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070 1071
		return;

1072 1073 1074 1075 1076 1077 1078 1079
	val = I915_READ(pll->pll_reg);
	cur_state = !!(val & DPLL_VCO_ENABLE);
	WARN(cur_state != state,
	     "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
	     pll->pll_reg, state_string(state), state_string(cur_state), val);

	/* Make sure the selected PLL is correctly attached to the transcoder */
	if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080 1081 1082
		u32 pch_dpll;

		pch_dpll = I915_READ(PCH_DPLL_SEL);
1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094
		cur_state = pll->pll_reg == _PCH_DPLL_B;
		if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
			  "PLL[%d] not attached to this transcoder %d: %08x\n",
			  cur_state, crtc->pipe, pch_dpll)) {
			cur_state = !!(val >> (4*crtc->pipe + 3));
			WARN(cur_state != state,
			     "PLL[%d] not %s on this transcoder %d: %08x\n",
			     pll->pll_reg == _PCH_DPLL_B,
			     state_string(state),
			     crtc->pipe,
			     val);
		}
1095
	}
1096
}
1097 1098
#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099 1100 1101 1102 1103 1104 1105 1106

static void assert_fdi_tx(struct drm_i915_private *dev_priv,
			  enum pipe pipe, bool state)
{
	int reg;
	u32 val;
	bool cur_state;

1107 1108 1109 1110 1111 1112 1113 1114 1115 1116
	if (IS_HASWELL(dev_priv->dev)) {
		/* On Haswell, DDI is used instead of FDI_TX_CTL */
		reg = DDI_FUNC_CTL(pipe);
		val = I915_READ(reg);
		cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
	} else {
		reg = FDI_TX_CTL(pipe);
		val = I915_READ(reg);
		cur_state = !!(val & FDI_TX_ENABLE);
	}
1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130
	WARN(cur_state != state,
	     "FDI TX state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}
#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)

static void assert_fdi_rx(struct drm_i915_private *dev_priv,
			  enum pipe pipe, bool state)
{
	int reg;
	u32 val;
	bool cur_state;

1131 1132 1133 1134 1135 1136 1137 1138
	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
			DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
			return;
	} else {
		reg = FDI_RX_CTL(pipe);
		val = I915_READ(reg);
		cur_state = !!(val & FDI_RX_ENABLE);
	}
1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155
	WARN(cur_state != state,
	     "FDI RX state assertion failure (expected %s, current %s)\n",
	     state_string(state), state_string(cur_state));
}
#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)

static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
				      enum pipe pipe)
{
	int reg;
	u32 val;

	/* ILK FDI PLL is always enabled */
	if (dev_priv->info->gen == 5)
		return;

1156 1157 1158 1159
	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
	if (IS_HASWELL(dev_priv->dev))
		return;

1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170
	reg = FDI_TX_CTL(pipe);
	val = I915_READ(reg);
	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
}

static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
				      enum pipe pipe)
{
	int reg;
	u32 val;

1171 1172 1173 1174
	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
		DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
		return;
	}
1175 1176 1177 1178 1179
	reg = FDI_RX_CTL(pipe);
	val = I915_READ(reg);
	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
}

1180 1181 1182 1183 1184 1185
static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
				  enum pipe pipe)
{
	int pp_reg, lvds_reg;
	u32 val;
	enum pipe panel_pipe = PIPE_A;
1186
	bool locked = true;
1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205

	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		pp_reg = PCH_PP_CONTROL;
		lvds_reg = PCH_LVDS;
	} else {
		pp_reg = PP_CONTROL;
		lvds_reg = LVDS;
	}

	val = I915_READ(pp_reg);
	if (!(val & PANEL_POWER_ON) ||
	    ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
		locked = false;

	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
		panel_pipe = PIPE_B;

	WARN(panel_pipe == pipe && locked,
	     "panel assertion failure, pipe %c regs locked\n",
1206
	     pipe_name(pipe));
1207 1208
}

1209 1210
void assert_pipe(struct drm_i915_private *dev_priv,
		 enum pipe pipe, bool state)
1211 1212 1213
{
	int reg;
	u32 val;
1214
	bool cur_state;
1215

1216 1217 1218 1219
	/* if we need the pipe A quirk it must be always on */
	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
		state = true;

1220 1221
	reg = PIPECONF(pipe);
	val = I915_READ(reg);
1222 1223 1224
	cur_state = !!(val & PIPECONF_ENABLE);
	WARN(cur_state != state,
	     "pipe %c assertion failure (expected %s, current %s)\n",
1225
	     pipe_name(pipe), state_string(state), state_string(cur_state));
1226 1227
}

1228 1229
static void assert_plane(struct drm_i915_private *dev_priv,
			 enum plane plane, bool state)
1230 1231 1232
{
	int reg;
	u32 val;
1233
	bool cur_state;
1234 1235 1236

	reg = DSPCNTR(plane);
	val = I915_READ(reg);
1237 1238 1239 1240
	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
	WARN(cur_state != state,
	     "plane %c assertion failure (expected %s, current %s)\n",
	     plane_name(plane), state_string(state), state_string(cur_state));
1241 1242
}

1243 1244 1245
#define assert_plane_enabled(d, p) assert_plane(d, p, true)
#define assert_plane_disabled(d, p) assert_plane(d, p, false)

1246 1247 1248 1249 1250 1251 1252
static void assert_planes_disabled(struct drm_i915_private *dev_priv,
				   enum pipe pipe)
{
	int reg, i;
	u32 val;
	int cur_pipe;

1253
	/* Planes are fixed to pipes on ILK+ */
1254 1255 1256 1257 1258 1259
	if (HAS_PCH_SPLIT(dev_priv->dev)) {
		reg = DSPCNTR(pipe);
		val = I915_READ(reg);
		WARN((val & DISPLAY_PLANE_ENABLE),
		     "plane %c assertion failure, should be disabled but not\n",
		     plane_name(pipe));
1260
		return;
1261
	}
1262

1263 1264 1265 1266 1267 1268 1269
	/* Need to check both planes against the pipe */
	for (i = 0; i < 2; i++) {
		reg = DSPCNTR(i);
		val = I915_READ(reg);
		cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
			DISPPLANE_SEL_PIPE_SHIFT;
		WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270 1271
		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
		     plane_name(i), pipe_name(pipe));
1272 1273 1274
	}
}

1275 1276 1277 1278 1279
static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
{
	u32 val;
	bool enabled;

1280 1281 1282 1283 1284
	if (HAS_PCH_LPT(dev_priv->dev)) {
		DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
		return;
	}

1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300
	val = I915_READ(PCH_DREF_CONTROL);
	enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
			    DREF_SUPERSPREAD_SOURCE_MASK));
	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
}

static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
				       enum pipe pipe)
{
	int reg;
	u32 val;
	bool enabled;

	reg = TRANSCONF(pipe);
	val = I915_READ(reg);
	enabled = !!(val & TRANS_ENABLE);
1301 1302 1303
	WARN(enabled,
	     "transcoder assertion failed, should be off on pipe %c but is still active\n",
	     pipe_name(pipe));
1304 1305
}

1306 1307
static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
			    enum pipe pipe, u32 port_sel, u32 val)
1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323
{
	if ((val & DP_PORT_EN) == 0)
		return false;

	if (HAS_PCH_CPT(dev_priv->dev)) {
		u32	trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
		u32	trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
		if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
			return false;
	} else {
		if ((val & DP_PIPE_MASK) != (pipe << 30))
			return false;
	}
	return true;
}

1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370
static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
			      enum pipe pipe, u32 val)
{
	if ((val & PORT_ENABLE) == 0)
		return false;

	if (HAS_PCH_CPT(dev_priv->dev)) {
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
			return false;
	} else {
		if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
			return false;
	}
	return true;
}

static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
			      enum pipe pipe, u32 val)
{
	if ((val & LVDS_PORT_EN) == 0)
		return false;

	if (HAS_PCH_CPT(dev_priv->dev)) {
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
			return false;
	} else {
		if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
			return false;
	}
	return true;
}

static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
			      enum pipe pipe, u32 val)
{
	if ((val & ADPA_DAC_ENABLE) == 0)
		return false;
	if (HAS_PCH_CPT(dev_priv->dev)) {
		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
			return false;
	} else {
		if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
			return false;
	}
	return true;
}

1371
static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372
				   enum pipe pipe, int reg, u32 port_sel)
1373
{
1374
	u32 val = I915_READ(reg);
1375
	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376
	     "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377
	     reg, pipe_name(pipe));
1378

1379 1380
	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
	     && (val & DP_PIPEB_SELECT),
1381
	     "IBX PCH dp port still using transcoder B\n");
1382 1383 1384 1385 1386
}

static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
				     enum pipe pipe, int reg)
{
1387
	u32 val = I915_READ(reg);
1388
	WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1389
	     "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1390
	     reg, pipe_name(pipe));
1391

1392 1393
	WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
	     && (val & SDVO_PIPE_B_SELECT),
1394
	     "IBX PCH hdmi port still using transcoder B\n");
1395 1396 1397 1398 1399 1400 1401 1402
}

static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
				      enum pipe pipe)
{
	int reg;
	u32 val;

1403 1404 1405
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1406 1407 1408

	reg = PCH_ADPA;
	val = I915_READ(reg);
1409
	WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1410
	     "PCH VGA enabled on transcoder %c, should be disabled\n",
1411
	     pipe_name(pipe));
1412 1413 1414

	reg = PCH_LVDS;
	val = I915_READ(reg);
1415
	WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1416
	     "PCH LVDS enabled on transcoder %c, should be disabled\n",
1417
	     pipe_name(pipe));
1418 1419 1420 1421 1422 1423

	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
	assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
}

1424 1425 1426 1427 1428 1429 1430 1431 1432 1433
/**
 * intel_enable_pll - enable a PLL
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to enable
 *
 * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
 * make sure the PLL reg is writable first though, since the panel write
 * protect mechanism may be enabled.
 *
 * Note!  This is for pre-ILK only.
1434 1435
 *
 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1436
 */
1437
static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1438 1439 1440 1441 1442
{
	int reg;
	u32 val;

	/* No really, not for ILK+ */
1443
	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492

	/* PLL is protected by panel, make sure we can write it */
	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
		assert_panel_unlocked(dev_priv, pipe);

	reg = DPLL(pipe);
	val = I915_READ(reg);
	val |= DPLL_VCO_ENABLE;

	/* We do this three times for luck */
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(150); /* wait for warmup */
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(150); /* wait for warmup */
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(150); /* wait for warmup */
}

/**
 * intel_disable_pll - disable a PLL
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to disable
 *
 * Disable the PLL for @pipe, making sure the pipe is off first.
 *
 * Note!  This is for pre-ILK only.
 */
static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
{
	int reg;
	u32 val;

	/* Don't disable pipe A or pipe A PLLs if needed */
	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		return;

	/* Make sure the pipe isn't still relying on us */
	assert_pipe_disabled(dev_priv, pipe);

	reg = DPLL(pipe);
	val = I915_READ(reg);
	val &= ~DPLL_VCO_ENABLE;
	I915_WRITE(reg, val);
	POSTING_READ(reg);
}

1493 1494 1495 1496 1497 1498 1499
/* SBI access */
static void
intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
{
	unsigned long flags;

	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1500
	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513
				100)) {
		DRM_ERROR("timeout waiting for SBI to become ready\n");
		goto out_unlock;
	}

	I915_WRITE(SBI_ADDR,
			(reg << 16));
	I915_WRITE(SBI_DATA,
			value);
	I915_WRITE(SBI_CTL_STAT,
			SBI_BUSY |
			SBI_CTL_OP_CRWR);

1514
	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527
				100)) {
		DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
		goto out_unlock;
	}

out_unlock:
	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
}

static u32
intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
{
	unsigned long flags;
1528
	u32 value = 0;
1529 1530

	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1531
	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542
				100)) {
		DRM_ERROR("timeout waiting for SBI to become ready\n");
		goto out_unlock;
	}

	I915_WRITE(SBI_ADDR,
			(reg << 16));
	I915_WRITE(SBI_CTL_STAT,
			SBI_BUSY |
			SBI_CTL_OP_CRRD);

1543
	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555
				100)) {
		DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
		goto out_unlock;
	}

	value = I915_READ(SBI_DATA);

out_unlock:
	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
	return value;
}

1556 1557 1558 1559 1560 1561 1562 1563
/**
 * intel_enable_pch_pll - enable PCH PLL
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to enable
 *
 * The PCH PLL needs to be enabled before the PCH transcoder, since it
 * drives the transcoder clock.
 */
1564
static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1565
{
1566
	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1567
	struct intel_pch_pll *pll;
1568 1569 1570
	int reg;
	u32 val;

1571
	/* PCH PLLs only available on ILK, SNB and IVB */
1572
	BUG_ON(dev_priv->info->gen < 5);
1573 1574 1575 1576 1577 1578
	pll = intel_crtc->pch_pll;
	if (pll == NULL)
		return;

	if (WARN_ON(pll->refcount == 0))
		return;
1579 1580 1581 1582

	DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
		      pll->pll_reg, pll->active, pll->on,
		      intel_crtc->base.base.id);
1583 1584 1585 1586

	/* PCH refclock must be enabled first */
	assert_pch_refclk_enabled(dev_priv);

1587
	if (pll->active++ && pll->on) {
1588
		assert_pch_pll_enabled(dev_priv, pll, NULL);
1589 1590 1591 1592 1593 1594
		return;
	}

	DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);

	reg = pll->pll_reg;
1595 1596 1597 1598 1599
	val = I915_READ(reg);
	val |= DPLL_VCO_ENABLE;
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(200);
1600 1601

	pll->on = true;
1602 1603
}

1604
static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1605
{
1606 1607
	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
	struct intel_pch_pll *pll = intel_crtc->pch_pll;
1608
	int reg;
1609
	u32 val;
1610

1611 1612
	/* PCH only available on ILK+ */
	BUG_ON(dev_priv->info->gen < 5);
1613 1614
	if (pll == NULL)
	       return;
1615

1616 1617
	if (WARN_ON(pll->refcount == 0))
		return;
1618

1619 1620 1621
	DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
		      pll->pll_reg, pll->active, pll->on,
		      intel_crtc->base.base.id);
1622

1623
	if (WARN_ON(pll->active == 0)) {
1624
		assert_pch_pll_disabled(dev_priv, pll, NULL);
1625 1626 1627
		return;
	}

1628
	if (--pll->active) {
1629
		assert_pch_pll_enabled(dev_priv, pll, NULL);
1630
		return;
1631 1632 1633 1634 1635 1636
	}

	DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);

	/* Make sure transcoder isn't still depending on us */
	assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1637

1638
	reg = pll->pll_reg;
1639 1640 1641 1642 1643
	val = I915_READ(reg);
	val &= ~DPLL_VCO_ENABLE;
	I915_WRITE(reg, val);
	POSTING_READ(reg);
	udelay(200);
1644 1645

	pll->on = false;
1646 1647
}

1648 1649 1650 1651
static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
				    enum pipe pipe)
{
	int reg;
1652
	u32 val, pipeconf_val;
1653
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1654 1655 1656 1657 1658

	/* PCH only available on ILK+ */
	BUG_ON(dev_priv->info->gen < 5);

	/* Make sure PCH DPLL is enabled */
1659 1660 1661
	assert_pch_pll_enabled(dev_priv,
			       to_intel_crtc(crtc)->pch_pll,
			       to_intel_crtc(crtc));
1662 1663 1664 1665 1666

	/* FDI must be feeding us bits for PCH ports */
	assert_fdi_tx_enabled(dev_priv, pipe);
	assert_fdi_rx_enabled(dev_priv, pipe);

1667 1668 1669 1670
	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
		DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
		return;
	}
1671 1672
	reg = TRANSCONF(pipe);
	val = I915_READ(reg);
1673
	pipeconf_val = I915_READ(PIPECONF(pipe));
1674 1675 1676 1677 1678 1679 1680

	if (HAS_PCH_IBX(dev_priv->dev)) {
		/*
		 * make the BPC in transcoder be consistent with
		 * that in pipeconf reg.
		 */
		val &= ~PIPE_BPC_MASK;
1681
		val |= pipeconf_val & PIPE_BPC_MASK;
1682
	}
1683 1684 1685

	val &= ~TRANS_INTERLACE_MASK;
	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1686 1687 1688 1689 1690
		if (HAS_PCH_IBX(dev_priv->dev) &&
		    intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
			val |= TRANS_LEGACY_INTERLACED_ILK;
		else
			val |= TRANS_INTERLACED;
1691 1692 1693
	else
		val |= TRANS_PROGRESSIVE;

1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708
	I915_WRITE(reg, val | TRANS_ENABLE);
	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
		DRM_ERROR("failed to enable transcoder %d\n", pipe);
}

static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
				     enum pipe pipe)
{
	int reg;
	u32 val;

	/* FDI relies on the transcoder */
	assert_fdi_tx_disabled(dev_priv, pipe);
	assert_fdi_rx_disabled(dev_priv, pipe);

1709 1710 1711
	/* Ports must be off as well */
	assert_pch_ports_disabled(dev_priv, pipe);

1712 1713 1714 1715 1716 1717
	reg = TRANSCONF(pipe);
	val = I915_READ(reg);
	val &= ~TRANS_ENABLE;
	I915_WRITE(reg, val);
	/* wait for PCH transcoder off, transcoder state */
	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1718
		DRM_ERROR("failed to disable transcoder %d\n", pipe);
1719 1720
}

1721
/**
1722
 * intel_enable_pipe - enable a pipe, asserting requirements
1723 1724
 * @dev_priv: i915 private structure
 * @pipe: pipe to enable
1725
 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1726 1727 1728 1729 1730 1731 1732 1733 1734
 *
 * Enable @pipe, making sure that various hardware specific requirements
 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
 *
 * @pipe should be %PIPE_A or %PIPE_B.
 *
 * Will wait until the pipe is actually running (i.e. first vblank) before
 * returning.
 */
1735 1736
static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
			      bool pch_port)
1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747
{
	int reg;
	u32 val;

	/*
	 * A pipe without a PLL won't actually be able to drive bits from
	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
	 * need the check.
	 */
	if (!HAS_PCH_SPLIT(dev_priv->dev))
		assert_pll_enabled(dev_priv, pipe);
1748 1749 1750 1751 1752 1753 1754 1755
	else {
		if (pch_port) {
			/* if driving the PCH, we need FDI enabled */
			assert_fdi_rx_pll_enabled(dev_priv, pipe);
			assert_fdi_tx_pll_enabled(dev_priv, pipe);
		}
		/* FIXME: assert CPU port conditions for SNB+ */
	}
1756 1757 1758

	reg = PIPECONF(pipe);
	val = I915_READ(reg);
1759 1760 1761 1762
	if (val & PIPECONF_ENABLE)
		return;

	I915_WRITE(reg, val | PIPECONF_ENABLE);
1763 1764 1765 1766
	intel_wait_for_vblank(dev_priv->dev, pipe);
}

/**
1767
 * intel_disable_pipe - disable a pipe, asserting requirements
1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795
 * @dev_priv: i915 private structure
 * @pipe: pipe to disable
 *
 * Disable @pipe, making sure that various hardware specific requirements
 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
 *
 * @pipe should be %PIPE_A or %PIPE_B.
 *
 * Will wait until the pipe has shut down before returning.
 */
static void intel_disable_pipe(struct drm_i915_private *dev_priv,
			       enum pipe pipe)
{
	int reg;
	u32 val;

	/*
	 * Make sure planes won't keep trying to pump pixels to us,
	 * or we might hang the display.
	 */
	assert_planes_disabled(dev_priv, pipe);

	/* Don't disable pipe A or pipe A PLLs if needed */
	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		return;

	reg = PIPECONF(pipe);
	val = I915_READ(reg);
1796 1797 1798 1799
	if ((val & PIPECONF_ENABLE) == 0)
		return;

	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1800 1801 1802
	intel_wait_for_pipe_off(dev_priv->dev, pipe);
}

1803 1804 1805 1806
/*
 * Plane regs are double buffered, going from enabled->disabled needs a
 * trigger in order to latch.  The display address reg provides this.
 */
1807
void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1808 1809 1810 1811 1812 1813
				      enum plane plane)
{
	I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
	I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
}

1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832
/**
 * intel_enable_plane - enable a display plane on a given pipe
 * @dev_priv: i915 private structure
 * @plane: plane to enable
 * @pipe: pipe being fed
 *
 * Enable @plane on @pipe, making sure that @pipe is running first.
 */
static void intel_enable_plane(struct drm_i915_private *dev_priv,
			       enum plane plane, enum pipe pipe)
{
	int reg;
	u32 val;

	/* If the pipe isn't enabled, we can't pump pixels and may hang */
	assert_pipe_enabled(dev_priv, pipe);

	reg = DSPCNTR(plane);
	val = I915_READ(reg);
1833 1834 1835 1836
	if (val & DISPLAY_PLANE_ENABLE)
		return;

	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1837
	intel_flush_display_plane(dev_priv, plane);
1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856
	intel_wait_for_vblank(dev_priv->dev, pipe);
}

/**
 * intel_disable_plane - disable a display plane
 * @dev_priv: i915 private structure
 * @plane: plane to disable
 * @pipe: pipe consuming the data
 *
 * Disable @plane; should be an independent operation.
 */
static void intel_disable_plane(struct drm_i915_private *dev_priv,
				enum plane plane, enum pipe pipe)
{
	int reg;
	u32 val;

	reg = DSPCNTR(plane);
	val = I915_READ(reg);
1857 1858 1859 1860
	if ((val & DISPLAY_PLANE_ENABLE) == 0)
		return;

	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1861 1862 1863 1864
	intel_flush_display_plane(dev_priv, plane);
	intel_wait_for_vblank(dev_priv->dev, pipe);
}

1865
int
1866
intel_pin_and_fence_fb_obj(struct drm_device *dev,
1867
			   struct drm_i915_gem_object *obj,
1868
			   struct intel_ring_buffer *pipelined)
1869
{
1870
	struct drm_i915_private *dev_priv = dev->dev_private;
1871 1872 1873
	u32 alignment;
	int ret;

1874
	switch (obj->tiling_mode) {
1875
	case I915_TILING_NONE:
1876 1877
		if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
			alignment = 128 * 1024;
1878
		else if (INTEL_INFO(dev)->gen >= 4)
1879 1880 1881
			alignment = 4 * 1024;
		else
			alignment = 64 * 1024;
1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894
		break;
	case I915_TILING_X:
		/* pin() will align the object as required by fence */
		alignment = 0;
		break;
	case I915_TILING_Y:
		/* FIXME: Is this true? */
		DRM_ERROR("Y tiled not allowed for scan out buffers\n");
		return -EINVAL;
	default:
		BUG();
	}

1895
	dev_priv->mm.interruptible = false;
1896
	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1897
	if (ret)
1898
		goto err_interruptible;
1899 1900 1901 1902 1903 1904

	/* Install a fence for tiled scan-out. Pre-i965 always needs a
	 * fence, whereas 965+ only requires a fence if using
	 * framebuffer compression.  For simplicity, we always install
	 * a fence as the cost is not that onerous.
	 */
1905
	ret = i915_gem_object_get_fence(obj);
1906 1907
	if (ret)
		goto err_unpin;
1908

1909
	i915_gem_object_pin_fence(obj);
1910

1911
	dev_priv->mm.interruptible = true;
1912
	return 0;
1913 1914 1915

err_unpin:
	i915_gem_object_unpin(obj);
1916 1917
err_interruptible:
	dev_priv->mm.interruptible = true;
1918
	return ret;
1919 1920
}

1921 1922 1923 1924 1925 1926
void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_fence(obj);
	i915_gem_object_unpin(obj);
}

1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942
/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
 * is assumed to be a power-of-two. */
static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
							unsigned int bpp,
							unsigned int pitch)
{
	int tile_rows, tiles;

	tile_rows = *y / 8;
	*y %= 8;
	tiles = *x / (512/bpp);
	*x %= 512/bpp;

	return tile_rows * pitch * 8 + tiles * 4096;
}

1943 1944
static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
			     int x, int y)
1945 1946 1947 1948 1949
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_framebuffer *intel_fb;
1950
	struct drm_i915_gem_object *obj;
1951
	int plane = intel_crtc->plane;
1952
	unsigned long linear_offset;
1953
	u32 dspcntr;
1954
	u32 reg;
1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967

	switch (plane) {
	case 0:
	case 1:
		break;
	default:
		DRM_ERROR("Can't update plane %d in SAREA\n", plane);
		return -EINVAL;
	}

	intel_fb = to_intel_framebuffer(fb);
	obj = intel_fb->obj;

1968 1969
	reg = DSPCNTR(plane);
	dspcntr = I915_READ(reg);
1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986
	/* Mask out pixel format bits in case we change it */
	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
	switch (fb->bits_per_pixel) {
	case 8:
		dspcntr |= DISPPLANE_8BPP;
		break;
	case 16:
		if (fb->depth == 15)
			dspcntr |= DISPPLANE_15_16BPP;
		else
			dspcntr |= DISPPLANE_16BPP;
		break;
	case 24:
	case 32:
		dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
		break;
	default:
1987
		DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1988 1989
		return -EINVAL;
	}
1990
	if (INTEL_INFO(dev)->gen >= 4) {
1991
		if (obj->tiling_mode != I915_TILING_NONE)
1992 1993 1994 1995 1996
			dspcntr |= DISPPLANE_TILED;
		else
			dspcntr &= ~DISPPLANE_TILED;
	}

1997
	I915_WRITE(reg, dspcntr);
1998

1999
	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2000

2001 2002 2003 2004 2005 2006 2007
	if (INTEL_INFO(dev)->gen >= 4) {
		intel_crtc->dspaddr_offset =
			gen4_compute_dspaddr_offset_xtiled(&x, &y,
							   fb->bits_per_pixel / 8,
							   fb->pitches[0]);
		linear_offset -= intel_crtc->dspaddr_offset;
	} else {
2008
		intel_crtc->dspaddr_offset = linear_offset;
2009
	}
2010 2011 2012

	DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
		      obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2013
	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2014
	if (INTEL_INFO(dev)->gen >= 4) {
2015 2016
		I915_MODIFY_DISPBASE(DSPSURF(plane),
				     obj->gtt_offset + intel_crtc->dspaddr_offset);
2017
		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2018
		I915_WRITE(DSPLINOFF(plane), linear_offset);
2019
	} else
2020
		I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2021
	POSTING_READ(reg);
2022

2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034
	return 0;
}

static int ironlake_update_plane(struct drm_crtc *crtc,
				 struct drm_framebuffer *fb, int x, int y)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_framebuffer *intel_fb;
	struct drm_i915_gem_object *obj;
	int plane = intel_crtc->plane;
2035
	unsigned long linear_offset;
2036 2037 2038 2039 2040 2041
	u32 dspcntr;
	u32 reg;

	switch (plane) {
	case 0:
	case 1:
2042
	case 2:
2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089
		break;
	default:
		DRM_ERROR("Can't update plane %d in SAREA\n", plane);
		return -EINVAL;
	}

	intel_fb = to_intel_framebuffer(fb);
	obj = intel_fb->obj;

	reg = DSPCNTR(plane);
	dspcntr = I915_READ(reg);
	/* Mask out pixel format bits in case we change it */
	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
	switch (fb->bits_per_pixel) {
	case 8:
		dspcntr |= DISPPLANE_8BPP;
		break;
	case 16:
		if (fb->depth != 16)
			return -EINVAL;

		dspcntr |= DISPPLANE_16BPP;
		break;
	case 24:
	case 32:
		if (fb->depth == 24)
			dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
		else if (fb->depth == 30)
			dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
		else
			return -EINVAL;
		break;
	default:
		DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
		return -EINVAL;
	}

	if (obj->tiling_mode != I915_TILING_NONE)
		dspcntr |= DISPPLANE_TILED;
	else
		dspcntr &= ~DISPPLANE_TILED;

	/* must disable */
	dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;

	I915_WRITE(reg, dspcntr);

2090
	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2091 2092 2093 2094 2095
	intel_crtc->dspaddr_offset =
		gen4_compute_dspaddr_offset_xtiled(&x, &y,
						   fb->bits_per_pixel / 8,
						   fb->pitches[0]);
	linear_offset -= intel_crtc->dspaddr_offset;
2096

2097 2098
	DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
		      obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2099
	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2100 2101
	I915_MODIFY_DISPBASE(DSPSURF(plane),
			     obj->gtt_offset + intel_crtc->dspaddr_offset);
2102
	I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2103
	I915_WRITE(DSPLINOFF(plane), linear_offset);
2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116
	POSTING_READ(reg);

	return 0;
}

/* Assume fb object is pinned & idle & fenced and just update base pointers */
static int
intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
			   int x, int y, enum mode_set_atomic state)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

2117 2118
	if (dev_priv->display.disable_fbc)
		dev_priv->display.disable_fbc(dev);
2119
	intel_increase_pllclock(crtc);
2120

2121
	return dev_priv->display.update_plane(crtc, fb, x, y);
2122 2123
}

2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150
static int
intel_finish_fb(struct drm_framebuffer *old_fb)
{
	struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	bool was_interruptible = dev_priv->mm.interruptible;
	int ret;

	wait_event(dev_priv->pending_flip_queue,
		   atomic_read(&dev_priv->mm.wedged) ||
		   atomic_read(&obj->pending_flip) == 0);

	/* Big Hammer, we also need to ensure that any pending
	 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
	 * current scanout is retired before unpinning the old
	 * framebuffer.
	 *
	 * This should only fail upon a hung GPU, in which case we
	 * can safely continue.
	 */
	dev_priv->mm.interruptible = false;
	ret = i915_gem_object_finish_gpu(obj);
	dev_priv->mm.interruptible = was_interruptible;

	return ret;
}

2151
static int
2152
intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2153
		    struct drm_framebuffer *fb)
2154 2155
{
	struct drm_device *dev = crtc->dev;
2156
	struct drm_i915_private *dev_priv = dev->dev_private;
2157 2158
	struct drm_i915_master_private *master_priv;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2159
	struct drm_framebuffer *old_fb;
2160
	int ret;
2161 2162

	/* no fb bound */
2163
	if (!fb) {
2164
		DRM_ERROR("No FB bound\n");
2165 2166 2167
		return 0;
	}

2168 2169 2170 2171
	if(intel_crtc->plane > dev_priv->num_pipe) {
		DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
				intel_crtc->plane,
				dev_priv->num_pipe);
2172
		return -EINVAL;
2173 2174
	}

2175
	mutex_lock(&dev->struct_mutex);
2176
	ret = intel_pin_and_fence_fb_obj(dev,
2177
					 to_intel_framebuffer(fb)->obj,
2178
					 NULL);
2179 2180
	if (ret != 0) {
		mutex_unlock(&dev->struct_mutex);
2181
		DRM_ERROR("pin & fence failed\n");
2182 2183
		return ret;
	}
2184

2185 2186
	if (crtc->fb)
		intel_finish_fb(crtc->fb);
2187

2188
	ret = dev_priv->display.update_plane(crtc, fb, x, y);
2189
	if (ret) {
2190
		intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2191
		mutex_unlock(&dev->struct_mutex);
2192
		DRM_ERROR("failed to update base address\n");
2193
		return ret;
2194
	}
2195

2196 2197
	old_fb = crtc->fb;
	crtc->fb = fb;
2198 2199
	crtc->x = x;
	crtc->y = y;
2200

2201 2202
	if (old_fb) {
		intel_wait_for_vblank(dev, intel_crtc->pipe);
2203
		intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2204
	}
2205

2206
	intel_update_fbc(dev);
2207
	mutex_unlock(&dev->struct_mutex);
2208 2209

	if (!dev->primary->master)
2210
		return 0;
2211 2212 2213

	master_priv = dev->primary->master->driver_priv;
	if (!master_priv->sarea_priv)
2214
		return 0;
2215

2216
	if (intel_crtc->pipe) {
2217 2218
		master_priv->sarea_priv->pipeB_x = x;
		master_priv->sarea_priv->pipeB_y = y;
2219 2220 2221
	} else {
		master_priv->sarea_priv->pipeA_x = x;
		master_priv->sarea_priv->pipeA_y = y;
2222
	}
2223 2224

	return 0;
2225 2226
}

2227
static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2228 2229 2230 2231 2232
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

2233
	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259
	dpa_ctl = I915_READ(DP_A);
	dpa_ctl &= ~DP_PLL_FREQ_MASK;

	if (clock < 200000) {
		u32 temp;
		dpa_ctl |= DP_PLL_FREQ_160MHZ;
		/* workaround for 160Mhz:
		   1) program 0x4600c bits 15:0 = 0x8124
		   2) program 0x46010 bit 0 = 1
		   3) program 0x46034 bit 24 = 1
		   4) program 0x64000 bit 14 = 1
		   */
		temp = I915_READ(0x4600c);
		temp &= 0xffff0000;
		I915_WRITE(0x4600c, temp | 0x8124);

		temp = I915_READ(0x46010);
		I915_WRITE(0x46010, temp | 1);

		temp = I915_READ(0x46034);
		I915_WRITE(0x46034, temp | (1 << 24));
	} else {
		dpa_ctl |= DP_PLL_FREQ_270MHZ;
	}
	I915_WRITE(DP_A, dpa_ctl);

2260
	POSTING_READ(DP_A);
2261 2262 2263
	udelay(500);
}

2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274
static void intel_fdi_normal_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 reg, temp;

	/* enable normal train */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2275
	if (IS_IVYBRIDGE(dev)) {
2276 2277
		temp &= ~FDI_LINK_TRAIN_NONE_IVB;
		temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2278 2279 2280
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2281
	}
2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297
	I915_WRITE(reg, temp);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_NORMAL_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_NONE;
	}
	I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);

	/* wait one idle pattern time */
	POSTING_READ(reg);
	udelay(1000);
2298 2299 2300 2301 2302

	/* IVB wants error correction enabled */
	if (IS_IVYBRIDGE(dev))
		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
			   FDI_FE_ERRC_ENABLE);
2303 2304
}

2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316
static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 flags = I915_READ(SOUTH_CHICKEN1);

	flags |= FDI_PHASE_SYNC_OVR(pipe);
	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
	flags |= FDI_PHASE_SYNC_EN(pipe);
	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
	POSTING_READ(SOUTH_CHICKEN1);
}

2317 2318 2319 2320 2321 2322 2323
/* The FDI link training functions for ILK/Ibexpeak. */
static void ironlake_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
2324
	int plane = intel_crtc->plane;
2325
	u32 reg, temp, tries;
2326

2327 2328 2329 2330
	/* FDI needs bits from pipe & plane first */
	assert_pipe_enabled(dev_priv, pipe);
	assert_plane_enabled(dev_priv, plane);

2331 2332
	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
	   for train result */
2333 2334
	reg = FDI_RX_IMR(pipe);
	temp = I915_READ(reg);
2335 2336
	temp &= ~FDI_RX_SYMBOL_LOCK;
	temp &= ~FDI_RX_BIT_LOCK;
2337 2338
	I915_WRITE(reg, temp);
	I915_READ(reg);
2339 2340
	udelay(150);

2341
	/* enable CPU FDI TX and PCH FDI RX */
2342 2343
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2344 2345
	temp &= ~(7 << 19);
	temp |= (intel_crtc->fdi_lanes - 1) << 19;
2346 2347
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
2348
	I915_WRITE(reg, temp | FDI_TX_ENABLE);
2349

2350 2351
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2352 2353
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
2354 2355 2356
	I915_WRITE(reg, temp | FDI_RX_ENABLE);

	POSTING_READ(reg);
2357 2358
	udelay(150);

2359
	/* Ironlake workaround, enable clock pointer after FDI enable*/
2360 2361 2362 2363 2364
	if (HAS_PCH_IBX(dev)) {
		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
			   FDI_RX_PHASE_SYNC_POINTER_EN);
	}
2365

2366
	reg = FDI_RX_IIR(pipe);
2367
	for (tries = 0; tries < 5; tries++) {
2368
		temp = I915_READ(reg);
2369 2370 2371 2372
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if ((temp & FDI_RX_BIT_LOCK)) {
			DRM_DEBUG_KMS("FDI train 1 done.\n");
2373
			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2374 2375 2376
			break;
		}
	}
2377
	if (tries == 5)
2378
		DRM_ERROR("FDI train 1 fail!\n");
2379 2380

	/* Train 2 */
2381 2382
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2383 2384
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_2;
2385
	I915_WRITE(reg, temp);
2386

2387 2388
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2389 2390
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_2;
2391
	I915_WRITE(reg, temp);
2392

2393 2394
	POSTING_READ(reg);
	udelay(150);
2395

2396
	reg = FDI_RX_IIR(pipe);
2397
	for (tries = 0; tries < 5; tries++) {
2398
		temp = I915_READ(reg);
2399 2400 2401
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if (temp & FDI_RX_SYMBOL_LOCK) {
2402
			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2403 2404 2405 2406
			DRM_DEBUG_KMS("FDI train 2 done.\n");
			break;
		}
	}
2407
	if (tries == 5)
2408
		DRM_ERROR("FDI train 2 fail!\n");
2409 2410

	DRM_DEBUG_KMS("FDI train done\n");
2411

2412 2413
}

2414
static const int snb_b_fdi_train_param[] = {
2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427
	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
};

/* The FDI link training functions for SNB/Cougarpoint. */
static void gen6_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
2428
	u32 reg, temp, i, retry;
2429

2430 2431
	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
	   for train result */
2432 2433
	reg = FDI_RX_IMR(pipe);
	temp = I915_READ(reg);
2434 2435
	temp &= ~FDI_RX_SYMBOL_LOCK;
	temp &= ~FDI_RX_BIT_LOCK;
2436 2437 2438
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
2439 2440
	udelay(150);

2441
	/* enable CPU FDI TX and PCH FDI RX */
2442 2443
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2444 2445
	temp &= ~(7 << 19);
	temp |= (intel_crtc->fdi_lanes - 1) << 19;
2446 2447 2448 2449 2450
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
	/* SNB-B */
	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2451
	I915_WRITE(reg, temp | FDI_TX_ENABLE);
2452

2453 2454
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2455 2456 2457 2458 2459 2460 2461
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_PATTERN_1;
	}
2462 2463 2464
	I915_WRITE(reg, temp | FDI_RX_ENABLE);

	POSTING_READ(reg);
2465 2466
	udelay(150);

2467 2468 2469
	if (HAS_PCH_CPT(dev))
		cpt_phase_pointer_enable(dev, pipe);

2470
	for (i = 0; i < 4; i++) {
2471 2472
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
2473 2474
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
2475 2476 2477
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
2478 2479
		udelay(500);

2480 2481 2482 2483 2484 2485 2486 2487 2488 2489
		for (retry = 0; retry < 5; retry++) {
			reg = FDI_RX_IIR(pipe);
			temp = I915_READ(reg);
			DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
			if (temp & FDI_RX_BIT_LOCK) {
				I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
				DRM_DEBUG_KMS("FDI train 1 done.\n");
				break;
			}
			udelay(50);
2490
		}
2491 2492
		if (retry < 5)
			break;
2493 2494
	}
	if (i == 4)
2495
		DRM_ERROR("FDI train 1 fail!\n");
2496 2497

	/* Train 2 */
2498 2499
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
2500 2501 2502 2503 2504 2505 2506
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_2;
	if (IS_GEN6(dev)) {
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		/* SNB-B */
		temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
	}
2507
	I915_WRITE(reg, temp);
2508

2509 2510
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
2511 2512 2513 2514 2515 2516 2517
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_PATTERN_2;
	}
2518 2519 2520
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
2521 2522
	udelay(150);

2523
	for (i = 0; i < 4; i++) {
2524 2525
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
2526 2527
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
2528 2529 2530
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
2531 2532
		udelay(500);

2533 2534 2535 2536 2537 2538 2539 2540 2541 2542
		for (retry = 0; retry < 5; retry++) {
			reg = FDI_RX_IIR(pipe);
			temp = I915_READ(reg);
			DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
			if (temp & FDI_RX_SYMBOL_LOCK) {
				I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
				DRM_DEBUG_KMS("FDI train 2 done.\n");
				break;
			}
			udelay(50);
2543
		}
2544 2545
		if (retry < 5)
			break;
2546 2547
	}
	if (i == 4)
2548
		DRM_ERROR("FDI train 2 fail!\n");
2549 2550 2551 2552

	DRM_DEBUG_KMS("FDI train done.\n");
}

2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581
/* Manual link training for Ivy Bridge A0 parts */
static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 reg, temp, i;

	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
	   for train result */
	reg = FDI_RX_IMR(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_RX_SYMBOL_LOCK;
	temp &= ~FDI_RX_BIT_LOCK;
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
	udelay(150);

	/* enable CPU FDI TX and PCH FDI RX */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~(7 << 19);
	temp |= (intel_crtc->fdi_lanes - 1) << 19;
	temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
	temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2582
	temp |= FDI_COMPOSITE_SYNC;
2583 2584 2585 2586 2587 2588 2589
	I915_WRITE(reg, temp | FDI_TX_ENABLE);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_AUTO;
	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
	temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2590
	temp |= FDI_COMPOSITE_SYNC;
2591 2592 2593 2594 2595
	I915_WRITE(reg, temp | FDI_RX_ENABLE);

	POSTING_READ(reg);
	udelay(150);

2596 2597 2598
	if (HAS_PCH_CPT(dev))
		cpt_phase_pointer_enable(dev, pipe);

2599
	for (i = 0; i < 4; i++) {
2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
		udelay(500);

		reg = FDI_RX_IIR(pipe);
		temp = I915_READ(reg);
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if (temp & FDI_RX_BIT_LOCK ||
		    (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
			DRM_DEBUG_KMS("FDI train 1 done.\n");
			break;
		}
	}
	if (i == 4)
		DRM_ERROR("FDI train 1 fail!\n");

	/* Train 2 */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
	temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
	I915_WRITE(reg, temp);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
	temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
	udelay(150);

2641
	for (i = 0; i < 4; i++) {
2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
		udelay(500);

		reg = FDI_RX_IIR(pipe);
		temp = I915_READ(reg);
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if (temp & FDI_RX_SYMBOL_LOCK) {
			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
			DRM_DEBUG_KMS("FDI train 2 done.\n");
			break;
		}
	}
	if (i == 4)
		DRM_ERROR("FDI train 2 fail!\n");

	DRM_DEBUG_KMS("FDI train done.\n");
}

2667
static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2668
{
2669
	struct drm_device *dev = intel_crtc->base.dev;
2670 2671
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe = intel_crtc->pipe;
2672
	u32 reg, temp;
2673

2674
	/* Write the TU size bits so error detection works */
2675 2676
	I915_WRITE(FDI_RX_TUSIZE1(pipe),
		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2677

2678
	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2679 2680 2681
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~((0x7 << 19) | (0x7 << 16));
2682
	temp |= (intel_crtc->fdi_lanes - 1) << 19;
2683 2684 2685 2686
	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);

	POSTING_READ(reg);
2687 2688 2689
	udelay(200);

	/* Switch from Rawclk to PCDclk */
2690 2691 2692 2693
	temp = I915_READ(reg);
	I915_WRITE(reg, temp | FDI_PCDCLK);

	POSTING_READ(reg);
2694 2695
	udelay(200);

2696 2697 2698 2699 2700 2701 2702 2703
	/* On Haswell, the PLL configuration for ports and pipes is handled
	 * separately, as part of DDI setup */
	if (!IS_HASWELL(dev)) {
		/* Enable CPU FDI TX PLL, always on for Ironlake */
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
		if ((temp & FDI_TX_PLL_ENABLE) == 0) {
			I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2704

2705 2706 2707
			POSTING_READ(reg);
			udelay(100);
		}
2708
	}
2709 2710
}

2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739
static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
{
	struct drm_device *dev = intel_crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe = intel_crtc->pipe;
	u32 reg, temp;

	/* Switch from PCDclk to Rawclk */
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_PCDCLK);

	/* Disable CPU FDI TX PLL */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);

	POSTING_READ(reg);
	udelay(100);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);

	/* Wait for the clocks to turn off. */
	POSTING_READ(reg);
	udelay(100);
}

2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750
static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 flags = I915_READ(SOUTH_CHICKEN1);

	flags &= ~(FDI_PHASE_SYNC_EN(pipe));
	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
	flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
	POSTING_READ(SOUTH_CHICKEN1);
}
2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774
static void ironlake_fdi_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 reg, temp;

	/* disable CPU FDI tx and PCH FDI rx */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
	POSTING_READ(reg);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~(0x7 << 16);
	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);

	POSTING_READ(reg);
	udelay(100);

	/* Ironlake workaround, disable clock pointer after downing FDI */
2775 2776
	if (HAS_PCH_IBX(dev)) {
		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2777 2778
		I915_WRITE(FDI_RX_CHICKEN(pipe),
			   I915_READ(FDI_RX_CHICKEN(pipe) &
2779
				     ~FDI_RX_PHASE_SYNC_POINTER_EN));
2780 2781
	} else if (HAS_PCH_CPT(dev)) {
		cpt_phase_pointer_disable(dev, pipe);
2782
	}
2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808

	/* still set train pattern 1 */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
	I915_WRITE(reg, temp);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_PATTERN_1;
	}
	/* BPC in FDI rx is consistent with that in PIPECONF */
	temp &= ~(0x07 << 16);
	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
	udelay(100);
}

2809 2810
static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
{
2811
	struct drm_device *dev = crtc->dev;
2812 2813 2814 2815

	if (crtc->fb == NULL)
		return;

2816 2817 2818
	mutex_lock(&dev->struct_mutex);
	intel_finish_fb(crtc->fb);
	mutex_unlock(&dev->struct_mutex);
2819 2820
}

2821 2822 2823
static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
2824
	struct intel_encoder *intel_encoder;
2825 2826 2827 2828 2829

	/*
	 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
	 * must be driven by its own crtc; no sharing is possible.
	 */
2830
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2831

2832 2833 2834 2835 2836 2837
		/* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
		 * CPU handles all others */
		if (IS_HASWELL(dev)) {
			/* It is still unclear how this will work on PPT, so throw up a warning */
			WARN_ON(!HAS_PCH_LPT(dev));

2838
			if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2839 2840 2841 2842
				DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
				return true;
			} else {
				DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2843
					      intel_encoder->type);
2844 2845 2846 2847
				return false;
			}
		}

2848
		switch (intel_encoder->type) {
2849
		case INTEL_OUTPUT_EDP:
2850
			if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2851 2852 2853 2854 2855 2856 2857 2858
				return false;
			continue;
		}
	}

	return true;
}

2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949
/* Program iCLKIP clock to the desired frequency */
static void lpt_program_iclkip(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 divsel, phaseinc, auxdiv, phasedir = 0;
	u32 temp;

	/* It is necessary to ungate the pixclk gate prior to programming
	 * the divisors, and gate it back when it is done.
	 */
	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);

	/* Disable SSCCTL */
	intel_sbi_write(dev_priv, SBI_SSCCTL6,
				intel_sbi_read(dev_priv, SBI_SSCCTL6) |
					SBI_SSCCTL_DISABLE);

	/* 20MHz is a corner case which is out of range for the 7-bit divisor */
	if (crtc->mode.clock == 20000) {
		auxdiv = 1;
		divsel = 0x41;
		phaseinc = 0x20;
	} else {
		/* The iCLK virtual clock root frequency is in MHz,
		 * but the crtc->mode.clock in in KHz. To get the divisors,
		 * it is necessary to divide one by another, so we
		 * convert the virtual clock precision to KHz here for higher
		 * precision.
		 */
		u32 iclk_virtual_root_freq = 172800 * 1000;
		u32 iclk_pi_range = 64;
		u32 desired_divisor, msb_divisor_value, pi_value;

		desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
		msb_divisor_value = desired_divisor / iclk_pi_range;
		pi_value = desired_divisor % iclk_pi_range;

		auxdiv = 0;
		divsel = msb_divisor_value - 2;
		phaseinc = pi_value;
	}

	/* This should not happen with any sane values */
	WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
		~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
	WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
		~SBI_SSCDIVINTPHASE_INCVAL_MASK);

	DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
			crtc->mode.clock,
			auxdiv,
			divsel,
			phasedir,
			phaseinc);

	/* Program SSCDIVINTPHASE6 */
	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
	temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
	temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
	temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
	temp |= SBI_SSCDIVINTPHASE_PROPAGATE;

	intel_sbi_write(dev_priv,
			SBI_SSCDIVINTPHASE6,
			temp);

	/* Program SSCAUXDIV */
	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
	temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
	intel_sbi_write(dev_priv,
			SBI_SSCAUXDIV6,
			temp);


	/* Enable modulator and associated divider */
	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
	temp &= ~SBI_SSCCTL_DISABLE;
	intel_sbi_write(dev_priv,
			SBI_SSCCTL6,
			temp);

	/* Wait for initialization time */
	udelay(24);

	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
}

2950 2951 2952 2953 2954 2955 2956 2957 2958
/*
 * Enable PCH resources required for PCH ports:
 *   - PCH PLLs
 *   - FDI training & RX/TX
 *   - update transcoder timings
 *   - DP transcoding bits
 *   - transcoder
 */
static void ironlake_pch_enable(struct drm_crtc *crtc)
2959 2960 2961 2962 2963
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
2964
	u32 reg, temp;
2965

2966 2967
	assert_transcoder_disabled(dev_priv, pipe);

2968
	/* For PCH output, training FDI link */
2969
	dev_priv->display.fdi_link_train(crtc);
2970

2971 2972
	intel_enable_pch_pll(intel_crtc);

2973 2974 2975 2976
	if (HAS_PCH_LPT(dev)) {
		DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
		lpt_program_iclkip(crtc);
	} else if (HAS_PCH_CPT(dev)) {
2977
		u32 sel;
2978

2979
		temp = I915_READ(PCH_DPLL_SEL);
2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993
		switch (pipe) {
		default:
		case 0:
			temp |= TRANSA_DPLL_ENABLE;
			sel = TRANSA_DPLLB_SEL;
			break;
		case 1:
			temp |= TRANSB_DPLL_ENABLE;
			sel = TRANSB_DPLLB_SEL;
			break;
		case 2:
			temp |= TRANSC_DPLL_ENABLE;
			sel = TRANSC_DPLLB_SEL;
			break;
2994
		}
2995 2996 2997 2998
		if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
			temp |= sel;
		else
			temp &= ~sel;
2999 3000
		I915_WRITE(PCH_DPLL_SEL, temp);
	}
3001

3002 3003
	/* set transcoder timing, panel must allow it */
	assert_panel_unlocked(dev_priv, pipe);
3004 3005 3006
	I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
	I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
	I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3007

3008 3009 3010
	I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
	I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3011
	I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3012

3013 3014
	if (!IS_HASWELL(dev))
		intel_fdi_normal_train(crtc);
3015

3016 3017
	/* For PCH DP, enable TRANS_DP_CTL */
	if (HAS_PCH_CPT(dev) &&
3018 3019
	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
	     intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3020
		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3021 3022 3023
		reg = TRANS_DP_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~(TRANS_DP_PORT_SEL_MASK |
3024 3025
			  TRANS_DP_SYNC_MASK |
			  TRANS_DP_BPC_MASK);
3026 3027
		temp |= (TRANS_DP_OUTPUT_ENABLE |
			 TRANS_DP_ENH_FRAMING);
3028
		temp |= bpc << 9; /* same format but at 11:9 */
3029 3030

		if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3031
			temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3032
		if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3033
			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3034 3035 3036

		switch (intel_trans_dp_port_sel(crtc)) {
		case PCH_DP_B:
3037
			temp |= TRANS_DP_PORT_SEL_B;
3038 3039
			break;
		case PCH_DP_C:
3040
			temp |= TRANS_DP_PORT_SEL_C;
3041 3042
			break;
		case PCH_DP_D:
3043
			temp |= TRANS_DP_PORT_SEL_D;
3044 3045 3046
			break;
		default:
			DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3047
			temp |= TRANS_DP_PORT_SEL_B;
3048
			break;
3049
		}
3050

3051
		I915_WRITE(reg, temp);
3052
	}
3053

3054
	intel_enable_transcoder(dev_priv, pipe);
3055 3056
}

3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085
static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
{
	struct intel_pch_pll *pll = intel_crtc->pch_pll;

	if (pll == NULL)
		return;

	if (pll->refcount == 0) {
		WARN(1, "bad PCH PLL refcount\n");
		return;
	}

	--pll->refcount;
	intel_crtc->pch_pll = NULL;
}

static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
{
	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
	struct intel_pch_pll *pll;
	int i;

	pll = intel_crtc->pch_pll;
	if (pll) {
		DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
			      intel_crtc->base.base.id, pll->pll_reg);
		goto prepare;
	}

3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096
	if (HAS_PCH_IBX(dev_priv->dev)) {
		/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
		i = intel_crtc->pipe;
		pll = &dev_priv->pch_plls[i];

		DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
			      intel_crtc->base.base.id, pll->pll_reg);

		goto found;
	}

3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132
	for (i = 0; i < dev_priv->num_pch_pll; i++) {
		pll = &dev_priv->pch_plls[i];

		/* Only want to check enabled timings first */
		if (pll->refcount == 0)
			continue;

		if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
		    fp == I915_READ(pll->fp0_reg)) {
			DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
				      intel_crtc->base.base.id,
				      pll->pll_reg, pll->refcount, pll->active);

			goto found;
		}
	}

	/* Ok no matching timings, maybe there's a free one? */
	for (i = 0; i < dev_priv->num_pch_pll; i++) {
		pll = &dev_priv->pch_plls[i];
		if (pll->refcount == 0) {
			DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
				      intel_crtc->base.base.id, pll->pll_reg);
			goto found;
		}
	}

	return NULL;

found:
	intel_crtc->pch_pll = pll;
	pll->refcount++;
	DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
prepare: /* separate function? */
	DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);

3133 3134
	/* Wait for the clocks to stabilize before rewriting the regs */
	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3135 3136
	POSTING_READ(pll->pll_reg);
	udelay(150);
3137 3138 3139

	I915_WRITE(pll->fp0_reg, fp);
	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3140 3141 3142 3143
	pll->on = false;
	return pll;
}

3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161
void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
	u32 temp;

	temp = I915_READ(dslreg);
	udelay(500);
	if (wait_for(I915_READ(dslreg) != temp, 5)) {
		/* Without this, mode sets may fail silently on FDI */
		I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
		udelay(250);
		I915_WRITE(tc2reg, 0);
		if (wait_for(I915_READ(dslreg) != temp, 5))
			DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
	}
}

3162 3163 3164 3165 3166
static void ironlake_crtc_enable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3167
	struct intel_encoder *encoder;
3168 3169 3170 3171 3172
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
	u32 temp;
	bool is_pch_port;

3173 3174
	WARN_ON(!crtc->enabled);

3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188
	if (intel_crtc->active)
		return;

	intel_crtc->active = true;
	intel_update_watermarks(dev);

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		temp = I915_READ(PCH_LVDS);
		if ((temp & LVDS_PORT_EN) == 0)
			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
	}

	is_pch_port = intel_crtc_driving_pch(crtc);

3189
	if (is_pch_port) {
3190
		ironlake_fdi_pll_enable(intel_crtc);
3191 3192 3193 3194
	} else {
		assert_fdi_tx_disabled(dev_priv, pipe);
		assert_fdi_rx_disabled(dev_priv, pipe);
	}
3195

3196 3197 3198 3199
	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->pre_enable)
			encoder->pre_enable(encoder);

3200 3201 3202
	if (IS_HASWELL(dev))
		intel_ddi_enable_pipe_clock(intel_crtc);

3203 3204 3205 3206 3207 3208 3209
	/* Enable panel fitting for LVDS */
	if (dev_priv->pch_pf_size &&
	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
		/* Force use of hard-coded filter coefficients
		 * as some pre-programmed values are broken,
		 * e.g. x201.
		 */
3210 3211 3212
		I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
		I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
		I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3213 3214
	}

3215 3216 3217 3218 3219 3220
	/*
	 * On ILK+ LUT must be loaded before the pipe is running but with
	 * clocks enabled
	 */
	intel_crtc_load_lut(crtc);

3221 3222 3223
	if (IS_HASWELL(dev))
		intel_ddi_enable_pipe_func(crtc);

3224 3225 3226 3227 3228
	intel_enable_pipe(dev_priv, pipe, is_pch_port);
	intel_enable_plane(dev_priv, plane, pipe);

	if (is_pch_port)
		ironlake_pch_enable(crtc);
3229

3230
	mutex_lock(&dev->struct_mutex);
C
Chris Wilson 已提交
3231
	intel_update_fbc(dev);
3232 3233
	mutex_unlock(&dev->struct_mutex);

3234
	intel_crtc_update_cursor(crtc, true);
3235

3236 3237
	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->enable(encoder);
3238 3239 3240

	if (HAS_PCH_CPT(dev))
		intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3241 3242 3243 3244 3245 3246 3247
}

static void ironlake_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3248
	struct intel_encoder *encoder;
3249 3250
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
3251
	u32 reg, temp;
3252

3253

3254 3255 3256
	if (!intel_crtc->active)
		return;

3257 3258 3259
	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->disable(encoder);

3260
	intel_crtc_wait_for_pending_flips(crtc);
3261
	drm_vblank_off(dev, pipe);
3262
	intel_crtc_update_cursor(crtc, false);
3263

3264
	intel_disable_plane(dev_priv, plane, pipe);
3265

3266 3267
	if (dev_priv->cfb_plane == plane)
		intel_disable_fbc(dev);
3268

3269
	intel_disable_pipe(dev_priv, pipe);
3270

3271 3272 3273
	if (IS_HASWELL(dev))
		intel_ddi_disable_pipe_func(dev_priv, pipe);

3274
	/* Disable PF */
3275 3276
	I915_WRITE(PF_CTL(pipe), 0);
	I915_WRITE(PF_WIN_SZ(pipe), 0);
3277

3278 3279 3280
	if (IS_HASWELL(dev))
		intel_ddi_disable_pipe_clock(intel_crtc);

3281 3282 3283 3284
	for_each_encoder_on_crtc(dev, crtc, encoder)
		if (encoder->post_disable)
			encoder->post_disable(encoder);

3285
	ironlake_fdi_disable(crtc);
3286

3287
	intel_disable_transcoder(dev_priv, pipe);
3288

3289 3290
	if (HAS_PCH_CPT(dev)) {
		/* disable TRANS_DP_CTL */
3291 3292 3293
		reg = TRANS_DP_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3294
		temp |= TRANS_DP_PORT_SEL_NONE;
3295
		I915_WRITE(reg, temp);
3296 3297 3298

		/* disable DPLL_SEL */
		temp = I915_READ(PCH_DPLL_SEL);
3299 3300
		switch (pipe) {
		case 0:
3301
			temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3302 3303
			break;
		case 1:
3304
			temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3305 3306
			break;
		case 2:
3307
			/* C shares PLL A or B */
3308
			temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3309 3310 3311 3312
			break;
		default:
			BUG(); /* wtf */
		}
3313 3314
		I915_WRITE(PCH_DPLL_SEL, temp);
	}
3315

3316
	/* disable PCH DPLL */
3317
	intel_disable_pch_pll(intel_crtc);
3318

3319
	ironlake_fdi_pll_disable(intel_crtc);
3320

3321
	intel_crtc->active = false;
3322
	intel_update_watermarks(dev);
3323 3324

	mutex_lock(&dev->struct_mutex);
3325
	intel_update_fbc(dev);
3326
	mutex_unlock(&dev->struct_mutex);
3327
}
3328

3329 3330 3331 3332 3333 3334
static void ironlake_crtc_off(struct drm_crtc *crtc)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	intel_put_pch_pll(intel_crtc);
}

3335 3336 3337 3338 3339
static void haswell_crtc_off(struct drm_crtc *crtc)
{
	intel_ddi_put_crtc_pll(crtc);
}

3340 3341 3342
static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
{
	if (!enable && intel_crtc->overlay) {
3343
		struct drm_device *dev = intel_crtc->base.dev;
3344
		struct drm_i915_private *dev_priv = dev->dev_private;
3345

3346
		mutex_lock(&dev->struct_mutex);
3347 3348 3349
		dev_priv->mm.interruptible = false;
		(void) intel_overlay_switch_off(intel_crtc->overlay);
		dev_priv->mm.interruptible = true;
3350
		mutex_unlock(&dev->struct_mutex);
3351 3352
	}

3353 3354 3355
	/* Let userspace switch the overlay on again. In most cases userspace
	 * has to recompute where to put it anyway.
	 */
3356 3357
}

3358
static void i9xx_crtc_enable(struct drm_crtc *crtc)
3359 3360 3361 3362
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3363
	struct intel_encoder *encoder;
3364
	int pipe = intel_crtc->pipe;
3365
	int plane = intel_crtc->plane;
3366

3367 3368
	WARN_ON(!crtc->enabled);

3369 3370 3371 3372
	if (intel_crtc->active)
		return;

	intel_crtc->active = true;
3373 3374
	intel_update_watermarks(dev);

3375
	intel_enable_pll(dev_priv, pipe);
3376
	intel_enable_pipe(dev_priv, pipe, false);
3377
	intel_enable_plane(dev_priv, plane, pipe);
3378

3379
	intel_crtc_load_lut(crtc);
C
Chris Wilson 已提交
3380
	intel_update_fbc(dev);
3381

3382 3383
	/* Give the overlay scaler a chance to enable if it's on this pipe */
	intel_crtc_dpms_overlay(intel_crtc, true);
3384
	intel_crtc_update_cursor(crtc, true);
3385

3386 3387
	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->enable(encoder);
3388
}
3389

3390 3391 3392 3393 3394
static void i9xx_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3395
	struct intel_encoder *encoder;
3396 3397
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
3398

3399

3400 3401 3402
	if (!intel_crtc->active)
		return;

3403 3404 3405
	for_each_encoder_on_crtc(dev, crtc, encoder)
		encoder->disable(encoder);

3406
	/* Give the overlay scaler a chance to disable if it's on this pipe */
3407 3408
	intel_crtc_wait_for_pending_flips(crtc);
	drm_vblank_off(dev, pipe);
3409
	intel_crtc_dpms_overlay(intel_crtc, false);
3410
	intel_crtc_update_cursor(crtc, false);
3411

3412 3413
	if (dev_priv->cfb_plane == plane)
		intel_disable_fbc(dev);
3414

3415 3416
	intel_disable_plane(dev_priv, plane, pipe);
	intel_disable_pipe(dev_priv, pipe);
3417
	intel_disable_pll(dev_priv, pipe);
3418

3419
	intel_crtc->active = false;
3420 3421
	intel_update_fbc(dev);
	intel_update_watermarks(dev);
3422 3423
}

3424 3425 3426 3427
static void i9xx_crtc_off(struct drm_crtc *crtc)
{
}

3428 3429
static void intel_crtc_update_sarea(struct drm_crtc *crtc,
				    bool enabled)
3430 3431 3432 3433 3434
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_master_private *master_priv;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452

	if (!dev->primary->master)
		return;

	master_priv = dev->primary->master->driver_priv;
	if (!master_priv->sarea_priv)
		return;

	switch (pipe) {
	case 0:
		master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
		master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
		break;
	case 1:
		master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
		master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
		break;
	default:
3453
		DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3454 3455 3456 3457
		break;
	}
}

3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482
/**
 * Sets the power management mode of the pipe and plane.
 */
void intel_crtc_update_dpms(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *intel_encoder;
	bool enable = false;

	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		enable |= intel_encoder->connectors_active;

	if (enable)
		dev_priv->display.crtc_enable(crtc);
	else
		dev_priv->display.crtc_disable(crtc);

	intel_crtc_update_sarea(crtc, enable);
}

static void intel_crtc_noop(struct drm_crtc *crtc)
{
}

3483 3484 3485
static void intel_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
3486
	struct drm_connector *connector;
3487
	struct drm_i915_private *dev_priv = dev->dev_private;
3488

3489 3490 3491 3492 3493
	/* crtc should still be enabled when we disable it. */
	WARN_ON(!crtc->enabled);

	dev_priv->display.crtc_disable(crtc);
	intel_crtc_update_sarea(crtc, false);
3494 3495
	dev_priv->display.off(crtc);

3496 3497
	assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
	assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3498 3499 3500

	if (crtc->fb) {
		mutex_lock(&dev->struct_mutex);
3501
		intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3502
		mutex_unlock(&dev->struct_mutex);
3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515
		crtc->fb = NULL;
	}

	/* Update computed state. */
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		if (!connector->encoder || !connector->encoder->crtc)
			continue;

		if (connector->encoder->crtc != crtc)
			continue;

		connector->dpms = DRM_MODE_DPMS_OFF;
		to_intel_encoder(connector->encoder)->connectors_active = false;
3516 3517 3518
	}
}

3519
void intel_modeset_disable(struct drm_device *dev)
3520
{
3521 3522 3523 3524 3525 3526
	struct drm_crtc *crtc;

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		if (crtc->enabled)
			intel_crtc_disable(crtc);
	}
3527 3528
}

3529
void intel_encoder_noop(struct drm_encoder *encoder)
3530
{
3531 3532
}

3533
void intel_encoder_destroy(struct drm_encoder *encoder)
3534
{
3535
	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3536 3537 3538

	drm_encoder_cleanup(encoder);
	kfree(intel_encoder);
3539 3540
}

3541 3542 3543 3544
/* Simple dpms helper for encodres with just one connector, no cloning and only
 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
 * state of the entire output pipe. */
void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3545
{
3546 3547 3548
	if (mode == DRM_MODE_DPMS_ON) {
		encoder->connectors_active = true;

3549
		intel_crtc_update_dpms(encoder->base.crtc);
3550 3551 3552
	} else {
		encoder->connectors_active = false;

3553
		intel_crtc_update_dpms(encoder->base.crtc);
3554
	}
3555 3556
}

3557 3558
/* Cross check the actual hw state with our own modeset state tracking (and it's
 * internal consistency). */
3559
static void intel_connector_check_state(struct intel_connector *connector)
3560
{
3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589
	if (connector->get_hw_state(connector)) {
		struct intel_encoder *encoder = connector->encoder;
		struct drm_crtc *crtc;
		bool encoder_enabled;
		enum pipe pipe;

		DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
			      connector->base.base.id,
			      drm_get_connector_name(&connector->base));

		WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
		     "wrong connector dpms state\n");
		WARN(connector->base.encoder != &encoder->base,
		     "active connector not linked to encoder\n");
		WARN(!encoder->connectors_active,
		     "encoder->connectors_active not set\n");

		encoder_enabled = encoder->get_hw_state(encoder, &pipe);
		WARN(!encoder_enabled, "encoder not enabled\n");
		if (WARN_ON(!encoder->base.crtc))
			return;

		crtc = encoder->base.crtc;

		WARN(!crtc->enabled, "crtc not enabled\n");
		WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
		WARN(pipe != to_intel_crtc(crtc)->pipe,
		     "encoder active on the wrong pipe\n");
	}
3590 3591
}

3592 3593 3594
/* Even simpler default implementation, if there's really no special case to
 * consider. */
void intel_connector_dpms(struct drm_connector *connector, int mode)
3595
{
3596
	struct intel_encoder *encoder = intel_attached_encoder(connector);
3597

3598 3599 3600
	/* All the simple cases only support two dpms states. */
	if (mode != DRM_MODE_DPMS_ON)
		mode = DRM_MODE_DPMS_OFF;
3601

3602 3603 3604 3605 3606 3607 3608 3609 3610
	if (mode == connector->dpms)
		return;

	connector->dpms = mode;

	/* Only need to change hw state when actually enabled */
	if (encoder->base.crtc)
		intel_encoder_dpms(encoder, mode);
	else
3611
		WARN_ON(encoder->connectors_active != false);
3612

3613
	intel_modeset_check_state(connector->dev);
3614 3615
}

3616 3617 3618 3619
/* Simple connector->get_hw_state implementation for encoders that support only
 * one connector and no cloning and hence the encoder state determines the state
 * of the connector. */
bool intel_connector_get_hw_state(struct intel_connector *connector)
3620
{
3621
	enum pipe pipe = 0;
3622
	struct intel_encoder *encoder = connector->encoder;
3623

3624
	return encoder->get_hw_state(encoder, &pipe);
3625 3626
}

3627
static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3628
				  const struct drm_display_mode *mode,
3629 3630
				  struct drm_display_mode *adjusted_mode)
{
3631
	struct drm_device *dev = crtc->dev;
3632

3633
	if (HAS_PCH_SPLIT(dev)) {
3634
		/* FDI link clock is fixed at 2.7G */
3635 3636
		if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
			return false;
3637
	}
3638

3639 3640 3641 3642 3643
	/* All interlaced capable intel hw wants timings in frames. Note though
	 * that intel_lvds_mode_fixup does some funny tricks with the crtc
	 * timings, so we need to be careful not to clobber these.*/
	if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
		drm_mode_set_crtcinfo(adjusted_mode, 0);
3644

3645 3646 3647 3648 3649 3650 3651
	/* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
	 * with a hsync front porch of 0.
	 */
	if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
		adjusted_mode->hsync_start == adjusted_mode->hdisplay)
		return false;

3652 3653 3654
	return true;
}

3655 3656 3657 3658 3659
static int valleyview_get_display_clock_speed(struct drm_device *dev)
{
	return 400000; /* FIXME */
}

3660 3661 3662 3663
static int i945_get_display_clock_speed(struct drm_device *dev)
{
	return 400000;
}
3664

3665
static int i915_get_display_clock_speed(struct drm_device *dev)
3666
{
3667 3668
	return 333000;
}
3669

3670 3671 3672 3673
static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
{
	return 200000;
}
3674

3675 3676 3677
static int i915gm_get_display_clock_speed(struct drm_device *dev)
{
	u16 gcfgc = 0;
3678

3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689
	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);

	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
		return 133000;
	else {
		switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		case GC_DISPLAY_CLOCK_333_MHZ:
			return 333000;
		default:
		case GC_DISPLAY_CLOCK_190_200_MHZ:
			return 190000;
3690
		}
3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711
	}
}

static int i865_get_display_clock_speed(struct drm_device *dev)
{
	return 266000;
}

static int i855_get_display_clock_speed(struct drm_device *dev)
{
	u16 hpllcc = 0;
	/* Assume that the hardware is in the high speed state.  This
	 * should be the default.
	 */
	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
	case GC_CLOCK_133_200:
	case GC_CLOCK_100_200:
		return 200000;
	case GC_CLOCK_166_250:
		return 250000;
	case GC_CLOCK_100_133:
3712
		return 133000;
3713
	}
3714

3715 3716 3717
	/* Shouldn't happen */
	return 0;
}
3718

3719 3720 3721
static int i830_get_display_clock_speed(struct drm_device *dev)
{
	return 133000;
3722 3723
}

3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741
struct fdi_m_n {
	u32        tu;
	u32        gmch_m;
	u32        gmch_n;
	u32        link_m;
	u32        link_n;
};

static void
fdi_reduce_ratio(u32 *num, u32 *den)
{
	while (*num > 0xffffff || *den > 0xffffff) {
		*num >>= 1;
		*den >>= 1;
	}
}

static void
3742 3743
ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
		     int link_clock, struct fdi_m_n *m_n)
3744 3745 3746
{
	m_n->tu = 64; /* default size */

3747 3748 3749
	/* BUG_ON(pixel_clock > INT_MAX / 36); */
	m_n->gmch_m = bits_per_pixel * pixel_clock;
	m_n->gmch_n = link_clock * nlanes * 8;
3750 3751
	fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);

3752 3753
	m_n->link_m = pixel_clock;
	m_n->link_n = link_clock;
3754 3755 3756
	fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
}

3757 3758
static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
{
3759 3760 3761
	if (i915_panel_use_ssc >= 0)
		return i915_panel_use_ssc != 0;
	return dev_priv->lvds_use_ssc
3762
		&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3763 3764
}

3765 3766 3767
/**
 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
 * @crtc: CRTC structure
3768
 * @mode: requested mode
3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779
 *
 * A pipe may be connected to one or more outputs.  Based on the depth of the
 * attached framebuffer, choose a good color depth to use on the pipe.
 *
 * If possible, match the pipe depth to the fb depth.  In some cases, this
 * isn't ideal, because the connected output supports a lesser or restricted
 * set of depths.  Resolve that here:
 *    LVDS typically supports only 6bpc, so clamp down in that case
 *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
 *    Displays may support a restricted set as well, check EDID and clamp as
 *      appropriate.
3780
 *    DP may want to dither down to 6bpc to fit larger modes
3781 3782 3783 3784 3785 3786
 *
 * RETURNS:
 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
 * true if they don't match).
 */
static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3787
					 struct drm_framebuffer *fb,
3788 3789
					 unsigned int *pipe_bpp,
					 struct drm_display_mode *mode)
3790 3791 3792 3793
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_connector *connector;
3794
	struct intel_encoder *intel_encoder;
3795 3796 3797
	unsigned int display_bpc = UINT_MAX, bpc;

	/* Walk the encoders & connectors on this crtc, get min bpc */
3798
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809

		if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
			unsigned int lvds_bpc;

			if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
			    LVDS_A3_POWER_UP)
				lvds_bpc = 8;
			else
				lvds_bpc = 6;

			if (lvds_bpc < display_bpc) {
3810
				DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3811 3812 3813 3814 3815 3816 3817 3818
				display_bpc = lvds_bpc;
			}
			continue;
		}

		/* Not one of the known troublemakers, check the EDID */
		list_for_each_entry(connector, &dev->mode_config.connector_list,
				    head) {
3819
			if (connector->encoder != &intel_encoder->base)
3820 3821
				continue;

3822 3823 3824
			/* Don't use an invalid EDID bpc value */
			if (connector->display_info.bpc &&
			    connector->display_info.bpc < display_bpc) {
3825
				DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3826 3827 3828 3829 3830 3831 3832 3833 3834 3835
				display_bpc = connector->display_info.bpc;
			}
		}

		/*
		 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
		 * through, clamp it down.  (Note: >12bpc will be caught below.)
		 */
		if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
			if (display_bpc > 8 && display_bpc < 12) {
3836
				DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3837 3838
				display_bpc = 12;
			} else {
3839
				DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3840 3841 3842 3843 3844
				display_bpc = 8;
			}
		}
	}

3845 3846 3847 3848 3849
	if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
		DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
		display_bpc = 6;
	}

3850 3851 3852 3853 3854 3855 3856
	/*
	 * We could just drive the pipe at the highest bpc all the time and
	 * enable dithering as needed, but that costs bandwidth.  So choose
	 * the minimum value that expresses the full color range of the fb but
	 * also stays within the max display bpc discovered above.
	 */

3857
	switch (fb->depth) {
3858 3859 3860 3861 3862 3863 3864 3865
	case 8:
		bpc = 8; /* since we go through a colormap */
		break;
	case 15:
	case 16:
		bpc = 6; /* min is 18bpp */
		break;
	case 24:
3866
		bpc = 8;
3867 3868
		break;
	case 30:
3869
		bpc = 10;
3870 3871
		break;
	case 48:
3872
		bpc = 12;
3873 3874 3875 3876 3877 3878 3879
		break;
	default:
		DRM_DEBUG("unsupported depth, assuming 24 bits\n");
		bpc = min((unsigned int)8, display_bpc);
		break;
	}

3880 3881
	display_bpc = min(display_bpc, bpc);

3882 3883
	DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
		      bpc, display_bpc);
3884

3885
	*pipe_bpp = display_bpc * 3;
3886 3887 3888 3889

	return display_bpc != bpc;
}

3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911
static int vlv_get_refclk(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int refclk = 27000; /* for DP & HDMI */

	return 100000; /* only one validated so far */

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		refclk = 96000;
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		if (intel_panel_use_ssc(dev_priv))
			refclk = 100000;
		else
			refclk = 96000;
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
		refclk = 100000;
	}

	return refclk;
}

3912 3913 3914 3915 3916 3917
static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int refclk;

3918 3919 3920
	if (IS_VALLEYVIEW(dev)) {
		refclk = vlv_get_refclk(crtc);
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955
	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		refclk = dev_priv->lvds_ssc_freq * 1000;
		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
			      refclk / 1000);
	} else if (!IS_GEN2(dev)) {
		refclk = 96000;
	} else {
		refclk = 48000;
	}

	return refclk;
}

static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
				      intel_clock_t *clock)
{
	/* SDVO TV has fixed PLL values depend on its clock range,
	   this mirrors vbios setting. */
	if (adjusted_mode->clock >= 100000
	    && adjusted_mode->clock < 140500) {
		clock->p1 = 2;
		clock->p2 = 10;
		clock->n = 3;
		clock->m1 = 16;
		clock->m2 = 8;
	} else if (adjusted_mode->clock >= 140500
		   && adjusted_mode->clock <= 200000) {
		clock->p1 = 1;
		clock->p2 = 10;
		clock->n = 6;
		clock->m1 = 12;
		clock->m2 = 8;
	}
}

3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989
static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
				     intel_clock_t *clock,
				     intel_clock_t *reduced_clock)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 fp, fp2 = 0;

	if (IS_PINEVIEW(dev)) {
		fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
		if (reduced_clock)
			fp2 = (1 << reduced_clock->n) << 16 |
				reduced_clock->m1 << 8 | reduced_clock->m2;
	} else {
		fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
		if (reduced_clock)
			fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
				reduced_clock->m2;
	}

	I915_WRITE(FP0(pipe), fp);

	intel_crtc->lowfreq_avail = false;
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
	    reduced_clock && i915_powersave) {
		I915_WRITE(FP1(pipe), fp2);
		intel_crtc->lowfreq_avail = true;
	} else {
		I915_WRITE(FP1(pipe), fp);
	}
}

3990 3991 3992 3993 3994 3995 3996
static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
			      struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
3997
	u32 temp;
3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026

	temp = I915_READ(LVDS);
	temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
	if (pipe == 1) {
		temp |= LVDS_PIPEB_SELECT;
	} else {
		temp &= ~LVDS_PIPEB_SELECT;
	}
	/* set the corresponsding LVDS_BORDER bit */
	temp |= dev_priv->lvds_border_bits;
	/* Set the B0-B3 data pairs corresponding to whether we're going to
	 * set the DPLLs for dual-channel mode or not.
	 */
	if (clock->p2 == 7)
		temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
	else
		temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);

	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
	 * appropriately here, but we need to look more thoroughly into how
	 * panels behave in the two modes.
	 */
	/* set the dithering flag on LVDS as needed */
	if (INTEL_INFO(dev)->gen >= 4) {
		if (dev_priv->lvds_dither)
			temp |= LVDS_ENABLE_DITHER;
		else
			temp &= ~LVDS_ENABLE_DITHER;
	}
4027
	temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4028
	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4029
		temp |= LVDS_HSYNC_POLARITY;
4030
	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4031
		temp |= LVDS_VSYNC_POLARITY;
4032 4033 4034
	I915_WRITE(LVDS, temp);
}

4035 4036 4037 4038
static void vlv_update_pll(struct drm_crtc *crtc,
			   struct drm_display_mode *mode,
			   struct drm_display_mode *adjusted_mode,
			   intel_clock_t *clock, intel_clock_t *reduced_clock,
4039
			   int num_connectors)
4040 4041 4042 4043 4044 4045 4046
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 dpll, mdiv, pdiv;
	u32 bestn, bestm1, bestm2, bestp1, bestp2;
4047 4048 4049 4050 4051
	bool is_sdvo;
	u32 temp;

	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4052

4053 4054 4055 4056 4057 4058 4059
	dpll = DPLL_VGA_MODE_DIS;
	dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
	dpll |= DPLL_REFA_CLK_ENABLE_VLV;
	dpll |= DPLL_INTEGRATED_CLOCK_VLV;

	I915_WRITE(DPLL(pipe), dpll);
	POSTING_READ(DPLL(pipe));
4060 4061 4062 4063 4064 4065 4066

	bestn = clock->n;
	bestm1 = clock->m1;
	bestm2 = clock->m2;
	bestp1 = clock->p1;
	bestp2 = clock->p2;

4067 4068 4069 4070
	/*
	 * In Valleyview PLL and program lane counter registers are exposed
	 * through DPIO interface
	 */
4071 4072 4073 4074 4075 4076 4077 4078 4079 4080
	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
	mdiv |= ((bestn << DPIO_N_SHIFT));
	mdiv |= (1 << DPIO_POST_DIV_SHIFT);
	mdiv |= (1 << DPIO_K_SHIFT);
	mdiv |= DPIO_ENABLE_CALIBRATION;
	intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);

	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);

4081
	pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4082
		(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4083 4084
		(7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
		(5 << DPIO_CLK_BIAS_CTL_SHIFT);
4085 4086
	intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);

4087
	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4088 4089 4090 4091 4092 4093 4094

	dpll |= DPLL_VCO_ENABLE;
	I915_WRITE(DPLL(pipe), dpll);
	POSTING_READ(DPLL(pipe));
	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
		DRM_ERROR("DPLL %d failed to lock\n", pipe);

4095 4096 4097 4098 4099 4100 4101 4102 4103 4104
	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
		intel_dp_set_m_n(crtc, mode, adjusted_mode);

	I915_WRITE(DPLL(pipe), dpll);

	/* Wait for the clocks to stabilize. */
	POSTING_READ(DPLL(pipe));
	udelay(150);
4105

4106 4107 4108
	temp = 0;
	if (is_sdvo) {
		temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4109 4110 4111 4112 4113
		if (temp > 1)
			temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
		else
			temp = 0;
	}
4114 4115
	I915_WRITE(DPLL_MD(pipe), temp);
	POSTING_READ(DPLL_MD(pipe));
4116

4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132
	/* Now program lane control registers */
	if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
			|| intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
	{
		temp = 0x1000C4;
		if(pipe == 1)
			temp |= (1 << 21);
		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
	}
	if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
	{
		temp = 0x1000C4;
		if(pipe == 1)
			temp |= (1 << 21);
		intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
	}
4133 4134
}

4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147
static void i9xx_update_pll(struct drm_crtc *crtc,
			    struct drm_display_mode *mode,
			    struct drm_display_mode *adjusted_mode,
			    intel_clock_t *clock, intel_clock_t *reduced_clock,
			    int num_connectors)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 dpll;
	bool is_sdvo;

4148 4149
	i9xx_update_pll_dividers(crtc, clock, reduced_clock);

4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249
	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);

	dpll = DPLL_VGA_MODE_DIS;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		dpll |= DPLLB_MODE_LVDS;
	else
		dpll |= DPLLB_MODE_DAC_SERIAL;
	if (is_sdvo) {
		int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
		if (pixel_multiplier > 1) {
			if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
				dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
		}
		dpll |= DPLL_DVO_HIGH_SPEED;
	}
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
		dpll |= DPLL_DVO_HIGH_SPEED;

	/* compute bitmask from p1 value */
	if (IS_PINEVIEW(dev))
		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
	else {
		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		if (IS_G4X(dev) && reduced_clock)
			dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
	}
	switch (clock->p2) {
	case 5:
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		break;
	case 7:
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
		break;
	case 10:
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		break;
	case 14:
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
		break;
	}
	if (INTEL_INFO(dev)->gen >= 4)
		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);

	if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
		dpll |= PLL_REF_INPUT_TVCLKINBC;
	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
		/* XXX: just matching BIOS for now */
		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
		dpll |= 3;
	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
	else
		dpll |= PLL_REF_INPUT_DREFCLK;

	dpll |= DPLL_VCO_ENABLE;
	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
	POSTING_READ(DPLL(pipe));
	udelay(150);

	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
	 * This is an exception to the general rule that mode_set doesn't turn
	 * things on.
	 */
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		intel_update_lvds(crtc, clock, adjusted_mode);

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
		intel_dp_set_m_n(crtc, mode, adjusted_mode);

	I915_WRITE(DPLL(pipe), dpll);

	/* Wait for the clocks to stabilize. */
	POSTING_READ(DPLL(pipe));
	udelay(150);

	if (INTEL_INFO(dev)->gen >= 4) {
		u32 temp = 0;
		if (is_sdvo) {
			temp = intel_mode_get_pixel_multiplier(adjusted_mode);
			if (temp > 1)
				temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
			else
				temp = 0;
		}
		I915_WRITE(DPLL_MD(pipe), temp);
	} else {
		/* The pixel multiplier can only be updated once the
		 * DPLL is enabled and the clocks are stable.
		 *
		 * So write it again.
		 */
		I915_WRITE(DPLL(pipe), dpll);
	}
}

static void i8xx_update_pll(struct drm_crtc *crtc,
			    struct drm_display_mode *adjusted_mode,
4250
			    intel_clock_t *clock, intel_clock_t *reduced_clock,
4251 4252 4253 4254 4255 4256 4257 4258
			    int num_connectors)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 dpll;

4259 4260
	i9xx_update_pll_dividers(crtc, clock, reduced_clock);

4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295
	dpll = DPLL_VGA_MODE_DIS;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
	} else {
		if (clock->p1 == 2)
			dpll |= PLL_P1_DIVIDE_BY_TWO;
		else
			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		if (clock->p2 == 4)
			dpll |= PLL_P2_DIVIDE_BY_4;
	}

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
		/* XXX: just matching BIOS for now */
		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
		dpll |= 3;
	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
	else
		dpll |= PLL_REF_INPUT_DREFCLK;

	dpll |= DPLL_VCO_ENABLE;
	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
	POSTING_READ(DPLL(pipe));
	udelay(150);

	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
	 * This is an exception to the general rule that mode_set doesn't turn
	 * things on.
	 */
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
		intel_update_lvds(crtc, clock, adjusted_mode);

4296 4297 4298 4299 4300 4301
	I915_WRITE(DPLL(pipe), dpll);

	/* Wait for the clocks to stabilize. */
	POSTING_READ(DPLL(pipe));
	udelay(150);

4302 4303 4304 4305 4306 4307 4308 4309
	/* The pixel multiplier can only be updated once the
	 * DPLL is enabled and the clocks are stable.
	 *
	 * So write it again.
	 */
	I915_WRITE(DPLL(pipe), dpll);
}

4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358
static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
				   struct drm_display_mode *mode,
				   struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = intel_crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe = intel_crtc->pipe;
	uint32_t vsyncshift;

	if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		/* the chip adds 2 halflines automatically */
		adjusted_mode->crtc_vtotal -= 1;
		adjusted_mode->crtc_vblank_end -= 1;
		vsyncshift = adjusted_mode->crtc_hsync_start
			     - adjusted_mode->crtc_htotal / 2;
	} else {
		vsyncshift = 0;
	}

	if (INTEL_INFO(dev)->gen > 3)
		I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);

	I915_WRITE(HTOTAL(pipe),
		   (adjusted_mode->crtc_hdisplay - 1) |
		   ((adjusted_mode->crtc_htotal - 1) << 16));
	I915_WRITE(HBLANK(pipe),
		   (adjusted_mode->crtc_hblank_start - 1) |
		   ((adjusted_mode->crtc_hblank_end - 1) << 16));
	I915_WRITE(HSYNC(pipe),
		   (adjusted_mode->crtc_hsync_start - 1) |
		   ((adjusted_mode->crtc_hsync_end - 1) << 16));

	I915_WRITE(VTOTAL(pipe),
		   (adjusted_mode->crtc_vdisplay - 1) |
		   ((adjusted_mode->crtc_vtotal - 1) << 16));
	I915_WRITE(VBLANK(pipe),
		   (adjusted_mode->crtc_vblank_start - 1) |
		   ((adjusted_mode->crtc_vblank_end - 1) << 16));
	I915_WRITE(VSYNC(pipe),
		   (adjusted_mode->crtc_vsync_start - 1) |
		   ((adjusted_mode->crtc_vsync_end - 1) << 16));

	/* pipesrc controls the size that is scaled from, which should
	 * always be the user's requested size.
	 */
	I915_WRITE(PIPESRC(pipe),
		   ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
}

4359 4360 4361 4362
static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
			      struct drm_display_mode *mode,
			      struct drm_display_mode *adjusted_mode,
			      int x, int y,
4363
			      struct drm_framebuffer *fb)
4364 4365 4366 4367 4368
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
4369
	int plane = intel_crtc->plane;
4370
	int refclk, num_connectors = 0;
4371
	intel_clock_t clock, reduced_clock;
4372
	u32 dspcntr, pipeconf;
4373 4374
	bool ok, has_reduced_clock = false, is_sdvo = false;
	bool is_lvds = false, is_tv = false, is_dp = false;
4375
	struct intel_encoder *encoder;
4376
	const intel_limit_t *limit;
4377
	int ret;
4378

4379
	for_each_encoder_on_crtc(dev, crtc, encoder) {
4380
		switch (encoder->type) {
4381 4382 4383 4384
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		case INTEL_OUTPUT_SDVO:
4385
		case INTEL_OUTPUT_HDMI:
4386
			is_sdvo = true;
4387
			if (encoder->needs_tv_clock)
4388
				is_tv = true;
4389 4390 4391 4392
			break;
		case INTEL_OUTPUT_TVOUT:
			is_tv = true;
			break;
4393 4394 4395
		case INTEL_OUTPUT_DISPLAYPORT:
			is_dp = true;
			break;
4396
		}
4397

4398
		num_connectors++;
4399 4400
	}

4401
	refclk = i9xx_get_refclk(crtc, num_connectors);
4402

4403 4404 4405 4406 4407
	/*
	 * Returns a set of divisors for the desired target clock with the given
	 * refclk, or FALSE.  The returned values represent the clock equation:
	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
	 */
4408
	limit = intel_limit(crtc, refclk);
4409 4410
	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
			     &clock);
4411 4412
	if (!ok) {
		DRM_ERROR("Couldn't find PLL settings for mode!\n");
4413
		return -EINVAL;
4414 4415
	}

4416
	/* Ensure that the cursor is valid for the new mode before changing... */
4417
	intel_crtc_update_cursor(crtc, true);
4418

4419
	if (is_lvds && dev_priv->lvds_downclock_avail) {
4420 4421 4422 4423 4424 4425
		/*
		 * Ensure we match the reduced clock's P to the target clock.
		 * If the clocks don't match, we can't switch the display clock
		 * by using the FP0/FP1. In such case we will disable the LVDS
		 * downclock feature.
		*/
4426
		has_reduced_clock = limit->find_pll(limit, crtc,
4427 4428
						    dev_priv->lvds_downclock,
						    refclk,
4429
						    &clock,
4430
						    &reduced_clock);
4431 4432
	}

4433 4434
	if (is_sdvo && is_tv)
		i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4435

4436
	if (IS_GEN2(dev))
4437 4438 4439
		i8xx_update_pll(crtc, adjusted_mode, &clock,
				has_reduced_clock ? &reduced_clock : NULL,
				num_connectors);
4440
	else if (IS_VALLEYVIEW(dev))
4441 4442 4443
		vlv_update_pll(crtc, mode, adjusted_mode, &clock,
				has_reduced_clock ? &reduced_clock : NULL,
				num_connectors);
4444
	else
4445 4446 4447
		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
				has_reduced_clock ? &reduced_clock : NULL,
				num_connectors);
4448 4449

	/* setup pipeconf */
4450
	pipeconf = I915_READ(PIPECONF(pipe));
4451 4452 4453 4454

	/* Set up the display plane register */
	dspcntr = DISPPLANE_GAMMA_ENABLE;

4455 4456 4457 4458
	if (pipe == 0)
		dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
	else
		dspcntr |= DISPPLANE_SEL_PIPE_B;
4459

4460
	if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4461 4462 4463 4464 4465 4466
		/* Enable pixel doubling when the dot clock is > 90% of the (display)
		 * core speed.
		 *
		 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
		 * pipe == 0 check?
		 */
4467 4468
		if (mode->clock >
		    dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4469
			pipeconf |= PIPECONF_DOUBLE_WIDE;
4470
		else
4471
			pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4472 4473
	}

4474 4475 4476 4477 4478 4479 4480 4481 4482 4483
	/* default to 8bpc */
	pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
	if (is_dp) {
		if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
			pipeconf |= PIPECONF_BPP_6 |
				    PIPECONF_DITHER_EN |
				    PIPECONF_DITHER_TYPE_SP;
		}
	}

4484 4485 4486 4487 4488 4489 4490 4491
	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
		if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
			pipeconf |= PIPECONF_BPP_6 |
					PIPECONF_ENABLE |
					I965_PIPECONF_ACTIVE;
		}
	}

4492
	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4493 4494
	drm_mode_debug_printmodeline(mode);

4495 4496
	if (HAS_PIPE_CXSR(dev)) {
		if (intel_crtc->lowfreq_avail) {
4497
			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4498
			pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4499
		} else {
4500
			DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4501 4502 4503 4504
			pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
		}
	}

4505
	pipeconf &= ~PIPECONF_INTERLACE_MASK;
4506
	if (!IS_GEN2(dev) &&
4507
	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4508
		pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4509
	else
4510
		pipeconf |= PIPECONF_PROGRESSIVE;
4511

4512
	intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4513 4514 4515

	/* pipesrc and dspsize control the size that is scaled from,
	 * which should always be the user's requested size.
4516
	 */
4517 4518 4519 4520
	I915_WRITE(DSPSIZE(plane),
		   ((mode->vdisplay - 1) << 16) |
		   (mode->hdisplay - 1));
	I915_WRITE(DSPPOS(plane), 0);
4521

4522 4523
	I915_WRITE(PIPECONF(pipe), pipeconf);
	POSTING_READ(PIPECONF(pipe));
4524
	intel_enable_pipe(dev_priv, pipe, false);
4525 4526 4527 4528 4529 4530

	intel_wait_for_vblank(dev, pipe);

	I915_WRITE(DSPCNTR(plane), dspcntr);
	POSTING_READ(DSPCNTR(plane));

4531
	ret = intel_pipe_set_base(crtc, x, y, fb);
4532 4533 4534 4535 4536 4537

	intel_update_watermarks(dev);

	return ret;
}

4538 4539 4540 4541
/*
 * Initialize reference clocks when the driver loads
 */
void ironlake_init_pch_refclk(struct drm_device *dev)
4542 4543 4544 4545 4546 4547
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *encoder;
	u32 temp;
	bool has_lvds = false;
4548 4549 4550
	bool has_cpu_edp = false;
	bool has_pch_edp = false;
	bool has_panel = false;
4551 4552
	bool has_ck505 = false;
	bool can_ssc = false;
4553 4554

	/* We need to take the global config into account */
4555 4556 4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568
	list_for_each_entry(encoder, &mode_config->encoder_list,
			    base.head) {
		switch (encoder->type) {
		case INTEL_OUTPUT_LVDS:
			has_panel = true;
			has_lvds = true;
			break;
		case INTEL_OUTPUT_EDP:
			has_panel = true;
			if (intel_encoder_is_pch_edp(&encoder->base))
				has_pch_edp = true;
			else
				has_cpu_edp = true;
			break;
4569 4570 4571
		}
	}

4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582
	if (HAS_PCH_IBX(dev)) {
		has_ck505 = dev_priv->display_clock_mode;
		can_ssc = has_ck505;
	} else {
		has_ck505 = false;
		can_ssc = true;
	}

	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
		      has_panel, has_lvds, has_pch_edp, has_cpu_edp,
		      has_ck505);
4583 4584 4585 4586 4587 4588 4589 4590 4591 4592

	/* Ironlake: try to setup display ref clock before DPLL
	 * enabling. This is only under driver's control after
	 * PCH B stepping, previous chipset stepping should be
	 * ignoring this setting.
	 */
	temp = I915_READ(PCH_DREF_CONTROL);
	/* Always enable nonspread source */
	temp &= ~DREF_NONSPREAD_SOURCE_MASK;

4593 4594 4595 4596
	if (has_ck505)
		temp |= DREF_NONSPREAD_CK505_ENABLE;
	else
		temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4597

4598 4599 4600
	if (has_panel) {
		temp &= ~DREF_SSC_SOURCE_MASK;
		temp |= DREF_SSC_SOURCE_ENABLE;
4601

4602
		/* SSC must be turned on before enabling the CPU output  */
4603
		if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4604
			DRM_DEBUG_KMS("Using SSC on panel\n");
4605
			temp |= DREF_SSC1_ENABLE;
4606 4607
		} else
			temp &= ~DREF_SSC1_ENABLE;
4608 4609 4610 4611 4612 4613

		/* Get SSC going before enabling the outputs */
		I915_WRITE(PCH_DREF_CONTROL, temp);
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);

4614 4615 4616
		temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;

		/* Enable CPU source on CPU attached eDP */
4617
		if (has_cpu_edp) {
4618
			if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4619
				DRM_DEBUG_KMS("Using SSC on eDP\n");
4620
				temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4621
			}
4622 4623
			else
				temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648
		} else
			temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;

		I915_WRITE(PCH_DREF_CONTROL, temp);
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);
	} else {
		DRM_DEBUG_KMS("Disabling SSC entirely\n");

		temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;

		/* Turn off CPU output */
		temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;

		I915_WRITE(PCH_DREF_CONTROL, temp);
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);

		/* Turn off the SSC source */
		temp &= ~DREF_SSC_SOURCE_MASK;
		temp |= DREF_SSC_SOURCE_DISABLE;

		/* Turn off SSC1 */
		temp &= ~ DREF_SSC1_ENABLE;

4649 4650 4651 4652 4653 4654
		I915_WRITE(PCH_DREF_CONTROL, temp);
		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);
	}
}

4655 4656 4657 4658 4659 4660 4661 4662 4663
static int ironlake_get_refclk(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;
	struct intel_encoder *edp_encoder = NULL;
	int num_connectors = 0;
	bool is_lvds = false;

4664
	for_each_encoder_on_crtc(dev, crtc, encoder) {
4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675 4676 4677 4678 4679 4680 4681 4682 4683 4684
		switch (encoder->type) {
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		case INTEL_OUTPUT_EDP:
			edp_encoder = encoder;
			break;
		}
		num_connectors++;
	}

	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
			      dev_priv->lvds_ssc_freq);
		return dev_priv->lvds_ssc_freq * 1000;
	}

	return 120000;
}

4685 4686 4687 4688 4689 4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709 4710
static void ironlake_set_pipeconf(struct drm_crtc *crtc,
				  struct drm_display_mode *adjusted_mode,
				  bool dither)
{
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	uint32_t val;

	val = I915_READ(PIPECONF(pipe));

	val &= ~PIPE_BPC_MASK;
	switch (intel_crtc->bpp) {
	case 18:
		val |= PIPE_6BPC;
		break;
	case 24:
		val |= PIPE_8BPC;
		break;
	case 30:
		val |= PIPE_10BPC;
		break;
	case 36:
		val |= PIPE_12BPC;
		break;
	default:
4711 4712
		/* Case prevented by intel_choose_pipe_bpp_dither. */
		BUG();
4713 4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726 4727 4728
	}

	val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
	if (dither)
		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);

	val &= ~PIPECONF_INTERLACE_MASK;
	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
		val |= PIPECONF_INTERLACED_ILK;
	else
		val |= PIPECONF_PROGRESSIVE;

	I915_WRITE(PIPECONF(pipe), val);
	POSTING_READ(PIPECONF(pipe));
}

4729 4730 4731 4732 4733 4734 4735 4736 4737 4738 4739 4740 4741 4742 4743 4744 4745 4746 4747 4748 4749 4750 4751 4752 4753
static void haswell_set_pipeconf(struct drm_crtc *crtc,
				 struct drm_display_mode *adjusted_mode,
				 bool dither)
{
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	uint32_t val;

	val = I915_READ(PIPECONF(pipe));

	val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
	if (dither)
		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);

	val &= ~PIPECONF_INTERLACE_MASK_HSW;
	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
		val |= PIPECONF_INTERLACED_ILK;
	else
		val |= PIPECONF_PROGRESSIVE;

	I915_WRITE(PIPECONF(pipe), val);
	POSTING_READ(PIPECONF(pipe));
}

4754 4755 4756 4757 4758 4759 4760 4761 4762 4763 4764 4765 4766 4767 4768 4769 4770 4771 4772 4773 4774 4775 4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788 4789 4790 4791 4792 4793 4794 4795 4796 4797 4798 4799 4800 4801 4802 4803 4804 4805 4806 4807 4808 4809 4810 4811 4812 4813 4814 4815 4816
static bool ironlake_compute_clocks(struct drm_crtc *crtc,
				    struct drm_display_mode *adjusted_mode,
				    intel_clock_t *clock,
				    bool *has_reduced_clock,
				    intel_clock_t *reduced_clock)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *intel_encoder;
	int refclk;
	const intel_limit_t *limit;
	bool ret, is_sdvo = false, is_tv = false, is_lvds = false;

	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		switch (intel_encoder->type) {
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		case INTEL_OUTPUT_SDVO:
		case INTEL_OUTPUT_HDMI:
			is_sdvo = true;
			if (intel_encoder->needs_tv_clock)
				is_tv = true;
			break;
		case INTEL_OUTPUT_TVOUT:
			is_tv = true;
			break;
		}
	}

	refclk = ironlake_get_refclk(crtc);

	/*
	 * Returns a set of divisors for the desired target clock with the given
	 * refclk, or FALSE.  The returned values represent the clock equation:
	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
	 */
	limit = intel_limit(crtc, refclk);
	ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
			      clock);
	if (!ret)
		return false;

	if (is_lvds && dev_priv->lvds_downclock_avail) {
		/*
		 * Ensure we match the reduced clock's P to the target clock.
		 * If the clocks don't match, we can't switch the display clock
		 * by using the FP0/FP1. In such case we will disable the LVDS
		 * downclock feature.
		*/
		*has_reduced_clock = limit->find_pll(limit, crtc,
						     dev_priv->lvds_downclock,
						     refclk,
						     clock,
						     reduced_clock);
	}

	if (is_sdvo && is_tv)
		i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);

	return true;
}

4817 4818 4819 4820 4821 4822 4823 4824 4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848 4849 4850 4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892
static void ironlake_set_m_n(struct drm_crtc *crtc,
			     struct drm_display_mode *mode,
			     struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	enum pipe pipe = intel_crtc->pipe;
	struct intel_encoder *intel_encoder, *edp_encoder = NULL;
	struct fdi_m_n m_n = {0};
	int target_clock, pixel_multiplier, lane, link_bw;
	bool is_dp = false, is_cpu_edp = false;

	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		switch (intel_encoder->type) {
		case INTEL_OUTPUT_DISPLAYPORT:
			is_dp = true;
			break;
		case INTEL_OUTPUT_EDP:
			is_dp = true;
			if (!intel_encoder_is_pch_edp(&intel_encoder->base))
				is_cpu_edp = true;
			edp_encoder = intel_encoder;
			break;
		}
	}

	/* FDI link */
	pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
	lane = 0;
	/* CPU eDP doesn't require FDI link, so just set DP M/N
	   according to current link config */
	if (is_cpu_edp) {
		intel_edp_link_config(edp_encoder, &lane, &link_bw);
	} else {
		/* FDI is a binary signal running at ~2.7GHz, encoding
		 * each output octet as 10 bits. The actual frequency
		 * is stored as a divider into a 100MHz clock, and the
		 * mode pixel clock is stored in units of 1KHz.
		 * Hence the bw of each lane in terms of the mode signal
		 * is:
		 */
		link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
	}

	/* [e]DP over FDI requires target mode clock instead of link clock. */
	if (edp_encoder)
		target_clock = intel_edp_target_clock(edp_encoder, mode);
	else if (is_dp)
		target_clock = mode->clock;
	else
		target_clock = adjusted_mode->clock;

	if (!lane) {
		/*
		 * Account for spread spectrum to avoid
		 * oversubscribing the link. Max center spread
		 * is 2.5%; use 5% for safety's sake.
		 */
		u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
		lane = bps / (link_bw * 8) + 1;
	}

	intel_crtc->fdi_lanes = lane;

	if (pixel_multiplier > 1)
		link_bw *= pixel_multiplier;
	ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
			     &m_n);

	I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
	I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
	I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
	I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
}

4893 4894 4895
static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
				      struct drm_display_mode *adjusted_mode,
				      intel_clock_t *clock, u32 fp)
4896
{
4897
	struct drm_crtc *crtc = &intel_crtc->base;
4898 4899
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
4900 4901 4902 4903 4904
	struct intel_encoder *intel_encoder;
	uint32_t dpll;
	int factor, pixel_multiplier, num_connectors = 0;
	bool is_lvds = false, is_sdvo = false, is_tv = false;
	bool is_dp = false, is_cpu_edp = false;
4905

4906 4907
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		switch (intel_encoder->type) {
4908 4909 4910 4911
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		case INTEL_OUTPUT_SDVO:
4912
		case INTEL_OUTPUT_HDMI:
4913
			is_sdvo = true;
4914
			if (intel_encoder->needs_tv_clock)
4915
				is_tv = true;
4916 4917 4918 4919
			break;
		case INTEL_OUTPUT_TVOUT:
			is_tv = true;
			break;
4920 4921 4922
		case INTEL_OUTPUT_DISPLAYPORT:
			is_dp = true;
			break;
4923
		case INTEL_OUTPUT_EDP:
4924
			is_dp = true;
4925
			if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4926
				is_cpu_edp = true;
4927
			break;
4928
		}
4929

4930
		num_connectors++;
4931 4932
	}

4933
	/* Enable autotuning of the PLL clock (if permissible) */
4934 4935 4936 4937 4938 4939 4940 4941
	factor = 21;
	if (is_lvds) {
		if ((intel_panel_use_ssc(dev_priv) &&
		     dev_priv->lvds_ssc_freq == 100) ||
		    (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
			factor = 25;
	} else if (is_sdvo && is_tv)
		factor = 20;
4942

4943
	if (clock->m < factor * clock->n)
4944
		fp |= FP_CB_TUNE;
4945

4946
	dpll = 0;
4947

4948 4949 4950 4951 4952
	if (is_lvds)
		dpll |= DPLLB_MODE_LVDS;
	else
		dpll |= DPLLB_MODE_DAC_SERIAL;
	if (is_sdvo) {
4953
		pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4954 4955
		if (pixel_multiplier > 1) {
			dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4956
		}
4957 4958
		dpll |= DPLL_DVO_HIGH_SPEED;
	}
4959
	if (is_dp && !is_cpu_edp)
4960
		dpll |= DPLL_DVO_HIGH_SPEED;
4961

4962
	/* compute bitmask from p1 value */
4963
	dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4964
	/* also FPA1 */
4965
	dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4966

4967
	switch (clock->p2) {
4968 4969 4970 4971 4972 4973 4974 4975 4976 4977 4978 4979
	case 5:
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
		break;
	case 7:
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
		break;
	case 10:
		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
		break;
	case 14:
		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
		break;
4980 4981
	}

4982 4983 4984
	if (is_sdvo && is_tv)
		dpll |= PLL_REF_INPUT_TVCLKINBC;
	else if (is_tv)
4985
		/* XXX: just matching BIOS for now */
4986
		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
4987
		dpll |= 3;
4988
	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4989
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4990 4991 4992
	else
		dpll |= PLL_REF_INPUT_DREFCLK;

4993 4994 4995 4996 4997 4998 4999 5000 5001 5002 5003 5004 5005 5006 5007 5008 5009
	return dpll;
}

static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
				  struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode,
				  int x, int y,
				  struct drm_framebuffer *fb)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
	int num_connectors = 0;
	intel_clock_t clock, reduced_clock;
	u32 dpll, fp = 0, fp2 = 0;
5010 5011
	bool ok, has_reduced_clock = false;
	bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5012 5013 5014 5015 5016 5017 5018 5019 5020 5021 5022 5023 5024 5025 5026
	struct intel_encoder *encoder;
	u32 temp;
	int ret;
	bool dither;

	for_each_encoder_on_crtc(dev, crtc, encoder) {
		switch (encoder->type) {
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		case INTEL_OUTPUT_DISPLAYPORT:
			is_dp = true;
			break;
		case INTEL_OUTPUT_EDP:
			is_dp = true;
5027
			if (!intel_encoder_is_pch_edp(&encoder->base))
5028 5029 5030 5031 5032 5033 5034
				is_cpu_edp = true;
			break;
		}

		num_connectors++;
	}

5035 5036 5037
	WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
	     "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));

5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 5058 5059
	ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
				     &has_reduced_clock, &reduced_clock);
	if (!ok) {
		DRM_ERROR("Couldn't find PLL settings for mode!\n");
		return -EINVAL;
	}

	/* Ensure that the cursor is valid for the new mode before changing... */
	intel_crtc_update_cursor(crtc, true);

	/* determine panel color depth */
	dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
	if (is_lvds && dev_priv->lvds_dither)
		dither = true;

	fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
	if (has_reduced_clock)
		fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
			reduced_clock.m2;

	dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);

5060
	DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5061 5062
	drm_mode_debug_printmodeline(mode);

5063 5064
	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
	if (!is_cpu_edp) {
5065
		struct intel_pch_pll *pll;
5066

5067 5068 5069 5070
		pll = intel_get_pch_pll(intel_crtc, dpll, fp);
		if (pll == NULL) {
			DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
					 pipe);
5071 5072
			return -EINVAL;
		}
5073 5074
	} else
		intel_put_pch_pll(intel_crtc);
5075 5076 5077 5078 5079 5080

	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
	 * This is an exception to the general rule that mode_set doesn't turn
	 * things on.
	 */
	if (is_lvds) {
5081
		temp = I915_READ(PCH_LVDS);
5082
		temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5083 5084
		if (HAS_PCH_CPT(dev)) {
			temp &= ~PORT_TRANS_SEL_MASK;
5085
			temp |= PORT_TRANS_SEL_CPT(pipe);
5086 5087 5088 5089 5090 5091
		} else {
			if (pipe == 1)
				temp |= LVDS_PIPEB_SELECT;
			else
				temp &= ~LVDS_PIPEB_SELECT;
		}
5092

5093
		/* set the corresponsding LVDS_BORDER bit */
5094
		temp |= dev_priv->lvds_border_bits;
5095 5096 5097 5098
		/* Set the B0-B3 data pairs corresponding to whether we're going to
		 * set the DPLLs for dual-channel mode or not.
		 */
		if (clock.p2 == 7)
5099
			temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5100
		else
5101
			temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5102 5103 5104 5105 5106

		/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
		 * appropriately here, but we need to look more thoroughly into how
		 * panels behave in the two modes.
		 */
5107
		temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5108
		if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5109
			temp |= LVDS_HSYNC_POLARITY;
5110
		if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5111
			temp |= LVDS_VSYNC_POLARITY;
5112
		I915_WRITE(PCH_LVDS, temp);
5113
	}
5114

5115
	if (is_dp && !is_cpu_edp) {
5116
		intel_dp_set_m_n(crtc, mode, adjusted_mode);
5117
	} else {
5118
		/* For non-DP output, clear any trans DP clock recovery setting.*/
5119 5120 5121 5122
		I915_WRITE(TRANSDATA_M1(pipe), 0);
		I915_WRITE(TRANSDATA_N1(pipe), 0);
		I915_WRITE(TRANSDPLINK_M1(pipe), 0);
		I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5123
	}
5124

5125 5126
	if (intel_crtc->pch_pll) {
		I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5127

5128
		/* Wait for the clocks to stabilize. */
5129
		POSTING_READ(intel_crtc->pch_pll->pll_reg);
5130 5131
		udelay(150);

5132 5133 5134 5135 5136
		/* The pixel multiplier can only be updated once the
		 * DPLL is enabled and the clocks are stable.
		 *
		 * So write it again.
		 */
5137
		I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5138 5139
	}

5140
	intel_crtc->lowfreq_avail = false;
5141
	if (intel_crtc->pch_pll) {
5142
		if (is_lvds && has_reduced_clock && i915_powersave) {
5143
			I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5144 5145
			intel_crtc->lowfreq_avail = true;
		} else {
5146
			I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5147 5148 5149
		}
	}

5150
	intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5151

5152
	ironlake_set_m_n(crtc, mode, adjusted_mode);
5153

5154
	if (is_cpu_edp)
5155
		ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5156

5157
	ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5158

5159
	intel_wait_for_vblank(dev, pipe);
5160

5161 5162
	/* Set up the display plane register */
	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5163
	POSTING_READ(DSPCNTR(plane));
5164

5165
	ret = intel_pipe_set_base(crtc, x, y, fb);
5166 5167 5168

	intel_update_watermarks(dev);

5169 5170
	intel_update_linetime_watermarks(dev, pipe, adjusted_mode);

5171
	return ret;
5172 5173
}

5174 5175 5176 5177 5178 5179 5180 5181 5182 5183 5184 5185 5186
static int haswell_crtc_mode_set(struct drm_crtc *crtc,
				 struct drm_display_mode *mode,
				 struct drm_display_mode *adjusted_mode,
				 int x, int y,
				 struct drm_framebuffer *fb)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
	int num_connectors = 0;
	intel_clock_t clock, reduced_clock;
5187
	u32 dpll = 0, fp = 0, fp2 = 0;
5188 5189 5190 5191 5192 5193 5194 5195 5196 5197 5198 5199 5200 5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212
	bool ok, has_reduced_clock = false;
	bool is_lvds = false, is_dp = false, is_cpu_edp = false;
	struct intel_encoder *encoder;
	u32 temp;
	int ret;
	bool dither;

	for_each_encoder_on_crtc(dev, crtc, encoder) {
		switch (encoder->type) {
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		case INTEL_OUTPUT_DISPLAYPORT:
			is_dp = true;
			break;
		case INTEL_OUTPUT_EDP:
			is_dp = true;
			if (!intel_encoder_is_pch_edp(&encoder->base))
				is_cpu_edp = true;
			break;
		}

		num_connectors++;
	}

5213 5214 5215 5216 5217 5218 5219
	/* We are not sure yet this won't happen. */
	WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
	     INTEL_PCH_TYPE(dev));

	WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
	     num_connectors, pipe_name(pipe));

5220 5221 5222 5223 5224
	WARN_ON(I915_READ(PIPECONF(pipe)) &
		(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));

	WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);

5225 5226 5227
	if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
		return -EINVAL;

5228 5229 5230 5231 5232 5233 5234 5235
	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
		ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
					     &has_reduced_clock,
					     &reduced_clock);
		if (!ok) {
			DRM_ERROR("Couldn't find PLL settings for mode!\n");
			return -EINVAL;
		}
5236 5237 5238 5239 5240 5241 5242 5243 5244 5245 5246 5247 5248
	}

	/* Ensure that the cursor is valid for the new mode before changing... */
	intel_crtc_update_cursor(crtc, true);

	/* determine panel color depth */
	dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
	if (is_lvds && dev_priv->lvds_dither)
		dither = true;

	DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
	drm_mode_debug_printmodeline(mode);

5249 5250 5251 5252 5253 5254 5255 5256 5257 5258 5259 5260 5261 5262 5263 5264 5265 5266 5267 5268 5269 5270
	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
		fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
		if (has_reduced_clock)
			fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
			      reduced_clock.m2;

		dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
					     fp);

		/* CPU eDP is the only output that doesn't need a PCH PLL of its
		 * own on pre-Haswell/LPT generation */
		if (!is_cpu_edp) {
			struct intel_pch_pll *pll;

			pll = intel_get_pch_pll(intel_crtc, dpll, fp);
			if (pll == NULL) {
				DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
						 pipe);
				return -EINVAL;
			}
		} else
			intel_put_pch_pll(intel_crtc);
5271

5272 5273 5274 5275 5276 5277 5278 5279 5280 5281 5282 5283 5284 5285 5286 5287
		/* The LVDS pin pair needs to be on before the DPLLs are
		 * enabled.  This is an exception to the general rule that
		 * mode_set doesn't turn things on.
		 */
		if (is_lvds) {
			temp = I915_READ(PCH_LVDS);
			temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
			if (HAS_PCH_CPT(dev)) {
				temp &= ~PORT_TRANS_SEL_MASK;
				temp |= PORT_TRANS_SEL_CPT(pipe);
			} else {
				if (pipe == 1)
					temp |= LVDS_PIPEB_SELECT;
				else
					temp &= ~LVDS_PIPEB_SELECT;
			}
5288

5289 5290 5291 5292 5293 5294 5295 5296
			/* set the corresponsding LVDS_BORDER bit */
			temp |= dev_priv->lvds_border_bits;
			/* Set the B0-B3 data pairs corresponding to whether
			 * we're going to set the DPLLs for dual-channel mode or
			 * not.
			 */
			if (clock.p2 == 7)
				temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5297
			else
5298 5299 5300 5301 5302 5303 5304 5305 5306 5307 5308 5309 5310 5311
				temp &= ~(LVDS_B0B3_POWER_UP |
					  LVDS_CLKB_POWER_UP);

			/* It would be nice to set 24 vs 18-bit mode
			 * (LVDS_A3_POWER_UP) appropriately here, but we need to
			 * look more thoroughly into how panels behave in the
			 * two modes.
			 */
			temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
			if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
				temp |= LVDS_HSYNC_POLARITY;
			if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
				temp |= LVDS_VSYNC_POLARITY;
			I915_WRITE(PCH_LVDS, temp);
5312 5313 5314 5315 5316 5317
		}
	}

	if (is_dp && !is_cpu_edp) {
		intel_dp_set_m_n(crtc, mode, adjusted_mode);
	} else {
5318 5319 5320 5321 5322 5323 5324 5325
		if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
			/* For non-DP output, clear any trans DP clock recovery
			 * setting.*/
			I915_WRITE(TRANSDATA_M1(pipe), 0);
			I915_WRITE(TRANSDATA_N1(pipe), 0);
			I915_WRITE(TRANSDPLINK_M1(pipe), 0);
			I915_WRITE(TRANSDPLINK_N1(pipe), 0);
		}
5326 5327 5328
	}

	intel_crtc->lowfreq_avail = false;
5329 5330 5331 5332 5333 5334 5335 5336 5337 5338 5339 5340 5341 5342 5343 5344 5345 5346 5347 5348 5349 5350 5351
	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
		if (intel_crtc->pch_pll) {
			I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);

			/* Wait for the clocks to stabilize. */
			POSTING_READ(intel_crtc->pch_pll->pll_reg);
			udelay(150);

			/* The pixel multiplier can only be updated once the
			 * DPLL is enabled and the clocks are stable.
			 *
			 * So write it again.
			 */
			I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
		}

		if (intel_crtc->pch_pll) {
			if (is_lvds && has_reduced_clock && i915_powersave) {
				I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
				intel_crtc->lowfreq_avail = true;
			} else {
				I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
			}
5352 5353 5354 5355 5356 5357 5358
		}
	}

	intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);

	ironlake_set_m_n(crtc, mode, adjusted_mode);

5359 5360 5361
	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
		if (is_cpu_edp)
			ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5362

5363
	haswell_set_pipeconf(crtc, adjusted_mode, dither);
5364 5365 5366 5367 5368 5369 5370 5371 5372 5373 5374 5375 5376 5377

	/* Set up the display plane register */
	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
	POSTING_READ(DSPCNTR(plane));

	ret = intel_pipe_set_base(crtc, x, y, fb);

	intel_update_watermarks(dev);

	intel_update_linetime_watermarks(dev, pipe, adjusted_mode);

	return ret;
}

5378 5379 5380 5381
static int intel_crtc_mode_set(struct drm_crtc *crtc,
			       struct drm_display_mode *mode,
			       struct drm_display_mode *adjusted_mode,
			       int x, int y,
5382
			       struct drm_framebuffer *fb)
5383 5384 5385
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
5386 5387
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
5388 5389
	int ret;

5390
	drm_vblank_pre_modeset(dev, pipe);
5391

5392
	ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5393
					      x, y, fb);
5394
	drm_vblank_post_modeset(dev, pipe);
5395

5396
	return ret;
5397 5398
}

5399 5400 5401 5402 5403 5404 5405 5406 5407 5408 5409 5410 5411 5412 5413 5414 5415 5416 5417 5418 5419 5420 5421 5422 5423 5424 5425 5426 5427
static bool intel_eld_uptodate(struct drm_connector *connector,
			       int reg_eldv, uint32_t bits_eldv,
			       int reg_elda, uint32_t bits_elda,
			       int reg_edid)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t i;

	i = I915_READ(reg_eldv);
	i &= bits_eldv;

	if (!eld[0])
		return !i;

	if (!i)
		return false;

	i = I915_READ(reg_elda);
	i &= ~bits_elda;
	I915_WRITE(reg_elda, i);

	for (i = 0; i < eld[2]; i++)
		if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
			return false;

	return true;
}

5428 5429 5430 5431 5432 5433 5434 5435 5436 5437 5438 5439 5440 5441 5442 5443
static void g4x_write_eld(struct drm_connector *connector,
			  struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t eldv;
	uint32_t len;
	uint32_t i;

	i = I915_READ(G4X_AUD_VID_DID);

	if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
		eldv = G4X_ELDV_DEVCL_DEVBLC;
	else
		eldv = G4X_ELDV_DEVCTG;

5444 5445 5446 5447 5448 5449
	if (intel_eld_uptodate(connector,
			       G4X_AUD_CNTL_ST, eldv,
			       G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
			       G4X_HDMIW_HDMIEDID))
		return;

5450 5451 5452 5453 5454 5455 5456 5457 5458 5459 5460 5461 5462 5463 5464 5465 5466 5467
	i = I915_READ(G4X_AUD_CNTL_ST);
	i &= ~(eldv | G4X_ELD_ADDR);
	len = (i >> 9) & 0x1f;		/* ELD buffer size */
	I915_WRITE(G4X_AUD_CNTL_ST, i);

	if (!eld[0])
		return;

	len = min_t(uint8_t, eld[2], len);
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	for (i = 0; i < len; i++)
		I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));

	i = I915_READ(G4X_AUD_CNTL_ST);
	i |= eldv;
	I915_WRITE(G4X_AUD_CNTL_ST, i);
}

5468 5469 5470 5471 5472 5473 5474 5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488 5489 5490 5491 5492 5493 5494 5495 5496 5497 5498 5499 5500 5501 5502 5503 5504 5505 5506 5507 5508 5509 5510 5511 5512 5513 5514 5515 5516 5517 5518 5519 5520 5521 5522 5523 5524 5525 5526 5527 5528 5529 5530 5531 5532 5533 5534 5535 5536 5537 5538 5539 5540 5541 5542 5543 5544 5545 5546 5547 5548 5549 5550 5551 5552
static void haswell_write_eld(struct drm_connector *connector,
				     struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	struct drm_device *dev = crtc->dev;
	uint32_t eldv;
	uint32_t i;
	int len;
	int pipe = to_intel_crtc(crtc)->pipe;
	int tmp;

	int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
	int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
	int aud_config = HSW_AUD_CFG(pipe);
	int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;


	DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");

	/* Audio output enable */
	DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
	tmp = I915_READ(aud_cntrl_st2);
	tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
	I915_WRITE(aud_cntrl_st2, tmp);

	/* Wait for 1 vertical blank */
	intel_wait_for_vblank(dev, pipe);

	/* Set ELD valid state */
	tmp = I915_READ(aud_cntrl_st2);
	DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
	tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
	I915_WRITE(aud_cntrl_st2, tmp);
	tmp = I915_READ(aud_cntrl_st2);
	DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);

	/* Enable HDMI mode */
	tmp = I915_READ(aud_config);
	DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
	/* clear N_programing_enable and N_value_index */
	tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
	I915_WRITE(aud_config, tmp);

	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));

	eldv = AUDIO_ELD_VALID_A << (pipe * 4);

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		eld[5] |= (1 << 2);	/* Conn_Type, 0x1 = DisplayPort */
		I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
	} else
		I915_WRITE(aud_config, 0);

	if (intel_eld_uptodate(connector,
			       aud_cntrl_st2, eldv,
			       aud_cntl_st, IBX_ELD_ADDRESS,
			       hdmiw_hdmiedid))
		return;

	i = I915_READ(aud_cntrl_st2);
	i &= ~eldv;
	I915_WRITE(aud_cntrl_st2, i);

	if (!eld[0])
		return;

	i = I915_READ(aud_cntl_st);
	i &= ~IBX_ELD_ADDRESS;
	I915_WRITE(aud_cntl_st, i);
	i = (i >> 29) & DIP_PORT_SEL_MASK;		/* DIP_Port_Select, 0x1 = PortB */
	DRM_DEBUG_DRIVER("port num:%d\n", i);

	len = min_t(uint8_t, eld[2], 21);	/* 84 bytes of hw ELD buffer */
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	for (i = 0; i < len; i++)
		I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));

	i = I915_READ(aud_cntrl_st2);
	i |= eldv;
	I915_WRITE(aud_cntrl_st2, i);

}

5553 5554 5555 5556 5557 5558 5559 5560 5561
static void ironlake_write_eld(struct drm_connector *connector,
				     struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	uint8_t *eld = connector->eld;
	uint32_t eldv;
	uint32_t i;
	int len;
	int hdmiw_hdmiedid;
5562
	int aud_config;
5563 5564
	int aud_cntl_st;
	int aud_cntrl_st2;
5565
	int pipe = to_intel_crtc(crtc)->pipe;
5566

5567
	if (HAS_PCH_IBX(connector->dev)) {
5568 5569 5570
		hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
		aud_config = IBX_AUD_CFG(pipe);
		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5571
		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5572
	} else {
5573 5574 5575
		hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
		aud_config = CPT_AUD_CFG(pipe);
		aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5576
		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5577 5578
	}

5579
	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5580 5581

	i = I915_READ(aud_cntl_st);
5582
	i = (i >> 29) & DIP_PORT_SEL_MASK;		/* DIP_Port_Select, 0x1 = PortB */
5583 5584 5585
	if (!i) {
		DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
		/* operate blindly on all ports */
5586 5587 5588
		eldv = IBX_ELD_VALIDB;
		eldv |= IBX_ELD_VALIDB << 4;
		eldv |= IBX_ELD_VALIDB << 8;
5589 5590
	} else {
		DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5591
		eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5592 5593
	}

5594 5595 5596
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
		eld[5] |= (1 << 2);	/* Conn_Type, 0x1 = DisplayPort */
5597 5598 5599
		I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
	} else
		I915_WRITE(aud_config, 0);
5600

5601 5602 5603 5604 5605 5606
	if (intel_eld_uptodate(connector,
			       aud_cntrl_st2, eldv,
			       aud_cntl_st, IBX_ELD_ADDRESS,
			       hdmiw_hdmiedid))
		return;

5607 5608 5609 5610 5611 5612 5613 5614
	i = I915_READ(aud_cntrl_st2);
	i &= ~eldv;
	I915_WRITE(aud_cntrl_st2, i);

	if (!eld[0])
		return;

	i = I915_READ(aud_cntl_st);
5615
	i &= ~IBX_ELD_ADDRESS;
5616 5617 5618 5619 5620 5621 5622 5623 5624 5625 5626 5627 5628 5629 5630 5631 5632 5633 5634 5635 5636 5637 5638 5639 5640 5641 5642 5643 5644 5645 5646 5647 5648 5649 5650 5651
	I915_WRITE(aud_cntl_st, i);

	len = min_t(uint8_t, eld[2], 21);	/* 84 bytes of hw ELD buffer */
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	for (i = 0; i < len; i++)
		I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));

	i = I915_READ(aud_cntrl_st2);
	i |= eldv;
	I915_WRITE(aud_cntrl_st2, i);
}

void intel_write_eld(struct drm_encoder *encoder,
		     struct drm_display_mode *mode)
{
	struct drm_crtc *crtc = encoder->crtc;
	struct drm_connector *connector;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	connector = drm_select_eld(encoder, mode);
	if (!connector)
		return;

	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
			 connector->base.id,
			 drm_get_connector_name(connector),
			 connector->encoder->base.id,
			 drm_get_encoder_name(connector->encoder));

	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;

	if (dev_priv->display.write_eld)
		dev_priv->display.write_eld(connector, crtc);
}

5652 5653 5654 5655 5656 5657
/** Loads the palette/gamma unit for the CRTC with the prepared values */
void intel_crtc_load_lut(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5658
	int palreg = PALETTE(intel_crtc->pipe);
5659 5660 5661
	int i;

	/* The clocks have to be on to load the palette. */
5662
	if (!crtc->enabled || !intel_crtc->active)
5663 5664
		return;

5665
	/* use legacy palette for Ironlake */
5666
	if (HAS_PCH_SPLIT(dev))
5667
		palreg = LGC_PALETTE(intel_crtc->pipe);
5668

5669 5670 5671 5672 5673 5674 5675 5676
	for (i = 0; i < 256; i++) {
		I915_WRITE(palreg + 4 * i,
			   (intel_crtc->lut_r[i] << 16) |
			   (intel_crtc->lut_g[i] << 8) |
			   intel_crtc->lut_b[i]);
	}
}

5677 5678 5679 5680 5681 5682 5683 5684 5685 5686 5687
static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	bool visible = base != 0;
	u32 cntl;

	if (intel_crtc->cursor_visible == visible)
		return;

5688
	cntl = I915_READ(_CURACNTR);
5689 5690 5691 5692
	if (visible) {
		/* On these chipsets we can only modify the base whilst
		 * the cursor is disabled.
		 */
5693
		I915_WRITE(_CURABASE, base);
5694 5695 5696 5697 5698 5699 5700 5701

		cntl &= ~(CURSOR_FORMAT_MASK);
		/* XXX width must be 64, stride 256 => 0x00 << 28 */
		cntl |= CURSOR_ENABLE |
			CURSOR_GAMMA_ENABLE |
			CURSOR_FORMAT_ARGB;
	} else
		cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5702
	I915_WRITE(_CURACNTR, cntl);
5703 5704 5705 5706 5707 5708 5709 5710 5711 5712 5713 5714 5715

	intel_crtc->cursor_visible = visible;
}

static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	bool visible = base != 0;

	if (intel_crtc->cursor_visible != visible) {
5716
		uint32_t cntl = I915_READ(CURCNTR(pipe));
5717 5718 5719 5720 5721 5722 5723 5724
		if (base) {
			cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
			cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
			cntl |= pipe << 28; /* Connect to correct pipe */
		} else {
			cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
			cntl |= CURSOR_MODE_DISABLE;
		}
5725
		I915_WRITE(CURCNTR(pipe), cntl);
5726 5727 5728 5729

		intel_crtc->cursor_visible = visible;
	}
	/* and commit changes on next vblank */
5730
	I915_WRITE(CURBASE(pipe), base);
5731 5732
}

5733 5734 5735 5736 5737 5738 5739 5740 5741 5742 5743 5744 5745 5746 5747 5748 5749 5750 5751 5752 5753 5754 5755 5756 5757
static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	bool visible = base != 0;

	if (intel_crtc->cursor_visible != visible) {
		uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
		if (base) {
			cntl &= ~CURSOR_MODE;
			cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
		} else {
			cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
			cntl |= CURSOR_MODE_DISABLE;
		}
		I915_WRITE(CURCNTR_IVB(pipe), cntl);

		intel_crtc->cursor_visible = visible;
	}
	/* and commit changes on next vblank */
	I915_WRITE(CURBASE_IVB(pipe), base);
}

5758
/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5759 5760
static void intel_crtc_update_cursor(struct drm_crtc *crtc,
				     bool on)
5761 5762 5763 5764 5765 5766 5767
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int x = intel_crtc->cursor_x;
	int y = intel_crtc->cursor_y;
5768
	u32 base, pos;
5769 5770 5771 5772
	bool visible;

	pos = 0;

5773
	if (on && crtc->enabled && crtc->fb) {
5774 5775 5776 5777 5778 5779 5780 5781 5782 5783 5784 5785 5786 5787 5788 5789 5790 5791 5792 5793 5794 5795 5796 5797 5798 5799 5800 5801
		base = intel_crtc->cursor_addr;
		if (x > (int) crtc->fb->width)
			base = 0;

		if (y > (int) crtc->fb->height)
			base = 0;
	} else
		base = 0;

	if (x < 0) {
		if (x + intel_crtc->cursor_width < 0)
			base = 0;

		pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
		x = -x;
	}
	pos |= x << CURSOR_X_SHIFT;

	if (y < 0) {
		if (y + intel_crtc->cursor_height < 0)
			base = 0;

		pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
		y = -y;
	}
	pos |= y << CURSOR_Y_SHIFT;

	visible = base != 0;
5802
	if (!visible && !intel_crtc->cursor_visible)
5803 5804
		return;

5805
	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5806 5807 5808 5809 5810 5811 5812 5813 5814
		I915_WRITE(CURPOS_IVB(pipe), pos);
		ivb_update_cursor(crtc, base);
	} else {
		I915_WRITE(CURPOS(pipe), pos);
		if (IS_845G(dev) || IS_I865G(dev))
			i845_update_cursor(crtc, base);
		else
			i9xx_update_cursor(crtc, base);
	}
5815 5816
}

5817
static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5818
				 struct drm_file *file,
5819 5820 5821 5822 5823 5824
				 uint32_t handle,
				 uint32_t width, uint32_t height)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5825
	struct drm_i915_gem_object *obj;
5826
	uint32_t addr;
5827
	int ret;
5828 5829 5830

	/* if we want to turn off the cursor ignore width and height */
	if (!handle) {
5831
		DRM_DEBUG_KMS("cursor off\n");
5832
		addr = 0;
5833
		obj = NULL;
5834
		mutex_lock(&dev->struct_mutex);
5835
		goto finish;
5836 5837 5838 5839 5840 5841 5842 5843
	}

	/* Currently we only support 64x64 cursors */
	if (width != 64 || height != 64) {
		DRM_ERROR("we currently only support 64x64 cursors\n");
		return -EINVAL;
	}

5844
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5845
	if (&obj->base == NULL)
5846 5847
		return -ENOENT;

5848
	if (obj->base.size < width * height * 4) {
5849
		DRM_ERROR("buffer is to small\n");
5850 5851
		ret = -ENOMEM;
		goto fail;
5852 5853
	}

5854
	/* we only need to pin inside GTT if cursor is non-phy */
5855
	mutex_lock(&dev->struct_mutex);
5856
	if (!dev_priv->info->cursor_needs_physical) {
5857 5858 5859 5860 5861 5862
		if (obj->tiling_mode) {
			DRM_ERROR("cursor cannot be tiled\n");
			ret = -EINVAL;
			goto fail_locked;
		}

5863
		ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5864 5865
		if (ret) {
			DRM_ERROR("failed to move cursor bo into the GTT\n");
5866
			goto fail_locked;
5867 5868
		}

5869 5870
		ret = i915_gem_object_put_fence(obj);
		if (ret) {
5871
			DRM_ERROR("failed to release fence for cursor");
5872 5873 5874
			goto fail_unpin;
		}

5875
		addr = obj->gtt_offset;
5876
	} else {
5877
		int align = IS_I830(dev) ? 16 * 1024 : 256;
5878
		ret = i915_gem_attach_phys_object(dev, obj,
5879 5880
						  (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
						  align);
5881 5882
		if (ret) {
			DRM_ERROR("failed to attach phys object\n");
5883
			goto fail_locked;
5884
		}
5885
		addr = obj->phys_obj->handle->busaddr;
5886 5887
	}

5888
	if (IS_GEN2(dev))
5889 5890
		I915_WRITE(CURSIZE, (height << 12) | width);

5891 5892
 finish:
	if (intel_crtc->cursor_bo) {
5893
		if (dev_priv->info->cursor_needs_physical) {
5894
			if (intel_crtc->cursor_bo != obj)
5895 5896 5897
				i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
		} else
			i915_gem_object_unpin(intel_crtc->cursor_bo);
5898
		drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5899
	}
5900

5901
	mutex_unlock(&dev->struct_mutex);
5902 5903

	intel_crtc->cursor_addr = addr;
5904
	intel_crtc->cursor_bo = obj;
5905 5906 5907
	intel_crtc->cursor_width = width;
	intel_crtc->cursor_height = height;

5908
	intel_crtc_update_cursor(crtc, true);
5909

5910
	return 0;
5911
fail_unpin:
5912
	i915_gem_object_unpin(obj);
5913
fail_locked:
5914
	mutex_unlock(&dev->struct_mutex);
5915
fail:
5916
	drm_gem_object_unreference_unlocked(&obj->base);
5917
	return ret;
5918 5919 5920 5921 5922 5923
}

static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

5924 5925
	intel_crtc->cursor_x = x;
	intel_crtc->cursor_y = y;
5926

5927
	intel_crtc_update_cursor(crtc, true);
5928 5929 5930 5931 5932 5933 5934 5935 5936 5937 5938 5939 5940 5941 5942

	return 0;
}

/** Sets the color ramps on behalf of RandR */
void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
				 u16 blue, int regno)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	intel_crtc->lut_r[regno] = red >> 8;
	intel_crtc->lut_g[regno] = green >> 8;
	intel_crtc->lut_b[regno] = blue >> 8;
}

5943 5944 5945 5946 5947 5948 5949 5950 5951 5952
void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
			     u16 *blue, int regno)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	*red = intel_crtc->lut_r[regno] << 8;
	*green = intel_crtc->lut_g[regno] << 8;
	*blue = intel_crtc->lut_b[regno] << 8;
}

5953
static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
J
James Simmons 已提交
5954
				 u16 *blue, uint32_t start, uint32_t size)
5955
{
J
James Simmons 已提交
5956
	int end = (start + size > 256) ? 256 : start + size, i;
5957 5958
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

J
James Simmons 已提交
5959
	for (i = start; i < end; i++) {
5960 5961 5962 5963 5964 5965 5966 5967 5968 5969 5970 5971 5972
		intel_crtc->lut_r[i] = red[i] >> 8;
		intel_crtc->lut_g[i] = green[i] >> 8;
		intel_crtc->lut_b[i] = blue[i] >> 8;
	}

	intel_crtc_load_lut(crtc);
}

/**
 * Get a pipe with a simple mode set on it for doing load-based monitor
 * detection.
 *
 * It will be up to the load-detect code to adjust the pipe as appropriate for
5973
 * its requirements.  The pipe will be connected to no other encoders.
5974
 *
5975
 * Currently this code will only succeed if there is a pipe with no encoders
5976 5977 5978 5979 5980 5981 5982 5983 5984 5985 5986 5987
 * configured for it.  In the future, it could choose to temporarily disable
 * some outputs to free up a pipe for its use.
 *
 * \return crtc, or NULL if no pipes are available.
 */

/* VESA 640x480x72Hz mode to set on the pipe */
static struct drm_display_mode load_detect_mode = {
	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
		 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
};

5988 5989
static struct drm_framebuffer *
intel_framebuffer_create(struct drm_device *dev,
5990
			 struct drm_mode_fb_cmd2 *mode_cmd,
5991 5992 5993 5994 5995 5996 5997 5998 5999 6000 6001 6002 6003 6004 6005 6006 6007 6008 6009 6010 6011 6012 6013 6014 6015 6016 6017 6018 6019 6020 6021 6022 6023 6024 6025 6026 6027 6028 6029 6030 6031
			 struct drm_i915_gem_object *obj)
{
	struct intel_framebuffer *intel_fb;
	int ret;

	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
	if (!intel_fb) {
		drm_gem_object_unreference_unlocked(&obj->base);
		return ERR_PTR(-ENOMEM);
	}

	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
	if (ret) {
		drm_gem_object_unreference_unlocked(&obj->base);
		kfree(intel_fb);
		return ERR_PTR(ret);
	}

	return &intel_fb->base;
}

static u32
intel_framebuffer_pitch_for_width(int width, int bpp)
{
	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
	return ALIGN(pitch, 64);
}

static u32
intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
{
	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
	return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
}

static struct drm_framebuffer *
intel_framebuffer_create_for_mode(struct drm_device *dev,
				  struct drm_display_mode *mode,
				  int depth, int bpp)
{
	struct drm_i915_gem_object *obj;
6032
	struct drm_mode_fb_cmd2 mode_cmd;
6033 6034 6035 6036 6037 6038 6039 6040

	obj = i915_gem_alloc_object(dev,
				    intel_framebuffer_size_for_mode(mode, bpp));
	if (obj == NULL)
		return ERR_PTR(-ENOMEM);

	mode_cmd.width = mode->hdisplay;
	mode_cmd.height = mode->vdisplay;
6041 6042
	mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
								bpp);
6043
	mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6044 6045 6046 6047 6048 6049 6050 6051 6052 6053 6054 6055 6056 6057 6058 6059 6060 6061 6062 6063

	return intel_framebuffer_create(dev, &mode_cmd, obj);
}

static struct drm_framebuffer *
mode_fits_in_fbdev(struct drm_device *dev,
		   struct drm_display_mode *mode)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
	struct drm_framebuffer *fb;

	if (dev_priv->fbdev == NULL)
		return NULL;

	obj = dev_priv->fbdev->ifb.obj;
	if (obj == NULL)
		return NULL;

	fb = &dev_priv->fbdev->ifb.base;
6064 6065
	if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
							       fb->bits_per_pixel))
6066 6067
		return NULL;

6068
	if (obj->base.size < mode->vdisplay * fb->pitches[0])
6069 6070 6071 6072 6073
		return NULL;

	return fb;
}

6074
bool intel_get_load_detect_pipe(struct drm_connector *connector,
6075
				struct drm_display_mode *mode,
6076
				struct intel_load_detect_pipe *old)
6077 6078
{
	struct intel_crtc *intel_crtc;
6079 6080
	struct intel_encoder *intel_encoder =
		intel_attached_encoder(connector);
6081
	struct drm_crtc *possible_crtc;
6082
	struct drm_encoder *encoder = &intel_encoder->base;
6083 6084
	struct drm_crtc *crtc = NULL;
	struct drm_device *dev = encoder->dev;
6085
	struct drm_framebuffer *fb;
6086 6087
	int i = -1;

6088 6089 6090 6091
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		      connector->base.id, drm_get_connector_name(connector),
		      encoder->base.id, drm_get_encoder_name(encoder));

6092 6093
	/*
	 * Algorithm gets a little messy:
6094
	 *
6095 6096
	 *   - if the connector already has an assigned crtc, use it (but make
	 *     sure it's on first)
6097
	 *
6098 6099 6100 6101 6102 6103 6104
	 *   - try to find the first unused crtc that can drive this connector,
	 *     and use that if we find one
	 */

	/* See if we already have a CRTC for this connector */
	if (encoder->crtc) {
		crtc = encoder->crtc;
6105

6106
		old->dpms_mode = connector->dpms;
6107 6108 6109
		old->load_detect_temp = false;

		/* Make sure the crtc and connector are running */
6110 6111
		if (connector->dpms != DRM_MODE_DPMS_ON)
			connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6112

6113
		return true;
6114 6115 6116 6117 6118 6119 6120 6121 6122 6123 6124 6125 6126 6127 6128 6129 6130
	}

	/* Find an unused one (if possible) */
	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
		i++;
		if (!(encoder->possible_crtcs & (1 << i)))
			continue;
		if (!possible_crtc->enabled) {
			crtc = possible_crtc;
			break;
		}
	}

	/*
	 * If we didn't find an unused CRTC, don't use any.
	 */
	if (!crtc) {
6131 6132
		DRM_DEBUG_KMS("no pipe available for load-detect\n");
		return false;
6133 6134
	}

6135 6136
	intel_encoder->new_crtc = to_intel_crtc(crtc);
	to_intel_connector(connector)->new_encoder = intel_encoder;
6137 6138

	intel_crtc = to_intel_crtc(crtc);
6139
	old->dpms_mode = connector->dpms;
6140
	old->load_detect_temp = true;
6141
	old->release_fb = NULL;
6142

6143 6144
	if (!mode)
		mode = &load_detect_mode;
6145

6146 6147 6148 6149 6150 6151 6152
	/* We need a framebuffer large enough to accommodate all accesses
	 * that the plane may generate whilst we perform load detection.
	 * We can not rely on the fbcon either being present (we get called
	 * during its initialisation to detect all boot displays, or it may
	 * not even exist) or that it is large enough to satisfy the
	 * requested mode.
	 */
6153 6154
	fb = mode_fits_in_fbdev(dev, mode);
	if (fb == NULL) {
6155
		DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6156 6157
		fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
		old->release_fb = fb;
6158 6159
	} else
		DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6160
	if (IS_ERR(fb)) {
6161
		DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6162
		goto fail;
6163 6164
	}

6165
	if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6166
		DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6167 6168
		if (old->release_fb)
			old->release_fb->funcs->destroy(old->release_fb);
6169
		goto fail;
6170
	}
6171

6172
	/* let the connector get through one full cycle before testing */
6173
	intel_wait_for_vblank(dev, intel_crtc->pipe);
6174

6175
	return true;
6176 6177 6178 6179
fail:
	connector->encoder = NULL;
	encoder->crtc = NULL;
	return false;
6180 6181
}

6182
void intel_release_load_detect_pipe(struct drm_connector *connector,
6183
				    struct intel_load_detect_pipe *old)
6184
{
6185 6186
	struct intel_encoder *intel_encoder =
		intel_attached_encoder(connector);
6187
	struct drm_encoder *encoder = &intel_encoder->base;
6188

6189 6190 6191 6192
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
		      connector->base.id, drm_get_connector_name(connector),
		      encoder->base.id, drm_get_encoder_name(encoder));

6193
	if (old->load_detect_temp) {
6194 6195 6196 6197 6198
		struct drm_crtc *crtc = encoder->crtc;

		to_intel_connector(connector)->new_encoder = NULL;
		intel_encoder->new_crtc = NULL;
		intel_set_mode(crtc, NULL, 0, 0, NULL);
6199 6200 6201 6202

		if (old->release_fb)
			old->release_fb->funcs->destroy(old->release_fb);

6203
		return;
6204 6205
	}

6206
	/* Switch crtc and encoder back off if necessary */
6207 6208
	if (old->dpms_mode != DRM_MODE_DPMS_ON)
		connector->funcs->dpms(connector, old->dpms_mode);
6209 6210 6211 6212 6213 6214 6215 6216
}

/* Returns the clock of the currently programmed mode of the given pipe. */
static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
6217
	u32 dpll = I915_READ(DPLL(pipe));
6218 6219 6220 6221
	u32 fp;
	intel_clock_t clock;

	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6222
		fp = I915_READ(FP0(pipe));
6223
	else
6224
		fp = I915_READ(FP1(pipe));
6225 6226

	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6227 6228 6229
	if (IS_PINEVIEW(dev)) {
		clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
		clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6230 6231 6232 6233 6234
	} else {
		clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
		clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
	}

6235
	if (!IS_GEN2(dev)) {
6236 6237 6238
		if (IS_PINEVIEW(dev))
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
				DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6239 6240
		else
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6241 6242 6243 6244 6245 6246 6247 6248 6249 6250 6251 6252
			       DPLL_FPA01_P1_POST_DIV_SHIFT);

		switch (dpll & DPLL_MODE_MASK) {
		case DPLLB_MODE_DAC_SERIAL:
			clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
				5 : 10;
			break;
		case DPLLB_MODE_LVDS:
			clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
				7 : 14;
			break;
		default:
6253
			DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6254 6255 6256 6257 6258
				  "mode\n", (int)(dpll & DPLL_MODE_MASK));
			return 0;
		}

		/* XXX: Handle the 100Mhz refclk */
6259
		intel_clock(dev, 96000, &clock);
6260 6261 6262 6263 6264 6265 6266 6267 6268 6269 6270
	} else {
		bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);

		if (is_lvds) {
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
				       DPLL_FPA01_P1_POST_DIV_SHIFT);
			clock.p2 = 14;

			if ((dpll & PLL_REF_INPUT_MASK) ==
			    PLLB_REF_INPUT_SPREADSPECTRUMIN) {
				/* XXX: might not be 66MHz */
6271
				intel_clock(dev, 66000, &clock);
6272
			} else
6273
				intel_clock(dev, 48000, &clock);
6274 6275 6276 6277 6278 6279 6280 6281 6282 6283 6284 6285
		} else {
			if (dpll & PLL_P1_DIVIDE_BY_TWO)
				clock.p1 = 2;
			else {
				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
					    DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
			}
			if (dpll & PLL_P2_DIVIDE_BY_4)
				clock.p2 = 4;
			else
				clock.p2 = 2;

6286
			intel_clock(dev, 48000, &clock);
6287 6288 6289 6290 6291 6292 6293 6294 6295 6296 6297 6298 6299 6300 6301
		}
	}

	/* XXX: It would be nice to validate the clocks, but we can't reuse
	 * i830PllIsValid() because it relies on the xf86_config connector
	 * configuration being accurate, which it isn't necessarily.
	 */

	return clock.dot;
}

/** Returns the currently programmed mode of the given pipe. */
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
					     struct drm_crtc *crtc)
{
6302
	struct drm_i915_private *dev_priv = dev->dev_private;
6303 6304 6305
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	struct drm_display_mode *mode;
6306 6307 6308 6309
	int htot = I915_READ(HTOTAL(pipe));
	int hsync = I915_READ(HSYNC(pipe));
	int vtot = I915_READ(VTOTAL(pipe));
	int vsync = I915_READ(VSYNC(pipe));
6310 6311 6312 6313 6314 6315 6316 6317 6318 6319 6320 6321 6322 6323 6324 6325 6326 6327 6328 6329

	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
	if (!mode)
		return NULL;

	mode->clock = intel_crtc_clock_get(dev, crtc);
	mode->hdisplay = (htot & 0xffff) + 1;
	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
	mode->hsync_start = (hsync & 0xffff) + 1;
	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
	mode->vdisplay = (vtot & 0xffff) + 1;
	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
	mode->vsync_start = (vsync & 0xffff) + 1;
	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;

	drm_mode_set_name(mode);

	return mode;
}

6330
static void intel_increase_pllclock(struct drm_crtc *crtc)
6331 6332 6333 6334 6335
{
	struct drm_device *dev = crtc->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
6336 6337
	int dpll_reg = DPLL(pipe);
	int dpll;
6338

6339
	if (HAS_PCH_SPLIT(dev))
6340 6341 6342 6343 6344
		return;

	if (!dev_priv->lvds_downclock_avail)
		return;

6345
	dpll = I915_READ(dpll_reg);
6346
	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6347
		DRM_DEBUG_DRIVER("upclocking LVDS\n");
6348

6349
		assert_panel_unlocked(dev_priv, pipe);
6350 6351 6352

		dpll &= ~DISPLAY_RATE_SELECT_FPA1;
		I915_WRITE(dpll_reg, dpll);
6353
		intel_wait_for_vblank(dev, pipe);
6354

6355 6356
		dpll = I915_READ(dpll_reg);
		if (dpll & DISPLAY_RATE_SELECT_FPA1)
6357
			DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6358 6359 6360 6361 6362 6363 6364 6365 6366
	}
}

static void intel_decrease_pllclock(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6367
	if (HAS_PCH_SPLIT(dev))
6368 6369 6370 6371 6372 6373 6374 6375 6376 6377
		return;

	if (!dev_priv->lvds_downclock_avail)
		return;

	/*
	 * Since this is called by a timer, we should never get here in
	 * the manual case.
	 */
	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6378 6379 6380
		int pipe = intel_crtc->pipe;
		int dpll_reg = DPLL(pipe);
		int dpll;
6381

6382
		DRM_DEBUG_DRIVER("downclocking LVDS\n");
6383

6384
		assert_panel_unlocked(dev_priv, pipe);
6385

6386
		dpll = I915_READ(dpll_reg);
6387 6388
		dpll |= DISPLAY_RATE_SELECT_FPA1;
		I915_WRITE(dpll_reg, dpll);
6389
		intel_wait_for_vblank(dev, pipe);
6390 6391
		dpll = I915_READ(dpll_reg);
		if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6392
			DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6393 6394 6395 6396
	}

}

6397 6398 6399 6400 6401 6402
void intel_mark_busy(struct drm_device *dev)
{
	i915_update_gfx_val(dev->dev_private);
}

void intel_mark_idle(struct drm_device *dev)
6403
{
6404 6405 6406 6407 6408
}

void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
{
	struct drm_device *dev = obj->base.dev;
6409 6410 6411 6412 6413 6414 6415 6416 6417
	struct drm_crtc *crtc;

	if (!i915_powersave)
		return;

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		if (!crtc->fb)
			continue;

6418 6419
		if (to_intel_framebuffer(crtc->fb)->obj == obj)
			intel_increase_pllclock(crtc);
6420 6421 6422
	}
}

6423
void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6424
{
6425 6426
	struct drm_device *dev = obj->base.dev;
	struct drm_crtc *crtc;
6427

6428
	if (!i915_powersave)
6429 6430
		return;

6431 6432 6433 6434
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		if (!crtc->fb)
			continue;

6435 6436
		if (to_intel_framebuffer(crtc->fb)->obj == obj)
			intel_decrease_pllclock(crtc);
6437 6438 6439
	}
}

6440 6441 6442
static void intel_crtc_destroy(struct drm_crtc *crtc)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6443 6444 6445 6446 6447 6448 6449 6450 6451 6452 6453 6454 6455
	struct drm_device *dev = crtc->dev;
	struct intel_unpin_work *work;
	unsigned long flags;

	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;
	intel_crtc->unpin_work = NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

	if (work) {
		cancel_work_sync(&work->work);
		kfree(work);
	}
6456 6457

	drm_crtc_cleanup(crtc);
6458

6459 6460 6461
	kfree(intel_crtc);
}

6462 6463 6464 6465 6466 6467
static void intel_unpin_work_fn(struct work_struct *__work)
{
	struct intel_unpin_work *work =
		container_of(__work, struct intel_unpin_work, work);

	mutex_lock(&work->dev->struct_mutex);
6468
	intel_unpin_fb_obj(work->old_fb_obj);
6469 6470
	drm_gem_object_unreference(&work->pending_flip_obj->base);
	drm_gem_object_unreference(&work->old_fb_obj->base);
6471

6472
	intel_update_fbc(work->dev);
6473 6474 6475 6476
	mutex_unlock(&work->dev->struct_mutex);
	kfree(work);
}

6477
static void do_intel_finish_page_flip(struct drm_device *dev,
6478
				      struct drm_crtc *crtc)
6479 6480 6481 6482
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_unpin_work *work;
6483
	struct drm_i915_gem_object *obj;
6484
	struct drm_pending_vblank_event *e;
6485
	struct timeval tnow, tvbl;
6486 6487 6488 6489 6490 6491
	unsigned long flags;

	/* Ignore early vblank irqs */
	if (intel_crtc == NULL)
		return;

6492 6493
	do_gettimeofday(&tnow);

6494 6495 6496 6497 6498 6499 6500 6501 6502 6503 6504
	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;
	if (work == NULL || !work->pending) {
		spin_unlock_irqrestore(&dev->event_lock, flags);
		return;
	}

	intel_crtc->unpin_work = NULL;

	if (work->event) {
		e = work->event;
6505
		e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6506 6507 6508 6509 6510

		/* Called before vblank count and timestamps have
		 * been updated for the vblank interval of flip
		 * completion? Need to increment vblank count and
		 * add one videorefresh duration to returned timestamp
6511 6512 6513 6514 6515 6516 6517
		 * to account for this. We assume this happened if we
		 * get called over 0.9 frame durations after the last
		 * timestamped vblank.
		 *
		 * This calculation can not be used with vrefresh rates
		 * below 5Hz (10Hz to be on the safe side) without
		 * promoting to 64 integers.
6518
		 */
6519 6520
		if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
		    9 * crtc->framedur_ns) {
6521
			e->event.sequence++;
6522 6523
			tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
					     crtc->framedur_ns);
6524 6525
		}

6526 6527
		e->event.tv_sec = tvbl.tv_sec;
		e->event.tv_usec = tvbl.tv_usec;
6528

6529 6530 6531 6532 6533
		list_add_tail(&e->base.link,
			      &e->base.file_priv->event_list);
		wake_up_interruptible(&e->base.file_priv->event_wait);
	}

6534 6535
	drm_vblank_put(dev, intel_crtc->pipe);

6536 6537
	spin_unlock_irqrestore(&dev->event_lock, flags);

6538
	obj = work->old_fb_obj;
6539

6540
	atomic_clear_mask(1 << intel_crtc->plane,
6541 6542
			  &obj->pending_flip.counter);
	if (atomic_read(&obj->pending_flip) == 0)
6543
		wake_up(&dev_priv->pending_flip_queue);
6544

6545
	schedule_work(&work->work);
6546 6547

	trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6548 6549
}

6550 6551 6552 6553 6554
void intel_finish_page_flip(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];

6555
	do_intel_finish_page_flip(dev, crtc);
6556 6557 6558 6559 6560 6561 6562
}

void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];

6563
	do_intel_finish_page_flip(dev, crtc);
6564 6565
}

6566 6567 6568 6569 6570 6571 6572 6573
void intel_prepare_page_flip(struct drm_device *dev, int plane)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
	unsigned long flags;

	spin_lock_irqsave(&dev->event_lock, flags);
6574
	if (intel_crtc->unpin_work) {
6575 6576
		if ((++intel_crtc->unpin_work->pending) > 1)
			DRM_ERROR("Prepared flip multiple times\n");
6577 6578 6579
	} else {
		DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
	}
6580 6581 6582
	spin_unlock_irqrestore(&dev->event_lock, flags);
}

6583 6584 6585 6586 6587 6588 6589 6590
static int intel_gen2_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	u32 flip_mask;
6591
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6592 6593
	int ret;

6594
	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6595
	if (ret)
6596
		goto err;
6597

6598
	ret = intel_ring_begin(ring, 6);
6599
	if (ret)
6600
		goto err_unpin;
6601 6602 6603 6604 6605 6606 6607 6608

	/* Can't queue multiple flips, so wait for the previous
	 * one to finish before executing the next.
	 */
	if (intel_crtc->plane)
		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
	else
		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6609 6610 6611 6612 6613
	intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_emit(ring, MI_DISPLAY_FLIP |
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
	intel_ring_emit(ring, fb->pitches[0]);
6614
	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6615 6616
	intel_ring_emit(ring, 0); /* aux display base address, unused */
	intel_ring_advance(ring);
6617 6618 6619 6620 6621
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
6622 6623 6624 6625 6626 6627 6628 6629 6630 6631 6632
	return ret;
}

static int intel_gen3_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	u32 flip_mask;
6633
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6634 6635
	int ret;

6636
	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6637
	if (ret)
6638
		goto err;
6639

6640
	ret = intel_ring_begin(ring, 6);
6641
	if (ret)
6642
		goto err_unpin;
6643 6644 6645 6646 6647

	if (intel_crtc->plane)
		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
	else
		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6648 6649 6650 6651 6652
	intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
	intel_ring_emit(ring, fb->pitches[0]);
6653
	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6654 6655 6656
	intel_ring_emit(ring, MI_NOOP);

	intel_ring_advance(ring);
6657 6658 6659 6660 6661
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
6662 6663 6664 6665 6666 6667 6668 6669 6670 6671 6672
	return ret;
}

static int intel_gen4_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	uint32_t pf, pipesrc;
6673
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6674 6675
	int ret;

6676
	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6677
	if (ret)
6678
		goto err;
6679

6680
	ret = intel_ring_begin(ring, 4);
6681
	if (ret)
6682
		goto err_unpin;
6683 6684 6685 6686 6687

	/* i965+ uses the linear or tiled offsets from the
	 * Display Registers (which do not change across a page-flip)
	 * so we need only reprogram the base address.
	 */
6688 6689 6690
	intel_ring_emit(ring, MI_DISPLAY_FLIP |
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
	intel_ring_emit(ring, fb->pitches[0]);
6691 6692 6693
	intel_ring_emit(ring,
			(obj->gtt_offset + intel_crtc->dspaddr_offset) |
			obj->tiling_mode);
6694 6695 6696 6697 6698 6699 6700

	/* XXX Enabling the panel-fitter across page-flip is so far
	 * untested on non-native modes, so ignore it for now.
	 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
	 */
	pf = 0;
	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6701 6702
	intel_ring_emit(ring, pf | pipesrc);
	intel_ring_advance(ring);
6703 6704 6705 6706 6707
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
6708 6709 6710 6711 6712 6713 6714 6715 6716 6717
	return ret;
}

static int intel_gen6_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6718
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6719 6720 6721
	uint32_t pf, pipesrc;
	int ret;

6722
	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6723
	if (ret)
6724
		goto err;
6725

6726
	ret = intel_ring_begin(ring, 4);
6727
	if (ret)
6728
		goto err_unpin;
6729

6730 6731 6732
	intel_ring_emit(ring, MI_DISPLAY_FLIP |
			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
	intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6733
	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6734

6735 6736 6737 6738 6739 6740 6741
	/* Contrary to the suggestions in the documentation,
	 * "Enable Panel Fitter" does not seem to be required when page
	 * flipping with a non-native mode, and worse causes a normal
	 * modeset to fail.
	 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
	 */
	pf = 0;
6742
	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6743 6744
	intel_ring_emit(ring, pf | pipesrc);
	intel_ring_advance(ring);
6745 6746 6747 6748 6749
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
6750 6751 6752
	return ret;
}

6753 6754 6755 6756 6757 6758 6759 6760 6761 6762 6763 6764 6765 6766
/*
 * On gen7 we currently use the blit ring because (in early silicon at least)
 * the render ring doesn't give us interrpts for page flip completion, which
 * means clients will hang after the first flip is queued.  Fortunately the
 * blit ring generates interrupts properly, so use it instead.
 */
static int intel_gen7_queue_flip(struct drm_device *dev,
				 struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6767
	uint32_t plane_bit = 0;
6768 6769 6770 6771
	int ret;

	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
	if (ret)
6772
		goto err;
6773

6774 6775 6776 6777 6778 6779 6780 6781 6782 6783 6784 6785 6786
	switch(intel_crtc->plane) {
	case PLANE_A:
		plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
		break;
	case PLANE_B:
		plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
		break;
	case PLANE_C:
		plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
		break;
	default:
		WARN_ONCE(1, "unknown plane in flip command\n");
		ret = -ENODEV;
6787
		goto err_unpin;
6788 6789
	}

6790 6791
	ret = intel_ring_begin(ring, 4);
	if (ret)
6792
		goto err_unpin;
6793

6794
	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6795
	intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6796
	intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6797 6798
	intel_ring_emit(ring, (MI_NOOP));
	intel_ring_advance(ring);
6799 6800 6801 6802 6803
	return 0;

err_unpin:
	intel_unpin_fb_obj(obj);
err:
6804 6805 6806
	return ret;
}

6807 6808 6809 6810 6811 6812 6813 6814
static int intel_default_queue_flip(struct drm_device *dev,
				    struct drm_crtc *crtc,
				    struct drm_framebuffer *fb,
				    struct drm_i915_gem_object *obj)
{
	return -ENODEV;
}

6815 6816 6817 6818 6819 6820 6821
static int intel_crtc_page_flip(struct drm_crtc *crtc,
				struct drm_framebuffer *fb,
				struct drm_pending_vblank_event *event)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_framebuffer *intel_fb;
6822
	struct drm_i915_gem_object *obj;
6823 6824
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_unpin_work *work;
6825
	unsigned long flags;
6826
	int ret;
6827

6828 6829 6830 6831 6832 6833 6834 6835 6836 6837 6838 6839 6840
	/* Can't change pixel format via MI display flips. */
	if (fb->pixel_format != crtc->fb->pixel_format)
		return -EINVAL;

	/*
	 * TILEOFF/LINOFF registers can't be changed via MI display flips.
	 * Note that pitch changes could also affect these register.
	 */
	if (INTEL_INFO(dev)->gen > 3 &&
	    (fb->offsets[0] != crtc->fb->offsets[0] ||
	     fb->pitches[0] != crtc->fb->pitches[0]))
		return -EINVAL;

6841 6842 6843 6844 6845 6846 6847
	work = kzalloc(sizeof *work, GFP_KERNEL);
	if (work == NULL)
		return -ENOMEM;

	work->event = event;
	work->dev = crtc->dev;
	intel_fb = to_intel_framebuffer(crtc->fb);
6848
	work->old_fb_obj = intel_fb->obj;
6849 6850
	INIT_WORK(&work->work, intel_unpin_work_fn);

6851 6852 6853 6854
	ret = drm_vblank_get(dev, intel_crtc->pipe);
	if (ret)
		goto free_work;

6855 6856 6857 6858 6859
	/* We borrow the event spin lock for protecting unpin_work */
	spin_lock_irqsave(&dev->event_lock, flags);
	if (intel_crtc->unpin_work) {
		spin_unlock_irqrestore(&dev->event_lock, flags);
		kfree(work);
6860
		drm_vblank_put(dev, intel_crtc->pipe);
6861 6862

		DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6863 6864 6865 6866 6867 6868 6869 6870
		return -EBUSY;
	}
	intel_crtc->unpin_work = work;
	spin_unlock_irqrestore(&dev->event_lock, flags);

	intel_fb = to_intel_framebuffer(fb);
	obj = intel_fb->obj;

6871 6872 6873
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		goto cleanup;
6874

6875
	/* Reference the objects for the scheduled work. */
6876 6877
	drm_gem_object_reference(&work->old_fb_obj->base);
	drm_gem_object_reference(&obj->base);
6878 6879

	crtc->fb = fb;
6880

6881 6882
	work->pending_flip_obj = obj;

6883 6884
	work->enable_stall_check = true;

6885 6886 6887
	/* Block clients from rendering to the new back buffer until
	 * the flip occurs and the object is no longer visible.
	 */
6888
	atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6889

6890 6891 6892
	ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
	if (ret)
		goto cleanup_pending;
6893

6894
	intel_disable_fbc(dev);
6895
	intel_mark_fb_busy(obj);
6896 6897
	mutex_unlock(&dev->struct_mutex);

6898 6899
	trace_i915_flip_request(intel_crtc->plane, obj);

6900
	return 0;
6901

6902 6903
cleanup_pending:
	atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6904 6905
	drm_gem_object_unreference(&work->old_fb_obj->base);
	drm_gem_object_unreference(&obj->base);
6906 6907
	mutex_unlock(&dev->struct_mutex);

6908
cleanup:
6909 6910 6911 6912
	spin_lock_irqsave(&dev->event_lock, flags);
	intel_crtc->unpin_work = NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

6913 6914
	drm_vblank_put(dev, intel_crtc->pipe);
free_work:
6915 6916 6917
	kfree(work);

	return ret;
6918 6919
}

6920 6921 6922
static struct drm_crtc_helper_funcs intel_helper_funcs = {
	.mode_set_base_atomic = intel_pipe_set_base_atomic,
	.load_lut = intel_crtc_load_lut,
6923
	.disable = intel_crtc_noop,
6924 6925
};

6926
bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
6927
{
6928 6929
	struct intel_encoder *other_encoder;
	struct drm_crtc *crtc = &encoder->new_crtc->base;
6930

6931 6932 6933 6934 6935 6936 6937 6938 6939 6940 6941 6942
	if (WARN_ON(!crtc))
		return false;

	list_for_each_entry(other_encoder,
			    &crtc->dev->mode_config.encoder_list,
			    base.head) {

		if (&other_encoder->new_crtc->base != crtc ||
		    encoder == other_encoder)
			continue;
		else
			return true;
6943 6944
	}

6945 6946
	return false;
}
6947

6948 6949 6950 6951 6952 6953
static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
				  struct drm_crtc *crtc)
{
	struct drm_device *dev;
	struct drm_crtc *tmp;
	int crtc_mask = 1;
6954

6955
	WARN(!crtc, "checking null crtc?\n");
6956

6957
	dev = crtc->dev;
6958

6959 6960 6961 6962 6963
	list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
		if (tmp == crtc)
			break;
		crtc_mask <<= 1;
	}
6964

6965 6966 6967
	if (encoder->possible_crtcs & crtc_mask)
		return true;
	return false;
6968
}
6969

6970 6971 6972 6973 6974 6975 6976
/**
 * intel_modeset_update_staged_output_state
 *
 * Updates the staged output configuration state, e.g. after we've read out the
 * current hw state.
 */
static void intel_modeset_update_staged_output_state(struct drm_device *dev)
6977
{
6978 6979
	struct intel_encoder *encoder;
	struct intel_connector *connector;
6980

6981 6982 6983 6984 6985
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		connector->new_encoder =
			to_intel_encoder(connector->base.encoder);
	}
6986

6987 6988 6989 6990 6991
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		encoder->new_crtc =
			to_intel_crtc(encoder->base.crtc);
	}
6992 6993
}

6994 6995 6996 6997 6998 6999 7000 7001 7002
/**
 * intel_modeset_commit_output_state
 *
 * This function copies the stage display pipe configuration to the real one.
 */
static void intel_modeset_commit_output_state(struct drm_device *dev)
{
	struct intel_encoder *encoder;
	struct intel_connector *connector;
7003

7004 7005 7006 7007
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		connector->base.encoder = &connector->new_encoder->base;
	}
7008

7009 7010 7011 7012 7013 7014
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		encoder->base.crtc = &encoder->new_crtc->base;
	}
}

7015 7016 7017
static struct drm_display_mode *
intel_modeset_adjusted_mode(struct drm_crtc *crtc,
			    struct drm_display_mode *mode)
7018
{
7019 7020 7021 7022
	struct drm_device *dev = crtc->dev;
	struct drm_display_mode *adjusted_mode;
	struct drm_encoder_helper_funcs *encoder_funcs;
	struct intel_encoder *encoder;
7023

7024 7025 7026 7027 7028 7029 7030 7031 7032 7033 7034 7035 7036 7037 7038 7039 7040 7041 7042
	adjusted_mode = drm_mode_duplicate(dev, mode);
	if (!adjusted_mode)
		return ERR_PTR(-ENOMEM);

	/* Pass our mode to the connectors and the CRTC to give them a chance to
	 * adjust it according to limitations or connector properties, and also
	 * a chance to reject the mode entirely.
	 */
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {

		if (&encoder->new_crtc->base != crtc)
			continue;
		encoder_funcs = encoder->base.helper_private;
		if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
						adjusted_mode))) {
			DRM_DEBUG_KMS("Encoder fixup failed\n");
			goto fail;
		}
7043 7044
	}

7045 7046 7047
	if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
		DRM_DEBUG_KMS("CRTC fixup failed\n");
		goto fail;
7048
	}
7049 7050 7051 7052 7053 7054
	DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);

	return adjusted_mode;
fail:
	drm_mode_destroy(dev, adjusted_mode);
	return ERR_PTR(-EINVAL);
7055 7056
}

7057 7058 7059 7060 7061
/* Computes which crtcs are affected and sets the relevant bits in the mask. For
 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
static void
intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
			     unsigned *prepare_pipes, unsigned *disable_pipes)
7062 7063
{
	struct intel_crtc *intel_crtc;
7064 7065 7066 7067
	struct drm_device *dev = crtc->dev;
	struct intel_encoder *encoder;
	struct intel_connector *connector;
	struct drm_crtc *tmp_crtc;
7068

7069
	*disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7070

7071 7072 7073 7074 7075 7076 7077 7078
	/* Check which crtcs have changed outputs connected to them, these need
	 * to be part of the prepare_pipes mask. We don't (yet) support global
	 * modeset across multiple crtcs, so modeset_pipes will only have one
	 * bit set at most. */
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		if (connector->base.encoder == &connector->new_encoder->base)
			continue;
7079

7080 7081 7082 7083 7084 7085 7086 7087 7088
		if (connector->base.encoder) {
			tmp_crtc = connector->base.encoder->crtc;

			*prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
		}

		if (connector->new_encoder)
			*prepare_pipes |=
				1 << connector->new_encoder->new_crtc->pipe;
7089 7090
	}

7091 7092 7093 7094 7095 7096 7097 7098 7099 7100 7101 7102 7103
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		if (encoder->base.crtc == &encoder->new_crtc->base)
			continue;

		if (encoder->base.crtc) {
			tmp_crtc = encoder->base.crtc;

			*prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
		}

		if (encoder->new_crtc)
			*prepare_pipes |= 1 << encoder->new_crtc->pipe;
7104 7105
	}

7106 7107 7108 7109
	/* Check for any pipes that will be fully disabled ... */
	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
			    base.head) {
		bool used = false;
J
Jesse Barnes 已提交
7110

7111 7112 7113
		/* Don't try to disable disabled crtcs. */
		if (!intel_crtc->base.enabled)
			continue;
7114

7115 7116 7117 7118 7119 7120 7121 7122
		list_for_each_entry(encoder, &dev->mode_config.encoder_list,
				    base.head) {
			if (encoder->new_crtc == intel_crtc)
				used = true;
		}

		if (!used)
			*disable_pipes |= 1 << intel_crtc->pipe;
7123 7124
	}

7125 7126 7127 7128 7129 7130 7131 7132 7133 7134 7135 7136 7137 7138 7139 7140 7141 7142 7143 7144 7145 7146 7147 7148

	/* set_mode is also used to update properties on life display pipes. */
	intel_crtc = to_intel_crtc(crtc);
	if (crtc->enabled)
		*prepare_pipes |= 1 << intel_crtc->pipe;

	/* We only support modeset on one single crtc, hence we need to do that
	 * only for the passed in crtc iff we change anything else than just
	 * disable crtcs.
	 *
	 * This is actually not true, to be fully compatible with the old crtc
	 * helper we automatically disable _any_ output (i.e. doesn't need to be
	 * connected to the crtc we're modesetting on) if it's disconnected.
	 * Which is a rather nutty api (since changed the output configuration
	 * without userspace's explicit request can lead to confusion), but
	 * alas. Hence we currently need to modeset on all pipes we prepare. */
	if (*prepare_pipes)
		*modeset_pipes = *prepare_pipes;

	/* ... and mask these out. */
	*modeset_pipes &= ~(*disable_pipes);
	*prepare_pipes &= ~(*disable_pipes);
}

7149 7150 7151 7152 7153 7154 7155 7156 7157 7158 7159 7160 7161 7162 7163 7164 7165 7166 7167 7168 7169 7170 7171 7172 7173 7174 7175 7176 7177 7178 7179 7180 7181 7182 7183 7184 7185 7186 7187 7188 7189 7190 7191 7192 7193
static bool intel_crtc_in_use(struct drm_crtc *crtc)
{
	struct drm_encoder *encoder;
	struct drm_device *dev = crtc->dev;

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
		if (encoder->crtc == crtc)
			return true;

	return false;
}

static void
intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
{
	struct intel_encoder *intel_encoder;
	struct intel_crtc *intel_crtc;
	struct drm_connector *connector;

	list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
			    base.head) {
		if (!intel_encoder->base.crtc)
			continue;

		intel_crtc = to_intel_crtc(intel_encoder->base.crtc);

		if (prepare_pipes & (1 << intel_crtc->pipe))
			intel_encoder->connectors_active = false;
	}

	intel_modeset_commit_output_state(dev);

	/* Update computed state. */
	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
			    base.head) {
		intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
	}

	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		if (!connector->encoder || !connector->encoder->crtc)
			continue;

		intel_crtc = to_intel_crtc(connector->encoder->crtc);

		if (prepare_pipes & (1 << intel_crtc->pipe)) {
7194 7195 7196
			struct drm_property *dpms_property =
				dev->mode_config.dpms_property;

7197
			connector->dpms = DRM_MODE_DPMS_ON;
7198 7199 7200
			drm_connector_property_set_value(connector,
							 dpms_property,
							 DRM_MODE_DPMS_ON);
7201 7202 7203 7204 7205 7206 7207 7208

			intel_encoder = to_intel_encoder(connector->encoder);
			intel_encoder->connectors_active = true;
		}
	}

}

7209 7210 7211 7212 7213 7214
#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
	list_for_each_entry((intel_crtc), \
			    &(dev)->mode_config.crtc_list, \
			    base.head) \
		if (mask & (1 <<(intel_crtc)->pipe)) \

7215
void
7216 7217 7218 7219 7220 7221 7222 7223 7224 7225 7226 7227 7228 7229 7230 7231 7232 7233 7234 7235 7236 7237 7238 7239 7240 7241 7242 7243 7244 7245 7246 7247 7248 7249 7250 7251 7252 7253 7254 7255 7256 7257 7258 7259 7260 7261 7262 7263 7264 7265 7266 7267 7268 7269 7270 7271 7272 7273 7274 7275 7276 7277 7278 7279 7280 7281 7282 7283 7284 7285 7286 7287 7288 7289 7290 7291 7292 7293 7294 7295 7296 7297 7298 7299 7300 7301 7302 7303 7304 7305 7306 7307 7308 7309 7310 7311 7312
intel_modeset_check_state(struct drm_device *dev)
{
	struct intel_crtc *crtc;
	struct intel_encoder *encoder;
	struct intel_connector *connector;

	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		/* This also checks the encoder/connector hw state with the
		 * ->get_hw_state callbacks. */
		intel_connector_check_state(connector);

		WARN(&connector->new_encoder->base != connector->base.encoder,
		     "connector's staged encoder doesn't match current encoder\n");
	}

	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		bool enabled = false;
		bool active = false;
		enum pipe pipe, tracked_pipe;

		DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
			      encoder->base.base.id,
			      drm_get_encoder_name(&encoder->base));

		WARN(&encoder->new_crtc->base != encoder->base.crtc,
		     "encoder's stage crtc doesn't match current crtc\n");
		WARN(encoder->connectors_active && !encoder->base.crtc,
		     "encoder's active_connectors set, but no crtc\n");

		list_for_each_entry(connector, &dev->mode_config.connector_list,
				    base.head) {
			if (connector->base.encoder != &encoder->base)
				continue;
			enabled = true;
			if (connector->base.dpms != DRM_MODE_DPMS_OFF)
				active = true;
		}
		WARN(!!encoder->base.crtc != enabled,
		     "encoder's enabled state mismatch "
		     "(expected %i, found %i)\n",
		     !!encoder->base.crtc, enabled);
		WARN(active && !encoder->base.crtc,
		     "active encoder with no crtc\n");

		WARN(encoder->connectors_active != active,
		     "encoder's computed active state doesn't match tracked active state "
		     "(expected %i, found %i)\n", active, encoder->connectors_active);

		active = encoder->get_hw_state(encoder, &pipe);
		WARN(active != encoder->connectors_active,
		     "encoder's hw state doesn't match sw tracking "
		     "(expected %i, found %i)\n",
		     encoder->connectors_active, active);

		if (!encoder->base.crtc)
			continue;

		tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
		WARN(active && pipe != tracked_pipe,
		     "active encoder's pipe doesn't match"
		     "(expected %i, found %i)\n",
		     tracked_pipe, pipe);

	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list,
			    base.head) {
		bool enabled = false;
		bool active = false;

		DRM_DEBUG_KMS("[CRTC:%d]\n",
			      crtc->base.base.id);

		WARN(crtc->active && !crtc->base.enabled,
		     "active crtc, but not enabled in sw tracking\n");

		list_for_each_entry(encoder, &dev->mode_config.encoder_list,
				    base.head) {
			if (encoder->base.crtc != &crtc->base)
				continue;
			enabled = true;
			if (encoder->connectors_active)
				active = true;
		}
		WARN(active != crtc->active,
		     "crtc's computed active state doesn't match tracked active state "
		     "(expected %i, found %i)\n", active, crtc->active);
		WARN(enabled != crtc->base.enabled,
		     "crtc's computed enabled state doesn't match tracked enabled state "
		     "(expected %i, found %i)\n", enabled, crtc->base.enabled);

		assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
	}
}

7313 7314
bool intel_set_mode(struct drm_crtc *crtc,
		    struct drm_display_mode *mode,
7315
		    int x, int y, struct drm_framebuffer *fb)
7316 7317
{
	struct drm_device *dev = crtc->dev;
7318
	drm_i915_private_t *dev_priv = dev->dev_private;
7319 7320 7321
	struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
	struct drm_encoder_helper_funcs *encoder_funcs;
	struct drm_encoder *encoder;
7322 7323
	struct intel_crtc *intel_crtc;
	unsigned disable_pipes, prepare_pipes, modeset_pipes;
7324 7325
	bool ret = true;

7326
	intel_modeset_affected_pipes(crtc, &modeset_pipes,
7327 7328 7329 7330
				     &prepare_pipes, &disable_pipes);

	DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
		      modeset_pipes, prepare_pipes, disable_pipes);
7331

7332 7333
	for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
		intel_crtc_disable(&intel_crtc->base);
7334

7335 7336 7337
	saved_hwmode = crtc->hwmode;
	saved_mode = crtc->mode;

7338 7339 7340 7341 7342 7343 7344 7345 7346 7347 7348 7349
	/* Hack: Because we don't (yet) support global modeset on multiple
	 * crtcs, we don't keep track of the new mode for more than one crtc.
	 * Hence simply check whether any bit is set in modeset_pipes in all the
	 * pieces of code that are not yet converted to deal with mutliple crtcs
	 * changing their mode at the same time. */
	adjusted_mode = NULL;
	if (modeset_pipes) {
		adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
		if (IS_ERR(adjusted_mode)) {
			return false;
		}
	}
7350

7351 7352 7353 7354
	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
		if (intel_crtc->base.enabled)
			dev_priv->display.crtc_disable(&intel_crtc->base);
	}
7355

7356 7357 7358 7359
	/* crtc->mode is already used by the ->mode_set callbacks, hence we need
	 * to set it here already despite that we pass it down the callchain.
	 */
	if (modeset_pipes)
7360
		crtc->mode = *mode;
7361

7362 7363 7364 7365
	/* Only after disabling all output pipelines that will be changed can we
	 * update the the output configuration. */
	intel_modeset_update_state(dev, prepare_pipes);

7366 7367 7368
	/* Set up the DPLL and any encoders state that needs to adjust or depend
	 * on the DPLL.
	 */
7369 7370 7371 7372 7373 7374
	for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
		ret = !intel_crtc_mode_set(&intel_crtc->base,
					   mode, adjusted_mode,
					   x, y, fb);
		if (!ret)
		    goto done;
7375

7376
		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7377

7378 7379
			if (encoder->crtc != &intel_crtc->base)
				continue;
7380

7381 7382 7383 7384 7385 7386
			DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
				encoder->base.id, drm_get_encoder_name(encoder),
				mode->base.id, mode->name);
			encoder_funcs = encoder->helper_private;
			encoder_funcs->mode_set(encoder, mode, adjusted_mode);
		}
7387 7388 7389
	}

	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
7390 7391
	for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
		dev_priv->display.crtc_enable(&intel_crtc->base);
7392

7393 7394 7395
	if (modeset_pipes) {
		/* Store real post-adjustment hardware mode. */
		crtc->hwmode = *adjusted_mode;
7396

7397 7398 7399 7400 7401 7402
		/* Calculate and store various constants which
		 * are later needed by vblank and swap-completion
		 * timestamping. They are derived from true hwmode.
		 */
		drm_calc_timestamping_constants(crtc);
	}
7403 7404 7405 7406

	/* FIXME: add subpixel order */
done:
	drm_mode_destroy(dev, adjusted_mode);
7407
	if (!ret && crtc->enabled) {
7408 7409
		crtc->hwmode = saved_hwmode;
		crtc->mode = saved_mode;
7410 7411
	} else {
		intel_modeset_check_state(dev);
7412 7413 7414 7415 7416
	}

	return ret;
}

7417 7418
#undef for_each_intel_crtc_masked

7419 7420 7421 7422 7423
static void intel_set_config_free(struct intel_set_config *config)
{
	if (!config)
		return;

7424 7425
	kfree(config->save_connector_encoders);
	kfree(config->save_encoder_crtcs);
7426 7427 7428
	kfree(config);
}

7429 7430 7431 7432 7433 7434 7435
static int intel_set_config_save_state(struct drm_device *dev,
				       struct intel_set_config *config)
{
	struct drm_encoder *encoder;
	struct drm_connector *connector;
	int count;

7436 7437 7438 7439
	config->save_encoder_crtcs =
		kcalloc(dev->mode_config.num_encoder,
			sizeof(struct drm_crtc *), GFP_KERNEL);
	if (!config->save_encoder_crtcs)
7440 7441
		return -ENOMEM;

7442 7443 7444 7445
	config->save_connector_encoders =
		kcalloc(dev->mode_config.num_connector,
			sizeof(struct drm_encoder *), GFP_KERNEL);
	if (!config->save_connector_encoders)
7446 7447 7448 7449 7450 7451 7452 7453
		return -ENOMEM;

	/* Copy data. Note that driver private data is not affected.
	 * Should anything bad happen only the expected state is
	 * restored, not the drivers personal bookkeeping.
	 */
	count = 0;
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7454
		config->save_encoder_crtcs[count++] = encoder->crtc;
7455 7456 7457 7458
	}

	count = 0;
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7459
		config->save_connector_encoders[count++] = connector->encoder;
7460 7461 7462 7463 7464 7465 7466 7467
	}

	return 0;
}

static void intel_set_config_restore_state(struct drm_device *dev,
					   struct intel_set_config *config)
{
7468 7469
	struct intel_encoder *encoder;
	struct intel_connector *connector;
7470 7471 7472
	int count;

	count = 0;
7473 7474 7475
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		encoder->new_crtc =
			to_intel_crtc(config->save_encoder_crtcs[count++]);
7476 7477 7478
	}

	count = 0;
7479 7480 7481
	list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
		connector->new_encoder =
			to_intel_encoder(config->save_connector_encoders[count++]);
7482 7483 7484
	}
}

7485 7486 7487 7488 7489 7490 7491 7492 7493 7494 7495 7496 7497 7498 7499 7500 7501 7502 7503 7504 7505 7506 7507
static void
intel_set_config_compute_mode_changes(struct drm_mode_set *set,
				      struct intel_set_config *config)
{

	/* We should be able to check here if the fb has the same properties
	 * and then just flip_or_move it */
	if (set->crtc->fb != set->fb) {
		/* If we have no fb then treat it as a full mode set */
		if (set->crtc->fb == NULL) {
			DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
			config->mode_changed = true;
		} else if (set->fb == NULL) {
			config->mode_changed = true;
		} else if (set->fb->depth != set->crtc->fb->depth) {
			config->mode_changed = true;
		} else if (set->fb->bits_per_pixel !=
			   set->crtc->fb->bits_per_pixel) {
			config->mode_changed = true;
		} else
			config->fb_changed = true;
	}

7508
	if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7509 7510 7511 7512 7513 7514 7515 7516 7517 7518
		config->fb_changed = true;

	if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
		DRM_DEBUG_KMS("modes are different, full mode set\n");
		drm_mode_debug_printmodeline(&set->crtc->mode);
		drm_mode_debug_printmodeline(set->mode);
		config->mode_changed = true;
	}
}

7519
static int
7520 7521 7522
intel_modeset_stage_output_state(struct drm_device *dev,
				 struct drm_mode_set *set,
				 struct intel_set_config *config)
7523
{
7524
	struct drm_crtc *new_crtc;
7525 7526
	struct intel_connector *connector;
	struct intel_encoder *encoder;
7527
	int count, ro;
7528

7529 7530 7531 7532 7533
	/* The upper layers ensure that we either disabl a crtc or have a list
	 * of connectors. For paranoia, double-check this. */
	WARN_ON(!set->fb && (set->num_connectors != 0));
	WARN_ON(set->fb && (set->num_connectors == 0));

7534
	count = 0;
7535 7536 7537 7538
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		/* Otherwise traverse passed in connector list and get encoders
		 * for them. */
7539
		for (ro = 0; ro < set->num_connectors; ro++) {
7540 7541
			if (set->connectors[ro] == &connector->base) {
				connector->new_encoder = connector->encoder;
7542 7543 7544 7545
				break;
			}
		}

7546 7547 7548 7549 7550 7551 7552 7553 7554 7555 7556 7557 7558 7559 7560
		/* If we disable the crtc, disable all its connectors. Also, if
		 * the connector is on the changing crtc but not on the new
		 * connector list, disable it. */
		if ((!set->fb || ro == set->num_connectors) &&
		    connector->base.encoder &&
		    connector->base.encoder->crtc == set->crtc) {
			connector->new_encoder = NULL;

			DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
				connector->base.base.id,
				drm_get_connector_name(&connector->base));
		}


		if (&connector->new_encoder->base != connector->base.encoder) {
7561
			DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7562
			config->mode_changed = true;
7563
		}
7564 7565 7566 7567

		/* Disable all disconnected encoders. */
		if (connector->base.status == connector_status_disconnected)
			connector->new_encoder = NULL;
7568
	}
7569
	/* connector->new_encoder is now updated for all connectors. */
7570

7571
	/* Update crtc of enabled connectors. */
7572
	count = 0;
7573 7574 7575
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		if (!connector->new_encoder)
7576 7577
			continue;

7578
		new_crtc = connector->new_encoder->base.crtc;
7579 7580

		for (ro = 0; ro < set->num_connectors; ro++) {
7581
			if (set->connectors[ro] == &connector->base)
7582 7583 7584 7585
				new_crtc = set->crtc;
		}

		/* Make sure the new CRTC will work with the encoder */
7586 7587
		if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
					   new_crtc)) {
7588
			return -EINVAL;
7589
		}
7590 7591 7592 7593 7594 7595 7596 7597 7598 7599 7600 7601 7602 7603 7604 7605 7606 7607 7608 7609 7610 7611 7612 7613 7614
		connector->encoder->new_crtc = to_intel_crtc(new_crtc);

		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
			connector->base.base.id,
			drm_get_connector_name(&connector->base),
			new_crtc->base.id);
	}

	/* Check for any encoders that needs to be disabled. */
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		list_for_each_entry(connector,
				    &dev->mode_config.connector_list,
				    base.head) {
			if (connector->new_encoder == encoder) {
				WARN_ON(!connector->new_encoder->new_crtc);

				goto next_encoder;
			}
		}
		encoder->new_crtc = NULL;
next_encoder:
		/* Only now check for crtc changes so we don't miss encoders
		 * that will be disabled. */
		if (&encoder->new_crtc->base != encoder->base.crtc) {
7615
			DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7616
			config->mode_changed = true;
7617 7618
		}
	}
7619
	/* Now we've also updated encoder->new_crtc for all encoders. */
7620

7621 7622 7623 7624 7625 7626 7627 7628 7629 7630
	return 0;
}

static int intel_crtc_set_config(struct drm_mode_set *set)
{
	struct drm_device *dev;
	struct drm_mode_set save_set;
	struct intel_set_config *config;
	int ret;

7631 7632 7633
	BUG_ON(!set);
	BUG_ON(!set->crtc);
	BUG_ON(!set->crtc->helper_private);
7634 7635 7636 7637

	if (!set->mode)
		set->fb = NULL;

7638 7639 7640 7641 7642 7643
	/* The fb helper likes to play gross jokes with ->mode_set_config.
	 * Unfortunately the crtc helper doesn't do much at all for this case,
	 * so we have to cope with this madness until the fb helper is fixed up. */
	if (set->fb && set->num_connectors == 0)
		return 0;

7644 7645 7646 7647 7648 7649 7650 7651 7652 7653 7654 7655 7656 7657 7658 7659 7660 7661 7662 7663 7664 7665 7666 7667 7668 7669 7670 7671 7672 7673 7674
	if (set->fb) {
		DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
				set->crtc->base.id, set->fb->base.id,
				(int)set->num_connectors, set->x, set->y);
	} else {
		DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
	}

	dev = set->crtc->dev;

	ret = -ENOMEM;
	config = kzalloc(sizeof(*config), GFP_KERNEL);
	if (!config)
		goto out_config;

	ret = intel_set_config_save_state(dev, config);
	if (ret)
		goto out_config;

	save_set.crtc = set->crtc;
	save_set.mode = &set->crtc->mode;
	save_set.x = set->crtc->x;
	save_set.y = set->crtc->y;
	save_set.fb = set->crtc->fb;

	/* Compute whether we need a full modeset, only an fb base update or no
	 * change at all. In the future we might also check whether only the
	 * mode changed, e.g. for LVDS where we only change the panel fitter in
	 * such cases. */
	intel_set_config_compute_mode_changes(set, config);

7675
	ret = intel_modeset_stage_output_state(dev, set, config);
7676 7677 7678
	if (ret)
		goto fail;

7679
	if (config->mode_changed) {
7680
		if (set->mode) {
7681 7682 7683
			DRM_DEBUG_KMS("attempting to set mode from"
					" userspace\n");
			drm_mode_debug_printmodeline(set->mode);
7684 7685 7686 7687 7688 7689 7690 7691 7692
		}

		if (!intel_set_mode(set->crtc, set->mode,
				    set->x, set->y, set->fb)) {
			DRM_ERROR("failed to set mode on [CRTC:%d]\n",
				  set->crtc->base.id);
			ret = -EINVAL;
			goto fail;
		}
7693
	} else if (config->fb_changed) {
7694
		ret = intel_pipe_set_base(set->crtc,
7695
					  set->x, set->y, set->fb);
7696 7697
	}

7698 7699
	intel_set_config_free(config);

7700 7701 7702
	return 0;

fail:
7703
	intel_set_config_restore_state(dev, config);
7704 7705

	/* Try to restore the config */
7706
	if (config->mode_changed &&
7707 7708
	    !intel_set_mode(save_set.crtc, save_set.mode,
			    save_set.x, save_set.y, save_set.fb))
7709 7710
		DRM_ERROR("failed to restore config after modeset failure\n");

7711 7712
out_config:
	intel_set_config_free(config);
7713 7714 7715
	return ret;
}

7716 7717 7718 7719
static const struct drm_crtc_funcs intel_crtc_funcs = {
	.cursor_set = intel_crtc_cursor_set,
	.cursor_move = intel_crtc_cursor_move,
	.gamma_set = intel_crtc_gamma_set,
7720
	.set_config = intel_crtc_set_config,
7721 7722 7723 7724
	.destroy = intel_crtc_destroy,
	.page_flip = intel_crtc_page_flip,
};

7725 7726 7727 7728 7729 7730
static void intel_cpu_pll_init(struct drm_device *dev)
{
	if (IS_HASWELL(dev))
		intel_ddi_pll_init(dev);
}

7731 7732 7733 7734 7735 7736 7737 7738 7739 7740 7741 7742 7743 7744 7745 7746 7747
static void intel_pch_pll_init(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int i;

	if (dev_priv->num_pch_pll == 0) {
		DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
		return;
	}

	for (i = 0; i < dev_priv->num_pch_pll; i++) {
		dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
		dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
		dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
	}
}

7748
static void intel_crtc_init(struct drm_device *dev, int pipe)
7749
{
J
Jesse Barnes 已提交
7750
	drm_i915_private_t *dev_priv = dev->dev_private;
7751 7752 7753 7754 7755 7756 7757 7758 7759 7760 7761 7762 7763 7764 7765 7766
	struct intel_crtc *intel_crtc;
	int i;

	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
	if (intel_crtc == NULL)
		return;

	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);

	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
	for (i = 0; i < 256; i++) {
		intel_crtc->lut_r[i] = i;
		intel_crtc->lut_g[i] = i;
		intel_crtc->lut_b[i] = i;
	}

7767 7768 7769
	/* Swap pipes & planes for FBC on pre-965 */
	intel_crtc->pipe = pipe;
	intel_crtc->plane = pipe;
7770
	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7771
		DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7772
		intel_crtc->plane = !pipe;
7773 7774
	}

J
Jesse Barnes 已提交
7775 7776 7777 7778 7779
	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
	       dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;

7780
	intel_crtc->bpp = 24; /* default for pre-Ironlake */
7781

7782 7783 7784
	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
}

7785
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7786
				struct drm_file *file)
7787 7788
{
	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7789 7790
	struct drm_mode_object *drmmode_obj;
	struct intel_crtc *crtc;
7791

7792 7793
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		return -ENODEV;
7794

7795 7796
	drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
			DRM_MODE_OBJECT_CRTC);
7797

7798
	if (!drmmode_obj) {
7799 7800 7801 7802
		DRM_ERROR("no such CRTC id\n");
		return -EINVAL;
	}

7803 7804
	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
	pipe_from_crtc_id->pipe = crtc->pipe;
7805

7806
	return 0;
7807 7808
}

7809
static int intel_encoder_clones(struct intel_encoder *encoder)
7810
{
7811 7812
	struct drm_device *dev = encoder->base.dev;
	struct intel_encoder *source_encoder;
7813 7814 7815
	int index_mask = 0;
	int entry = 0;

7816 7817 7818 7819
	list_for_each_entry(source_encoder,
			    &dev->mode_config.encoder_list, base.head) {

		if (encoder == source_encoder)
7820
			index_mask |= (1 << entry);
7821 7822 7823 7824 7825

		/* Intel hw has only one MUX where enocoders could be cloned. */
		if (encoder->cloneable && source_encoder->cloneable)
			index_mask |= (1 << entry);

7826 7827
		entry++;
	}
7828

7829 7830 7831
	return index_mask;
}

7832 7833 7834 7835 7836 7837 7838 7839 7840 7841 7842 7843 7844 7845 7846 7847 7848
static bool has_edp_a(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!IS_MOBILE(dev))
		return false;

	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
		return false;

	if (IS_GEN5(dev) &&
	    (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
		return false;

	return true;
}

7849 7850
static void intel_setup_outputs(struct drm_device *dev)
{
7851
	struct drm_i915_private *dev_priv = dev->dev_private;
7852
	struct intel_encoder *encoder;
7853
	bool dpd_is_edp = false;
7854
	bool has_lvds;
7855

7856
	has_lvds = intel_lvds_init(dev);
7857 7858 7859 7860
	if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
		/* disable the panel fitter on everything but LVDS */
		I915_WRITE(PFIT_CONTROL, 0);
	}
7861

7862
	if (HAS_PCH_SPLIT(dev)) {
7863
		dpd_is_edp = intel_dpd_is_edp(dev);
7864

7865
		if (has_edp_a(dev))
7866
			intel_dp_init(dev, DP_A, PORT_A);
7867

7868
		if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7869
			intel_dp_init(dev, PCH_DP_D, PORT_D);
7870 7871 7872 7873
	}

	intel_crt_init(dev);

7874 7875 7876 7877 7878 7879 7880 7881 7882 7883 7884 7885 7886 7887 7888 7889 7890 7891 7892 7893
	if (IS_HASWELL(dev)) {
		int found;

		/* Haswell uses DDI functions to detect digital outputs */
		found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
		/* DDI A only supports eDP */
		if (found)
			intel_ddi_init(dev, PORT_A);

		/* DDI B, C and D detection is indicated by the SFUSE_STRAP
		 * register */
		found = I915_READ(SFUSE_STRAP);

		if (found & SFUSE_STRAP_DDIB_DETECTED)
			intel_ddi_init(dev, PORT_B);
		if (found & SFUSE_STRAP_DDIC_DETECTED)
			intel_ddi_init(dev, PORT_C);
		if (found & SFUSE_STRAP_DDID_DETECTED)
			intel_ddi_init(dev, PORT_D);
	} else if (HAS_PCH_SPLIT(dev)) {
7894 7895
		int found;

7896
		if (I915_READ(HDMIB) & PORT_DETECTED) {
7897
			/* PCH SDVOB multiplex with HDMIB */
7898
			found = intel_sdvo_init(dev, PCH_SDVOB, true);
7899
			if (!found)
7900
				intel_hdmi_init(dev, HDMIB, PORT_B);
7901
			if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7902
				intel_dp_init(dev, PCH_DP_B, PORT_B);
7903 7904 7905
		}

		if (I915_READ(HDMIC) & PORT_DETECTED)
7906
			intel_hdmi_init(dev, HDMIC, PORT_C);
7907

7908
		if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
7909
			intel_hdmi_init(dev, HDMID, PORT_D);
7910

7911
		if (I915_READ(PCH_DP_C) & DP_DETECTED)
7912
			intel_dp_init(dev, PCH_DP_C, PORT_C);
7913

7914
		if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7915
			intel_dp_init(dev, PCH_DP_D, PORT_D);
7916 7917 7918
	} else if (IS_VALLEYVIEW(dev)) {
		int found;

7919 7920 7921 7922
		/* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
		if (I915_READ(DP_C) & DP_DETECTED)
			intel_dp_init(dev, DP_C, PORT_C);

7923 7924 7925 7926
		if (I915_READ(SDVOB) & PORT_DETECTED) {
			/* SDVOB multiplex with HDMIB */
			found = intel_sdvo_init(dev, SDVOB, true);
			if (!found)
7927
				intel_hdmi_init(dev, SDVOB, PORT_B);
7928
			if (!found && (I915_READ(DP_B) & DP_DETECTED))
7929
				intel_dp_init(dev, DP_B, PORT_B);
7930 7931 7932
		}

		if (I915_READ(SDVOC) & PORT_DETECTED)
7933
			intel_hdmi_init(dev, SDVOC, PORT_C);
7934

7935
	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7936
		bool found = false;
7937

7938
		if (I915_READ(SDVOB) & SDVO_DETECTED) {
7939
			DRM_DEBUG_KMS("probing SDVOB\n");
7940
			found = intel_sdvo_init(dev, SDVOB, true);
7941 7942
			if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
				DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7943
				intel_hdmi_init(dev, SDVOB, PORT_B);
7944
			}
7945

7946 7947
			if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
				DRM_DEBUG_KMS("probing DP_B\n");
7948
				intel_dp_init(dev, DP_B, PORT_B);
7949
			}
7950
		}
7951 7952 7953

		/* Before G4X SDVOC doesn't have its own detect register */

7954 7955
		if (I915_READ(SDVOB) & SDVO_DETECTED) {
			DRM_DEBUG_KMS("probing SDVOC\n");
7956
			found = intel_sdvo_init(dev, SDVOC, false);
7957
		}
7958 7959 7960

		if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {

7961 7962
			if (SUPPORTS_INTEGRATED_HDMI(dev)) {
				DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7963
				intel_hdmi_init(dev, SDVOC, PORT_C);
7964 7965 7966
			}
			if (SUPPORTS_INTEGRATED_DP(dev)) {
				DRM_DEBUG_KMS("probing DP_C\n");
7967
				intel_dp_init(dev, DP_C, PORT_C);
7968
			}
7969
		}
7970

7971 7972 7973
		if (SUPPORTS_INTEGRATED_DP(dev) &&
		    (I915_READ(DP_D) & DP_DETECTED)) {
			DRM_DEBUG_KMS("probing DP_D\n");
7974
			intel_dp_init(dev, DP_D, PORT_D);
7975
		}
7976
	} else if (IS_GEN2(dev))
7977 7978
		intel_dvo_init(dev);

7979
	if (SUPPORTS_TV(dev))
7980 7981
		intel_tv_init(dev);

7982 7983 7984
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		encoder->base.possible_crtcs = encoder->crtc_mask;
		encoder->base.possible_clones =
7985
			intel_encoder_clones(encoder);
7986
	}
7987

7988
	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7989
		ironlake_init_pch_refclk(dev);
7990 7991 7992 7993 7994 7995 7996
}

static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
{
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);

	drm_framebuffer_cleanup(fb);
7997
	drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7998 7999 8000 8001 8002

	kfree(intel_fb);
}

static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8003
						struct drm_file *file,
8004 8005 8006
						unsigned int *handle)
{
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8007
	struct drm_i915_gem_object *obj = intel_fb->obj;
8008

8009
	return drm_gem_handle_create(file, &obj->base, handle);
8010 8011 8012 8013 8014 8015 8016
}

static const struct drm_framebuffer_funcs intel_fb_funcs = {
	.destroy = intel_user_framebuffer_destroy,
	.create_handle = intel_user_framebuffer_create_handle,
};

8017 8018
int intel_framebuffer_init(struct drm_device *dev,
			   struct intel_framebuffer *intel_fb,
8019
			   struct drm_mode_fb_cmd2 *mode_cmd,
8020
			   struct drm_i915_gem_object *obj)
8021 8022 8023
{
	int ret;

8024
	if (obj->tiling_mode == I915_TILING_Y)
8025 8026
		return -EINVAL;

8027
	if (mode_cmd->pitches[0] & 63)
8028 8029
		return -EINVAL;

8030
	switch (mode_cmd->pixel_format) {
8031 8032 8033
	case DRM_FORMAT_RGB332:
	case DRM_FORMAT_RGB565:
	case DRM_FORMAT_XRGB8888:
8034
	case DRM_FORMAT_XBGR8888:
8035 8036 8037
	case DRM_FORMAT_ARGB8888:
	case DRM_FORMAT_XRGB2101010:
	case DRM_FORMAT_ARGB2101010:
8038
		/* RGB formats are common across chipsets */
8039
		break;
8040 8041 8042 8043
	case DRM_FORMAT_YUYV:
	case DRM_FORMAT_UYVY:
	case DRM_FORMAT_YVYU:
	case DRM_FORMAT_VYUY:
8044 8045
		break;
	default:
8046 8047
		DRM_DEBUG_KMS("unsupported pixel format %u\n",
				mode_cmd->pixel_format);
8048 8049 8050
		return -EINVAL;
	}

8051 8052 8053 8054 8055 8056 8057 8058 8059 8060 8061 8062 8063 8064
	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
	if (ret) {
		DRM_ERROR("framebuffer init failed %d\n", ret);
		return ret;
	}

	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
	intel_fb->obj = obj;
	return 0;
}

static struct drm_framebuffer *
intel_user_framebuffer_create(struct drm_device *dev,
			      struct drm_file *filp,
8065
			      struct drm_mode_fb_cmd2 *mode_cmd)
8066
{
8067
	struct drm_i915_gem_object *obj;
8068

8069 8070
	obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
						mode_cmd->handles[0]));
8071
	if (&obj->base == NULL)
8072
		return ERR_PTR(-ENOENT);
8073

8074
	return intel_framebuffer_create(dev, mode_cmd, obj);
8075 8076 8077 8078
}

static const struct drm_mode_config_funcs intel_mode_funcs = {
	.fb_create = intel_user_framebuffer_create,
8079
	.output_poll_changed = intel_fb_output_poll_changed,
8080 8081
};

8082 8083 8084 8085 8086 8087
/* Set up chip specific display functions */
static void intel_init_display(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* We always want a DPMS function */
8088 8089 8090 8091
	if (IS_HASWELL(dev)) {
		dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
		dev_priv->display.crtc_enable = ironlake_crtc_enable;
		dev_priv->display.crtc_disable = ironlake_crtc_disable;
8092
		dev_priv->display.off = haswell_crtc_off;
8093 8094
		dev_priv->display.update_plane = ironlake_update_plane;
	} else if (HAS_PCH_SPLIT(dev)) {
8095
		dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8096 8097
		dev_priv->display.crtc_enable = ironlake_crtc_enable;
		dev_priv->display.crtc_disable = ironlake_crtc_disable;
8098
		dev_priv->display.off = ironlake_crtc_off;
8099
		dev_priv->display.update_plane = ironlake_update_plane;
8100 8101
	} else {
		dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8102 8103
		dev_priv->display.crtc_enable = i9xx_crtc_enable;
		dev_priv->display.crtc_disable = i9xx_crtc_disable;
8104
		dev_priv->display.off = i9xx_crtc_off;
8105
		dev_priv->display.update_plane = i9xx_update_plane;
8106
	}
8107 8108

	/* Returns the core display clock speed */
8109 8110 8111 8112
	if (IS_VALLEYVIEW(dev))
		dev_priv->display.get_display_clock_speed =
			valleyview_get_display_clock_speed;
	else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8113 8114 8115 8116 8117
		dev_priv->display.get_display_clock_speed =
			i945_get_display_clock_speed;
	else if (IS_I915G(dev))
		dev_priv->display.get_display_clock_speed =
			i915_get_display_clock_speed;
8118
	else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8119 8120 8121 8122 8123 8124 8125 8126
		dev_priv->display.get_display_clock_speed =
			i9xx_misc_get_display_clock_speed;
	else if (IS_I915GM(dev))
		dev_priv->display.get_display_clock_speed =
			i915gm_get_display_clock_speed;
	else if (IS_I865G(dev))
		dev_priv->display.get_display_clock_speed =
			i865_get_display_clock_speed;
8127
	else if (IS_I85X(dev))
8128 8129 8130 8131 8132 8133
		dev_priv->display.get_display_clock_speed =
			i855_get_display_clock_speed;
	else /* 852, 830 */
		dev_priv->display.get_display_clock_speed =
			i830_get_display_clock_speed;

8134
	if (HAS_PCH_SPLIT(dev)) {
8135
		if (IS_GEN5(dev)) {
8136
			dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8137
			dev_priv->display.write_eld = ironlake_write_eld;
8138
		} else if (IS_GEN6(dev)) {
8139
			dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8140
			dev_priv->display.write_eld = ironlake_write_eld;
8141 8142 8143
		} else if (IS_IVYBRIDGE(dev)) {
			/* FIXME: detect B0+ stepping and use auto training */
			dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8144
			dev_priv->display.write_eld = ironlake_write_eld;
8145 8146
		} else if (IS_HASWELL(dev)) {
			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8147
			dev_priv->display.write_eld = haswell_write_eld;
8148 8149
		} else
			dev_priv->display.update_wm = NULL;
8150
	} else if (IS_G4X(dev)) {
8151
		dev_priv->display.write_eld = g4x_write_eld;
8152
	}
8153 8154 8155 8156 8157 8158 8159 8160 8161 8162 8163 8164 8165 8166 8167 8168 8169 8170 8171 8172 8173

	/* Default just returns -ENODEV to indicate unsupported */
	dev_priv->display.queue_flip = intel_default_queue_flip;

	switch (INTEL_INFO(dev)->gen) {
	case 2:
		dev_priv->display.queue_flip = intel_gen2_queue_flip;
		break;

	case 3:
		dev_priv->display.queue_flip = intel_gen3_queue_flip;
		break;

	case 4:
	case 5:
		dev_priv->display.queue_flip = intel_gen4_queue_flip;
		break;

	case 6:
		dev_priv->display.queue_flip = intel_gen6_queue_flip;
		break;
8174 8175 8176
	case 7:
		dev_priv->display.queue_flip = intel_gen7_queue_flip;
		break;
8177
	}
8178 8179
}

8180 8181 8182 8183 8184
/*
 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
 * resume, or other times.  This quirk makes sure that's the case for
 * affected systems.
 */
8185
static void quirk_pipea_force(struct drm_device *dev)
8186 8187 8188 8189
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8190
	DRM_INFO("applying pipe a force quirk\n");
8191 8192
}

8193 8194 8195 8196 8197 8198 8199
/*
 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
 */
static void quirk_ssc_force_disable(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8200
	DRM_INFO("applying lvds SSC disable quirk\n");
8201 8202
}

8203
/*
8204 8205
 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
 * brightness value
8206 8207 8208 8209 8210
 */
static void quirk_invert_brightness(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8211
	DRM_INFO("applying inverted panel brightness quirk\n");
8212 8213
}

8214 8215 8216 8217 8218 8219 8220
struct intel_quirk {
	int device;
	int subsystem_vendor;
	int subsystem_device;
	void (*hook)(struct drm_device *dev);
};

8221
static struct intel_quirk intel_quirks[] = {
8222
	/* HP Mini needs pipe A force quirk (LP: #322104) */
8223
	{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8224 8225 8226 8227 8228 8229 8230 8231 8232 8233

	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },

	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },

	/* 855 & before need to leave pipe A & dpll A up */
	{ 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8234
	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8235 8236 8237

	/* Lenovo U160 cannot use SSC on LVDS */
	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8238 8239 8240

	/* Sony Vaio Y cannot use SSC on LVDS */
	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8241 8242 8243

	/* Acer Aspire 5734Z must invert backlight brightness */
	{ 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8244 8245 8246 8247 8248 8249 8250 8251 8252 8253 8254 8255 8256 8257 8258 8259 8260 8261 8262
};

static void intel_init_quirks(struct drm_device *dev)
{
	struct pci_dev *d = dev->pdev;
	int i;

	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
		struct intel_quirk *q = &intel_quirks[i];

		if (d->device == q->device &&
		    (d->subsystem_vendor == q->subsystem_vendor ||
		     q->subsystem_vendor == PCI_ANY_ID) &&
		    (d->subsystem_device == q->subsystem_device ||
		     q->subsystem_device == PCI_ANY_ID))
			q->hook(dev);
	}
}

8263 8264 8265 8266 8267 8268 8269 8270 8271 8272 8273 8274 8275
/* Disable the VGA plane that we never use */
static void i915_disable_vga(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u8 sr1;
	u32 vga_reg;

	if (HAS_PCH_SPLIT(dev))
		vga_reg = CPU_VGACNTRL;
	else
		vga_reg = VGACNTRL;

	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8276
	outb(SR01, VGA_SR_INDEX);
8277 8278 8279 8280 8281 8282 8283 8284 8285
	sr1 = inb(VGA_SR_DATA);
	outb(sr1 | 1<<5, VGA_SR_DATA);
	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
	udelay(300);

	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
	POSTING_READ(vga_reg);
}

8286 8287
void intel_modeset_init_hw(struct drm_device *dev)
{
8288 8289 8290 8291 8292
	/* We attempt to init the necessary power wells early in the initialization
	 * time, so the subsystems that expect power to be enabled can work.
	 */
	intel_init_power_wells(dev);

8293 8294
	intel_prepare_ddi(dev);

8295 8296
	intel_init_clock_gating(dev);

8297
	mutex_lock(&dev->struct_mutex);
8298
	intel_enable_gt_powersave(dev);
8299
	mutex_unlock(&dev->struct_mutex);
8300 8301
}

8302 8303
void intel_modeset_init(struct drm_device *dev)
{
8304
	struct drm_i915_private *dev_priv = dev->dev_private;
8305
	int i, ret;
8306 8307 8308 8309 8310 8311

	drm_mode_config_init(dev);

	dev->mode_config.min_width = 0;
	dev->mode_config.min_height = 0;

8312 8313 8314
	dev->mode_config.preferred_depth = 24;
	dev->mode_config.prefer_shadow = 1;

8315
	dev->mode_config.funcs = &intel_mode_funcs;
8316

8317 8318
	intel_init_quirks(dev);

8319 8320
	intel_init_pm(dev);

8321 8322
	intel_init_display(dev);

8323 8324 8325 8326
	if (IS_GEN2(dev)) {
		dev->mode_config.max_width = 2048;
		dev->mode_config.max_height = 2048;
	} else if (IS_GEN3(dev)) {
8327 8328
		dev->mode_config.max_width = 4096;
		dev->mode_config.max_height = 4096;
8329
	} else {
8330 8331
		dev->mode_config.max_width = 8192;
		dev->mode_config.max_height = 8192;
8332
	}
8333
	dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8334

8335
	DRM_DEBUG_KMS("%d display pipe%s available.\n",
8336
		      dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8337

8338
	for (i = 0; i < dev_priv->num_pipe; i++) {
8339
		intel_crtc_init(dev, i);
8340 8341 8342
		ret = intel_plane_init(dev, i);
		if (ret)
			DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8343 8344
	}

8345
	intel_cpu_pll_init(dev);
8346 8347
	intel_pch_pll_init(dev);

8348 8349
	/* Just disable it once at startup */
	i915_disable_vga(dev);
8350
	intel_setup_outputs(dev);
8351 8352
}

8353 8354 8355 8356 8357 8358 8359 8360 8361
static void
intel_connector_break_all_links(struct intel_connector *connector)
{
	connector->base.dpms = DRM_MODE_DPMS_OFF;
	connector->base.encoder = NULL;
	connector->encoder->connectors_active = false;
	connector->encoder->base.crtc = NULL;
}

8362 8363 8364 8365 8366 8367 8368 8369 8370 8371 8372 8373 8374 8375 8376 8377 8378 8379 8380 8381 8382 8383 8384 8385 8386 8387 8388
static void intel_enable_pipe_a(struct drm_device *dev)
{
	struct intel_connector *connector;
	struct drm_connector *crt = NULL;
	struct intel_load_detect_pipe load_detect_temp;

	/* We can't just switch on the pipe A, we need to set things up with a
	 * proper mode and output configuration. As a gross hack, enable pipe A
	 * by enabling the load detect pipe once. */
	list_for_each_entry(connector,
			    &dev->mode_config.connector_list,
			    base.head) {
		if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
			crt = &connector->base;
			break;
		}
	}

	if (!crt)
		return;

	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
		intel_release_load_detect_pipe(crt, &load_detect_temp);


}

8389 8390 8391 8392 8393 8394 8395 8396 8397 8398 8399 8400 8401 8402 8403 8404 8405 8406 8407 8408 8409 8410 8411 8412 8413 8414 8415 8416 8417 8418 8419 8420 8421 8422 8423 8424 8425 8426 8427 8428 8429 8430 8431 8432 8433 8434 8435 8436
static void intel_sanitize_crtc(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 reg, val;

	/* Clear any frame start delays used for debugging left by the BIOS */
	reg = PIPECONF(crtc->pipe);
	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);

	/* We need to sanitize the plane -> pipe mapping first because this will
	 * disable the crtc (and hence change the state) if it is wrong. */
	if (!HAS_PCH_SPLIT(dev)) {
		struct intel_connector *connector;
		bool plane;

		reg = DSPCNTR(crtc->plane);
		val = I915_READ(reg);

		if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
		    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
			goto ok;

		DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
			      crtc->base.base.id);

		/* Pipe has the wrong plane attached and the plane is active.
		 * Temporarily change the plane mapping and disable everything
		 * ...  */
		plane = crtc->plane;
		crtc->plane = !plane;
		dev_priv->display.crtc_disable(&crtc->base);
		crtc->plane = plane;

		/* ... and break all links. */
		list_for_each_entry(connector, &dev->mode_config.connector_list,
				    base.head) {
			if (connector->encoder->base.crtc != &crtc->base)
				continue;

			intel_connector_break_all_links(connector);
		}

		WARN_ON(crtc->active);
		crtc->base.enabled = false;
	}
ok:

8437 8438 8439 8440 8441 8442 8443 8444 8445
	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
	    crtc->pipe == PIPE_A && !crtc->active) {
		/* BIOS forgot to enable pipe A, this mostly happens after
		 * resume. Force-enable the pipe to fix this, the update_dpms
		 * call below we restore the pipe to the right state, but leave
		 * the required bits on. */
		intel_enable_pipe_a(dev);
	}

8446 8447 8448 8449 8450 8451 8452 8453 8454 8455 8456 8457 8458 8459 8460 8461 8462 8463 8464 8465 8466 8467 8468 8469 8470 8471 8472 8473 8474 8475 8476 8477 8478 8479 8480 8481 8482 8483 8484 8485 8486 8487 8488 8489 8490 8491 8492 8493 8494 8495 8496 8497 8498 8499 8500 8501 8502 8503 8504 8505 8506 8507 8508 8509 8510 8511 8512 8513 8514 8515 8516 8517 8518 8519 8520 8521 8522 8523 8524 8525 8526 8527 8528 8529 8530 8531 8532 8533 8534 8535 8536 8537 8538 8539 8540 8541 8542 8543 8544 8545 8546
	/* Adjust the state of the output pipe according to whether we
	 * have active connectors/encoders. */
	intel_crtc_update_dpms(&crtc->base);

	if (crtc->active != crtc->base.enabled) {
		struct intel_encoder *encoder;

		/* This can happen either due to bugs in the get_hw_state
		 * functions or because the pipe is force-enabled due to the
		 * pipe A quirk. */
		DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
			      crtc->base.base.id,
			      crtc->base.enabled ? "enabled" : "disabled",
			      crtc->active ? "enabled" : "disabled");

		crtc->base.enabled = crtc->active;

		/* Because we only establish the connector -> encoder ->
		 * crtc links if something is active, this means the
		 * crtc is now deactivated. Break the links. connector
		 * -> encoder links are only establish when things are
		 *  actually up, hence no need to break them. */
		WARN_ON(crtc->active);

		for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
			WARN_ON(encoder->connectors_active);
			encoder->base.crtc = NULL;
		}
	}
}

static void intel_sanitize_encoder(struct intel_encoder *encoder)
{
	struct intel_connector *connector;
	struct drm_device *dev = encoder->base.dev;

	/* We need to check both for a crtc link (meaning that the
	 * encoder is active and trying to read from a pipe) and the
	 * pipe itself being active. */
	bool has_active_crtc = encoder->base.crtc &&
		to_intel_crtc(encoder->base.crtc)->active;

	if (encoder->connectors_active && !has_active_crtc) {
		DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
			      encoder->base.base.id,
			      drm_get_encoder_name(&encoder->base));

		/* Connector is active, but has no active pipe. This is
		 * fallout from our resume register restoring. Disable
		 * the encoder manually again. */
		if (encoder->base.crtc) {
			DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
				      encoder->base.base.id,
				      drm_get_encoder_name(&encoder->base));
			encoder->disable(encoder);
		}

		/* Inconsistent output/port/pipe state happens presumably due to
		 * a bug in one of the get_hw_state functions. Or someplace else
		 * in our code, like the register restore mess on resume. Clamp
		 * things to off as a safer default. */
		list_for_each_entry(connector,
				    &dev->mode_config.connector_list,
				    base.head) {
			if (connector->encoder != encoder)
				continue;

			intel_connector_break_all_links(connector);
		}
	}
	/* Enabled encoders without active connectors will be fixed in
	 * the crtc fixup. */
}

/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
 * and i915 state tracking structures. */
void intel_modeset_setup_hw_state(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe;
	u32 tmp;
	struct intel_crtc *crtc;
	struct intel_encoder *encoder;
	struct intel_connector *connector;

	for_each_pipe(pipe) {
		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);

		tmp = I915_READ(PIPECONF(pipe));
		if (tmp & PIPECONF_ENABLE)
			crtc->active = true;
		else
			crtc->active = false;

		crtc->base.enabled = crtc->active;

		DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
			      crtc->base.base.id,
			      crtc->active ? "enabled" : "disabled");
	}

8547 8548 8549
	if (IS_HASWELL(dev))
		intel_ddi_setup_hw_pll_state(dev);

8550 8551 8552 8553 8554 8555 8556 8557 8558 8559 8560 8561 8562 8563 8564 8565 8566 8567 8568 8569 8570 8571 8572 8573 8574 8575 8576 8577 8578 8579 8580 8581 8582 8583 8584 8585 8586 8587 8588 8589 8590 8591 8592 8593 8594
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		pipe = 0;

		if (encoder->get_hw_state(encoder, &pipe)) {
			encoder->base.crtc =
				dev_priv->pipe_to_crtc_mapping[pipe];
		} else {
			encoder->base.crtc = NULL;
		}

		encoder->connectors_active = false;
		DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
			      encoder->base.base.id,
			      drm_get_encoder_name(&encoder->base),
			      encoder->base.crtc ? "enabled" : "disabled",
			      pipe);
	}

	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {
		if (connector->get_hw_state(connector)) {
			connector->base.dpms = DRM_MODE_DPMS_ON;
			connector->encoder->connectors_active = true;
			connector->base.encoder = &connector->encoder->base;
		} else {
			connector->base.dpms = DRM_MODE_DPMS_OFF;
			connector->base.encoder = NULL;
		}
		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
			      connector->base.base.id,
			      drm_get_connector_name(&connector->base),
			      connector->base.encoder ? "enabled" : "disabled");
	}

	/* HW state is read out, now we need to sanitize this mess. */
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		intel_sanitize_encoder(encoder);
	}

	for_each_pipe(pipe) {
		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		intel_sanitize_crtc(crtc);
	}
8595 8596

	intel_modeset_update_staged_output_state(dev);
8597 8598

	intel_modeset_check_state(dev);
8599 8600
}

8601 8602
void intel_modeset_gem_init(struct drm_device *dev)
{
8603
	intel_modeset_init_hw(dev);
8604 8605

	intel_setup_overlay(dev);
8606 8607

	intel_modeset_setup_hw_state(dev);
8608 8609 8610 8611
}

void intel_modeset_cleanup(struct drm_device *dev)
{
8612 8613 8614 8615
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	struct intel_crtc *intel_crtc;

8616
	drm_kms_helper_poll_fini(dev);
8617 8618
	mutex_lock(&dev->struct_mutex);

J
Jesse Barnes 已提交
8619 8620 8621
	intel_unregister_dsm_handler();


8622 8623 8624 8625 8626 8627
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		/* Skip inactive CRTCs */
		if (!crtc->fb)
			continue;

		intel_crtc = to_intel_crtc(crtc);
8628
		intel_increase_pllclock(crtc);
8629 8630
	}

8631
	intel_disable_fbc(dev);
8632

8633
	intel_disable_gt_powersave(dev);
8634

8635 8636
	ironlake_teardown_rc6(dev);

J
Jesse Barnes 已提交
8637 8638 8639
	if (IS_VALLEYVIEW(dev))
		vlv_init_dpio(dev);

8640 8641
	mutex_unlock(&dev->struct_mutex);

8642 8643 8644 8645
	/* Disable the irq before mode object teardown, for the irq might
	 * enqueue unpin/hotplug work. */
	drm_irq_uninstall(dev);
	cancel_work_sync(&dev_priv->hotplug_work);
8646
	cancel_work_sync(&dev_priv->rps.work);
8647

8648 8649 8650
	/* flush any delayed tasks or pending work */
	flush_scheduled_work();

8651 8652 8653
	drm_mode_config_cleanup(dev);
}

8654 8655 8656
/*
 * Return which encoder is currently attached for connector.
 */
8657
struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8658
{
8659 8660
	return &intel_attached_encoder(connector)->base;
}
8661

8662 8663 8664 8665 8666 8667
void intel_connector_attach_encoder(struct intel_connector *connector,
				    struct intel_encoder *encoder)
{
	connector->encoder = encoder;
	drm_mode_connector_attach_encoder(&connector->base,
					  &encoder->base);
8668
}
8669 8670 8671 8672 8673 8674 8675 8676 8677 8678 8679 8680 8681 8682 8683 8684 8685

/*
 * set vga decode state - true == enable VGA decode
 */
int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u16 gmch_ctrl;

	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
	if (state)
		gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
	else
		gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
	pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
	return 0;
}
8686 8687 8688 8689 8690 8691 8692 8693 8694 8695

#ifdef CONFIG_DEBUG_FS
#include <linux/seq_file.h>

struct intel_display_error_state {
	struct intel_cursor_error_state {
		u32 control;
		u32 position;
		u32 base;
		u32 size;
8696
	} cursor[I915_MAX_PIPES];
8697 8698 8699 8700 8701 8702 8703 8704 8705 8706 8707

	struct intel_pipe_error_state {
		u32 conf;
		u32 source;

		u32 htotal;
		u32 hblank;
		u32 hsync;
		u32 vtotal;
		u32 vblank;
		u32 vsync;
8708
	} pipe[I915_MAX_PIPES];
8709 8710 8711 8712 8713 8714 8715 8716 8717

	struct intel_plane_error_state {
		u32 control;
		u32 stride;
		u32 size;
		u32 pos;
		u32 addr;
		u32 surface;
		u32 tile_offset;
8718
	} plane[I915_MAX_PIPES];
8719 8720 8721 8722 8723
};

struct intel_display_error_state *
intel_display_capture_error_state(struct drm_device *dev)
{
8724
	drm_i915_private_t *dev_priv = dev->dev_private;
8725 8726 8727 8728 8729 8730 8731
	struct intel_display_error_state *error;
	int i;

	error = kmalloc(sizeof(*error), GFP_ATOMIC);
	if (error == NULL)
		return NULL;

8732
	for_each_pipe(i) {
8733 8734 8735 8736 8737 8738 8739
		error->cursor[i].control = I915_READ(CURCNTR(i));
		error->cursor[i].position = I915_READ(CURPOS(i));
		error->cursor[i].base = I915_READ(CURBASE(i));

		error->plane[i].control = I915_READ(DSPCNTR(i));
		error->plane[i].stride = I915_READ(DSPSTRIDE(i));
		error->plane[i].size = I915_READ(DSPSIZE(i));
8740
		error->plane[i].pos = I915_READ(DSPPOS(i));
8741 8742 8743 8744 8745 8746 8747 8748 8749 8750 8751 8752 8753 8754 8755 8756 8757 8758 8759 8760 8761 8762 8763 8764
		error->plane[i].addr = I915_READ(DSPADDR(i));
		if (INTEL_INFO(dev)->gen >= 4) {
			error->plane[i].surface = I915_READ(DSPSURF(i));
			error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
		}

		error->pipe[i].conf = I915_READ(PIPECONF(i));
		error->pipe[i].source = I915_READ(PIPESRC(i));
		error->pipe[i].htotal = I915_READ(HTOTAL(i));
		error->pipe[i].hblank = I915_READ(HBLANK(i));
		error->pipe[i].hsync = I915_READ(HSYNC(i));
		error->pipe[i].vtotal = I915_READ(VTOTAL(i));
		error->pipe[i].vblank = I915_READ(VBLANK(i));
		error->pipe[i].vsync = I915_READ(VSYNC(i));
	}

	return error;
}

void
intel_display_print_error_state(struct seq_file *m,
				struct drm_device *dev,
				struct intel_display_error_state *error)
{
8765
	drm_i915_private_t *dev_priv = dev->dev_private;
8766 8767
	int i;

8768 8769
	seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
	for_each_pipe(i) {
8770 8771 8772 8773 8774 8775 8776 8777 8778 8779 8780 8781 8782 8783 8784 8785 8786 8787 8788 8789 8790 8791 8792 8793 8794 8795 8796 8797
		seq_printf(m, "Pipe [%d]:\n", i);
		seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
		seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
		seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
		seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
		seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
		seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
		seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
		seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);

		seq_printf(m, "Plane [%d]:\n", i);
		seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
		seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
		seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
		seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
		seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
		if (INTEL_INFO(dev)->gen >= 4) {
			seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
			seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
		}

		seq_printf(m, "Cursor [%d]:\n", i);
		seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
		seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
		seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
	}
}
#endif
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