* lr_valid will be copied from processor to emulator when:
    * sc falied &&
    * processor's lr_valid is set to false &&
    * emulator's lr_valid is set to true

* It will make snapshot more precise
* NEMU that includes commit d4efeb7 is needed to use difftest

**NaiveTLToAXI4 has not been finished yet**.
None of them fully support tilelink.
FakeTLLLC supports:
* AcquireBlock on channel A for permission acquire
* ReleaseData on channel C for dcache eviction and writeback

It's supposed to work with L1 dcache.
Now, we still don't have a fully functional TL to AXI converter,
starving for diplomacy!!!

The goal of this commit is to remove 'implict val p: XSConfig' in our code becasue it's inconvenient

* this helps to recude about 40k lines of code, and improve the host
  time spent from 89s to 93s for running microbench with test input on
  9900k

ExcitingUtils provides some API to display and check connections between source and sinks

* Remove assert(), since they can be done at cpp files if needed
* Calculate `(GTimer() >= disp_begin) && (GTimer() <= disp_end)` at the
  top level module only once, and wire such bool signal to where XSLog()
  is called. This can reduce the number of instances of counter created
  while GTimer() is callled.
* Remove xsLogLevel. It seems meaningless, since we either need all logs
  for debugging, or no logs for running tests only.
* With the above optimizion, running microbench with test input spends
  120s on 9900k with log completely disabled (comment out the log code),
  but only spends 147s on 9900k with log enabled.

change 'PALY' to 'PLAY'