- 05 11月, 2020 1 次提交
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由 LinJiawei 提交于
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- 28 9月, 2020 1 次提交
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由 William Wang 提交于
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- 27 9月, 2020 1 次提交
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由 William Wang 提交于
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- 25 9月, 2020 1 次提交
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由 William Wang 提交于
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- 18 9月, 2020 2 次提交
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由 William Wang 提交于
* lr_valid will be copied from processor to emulator when: * sc falied && * processor's lr_valid is set to false && * emulator's lr_valid is set to true
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由 William Wang 提交于
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- 17 9月, 2020 1 次提交
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由 Allen 提交于
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- 14 9月, 2020 1 次提交
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由 William Wang 提交于
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- 12 9月, 2020 1 次提交
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由 William Wang 提交于
* It will make snapshot more precise * NEMU that includes commit d4efeb7 is needed to use difftest
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- 10 9月, 2020 1 次提交
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由 Yinan Xu 提交于
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- 30 8月, 2020 1 次提交
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由 linjiawei 提交于
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- 29 8月, 2020 1 次提交
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由 LinJiawei 提交于
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- 28 8月, 2020 1 次提交
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由 jinyue110 提交于
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- 21 8月, 2020 2 次提交
- 19 8月, 2020 2 次提交
- 17 8月, 2020 2 次提交
- 16 8月, 2020 2 次提交
- 13 8月, 2020 1 次提交
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由 Allen 提交于
**NaiveTLToAXI4 has not been finished yet**. None of them fully support tilelink. FakeTLLLC supports: * AcquireBlock on channel A for permission acquire * ReleaseData on channel C for dcache eviction and writeback It's supposed to work with L1 dcache. Now, we still don't have a fully functional TL to AXI converter, starving for diplomacy!!!
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- 11 8月, 2020 2 次提交
- 10 8月, 2020 1 次提交
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由 LinJiawei 提交于
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- 05 8月, 2020 1 次提交
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由 LinJiawei 提交于
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- 04 8月, 2020 1 次提交
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由 LinJiawei 提交于
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- 02 8月, 2020 4 次提交
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由 LinJiawei 提交于
The goal of this commit is to remove 'implict val p: XSConfig' in our code becasue it's inconvenient
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由 Zihao Yu 提交于
* this helps to recude about 40k lines of code, and improve the host time spent from 89s to 93s for running microbench with test input on 9900k
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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- 14 7月, 2020 2 次提交
- 13 7月, 2020 2 次提交
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由 LinJiawei 提交于
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由 Zihao Yu 提交于
* Remove assert(), since they can be done at cpp files if needed * Calculate `(GTimer() >= disp_begin) && (GTimer() <= disp_end)` at the top level module only once, and wire such bool signal to where XSLog() is called. This can reduce the number of instances of counter created while GTimer() is callled. * Remove xsLogLevel. It seems meaningless, since we either need all logs for debugging, or no logs for running tests only. * With the above optimizion, running microbench with test input spends 120s on 9900k with log completely disabled (comment out the log code), but only spends 147s on 9900k with log enabled.
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- 11 7月, 2020 1 次提交
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由 Yinan Xu 提交于
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- 09 7月, 2020 1 次提交
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由 LinJiawei 提交于
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- 29 6月, 2020 1 次提交
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由 William Wang 提交于
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- 27 6月, 2020 1 次提交
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由 LinJiawei 提交于
change 'PALY' to 'PLAY'
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- 25 6月, 2020 1 次提交
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由 LinJiawei 提交于
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