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提交 3e586e47 编写于 作者: L linjiawei
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diplomacy soc finish, use dummy core now

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Showing with 919 addition and 870 deletion
src/main/scala/gpu/GPU.scala
浏览文件 @ 3e586e47
package gpu
import chisel3._
import chisel3.util._
import bus.axi4._
import device.AXI4SlaveModule
import utils._
class PixelBundle extends Bundle {
val a = UInt(8.W)
val r = UInt(8.W)
val g = UInt(8.W)
val b = UInt(8.W)
}
/* struct texture {
* uint32_t pixels[TextureW * TextureH];
* } __attribute__((packed));
*/
class TextureLineBundle extends Bundle {
val pixels = Vec(8, new PixelBundle)
}
/* struct sprite {
* uint16_t texture, x, y;
* uint32_t display : 4;
* uint32_t z : 12;
* } __attribute__((packed));
*/
class SpriteBundle extends Bundle {
val z = UInt(12.W)
val display = UInt(4.W)
val y = UInt(16.W)
val x = UInt(16.W)
val texture = UInt(16.W)
}
trait GPUConst {
val BeatBytes = 4
val TextureW = 8
val TextureH = 8
val ColorBytes = 4
val TextureLineBytes = TextureW * ColorBytes
val TextureLineBeats = TextureLineBytes / BeatBytes
val TextureLineShift = log2Up(TextureLineBytes)
val TextureBytes = TextureLineBytes * TextureH
val TextureShift = log2Up(TextureBytes)
val TextureMaxNum = 65536 // 0 indicate the end
val TextureIdBits = log2Up(TextureMaxNum)
val TextureArrayBytes = TextureMaxNum * TextureBytes
val TextureBase = 0x60000000L - TextureArrayBytes * 2
def textureLineAddr(idx: UInt, line: UInt): UInt = TextureBase.U |
(idx(TextureIdBits - 1, 0) << TextureShift.U) |
(line(2, 0) << TextureLineShift.U)
val SpriteBase = TextureBase + TextureArrayBytes
val SpriteBytes = 8
val SpriteBeats = SpriteBytes / BeatBytes
val SpriteShift = log2Up(SpriteBytes)
def spriteAddr(idx: UInt): UInt = SpriteBase.U | (idx << SpriteShift.U)
val ScreenW = 400
val ScreenH = 300
val FrameBufBase = 0x40000000L
def fbAddr(x: UInt, y: UInt): UInt = {
assert(x < ScreenW.U && y < ScreenH.U)
FrameBufBase.U + ((y * ScreenW.U + x) << 2)
}
}
class GPUOutBundle extends Bundle {
// can use 32 bit after implementing burst
val metaData = new AXI4
val fb = new AXI4
}
class AXI4GPU extends AXI4SlaveModule(new AXI4Lite, new GPUOutBundle) with GPUConst {
val out = io.extra.get
// control registers
def index(addr: UInt) = (addr & 0xf.U) >> 2
val statIdx = 0
val ctrlIdx = 1
val statReg = Reg(UInt(32.W))
val ctrlReg = Reg(UInt(32.W))
def readReg(addr: UInt) = LookupTree(index(addr), List(
statIdx.U -> statReg,
ctrlIdx.U -> ctrlReg
))
in.r.bits.data := RegEnable(readReg(in.ar.bits.addr), in.ar.fire())
val wIdx = index(in.aw.bits.addr)
val wdata = genWdata(readReg(in.aw.bits.addr))
when (in.aw.fire()) {
when (wIdx === ctrlIdx.U) { ctrlReg := wdata }
}
val startCmd = ctrlReg(0) && !RegNext(ctrlReg(0))
val s_idle :: s_sprite_read :: s_texture_read :: s_render_line :: s_render_bwait :: Nil = Enum(5)
val state = RegInit(s_idle)
statReg := (state =/= s_idle)
out := DontCare
out.metaData.ar.bits.prot := AXI4Parameters.PROT_PRIVILEDGED
out.metaData.ar.bits.id := 0.U
out.metaData.ar.bits.size := "b10".U // 32 bit
out.metaData.ar.bits.burst := AXI4Parameters.BURST_INCR
out.metaData.ar.bits.lock := false.B
out.metaData.ar.bits.cache := 0.U
out.metaData.ar.bits.qos := 0.U
out.metaData.ar.bits.user := 0.U
out.fb.w.bits.last := false.B
out.fb.aw.bits := out.metaData.ar.bits
out.metaData.r.ready := false.B
val metaDataRwait = RegInit(false.B)
val spriteIdx = Counter(65536)
when (state === s_idle && startCmd) {
printf("GPU start!!!!\n");
state := s_sprite_read
spriteIdx.value := 0.U
}
val textureLineCnt = Counter(TextureH)
val spriteBufReg = Reg(Vec(SpriteBeats, UInt(32.W)))
val spriteBuf = spriteBufReg.asTypeOf(new SpriteBundle)
val spriteReadCnt = Counter(SpriteBeats)
when (state === s_sprite_read) {
out.metaData.ar.bits.addr := spriteAddr(spriteIdx.value)
out.metaData.ar.bits.len := (SpriteBeats - 1).U // 2 beats
out.metaData.r.ready := true.B
when (out.metaData.ar.fire()) { metaDataRwait := true.B }
when (out.metaData.r.fire()) {
spriteBufReg(spriteReadCnt.value) := out.metaData.r.bits.data
when (spriteReadCnt.inc()) {
metaDataRwait := false.B
textureLineCnt.value := 0.U
// since textureId is read at the first beat before,
// we can use a valid textureId here
val isEnd = spriteBuf.texture === 0.U
state := Mux(isEnd, s_idle, s_texture_read)
}
}
}
val textureLineBuf = Reg(Vec(TextureLineBeats, UInt(32.W)))
val textureLineReadCnt = Counter(TextureLineBeats)
when (state === s_texture_read) {
out.metaData.ar.bits.addr := textureLineAddr(spriteBuf.texture, textureLineCnt.value)
out.metaData.ar.bits.len := (TextureLineBeats - 1).U // 8 beats
out.metaData.r.ready := true.B
when (out.metaData.ar.fire()) { metaDataRwait := true.B }
when (out.metaData.r.fire()) {
textureLineBuf(textureLineReadCnt.value) := out.metaData.r.bits.data
when (textureLineReadCnt.inc()) {
metaDataRwait := false.B
state := s_render_line
}
}
}
val textureLineWriteCnt = Counter(TextureLineBeats)
val wSend = Wire(Bool())
out.fb.aw.bits.addr := fbAddr(x = spriteBuf.x, y = spriteBuf.y + textureLineCnt.value)
out.fb.aw.bits.len := (TextureLineBeats - 1).U // 8 beats
out.fb.w.bits.data := textureLineBuf(textureLineWriteCnt.value)
out.fb.w.bits.strb := 0xf.U
out.fb.w.bits.last := textureLineWriteCnt.value === (TextureLineBeats - 1).U
when (state === s_render_line) {
// FIXME: check the result of renderLineMask
//val renderLineMask = Cat(textureLineBuf.asTypeOf(new TextureLineBundle).pixels.map(
// c => Mux(c.a === 0.U, 0.U(4.W), 0xf.U(4.W))))
when (out.fb.w.fire()) { textureLineWriteCnt.inc() }
when (wSend) { state := s_render_bwait }
}
when (state === s_render_bwait) {
when (out.fb.b.fire()) {
val finishOneTexture = textureLineCnt.inc()
when (finishOneTexture) { spriteIdx.inc() }
state := Mux(finishOneTexture, s_sprite_read, s_texture_read)
}
}
out.metaData.ar.valid := BoolStopWatch(
(state === s_sprite_read || state === s_texture_read) && !metaDataRwait, out.metaData.ar.fire())
out.metaData.aw.valid := false.B
out.metaData.w.valid := false.B
out.metaData.b.ready := true.B
val awAck = BoolStopWatch(out.fb.aw.fire(), wSend)
val wAck = BoolStopWatch(out.fb.w.fire() && out.fb.w.bits.last, wSend)
wSend := (out.fb.aw.fire() && out.fb.w.fire() && out.fb.w.bits.last) || (awAck && wAck)
out.fb.aw.valid := (state === s_render_line) && !awAck
out.fb.w .valid := (state === s_render_line) && !wAck
out.fb.b.ready := BoolStopWatch(wSend, out.fb.b.fire())
out.fb.ar.valid := false.B
out.fb.r.ready := true.B
}
//package gpu
//
//import chisel3._
//import chisel3.util._
//
//import bus.axi4._
//import device.AXI4SlaveModule
//import utils._
//
//class PixelBundle extends Bundle {
// val a = UInt(8.W)
// val r = UInt(8.W)
// val g = UInt(8.W)
// val b = UInt(8.W)
//}
//
///* struct texture {
// * uint32_t pixels[TextureW * TextureH];
// * } __attribute__((packed));
// */
//class TextureLineBundle extends Bundle {
// val pixels = Vec(8, new PixelBundle)
//}
//
///* struct sprite {
// * uint16_t texture, x, y;
// * uint32_t display : 4;
// * uint32_t z : 12;
// * } __attribute__((packed));
// */
//class SpriteBundle extends Bundle {
// val z = UInt(12.W)
// val display = UInt(4.W)
// val y = UInt(16.W)
// val x = UInt(16.W)
// val texture = UInt(16.W)
//}
//
//trait GPUConst {
// val BeatBytes = 4
//
// val TextureW = 8
// val TextureH = 8
// val ColorBytes = 4
//
// val TextureLineBytes = TextureW * ColorBytes
// val TextureLineBeats = TextureLineBytes / BeatBytes
// val TextureLineShift = log2Up(TextureLineBytes)
// val TextureBytes = TextureLineBytes * TextureH
// val TextureShift = log2Up(TextureBytes)
// val TextureMaxNum = 65536 // 0 indicate the end
// val TextureIdBits = log2Up(TextureMaxNum)
// val TextureArrayBytes = TextureMaxNum * TextureBytes
// val TextureBase = 0x60000000L - TextureArrayBytes * 2
//
// def textureLineAddr(idx: UInt, line: UInt): UInt = TextureBase.U |
// (idx(TextureIdBits - 1, 0) << TextureShift.U) |
// (line(2, 0) << TextureLineShift.U)
//
// val SpriteBase = TextureBase + TextureArrayBytes
// val SpriteBytes = 8
// val SpriteBeats = SpriteBytes / BeatBytes
// val SpriteShift = log2Up(SpriteBytes)
// def spriteAddr(idx: UInt): UInt = SpriteBase.U | (idx << SpriteShift.U)
//
// val ScreenW = 400
// val ScreenH = 300
// val FrameBufBase = 0x40000000L
// def fbAddr(x: UInt, y: UInt): UInt = {
// assert(x < ScreenW.U && y < ScreenH.U)
// FrameBufBase.U + ((y * ScreenW.U + x) << 2)
// }
//}
//
//class GPUOutBundle extends Bundle {
// // can use 32 bit after implementing burst
// val metaData = new AXI4
// val fb = new AXI4
//}
//
//class AXI4GPU extends AXI4SlaveModule(new AXI4Lite, new GPUOutBundle) with GPUConst {
// val out = io.extra.get
//
// // control registers
// def index(addr: UInt) = (addr & 0xf.U) >> 2
// val statIdx = 0
// val ctrlIdx = 1
//
// val statReg = Reg(UInt(32.W))
// val ctrlReg = Reg(UInt(32.W))
//
// def readReg(addr: UInt) = LookupTree(index(addr), List(
// statIdx.U -> statReg,
// ctrlIdx.U -> ctrlReg
// ))
// in.r.bits.data := RegEnable(readReg(in.ar.bits.addr), in.ar.fire())
//
// val wIdx = index(in.aw.bits.addr)
// val wdata = genWdata(readReg(in.aw.bits.addr))
// when (in.aw.fire()) {
// when (wIdx === ctrlIdx.U) { ctrlReg := wdata }
// }
//
// val startCmd = ctrlReg(0) && !RegNext(ctrlReg(0))
//
// val s_idle :: s_sprite_read :: s_texture_read :: s_render_line :: s_render_bwait :: Nil = Enum(5)
// val state = RegInit(s_idle)
// statReg := (state =/= s_idle)
//
// out := DontCare
// out.metaData.ar.bits.prot := AXI4Parameters.PROT_PRIVILEDGED
// out.metaData.ar.bits.id := 0.U
// out.metaData.ar.bits.size := "b10".U // 32 bit
// out.metaData.ar.bits.burst := AXI4Parameters.BURST_INCR
// out.metaData.ar.bits.lock := false.B
// out.metaData.ar.bits.cache := 0.U
// out.metaData.ar.bits.qos := 0.U
// out.metaData.ar.bits.user := 0.U
// out.fb.w.bits.last := false.B
// out.fb.aw.bits := out.metaData.ar.bits
//
// out.metaData.r.ready := false.B
// val metaDataRwait = RegInit(false.B)
//
// val spriteIdx = Counter(65536)
// when (state === s_idle && startCmd) {
// printf("GPU start!!!!\n");
// state := s_sprite_read
// spriteIdx.value := 0.U
// }
//
// val textureLineCnt = Counter(TextureH)
//
// val spriteBufReg = Reg(Vec(SpriteBeats, UInt(32.W)))
// val spriteBuf = spriteBufReg.asTypeOf(new SpriteBundle)
// val spriteReadCnt = Counter(SpriteBeats)
// when (state === s_sprite_read) {
// out.metaData.ar.bits.addr := spriteAddr(spriteIdx.value)
// out.metaData.ar.bits.len := (SpriteBeats - 1).U // 2 beats
// out.metaData.r.ready := true.B
// when (out.metaData.ar.fire()) { metaDataRwait := true.B }
//
// when (out.metaData.r.fire()) {
// spriteBufReg(spriteReadCnt.value) := out.metaData.r.bits.data
// when (spriteReadCnt.inc()) {
// metaDataRwait := false.B
// textureLineCnt.value := 0.U
// // since textureId is read at the first beat before,
// // we can use a valid textureId here
// val isEnd = spriteBuf.texture === 0.U
// state := Mux(isEnd, s_idle, s_texture_read)
// }
// }
// }
//
// val textureLineBuf = Reg(Vec(TextureLineBeats, UInt(32.W)))
// val textureLineReadCnt = Counter(TextureLineBeats)
// when (state === s_texture_read) {
// out.metaData.ar.bits.addr := textureLineAddr(spriteBuf.texture, textureLineCnt.value)
// out.metaData.ar.bits.len := (TextureLineBeats - 1).U // 8 beats
// out.metaData.r.ready := true.B
// when (out.metaData.ar.fire()) { metaDataRwait := true.B }
//
// when (out.metaData.r.fire()) {
// textureLineBuf(textureLineReadCnt.value) := out.metaData.r.bits.data
// when (textureLineReadCnt.inc()) {
// metaDataRwait := false.B
// state := s_render_line
// }
// }
// }
//
// val textureLineWriteCnt = Counter(TextureLineBeats)
// val wSend = Wire(Bool())
// out.fb.aw.bits.addr := fbAddr(x = spriteBuf.x, y = spriteBuf.y + textureLineCnt.value)
// out.fb.aw.bits.len := (TextureLineBeats - 1).U // 8 beats
// out.fb.w.bits.data := textureLineBuf(textureLineWriteCnt.value)
// out.fb.w.bits.strb := 0xf.U
// out.fb.w.bits.last := textureLineWriteCnt.value === (TextureLineBeats - 1).U
// when (state === s_render_line) {
// // FIXME: check the result of renderLineMask
// //val renderLineMask = Cat(textureLineBuf.asTypeOf(new TextureLineBundle).pixels.map(
// // c => Mux(c.a === 0.U, 0.U(4.W), 0xf.U(4.W))))
//
// when (out.fb.w.fire()) { textureLineWriteCnt.inc() }
// when (wSend) { state := s_render_bwait }
// }
//
// when (state === s_render_bwait) {
// when (out.fb.b.fire()) {
// val finishOneTexture = textureLineCnt.inc()
// when (finishOneTexture) { spriteIdx.inc() }
// state := Mux(finishOneTexture, s_sprite_read, s_texture_read)
// }
// }
//
// out.metaData.ar.valid := BoolStopWatch(
// (state === s_sprite_read || state === s_texture_read) && !metaDataRwait, out.metaData.ar.fire())
// out.metaData.aw.valid := false.B
// out.metaData.w.valid := false.B
// out.metaData.b.ready := true.B
//
// val awAck = BoolStopWatch(out.fb.aw.fire(), wSend)
// val wAck = BoolStopWatch(out.fb.w.fire() && out.fb.w.bits.last, wSend)
// wSend := (out.fb.aw.fire() && out.fb.w.fire() && out.fb.w.bits.last) || (awAck && wAck)
//
// out.fb.aw.valid := (state === s_render_line) && !awAck
// out.fb.w .valid := (state === s_render_line) && !wAck
// out.fb.b.ready := BoolStopWatch(wSend, out.fb.b.fire())
// out.fb.ar.valid := false.B
// out.fb.r.ready := true.B
//}
src/main/scala/system/SoC.scala
浏览文件 @ 3e586e47
package system
import noop.{Cache, CacheConfig}
import bus.axi4.{AXI4, AXI4Lite, AXI4ToAXI4Lite}
import bus.simplebus._
import bus.tilelink.{NaiveTL1toN, MMIOTLToAXI4, TLCached}
import device.AXI4Timer
import chipsalliance.rocketchip.config.Parameters
import device.{AXI4Timer, TLTimer}
import chisel3._
import chisel3.util._
import chisel3.util.experimental.BoringUtils
import top.Parameters
import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp}
import freechips.rocketchip.tilelink.{TLFuzzer, TLIdentityNode, TLXbar}
import xiangshan.{HasXSParameter, XSCore}
......@@ -20,7 +17,7 @@ case class SoCParameters
)
trait HasSoCParameter extends HasXSParameter{
val soc = Parameters.get.socParameters
val soc = top.Parameters.get.socParameters
val EnableILA = soc.EnableILA
val HasL2cache = soc.HasL2Cache
val HasPrefetch = soc.HasPrefetch
......@@ -28,36 +25,79 @@ trait HasSoCParameter extends HasXSParameter{
class ILABundle extends Bundle {}
class XSSoc extends Module with HasSoCParameter {
val io = IO(new Bundle{
val mem = new TLCached(l1BusParams)
val mmio = new TLCached(l1BusParams)
val frontend = Flipped(new AXI4) //TODO: do we need it ?
val meip = Input(Bool())
val ila = if (env.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
})
val xsCore = Module(new XSCore)
class DummyCore()(implicit p: Parameters) extends LazyModule {
val mem = TLFuzzer(nOperations = 10)
val mmio = TLFuzzer(nOperations = 10)
io.frontend <> DontCare
lazy val module = new LazyModuleImp(this){
io.mem <> xsCore.io.mem
}
}
class XSSoc()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
private val xsCore = LazyModule(new DummyCore())
val addrSpace = List(
(0x40000000L, 0x40000000L), // external devices
(0x38000000L, 0x00010000L) // CLINT
)
val mmioXbar = Module(new NaiveTL1toN(addrSpace, xsCore.io.mem.params))
mmioXbar.io.in <> xsCore.io.mmio
// only mem and extDev visible externally
val mem = xsCore.mem
val extDev = TLIdentityNode()
val extDev = mmioXbar.io.out(0)
val clint = Module(new AXI4Timer(sim = !env.FPGAPlatform))
clint.io.in <> AXI4ToAXI4Lite(MMIOTLToAXI4(mmioXbar.io.out(1)))
private val mmioXbar = TLXbar()
private val clint = LazyModule(new TLTimer(
Seq(AddressSet(0x38000000L, 0x0000ffffL)),
sim = !env.FPGAPlatform
))
io.mmio <> extDev
mmioXbar := xsCore.mmio
clint.node := mmioXbar
extDev := mmioXbar
lazy val module = new LazyModuleImp(this){
val io = IO(new Bundle{
val meip = Input(Bool())
val ila = if(env.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
})
val mtipSync = WireInit(0.U(1.W)) //clint.module.mtip
val meipSync = RegNext(RegNext(io.meip))
ExcitingUtils.addSource(mtipSync, "mtip")
ExcitingUtils.addSource(meipSync, "meip")
}
val mtipSync = clint.io.extra.get.mtip
val meipSync = RegNext(RegNext(io.meip))
ExcitingUtils.addSource(mtipSync, "mtip")
ExcitingUtils.addSource(meipSync, "meip")
}
//class XSSoc extends Module with HasSoCParameter {
// val io = IO(new Bundle{
// val mem = new TLCached(l1BusParams)
// val mmio = new TLCached(l1BusParams)
// val frontend = Flipped(new AXI4) //TODO: do we need it ?
// val meip = Input(Bool())
// val ila = if (env.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
// })
//
// val xsCore = Module(new XSCore)
//
// io.frontend <> DontCare
//
// io.mem <> xsCore.io.mem
//
// val addrSpace = List(
// (0x40000000L, 0x40000000L), // external devices
// (0x38000000L, 0x00010000L) // CLINT
// )
// val mmioXbar = Module(new NaiveTL1toN(addrSpace, xsCore.io.mem.params))
// mmioXbar.io.in <> xsCore.io.mmio
//
// val extDev = mmioXbar.io.out(0)
// val clint = Module(new AXI4Timer(sim = !env.FPGAPlatform))
// clint.io.in <> AXI4ToAXI4Lite(MMIOTLToAXI4(mmioXbar.io.out(1)))
//
// io.mmio <> extDev
//
// val mtipSync = clint.io.extra.get.mtip
// val meipSync = RegNext(RegNext(io.meip))
// ExcitingUtils.addSource(mtipSync, "mtip")
// ExcitingUtils.addSource(meipSync, "meip")
//}
src/main/scala/top/TopMain.scala
浏览文件 @ 3e586e47
package top
import system.XSSoc
import device.{AXI4Flash, AXI4Timer, AXI4VGA}
import gpu._
import chisel3._
import chisel3.stage.ChiselGeneratorAnnotation
class Top extends Module {
val io = IO(new Bundle{})
val xsSoc = Module(new XSSoc())
val timer = Module(new AXI4Timer)
val vga = Module(new AXI4VGA)
val flash = Module(new AXI4Flash)
// val gpu = Module(new AXI4GPU)
xsSoc.io := DontCare
timer.io := DontCare
vga.io := DontCare
flash.io := DontCare
// gpu.io := DontCare
dontTouch(xsSoc.io)
dontTouch(timer.io)
dontTouch(vga.io)
dontTouch(flash.io)
// dontTouch(gpu.io)
}
object TopMain extends App {
(new chisel3.stage.ChiselStage).execute(
args,
Seq(ChiselGeneratorAnnotation(() => new Top))
)
}
//package top
//
//import system.XSSoc
//import device.{AXI4Flash, AXI4Timer, AXI4VGA}
//import gpu._
//import chisel3._
//import chisel3.stage.ChiselGeneratorAnnotation
//
//class Top extends Module {
// val io = IO(new Bundle{})
// val xsSoc = Module(new XSSoc())
// val timer = Module(new AXI4Timer)
// val vga = Module(new AXI4VGA)
// val flash = Module(new AXI4Flash)
//// val gpu = Module(new AXI4GPU)
//
// xsSoc.io := DontCare
// timer.io := DontCare
// vga.io := DontCare
// flash.io := DontCare
//// gpu.io := DontCare
// dontTouch(xsSoc.io)
// dontTouch(timer.io)
// dontTouch(vga.io)
// dontTouch(flash.io)
//// dontTouch(gpu.io)
//}
//
//object TopMain extends App {
// (new chisel3.stage.ChiselStage).execute(
// args,
// Seq(ChiselGeneratorAnnotation(() => new Top))
// )
//}
src/test/scala/top/SimMMIO.scala
浏览文件 @ 3e586e47
......@@ -3,9 +3,9 @@ package top
import chisel3._
import chipsalliance.rocketchip.config
import device._
import freechips.rocketchip.amba.axi4.{AXI4MasterParameters, AXI4MasterPortParameters, AXI4SlaveNode, AXI4SlavePortParameters, AXI4Xbar}
import freechips.rocketchip.amba.axi4.{AXI4MasterParameters, AXI4MasterPortParameters, AXI4SlaveNode, AXI4SlavePortParameters, AXI4ToTL, AXI4Xbar}
import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp}
import freechips.rocketchip.tilelink.{TLMasterParameters, TLXbar}
import freechips.rocketchip.tilelink.{TLErrorEvaluator, TLMasterParameters, TLXbar}
class SimMMIO()(implicit p: config.Parameters) extends LazyModule {
......
src/test/scala/top/XSSim.scala
浏览文件 @ 3e586e47
......@@ -4,10 +4,12 @@ import system._
import chisel3._
import chisel3.util._
import chisel3.util.experimental.BoringUtils
import bus.axi4._
import bus.tilelink.FakeTLLLC
import chipsalliance.rocketchip.config
import chisel3.stage.ChiselGeneratorAnnotation
import device._
import freechips.rocketchip.amba.axi4.AXI4UserYanker
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, LazyModule, LazyModuleImp}
import freechips.rocketchip.tilelink.{TLBuffer, TLFuzzer, TLToAXI4}
import xiangshan._
import utils._
......@@ -23,7 +25,7 @@ class DiffTestIO extends XSBundle {
val wpc = Output(Vec(CommitWidth, UInt(VAddrBits.W))) // set difftest width to 6
val isRVC = Output(Bool())
val intrNO = Output(UInt(64.W))
val priviledgeMode = Output(UInt(2.W))
val mstatus = Output(UInt(64.W))
val sstatus = Output(UInt(64.W))
......@@ -46,71 +48,77 @@ class TrapIO extends XSBundle {
val instrCnt = Output(UInt(XLEN.W))
}
class XSSimTop extends XSModule {
val io = IO(new Bundle{
val difftest = new DiffTestIO
val logCtrl = new LogCtrlIO
val trap = new TrapIO
val uart = new UARTIO
})
val soc = Module(new XSSoc())
val mem = Module(new AXI4RAM(memByte = 128 * 1024 * 1024, useBlackBox = true))
// Be careful with the commit checking of emu.
// A large delay will make emu incorrectly report getting stuck.
val memdelay = Module(new AXI4Delayer(0))
val mmio = Module(new SimMMIO(soc.io.mmio.params))
val tlToAXI = Module(new FakeTLLLC(l1BusParams))
soc.io.frontend := DontCare
tlToAXI.io.in <> soc.io.mem
memdelay.io.in <> tlToAXI.io.out
mem.io.in <> memdelay.io.out
mmio.io.rw <> soc.io.mmio
io.uart <> mmio.io.uart
// soc.io.meip := Counter(true.B, 9973)._2 // use prime here to not overlapped by mtip
soc.io.meip := false.B // use prime here to not overlapped by mtip
val difftest = WireInit(0.U.asTypeOf(new DiffTestIO))
BoringUtils.addSink(difftest.commit, "difftestCommit")
BoringUtils.addSink(difftest.thisPC, "difftestThisPC")
BoringUtils.addSink(difftest.thisINST, "difftestThisINST")
BoringUtils.addSink(difftest.skip, "difftestSkip")
BoringUtils.addSink(difftest.isRVC, "difftestIsRVC")
BoringUtils.addSink(difftest.wen, "difftestWen")
BoringUtils.addSink(difftest.wdata, "difftestWdata")
BoringUtils.addSink(difftest.wdst, "difftestWdst")
BoringUtils.addSink(difftest.wpc, "difftestWpc")
BoringUtils.addSink(difftest.intrNO, "difftestIntrNO")
BoringUtils.addSink(difftest.r, "difftestRegs")
BoringUtils.addSink(difftest.priviledgeMode, "difftestMode")
BoringUtils.addSink(difftest.mstatus, "difftestMstatus")
BoringUtils.addSink(difftest.sstatus, "difftestSstatus")
BoringUtils.addSink(difftest.mepc, "difftestMepc")
BoringUtils.addSink(difftest.sepc, "difftestSepc")
BoringUtils.addSink(difftest.mcause, "difftestMcause")
BoringUtils.addSink(difftest.scause, "difftestScause")
io.difftest := difftest
val trap = WireInit(0.U.asTypeOf(new TrapIO))
ExcitingUtils.addSink(trap.valid, "trapValid")
ExcitingUtils.addSink(trap.code, "trapCode")
ExcitingUtils.addSink(trap.pc, "trapPC")
ExcitingUtils.addSink(trap.cycleCnt, "trapCycleCnt")
ExcitingUtils.addSink(trap.instrCnt, "trapInstrCnt")
io.trap := trap
val timer = GTimer()
val logEnable = (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end)
ExcitingUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE")
ExcitingUtils.addSource(timer, "logTimestamp")
ExcitingUtils.fixConnections()
// Check and dispaly all source and sink connections
ExcitingUtils.checkAndDisplay()
class XSSimTop()(implicit p: config.Parameters) extends LazyModule {
val soc = LazyModule(new XSSoc())
val axiRam = LazyModule(new AXI4RAM(
AddressSet(0x0L, 0xffffffffffL),
memByte = 128 * 1024 * 1024,
useBlackBox = true
))
val axiMMIO = LazyModule(new SimMMIO())
axiRam.node :=
AXI4UserYanker() :=
TLToAXI4() :=
soc.mem
axiMMIO.axiBus :=
AXI4UserYanker() :=
TLToAXI4() :=
TLBuffer(BufferParams(2, flow = false, pipe = true)) := // use a tlbuffer to avoid CombLoop
soc.extDev
lazy val module = new LazyModuleImp(this) {
val io = IO(new Bundle {
val difftest = new DiffTestIO
val logCtrl = new LogCtrlIO
val trap = new TrapIO
val uart = new UARTIO
})
io.uart <> axiMMIO.module.io.uart
soc.module.io.meip := false.B
val difftest = WireInit(0.U.asTypeOf(new DiffTestIO))
BoringUtils.addSink(difftest.commit, "difftestCommit")
BoringUtils.addSink(difftest.thisPC, "difftestThisPC")
BoringUtils.addSink(difftest.thisINST, "difftestThisINST")
BoringUtils.addSink(difftest.skip, "difftestSkip")
BoringUtils.addSink(difftest.isRVC, "difftestIsRVC")
BoringUtils.addSink(difftest.wen, "difftestWen")
BoringUtils.addSink(difftest.wdata, "difftestWdata")
BoringUtils.addSink(difftest.wdst, "difftestWdst")
BoringUtils.addSink(difftest.wpc, "difftestWpc")
BoringUtils.addSink(difftest.intrNO, "difftestIntrNO")
BoringUtils.addSink(difftest.r, "difftestRegs")
BoringUtils.addSink(difftest.priviledgeMode, "difftestMode")
BoringUtils.addSink(difftest.mstatus, "difftestMstatus")
BoringUtils.addSink(difftest.sstatus, "difftestSstatus")
BoringUtils.addSink(difftest.mepc, "difftestMepc")
BoringUtils.addSink(difftest.sepc, "difftestSepc")
BoringUtils.addSink(difftest.mcause, "difftestMcause")
BoringUtils.addSink(difftest.scause, "difftestScause")
io.difftest := difftest
val trap = WireInit(0.U.asTypeOf(new TrapIO))
ExcitingUtils.addSink(trap.valid, "trapValid")
ExcitingUtils.addSink(trap.code, "trapCode")
ExcitingUtils.addSink(trap.pc, "trapPC")
ExcitingUtils.addSink(trap.cycleCnt, "trapCycleCnt")
ExcitingUtils.addSink(trap.instrCnt, "trapInstrCnt")
io.trap := trap
val timer = GTimer()
val logEnable = (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end)
ExcitingUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE")
ExcitingUtils.addSource(timer, "logTimestamp")
ExcitingUtils.fixConnections()
// Check and dispaly all source and sink connections
ExcitingUtils.checkAndDisplay()
}
}
object TestMain extends App {
......@@ -119,9 +127,10 @@ object TestMain extends App {
if(args.contains("--disable-log")) Parameters.simParameters // sim only, disable log
else Parameters.debugParameters // open log
)
implicit val p = config.Parameters.empty
// generate verilog
(new chisel3.stage.ChiselStage).execute(
args.filterNot(_ == "--disable-log"),
Seq(ChiselGeneratorAnnotation(() => new XSSimTop))
Seq(ChiselGeneratorAnnotation(() => LazyModule(new XSSimTop).module))
)
}
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