Difftest: link lr/sc reg to simtop

src/main/scala/xiangshan/cache/atomics.scala

@@ -2,6 +2,7 @@ package xiangshan.cache
 
 import chisel3._
 import chisel3.util._
+import chisel3.util.experimental.BoringUtils
 
 import utils.XSDebug
 
@@ -121,6 +122,9 @@ class AtomicsPipe extends DCacheModule
   val s2_sc_fail = s2_sc && !s2_lrsc_addr_match
   val s2_sc_resp = Mux(s2_sc_fail, 1.U, 0.U)
 
+  BoringUtils.addSource(lrsc_addr, "difftestLrscAddr")
+  BoringUtils.addSource(lrsc_valid, "difftestLrscValid")
+
   // we have permission on this block
   // but we can not finish in this pass
   // we need to go to miss queue to update meta and set dirty first

src/test/scala/top/XSSim.scala

@@ -43,6 +43,9 @@ class DiffTestIO extends XSBundle {
   val sscratch = Output(UInt(64.W))
   val mideleg = Output(UInt(64.W))
   val medeleg = Output(UInt(64.W))
+
+  val lrscValid = Output(Bool())
+  val lrscAddr = Output(UInt(64.W))
 }
 
 class LogCtrlIO extends Bundle {
@@ -120,6 +123,8 @@ class XSSimTop()(implicit p: config.Parameters) extends LazyModule {
     BoringUtils.addSink(difftest.sscratch, "difftestSscratch")
     BoringUtils.addSink(difftest.mideleg, "difftestMideleg")
     BoringUtils.addSink(difftest.medeleg, "difftestMedeleg")
+    BoringUtils.addSink(difftest.lrscValid, "difftestLrscValid")
+    BoringUtils.addSink(difftest.lrscAddr, "difftestLrscAddr")
     io.difftest := difftest
 
     val trap = WireInit(0.U.asTypeOf(new TrapIO))