ftb,ftq: add a bit indicating there is an rvi call at the last 2 byte for ras to push the right address

* IFU <timing>: f2_data select signal optimization

* ICacheMainPipe <timing>: latch fetch req when tlb miss

* Frontend <timing>: add additional PMP checker

* Ftq <timing>: delete flush condition for prefetch.req

* ICacheMainPipe <timing>: move hit state change to s2

* ICache <bug-fix> delete PMP check assertion

* ICache <bug-fix> fix parity error condition

* ICacheMainPipe <bug-fix>: fix tlb resp condition

* when TLB req has been latched into tlb_slot, the
tlb_all_resp condition, which affects s0_fire should
depend on the slot result.

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* left ras broken for the next commit to fix

* timing: use single ported SRAMs, invalidating read responses on write
* performance:
-- shortening history length to accelerate training
-- use a predictor to reduce s2_redirects on FTB not hit

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be occupied even when ICache miss

* Shut down IPrefetch

* IPrefetch: fix Hint not set PreferCache bit

* bump HuanCun

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be occupied even when ICache miss

* Shut down IPrefetch

* IPrefetch: fix Hint not set PreferCache bit

* bump HuanCun

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be occupied even when ICache miss

* Add Naive Instruction Prefetch

* Add instruction prefetch module in ICache

* send Hint to L2 (prefetched data stores in L2)

* Ftq: add prefetchPtr and prefetch interface

* Fix IPrefetch PMP Port preempting problem

* Fix merge conflict

This commit adds DelayN(2) to some CSR-related signals, including
control bits to ITLB, DTLB, PTW, etc.

To avoid accessing the ITLB before control bits change, we also need
to delay the flush for two cycles. We assume branch misprediction or
memory violation does not cause csrCtrl to change.

This commit optimizes the coding style and timing for hardware
performance counters.

By default, performance counters are RegNext(RegNext(_)).

* let ubtb store full targets and fall through addresses
* add some fields in BranchPrediction so that ifu requests can be solely derived from it

* decouple fall through address calculating logic from the pftAddr interface
* let ghr update from s1 has the highest priority
* fix the physical priority of PhyPriorityMuxGenerator

bpu: bring folded history into use, and use previous ghr to do difftest; move tage and ittage config to top

* use compressed info to do redirects
* implement folded history class

* IFU: move mmio to f3 and wait commit

* IFU: fix mmio_has_commit condition

* compare FtqPtr to ensure the mmio instruction has been committed

* Uncache fetch : cancel flush when backend redirect

* Add perf counters
* add reg from hpm counter source
* add print perfcounter enable

This PR optimizes out isFused and crossPageIPFFix usages in Rob's DispatchData. They will not be stored in ROB. Now DispatchData has only 38 bits.

* isFused is merged with commitType (2 bits reduced)
* crossPageIPFFix is used only in ExceptionGen (1 bit reduced)
* rename: reduce ldest usages
* decode: set isMove to false if ldest is zero