* difftest: disable runahead to make vcs happy

* difftest: bump huancun to make vcs happy

* difftest: bump difftest and ready-to-run

* difftest support ramsize and paddr base config
* 8GB/16GB nemu so are provided by ready-to-run

* ci: update nightly ci, manually set ram_size

* difftest: bump huancun to make vcs happy

* difftest,nemu: support run-time assign mem size

* ci: polish nightly ci script

The RISC-V WFI instruction is previously decoded as NOP. This commit
adds support for the real wait-for-interrupt (WFI).

We add a state_wfi FSM in the ROB. After WFI leaves the ROB, the next
instruction will wait in the ROB until an interrupt.

* Reduce trigger hit wires that goes into exceptiongen
* Fix frontend triggers rewriting hit wire
* Retrieved some accidentally dropped changes in branch dm-debug (mainly fixes to debug mode)
* Fix dmode in tdata1
* Fix ebreaks not causing exception in debug mode
* Fix dcsr field bugs
* Fix faulty distributed tEnable
* Fix store triggers not using vaddr
* Fix store trigger rewriting hit vector
* Initialize distributed tdata registers in MemBlock and Frontend to zero
* Fix load trigger select bit in mcontrol
* Fix singlestep bit valid in debug mode
* Mask all interrupts in debug mode

* fix invalidTakenFault use wrong seqTarget

* IFU: fix oversize bug

* ctrl: mark all flushes as level.flush for frontend

This commit changes how flushes behave for frontend.

When ROB commits an instruction with a flush, we notify the frontend
of the flush without the commit.

Flushes to frontend may be delayed by some cycles and commit before
flush causes errors. Thus, we make all flush reasons to behave the
same as exceptions for frontend, that is, RedirectLevel.flush.

* IFU: exclude lastTaken situation when judging beyond fetch
Co-authored-by: NYinan Xu <xuyinan@ict.ac.cn>

This commit adds fused load support by bypassing LUI results to load.

For better timing, detection is done at the rename stage. Imm is stored
in psrc(1), psrc(0) and imm.

This commit adds DelayN(2) to some CSR-related signals, including
control bits to ITLB, DTLB, PTW, etc.

To avoid accessing the ITLB before control bits change, we also need
to delay the flush for two cycles. We assume branch misprediction or
memory violation does not cause csrCtrl to change.

This commit optimizes the coding style and timing for hardware
performance counters.

By default, performance counters are RegNext(RegNext(_)).

This commit adds WritebackSink and WritebackSource parameters for
multiple modules. These traits hide implementation details from
other modules by defining IO-related functions in modules.

By using WritebackSink, ROB is able to choose the writeback sources.
Now fflags and exceptions are connected from exe units to reduce write
ports and optimize timing.

Further optimizations on write-back to RS and better coding style to
be added later.

* mdp: implement SSIT with sram

* mdp: use robIdx instead of sqIdx

Dispatch refactor moves lsq enq to dispatch2, as a result, mdp can not
get correct sqIdx in dispatch. Unlike robIdx, it is hard to maintain a
"speculatively assigned" sqIdx, as it is hard to track store insts in
dispatch queue. Yet we can still use "speculatively assigned" robIdx
for memory dependency predictor.

For now, memory dependency predictor uses "speculatively assigned"
robIdx to track inflight store.

However, sqIdx is still used to track those store which's addr is valid
but data it not valid. When load insts try to get forward data from
those store, load insts will get that store's sqIdx and wait in RS.
They will not waken until store data with that sqIdx is issued.

* mdp: add track robIdx recover logic

* FDivSqrt: use hierarchy API to avoid dedup bug

* Dedup: use hartId from io port instead of core parameters

* Bump fudian

This commit changes when instructions enter load/store queue.
Now, at dispatch2, load/store instructions enter load/store queue.

* Add perf counters
* add reg from hpm counter source
* add print perfcounter enable

This commit optimizes the move elimination implementation.

Reference counting for every physical register is recorded. Originally
0-31 registers have counters of ones. Every time the physical register
is allocated or deallocated, the counter is increased or decreased by
one. When the counter becomes zero from a non-zero value, the register
is freed and released to freelist.

This commit removes flush IO for every module. Flush now re-uses
redirect ports to flush the instructions.

This commit adds load balance support for two dispatch ports, between 0
and 2, 1 and 3, etc.

This commit optimizes RenameTable's timing.

Read addresses come from instruction buffer directly and has best
timing. So we let data read at decode stage and bypass write data
from this clock cycle to the read data at next cycle.

For write, we latch the write request and process it at the next cycle.

* runahead: add runahead support (WIP)

* runahead: fix redirect event

* difftest: bump difftest

* runahead: bump version

Note: current runahead does not support instruction fusion, disable that
in XiangShan if runahead is needed

* runahead: bump version

* difftest: bump version to support runahead

* chore: bump huancun to make ci happy

* chore: fix wrong submodule url

* difftest: bump version

BREAKING CHANGE: nemu update_config api has changed

This commit moves load/store reservation stations into the first
ExuBlock (or calling it IntegerBlock). The unnecessary dispatch module
is also removed from CtrlBlock.

Now the module organization becomes:
* ExuBlock: Int RS, Load/Store RS, Int RF, Int FUs
* ExuBlock_1: Fp RS, Fp RF, Fp FUs
* MemBlock: Load/Store FUs

Besides, load queue has 80 entries and store queue has 64 entries now.

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

This commit adds timer counters for some important pipeline stages,
including rename, dispatch, dispatch2, select, issue, execute, commit.
We add performance counters for different types of instructions to see
the latency in different pipeline stages.

This commit cleans up exception vector usages in backend.

Previously the exception vector will go through the pipeline with the
uop. However, instructions with exceptions will enter ROB when they are
dispatched. Thus, actually we don't need the exception vector when an
instruction enters a function unit.

* exceptionVec, flushPipe, replayInst are reset when an instruction
enters function units.

* For execution units that don't have exceptions, we reset their output
exception vectors to avoid ROB to record them.

* Move replayInst to CtrlSignals.

* Bundle, Rename: Add some comments
FreeList, RenameTable: Comment out unused variables

* refcnt: Implement AdderTree for reference counter

* build.sc: add testOne method for unit test

* AdderTest: add testbench for Adder (passed)

* AdderTree: Add testbench for AdderTree (passed)

* ReferenceCounter: implement a 2-bit counter

* Rename: remove redundant code

* Rename: prepared for move elimination [WIP]

* Roq: add eliminated move bit in roq entry;
  label elim move inst as writebacked
AlternativeFreeList: new impl for int free list
Rename: change io of free list
Dispatch1: (todo) not send move to intDq
Bundle: add eliminatedMove bit in roqCommitInfo, uop and debugio
ReferenceCounter: add debug print msg

* Dispatch1: [BUG FIX] not send move inst to IntDq

* DecodeUnit: [BUG FIX] differentiate li from mv

* Bug fix:
  1. Dispatch1: should not label pdest of move as busy in busy table
  2. Rename: use psrc0 to index bit vec isMax
  3. AlternativeFreeList: fix maxVec calculation logic and ref counter
     increment logic
Besides, more debug info and assertions were added.

* AlternativeFreeList Bug Fix:
  1. add redirect input - shouldn't allocate reg when redirect is
     valid
  2. handle duplicate preg in roqCommits in int free list

* AlternativeFreeList: Fix value assignment race condition

* Rename: Fix value assignment race condition too

* RenameTable: refactor spec/arch table write process

* Roq: Fix debug_exuData of move(addi) instruction
  (it was trash data before because move needn't enter exu)

* Rename: change intFreeList's redirect process
  (by setting headPtr back) and flush process

* ME: microbench & coremark & linux-hello passed
  1. DecodeUnit: treat `mv x,x` inst as non-move
  2. AlternativeFreeList: handle duplicate walk req correctly
  3. Roq: fix debug_exuData bug (make sure writeback that updates
debug_exuData happens before ME instruction in program order)

* AlternativeFreeList: License added
build.sc: remove unused config
Others: comments added

* package rename: remove unused modules

* Roq: Replace debug_prf with a cleaner fix method

* Disp1/AltFL/Rename: del unnecessary white spaces

* build.sc: change stack size
AlternativeFreeList: turn off assertions

* build.sc: change stack size for test

New option `EnableFastForward` is added to config list.
EnableFastForward will reduce L1D$ miss but make timing worse.

* `forwardMaskFast` is generated at load_s1, it is used to generate
fastUop for fast wakeup
* `forwardMask` is generated at load_s2, it will be used to check if
forward result is correct

Basic features of debug mode are implemented.

* Rewrite CSR for debug mode
* Peripheral work for implementing debug module
* Added single step support
* Use difftest with JTAG support

br_hit and hist is read at ftq when redirect is sent to bpu

Add Tage into Composer
Add global history manage logic in BPU
Modify CfiUpdate interface: sawNotTakenBranch -> br_hit

XiangShan is jointly released by ICT and PCL.