Fix multi-core dedup bug (#1235)

* FDivSqrt: use hierarchy API to avoid dedup bug

* Dedup: use hartId from io port instead of core parameters

* Bump fudian

fudian @ 4b694595

-Subproject commit db5c2b43c2f48e896d449ce825c4870dcf2fa314
+Subproject commit 4b694595f2d2dbd195313e110227957d40a8e484

src/main/scala/xiangshan/Parameters.scala

@@ -268,7 +268,6 @@ trait HasXSParameter {
   val env = p(DebugOptionsKey)
 
   val XLEN = coreParams.XLEN
-  val hardId = coreParams.HartId
   val minFLen = 32
   val fLen = 64
   def xLen = XLEN

src/main/scala/xiangshan/XSCore.scala

@@ -171,6 +171,13 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
   val ptw = outer.ptw.module
   val exuBlocks = outer.exuBlocks.map(_.module)
 
+
+  ctrlBlock.io.hartId := io.hartId
+  exuBlocks.foreach(_.io.hartId := io.hartId)
+  memBlock.io.hartId := io.hartId
+  outer.wbArbiter.module.io.hartId := io.hartId
+
+
   val allWriteback = exuBlocks.flatMap(_.io.fuWriteback) ++ memBlock.io.writeback
   require(exuConfigs.length == allWriteback.length, s"${exuConfigs.length} != ${allWriteback.length}")
   outer.wbArbiter.module.io.in <> allWriteback

src/main/scala/xiangshan/XSDts.scala

@@ -85,6 +85,6 @@ trait HasXSDts {
     }
   }
   ResourceBinding {
-    Resource(device, "reg").bind(ResourceAddress(hardId))
+    Resource(device, "reg").bind(ResourceAddress(coreParams.HartId))
   }
 }

src/main/scala/xiangshan/XSTile.scala

@@ -47,7 +47,7 @@ class XSTileMisc()(implicit p: Parameters) extends LazyModule
     new XSL1BusErrors(), BusErrorUnitParams(0x38010000), new GenericLogicalTreeNode
   ))
   val busPMU = BusPerfMonitor(enable = !debugOpts.FPGAPlatform)
-  val l1d_logger = TLLogger(s"L2_L1D_$hardId", !debugOpts.FPGAPlatform)
+  val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", !debugOpts.FPGAPlatform)
   val l2_binder = coreParams.L2CacheParamsOpt.map(_ => BankBinder(coreParams.L2NBanks, 64))
 
   val i_mmio_port = TLTempNode()
@@ -98,14 +98,14 @@ class XSTile()(implicit p: Parameters) extends LazyModule
     misc.l1d_logger := core.memBlock.dcache.clientNode
   }
   misc.busPMU :=
-    TLLogger(s"L2_L1I_$hardId", !debugOpts.FPGAPlatform) :=
+    TLLogger(s"L2_L1I_${coreParams.HartId}", !debugOpts.FPGAPlatform) :=
     TLBuffer() :=
     TLBuffer() :=
     core.frontend.icache.clientNode
 
   if (!coreParams.softPTW) {
     misc.busPMU :=
-      TLLogger(s"L2_PTW_$hardId", !debugOpts.FPGAPlatform) :=
+      TLLogger(s"L2_PTW_${coreParams.HartId}", !debugOpts.FPGAPlatform) :=
       TLBuffer() :=
       TLBuffer() :=
       core.ptw.node
@@ -124,6 +124,8 @@ class XSTile()(implicit p: Parameters) extends LazyModule
       val hartId = Input(UInt(64.W))
     })
 
+    dontTouch(io.hartId)
+
     val core_soft_rst = core_reset_sink.in.head._1
 
     core.module.io.hartId := io.hartId

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -41,6 +41,7 @@ class RedirectGenerator(implicit p: Parameters) extends XSModule
   with HasCircularQueuePtrHelper {
   val numRedirect = exuParameters.JmpCnt + exuParameters.AluCnt
   val io = IO(new Bundle() {
+    val hartId = Input(UInt(8.W))
     val exuMispredict = Vec(numRedirect, Flipped(ValidIO(new ExuOutput)))
     val loadReplay = Flipped(ValidIO(new Redirect))
     val flush = Input(Bool())
@@ -162,7 +163,7 @@ class RedirectGenerator(implicit p: Parameters) extends XSModule
   if (!env.FPGAPlatform) {
     val runahead_redirect = Module(new DifftestRunaheadRedirectEvent)
     runahead_redirect.io.clock := clock
-    runahead_redirect.io.coreid := hardId.U
+    runahead_redirect.io.coreid := io.hartId
     runahead_redirect.io.valid := io.stage3Redirect.valid
     runahead_redirect.io.pc :=  s2_pc // for debug only
     runahead_redirect.io.target_pc := s2_target // for debug only
@@ -173,6 +174,7 @@ class RedirectGenerator(implicit p: Parameters) extends XSModule
 class CtrlBlock(implicit p: Parameters) extends XSModule
   with HasCircularQueuePtrHelper {
   val io = IO(new Bundle {
+    val hartId = Input(UInt(8.W))
     val frontend = Flipped(new FrontendToCtrlIO)
     val allocPregs = Vec(RenameWidth, Output(new ResetPregStateReq))
     val dispatch = Vec(3*dpParams.IntDqDeqWidth, DecoupledIO(new MicroOp))
@@ -255,6 +257,7 @@ class CtrlBlock(implicit p: Parameters) extends XSModule
   loadReplay.bits := RegEnable(io.memoryViolation.bits, io.memoryViolation.valid)
   io.frontend.fromFtq.getRedirectPcRead <> redirectGen.io.stage1PcRead
   io.frontend.fromFtq.getMemPredPcRead <> redirectGen.io.memPredPcRead
+  redirectGen.io.hartId := io.hartId
   redirectGen.io.exuMispredict <> exuRedirect
   redirectGen.io.loadReplay <> loadReplay
   redirectGen.io.flush := RegNext(rob.io.flushOut.valid)
@@ -306,6 +309,7 @@ class CtrlBlock(implicit p: Parameters) extends XSModule
     PipelineConnect(rename.io.out(i), dispatch.io.fromRename(i), dispatch.io.recv(i), stage2Redirect.valid)
   }
 
+  dispatch.io.hartId := io.hartId
   dispatch.io.redirect <> stage2Redirect
   dispatch.io.enqRob <> rob.io.enq
   dispatch.io.toIntDq <> intDq.io.enq
@@ -330,6 +334,7 @@ class CtrlBlock(implicit p: Parameters) extends XSModule
   val jumpTargetRead = io.frontend.fromFtq.target_read
   io.jalr_target := jumpTargetRead(jumpInst.cf.ftqPtr, jumpInst.cf.ftqOffset)
 
+  rob.io.hartId := io.hartId
   rob.io.redirect <> stage2Redirect
   val exeWbResults = VecInit(io.writeback ++ io.stOut)
   val timer = GTimer()

src/main/scala/xiangshan/backend/ExuBlock.scala

@@ -52,6 +52,7 @@ class ExuBlockImp(outer: ExuBlock)(implicit p: Parameters) extends LazyModuleImp
   val numOutFu = outer.configs.filterNot(_._1.extendsExu).map(_._2).sum
 
   val io = IO(new Bundle {
+    val hartId = Input(UInt(8.W))
     // global control
     val redirect = Flipped(ValidIO(new Redirect))
     // dispatch ports
@@ -69,6 +70,7 @@ class ExuBlockImp(outer: ExuBlock)(implicit p: Parameters) extends LazyModuleImp
   })
 
   // IO for the scheduler
+  scheduler.io.hartId := io.hartId
   scheduler.io.redirect <> io.redirect
   scheduler.io.allocPregs <> io.allocPregs
   scheduler.io.in <> io.in

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -60,6 +60,7 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
 {
 
   val io = IO(new Bundle {
+    val hartId = Input(UInt(8.W))
     val redirect = Flipped(ValidIO(new Redirect))
     // in
     val issue = Vec(exuParameters.LsExuCnt + 2, Flipped(DecoupledIO(new ExuInput)))
@@ -130,6 +131,11 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
   // val sbuffer = Module(new FakeSbuffer)
   io.stIssuePtr := lsq.io.issuePtrExt
 
+  dcache.io.hartId := io.hartId
+  lsq.io.hartId := io.hartId
+  sbuffer.io.hartId := io.hartId
+  atomicsUnit.io.hartId := io.hartId
+
   // dtlb
   val sfence = RegNext(io.sfence)
   val tlbcsr = RegNext(io.tlbCsr)

src/main/scala/xiangshan/backend/Scheduler.scala

@@ -221,6 +221,7 @@ class SchedulerImp(outer: Scheduler) extends LazyModuleImp(outer) with HasXSPara
   val numFma = outer.reservationStations.map(_.module.io.fmaMid.getOrElse(Seq()).length).sum
 
   val io = IO(new Bundle {
+    val hartId = Input(UInt(8.W))
     // global control
     val redirect = Flipped(ValidIO(new Redirect))
     // dispatch and issue ports
@@ -451,13 +452,13 @@ class SchedulerImp(outer: Scheduler) extends LazyModuleImp(outer) with HasXSPara
   if ((env.AlwaysBasicDiff || env.EnableDifftest) && intRfConfig._1) {
     val difftest = Module(new DifftestArchIntRegState)
     difftest.io.clock := clock
-    difftest.io.coreid := hardId.U
+    difftest.io.coreid := io.hartId
     difftest.io.gpr := intRfReadData.takeRight(32)
   }
   if ((env.AlwaysBasicDiff || env.EnableDifftest) && fpRfConfig._1) {
     val difftest = Module(new DifftestArchFpRegState)
     difftest.io.clock := clock
-    difftest.io.coreid := hardId.U
+    difftest.io.coreid := io.hartId
     difftest.io.fpr := fpRfReadData.takeRight(32)
   }
 

src/main/scala/xiangshan/backend/dispatch/Dispatch.scala

@@ -40,6 +40,7 @@ case class DispatchParameters
 // read rob and enqueue
 class Dispatch(implicit p: Parameters) extends XSModule with HasExceptionNO {
   val io = IO(new Bundle() {
+    val hartId = Input(UInt(8.W))
     // from rename
     val fromRename = Vec(RenameWidth, Flipped(DecoupledIO(new MicroOp)))
     val recv = Output(Vec(RenameWidth, Bool()))
@@ -169,7 +170,7 @@ class Dispatch(implicit p: Parameters) extends XSModule with HasExceptionNO {
 
       val runahead = Module(new DifftestRunaheadEvent)
       runahead.io.clock         := clock
-      runahead.io.coreid        := hardId.U
+      runahead.io.coreid        := io.hartId
       runahead.io.index         := i.U
       runahead.io.valid         := io.fromRename(i).fire()
       runahead.io.branch        := isBranch(i) // setup checkpoint for branch
@@ -188,7 +189,7 @@ class Dispatch(implicit p: Parameters) extends XSModule with HasExceptionNO {
 
       val mempred_check = Module(new DifftestRunaheadMemdepPred)
       mempred_check.io.clock     := clock
-      mempred_check.io.coreid    := hardId.U
+      mempred_check.io.coreid    := io.hartId
       mempred_check.io.index     := i.U
       mempred_check.io.valid     := io.fromRename(i).fire() && isLs(i)
       mempred_check.io.is_load   := !isStore(i) && isLs(i)

src/main/scala/xiangshan/backend/exu/WbArbiter.scala

@@ -207,6 +207,7 @@ class WbArbiterWrapper(
 
   lazy val module = new LazyModuleImp(this) with HasXSParameter {
     val io = IO(new Bundle() {
+      val hartId = Input(UInt(8.W))
       val in = Vec(numInPorts, Flipped(DecoupledIO(new ExuOutput)))
       val out = Vec(numOutPorts, ValidIO(new ExuOutput))
     })
@@ -226,7 +227,7 @@ class WbArbiterWrapper(
     intArbiter.module.io.out.foreach(out => {
       val difftest = Module(new DifftestIntWriteback)
       difftest.io.clock := clock
-      difftest.io.coreid := hardId.U
+      difftest.io.coreid := io.hartId
       difftest.io.valid := out.valid
       difftest.io.dest := out.bits.uop.pdest
       difftest.io.data := out.bits.data
@@ -244,7 +245,7 @@ class WbArbiterWrapper(
     fpArbiter.module.io.out.foreach(out => {
       val difftest = Module(new DifftestFpWriteback)
       difftest.io.clock := clock
-      difftest.io.coreid := hardId.U
+      difftest.io.coreid := io.hartId
       difftest.io.valid := out.valid
       difftest.io.dest := out.bits.uop.pdest
       difftest.io.data := out.bits.data

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -190,7 +190,7 @@ class PerfCounterIO(implicit p: Parameters) extends XSBundle {
 }
 
 class CSRFileIO(implicit p: Parameters) extends XSBundle {
-  val hartId = Input(UInt(64.W))
+  val hartId = Input(UInt(8.W))
   // output (for func === CSROpType.jmp)
   val perf = Input(new PerfCounterIO)
   val isPerfCnt = Output(Bool())
@@ -1218,7 +1218,7 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
   if (env.AlwaysBasicDiff || env.EnableDifftest) {
     val difftest = Module(new DifftestArchEvent)
     difftest.io.clock := clock
-    difftest.io.coreid := hardId.U
+    difftest.io.coreid := csrio.hartId
     difftest.io.intrNO := RegNext(difftestIntrNO)
     difftest.io.cause := RegNext(Mux(csrio.exception.valid, causeNO, 0.U))
     difftest.io.exceptionPC := RegNext(SignExt(csrio.exception.bits.uop.cf.pc, XLEN))
@@ -1228,7 +1228,7 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
   if (env.AlwaysBasicDiff || env.EnableDifftest) {
     val difftest = Module(new DifftestCSRState)
     difftest.io.clock := clock
-    difftest.io.coreid := hardId.U
+    difftest.io.coreid := csrio.hartId
     difftest.io.priviledgeMode := priviledgeMode
     difftest.io.mstatus := mstatus
     difftest.io.sstatus := mstatus & sstatusRmask

src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala

@@ -18,9 +18,34 @@ package xiangshan.backend.fu.fpu
 
 import chipsalliance.rocketchip.config.Parameters
 import chisel3._
+import chisel3.experimental.hierarchy.{Definition, Instance, instantiable, public}
 import chisel3.util._
-import freechips.rocketchip.tile.FType
-import fudian.{FPUpConverter,FDIV}
+import fudian.FDIV
+
+import scala.collection.mutable
+
+/*
+    Because fdiv use the decoder and decoder has 'Dedup' bug now,
+    we use hierarchy API to force FDIV be deduped to avoid the bug.
+ */
+object FDivGen {
+  val defMap = new mutable.HashMap[FPU.FType, Definition[InstantiableFDIV]]()
+  def apply(t: FPU.FType) = {
+    val divDef = defMap.getOrElseUpdate(t, Definition(new InstantiableFDIV(t)))
+    Instance(divDef)
+  }
+}
+
+@instantiable
+class InstantiableFDIV(t: FPU.FType) extends Module {
+
+  val div = Module(new FDIV(t.expWidth, t.precision))
+
+  @public val io = IO(chiselTypeOf(div.io))
+
+  io <> div.io
+
+}
 
 class FDivSqrtDataModule(implicit p: Parameters) extends FPUDataModule {
   val in_valid, out_ready = IO(Input(Bool()))
@@ -40,7 +65,7 @@ class FDivSqrtDataModule(implicit p: Parameters) extends FPUDataModule {
   val outSel = RegEnable(typeSel, VecInit(Seq.fill(typeSel.length)(true.B)), in_fire)  // inelegant
 
   val divSqrt = FPU.ftypes.map{ t =>
-    val fdiv = Module(new FDIV(t.expWidth, t.precision))
+    val fdiv = FDivGen(t)
     fdiv.io.a := src1
     fdiv.io.b := src2
     fdiv.io.rm := rm

src/main/scala/xiangshan/backend/rob/Rob.scala

@@ -265,6 +265,7 @@ class RobFlushInfo(implicit p: Parameters) extends XSBundle {
 
 class Rob(numWbPorts: Int)(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper {
   val io = IO(new Bundle() {
+    val hartId = Input(UInt(8.W))
     val redirect = Input(Valid(new Redirect))
     val enq = new RobEnqIO
     val flushOut = ValidIO(new Redirect)
@@ -941,7 +942,7 @@ class Rob(numWbPorts: Int)(implicit p: Parameters) extends XSModule with HasCirc
     for (i <- 0 until CommitWidth) {
       val difftest = Module(new DifftestInstrCommit)
       difftest.io.clock    := clock
-      difftest.io.coreid   := hardId.U
+      difftest.io.coreid   := io.hartId
       difftest.io.index    := i.U
 
       val ptr = deqPtrVec(i).value
@@ -961,12 +962,12 @@ class Rob(numWbPorts: Int)(implicit p: Parameters) extends XSModule with HasCirc
         (uop.ctrl.fuOpType === LSUOpType.sc_d || uop.ctrl.fuOpType === LSUOpType.sc_w))
       difftest.io.wen      := RegNext(io.commits.valid(i) && io.commits.info(i).rfWen && io.commits.info(i).ldest =/= 0.U)
       difftest.io.wpdest   := RegNext(io.commits.info(i).pdest)
-      difftest.io.wdest    := RegNext(io.commits.info(i)ldest)
+      difftest.io.wdest    := RegNext(io.commits.info(i).ldest)
 
       // runahead commit hint
       val runahead_commit = Module(new DifftestRunaheadCommitEvent)
       runahead_commit.io.clock := clock
-      runahead_commit.io.coreid := hardId.U
+      runahead_commit.io.coreid := io.hartId
       runahead_commit.io.index := i.U
       runahead_commit.io.valid := difftest.io.valid && 
         (commitBranchValid(i) || commitIsStore(i))
@@ -1001,7 +1002,7 @@ class Rob(numWbPorts: Int)(implicit p: Parameters) extends XSModule with HasCirc
 
       val difftest = Module(new DifftestBasicInstrCommit)
       difftest.io.clock   := clock
-      difftest.io.coreid  := hardId.U
+      difftest.io.coreid  := io.hartId
       difftest.io.index   := i.U
       difftest.io.valid   := RegNext(io.commits.valid(i) && !io.commits.isWalk)
       difftest.io.special := RegNext(CommitType.isFused(commitInfo.commitType))
@@ -1017,7 +1018,7 @@ class Rob(numWbPorts: Int)(implicit p: Parameters) extends XSModule with HasCirc
     for (i <- 0 until CommitWidth) {
       val difftest = Module(new DifftestLoadEvent)
       difftest.io.clock  := clock
-      difftest.io.coreid := hardId.U
+      difftest.io.coreid := io.hartId
       difftest.io.index  := i.U
 
       val ptr = deqPtrVec(i).value
@@ -1044,7 +1045,7 @@ class Rob(numWbPorts: Int)(implicit p: Parameters) extends XSModule with HasCirc
     val trapPC = SignExt(PriorityMux(wpc.zip(trapVec).map(x => x._2 ->x._1)), XLEN)
     val difftest = Module(new DifftestTrapEvent)
     difftest.io.clock    := clock
-    difftest.io.coreid   := hardId.U
+    difftest.io.coreid   := io.hartId
     difftest.io.valid    := hitTrap
     difftest.io.code     := trapCode
     difftest.io.pc       := trapPC
@@ -1062,7 +1063,7 @@ class Rob(numWbPorts: Int)(implicit p: Parameters) extends XSModule with HasCirc
     val hitTrap = trapVec.reduce(_||_)
     val difftest = Module(new DifftestBasicTrapEvent)
     difftest.io.clock    := clock
-    difftest.io.coreid   := hardId.U
+    difftest.io.coreid   := io.hartId
     difftest.io.valid    := hitTrap
     difftest.io.cycleCnt := timer
     difftest.io.instrCnt := instrCnt

src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala

@@ -24,9 +24,10 @@ import xiangshan._
 import utils._
 import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp, TransferSizes}
 import freechips.rocketchip.tilelink._
-import freechips.rocketchip.util.BundleFieldBase
+import freechips.rocketchip.util.{BundleFieldBase, UIntToOH1}
 import device.RAMHelper
-import huancun.{AliasField, AliasKey, PreferCacheField, PrefetchField, DirtyField}
+import huancun.{AliasField, AliasKey, DirtyField, PreferCacheField, PrefetchField}
+
 import scala.math.max
 
 // DCache specific parameters
@@ -321,6 +322,7 @@ class DCacheToLsuIO(implicit p: Parameters) extends DCacheBundle {
 }
 
 class DCacheIO(implicit p: Parameters) extends DCacheBundle {
+  val hartId = Input(UInt(8.W))
   val lsu = new DCacheToLsuIO
   val csr = new L1CacheToCsrIO
   val error = new L1CacheErrorInfo
@@ -386,6 +388,8 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
   val probeQueue = Module(new ProbeQueue(edge))
   val wb         = Module(new WritebackQueue(edge))
 
+  missQueue.io.hartId := io.hartId
+
   //----------------------------------------
   // meta array
   val meta_read_ports = ldu.map(_.io.meta_read) ++

src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala

@@ -416,6 +416,7 @@ class MissEntry(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule {
 
 class MissQueue(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule {
   val io = IO(new Bundle {
+    val hartId = Input(UInt(8.W))
     val req = Flipped(DecoupledIO(new MissReq))
     val refill_to_ldq = ValidIO(new Refill)
 
@@ -559,7 +560,7 @@ class MissQueue(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule {
   if (env.EnableDifftest) {
     val difftest = Module(new DifftestRefillEvent)
     difftest.io.clock := clock
-    difftest.io.coreid := hardId.U
+    difftest.io.coreid := io.hartId
     difftest.io.valid := io.refill_to_ldq.valid && io.refill_to_ldq.bits.hasdata && io.refill_to_ldq.bits.refill_done
     difftest.io.addr := io.refill_to_ldq.bits.addr
     difftest.io.data := io.refill_to_ldq.bits.data_raw.asTypeOf(difftest.io.data)

src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala

@@ -55,6 +55,7 @@ class LsqEnqIO(implicit p: Parameters) extends XSBundle {
 // Load / Store Queue Wrapper for XiangShan Out of Order LSU
 class LsqWrappper(implicit p: Parameters) extends XSModule with HasDCacheParameters {
   val io = IO(new Bundle() {
+    val hartId = Input(UInt(8.W))
     val enq = new LsqEnqIO
     val brqRedirect = Flipped(ValidIO(new Redirect))
     val loadIn = Vec(LoadPipelineWidth, Flipped(Valid(new LsPipelineBundle)))
@@ -83,6 +84,8 @@ class LsqWrappper(implicit p: Parameters) extends XSModule with HasDCacheParamet
   val loadQueue = Module(new LoadQueue)
   val storeQueue = Module(new StoreQueue)
 
+  storeQueue.io.hartId := io.hartId
+
   // io.enq logic
   // LSQ: send out canAccept when both load queue and store queue are ready
   // Dispatch: send instructions to LSQ only when they are ready

src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala

@@ -62,6 +62,7 @@ class DataBufferEntry (implicit p: Parameters)  extends DCacheBundle {
 // Store Queue
 class StoreQueue(implicit p: Parameters) extends XSModule with HasDCacheParameters with HasCircularQueuePtrHelper {
   val io = IO(new Bundle() {
+    val hartId = Input(UInt(8.W))
     val enq = new SqEnqIO
     val brqRedirect = Flipped(ValidIO(new Redirect))
     val storeIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) // store addr, data is not included
@@ -566,7 +567,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule with HasDCacheParamete
 
       val difftest = Module(new DifftestStoreEvent)
       difftest.io.clock       := clock
-      difftest.io.coreid      := hardId.U
+      difftest.io.coreid      := io.hartId
       difftest.io.index       := i.U
       difftest.io.valid       := storeCommit
       difftest.io.storeAddr   := waddr

src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala

@@ -28,6 +28,7 @@ import xiangshan.backend.fu.PMPRespBundle
 
 class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstants{
   val io = IO(new Bundle() {
+    val hartId = Input(UInt(8.W))
     val in            = Flipped(Decoupled(new ExuInput))
     val storeDataIn   = Flipped(Valid(new StoreDataBundle)) // src2 from rs
     val out           = Decoupled(new ExuOutput)
@@ -293,7 +294,7 @@ class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstant
   if (env.EnableDifftest) {
     val difftest = Module(new DifftestAtomicEvent)
     difftest.io.clock      := clock
-    difftest.io.coreid     := hardId.U
+    difftest.io.coreid     := io.hartId
     difftest.io.atomicResp := io.dcache.resp.fire()
     difftest.io.atomicAddr := paddr_reg
     difftest.io.atomicData := data_reg

src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala

@@ -98,6 +98,7 @@ class SbufferData(implicit p: Parameters) extends XSModule with HasSbufferConst
 
 class Sbuffer(implicit p: Parameters) extends DCacheModule with HasSbufferConst {
   val io = IO(new Bundle() {
+    val hartId = Input(UInt(8.W))
     val in = Vec(StorePipelineWidth, Flipped(Decoupled(new DCacheWordReqWithVaddr)))  //Todo: store logic only support Width == 2 now
     val dcache = Flipped(new DCacheToSbufferIO)
     val forward = Vec(LoadPipelineWidth, Flipped(new LoadForwardQueryIO))
@@ -474,14 +475,13 @@ class Sbuffer(implicit p: Parameters) extends DCacheModule with HasSbufferConst
       val difftest = Module(new DifftestSbufferEvent)
       val dcache_resp_id = resp.bits.id
       difftest.io.clock := clock
-      difftest.io.coreid := hardId.U
+      difftest.io.coreid := io.hartId
       difftest.io.index := index.U
       difftest.io.sbufferResp := RegNext(resp.fire())
       difftest.io.sbufferAddr := RegNext(getAddr(ptag(dcache_resp_id)))
       difftest.io.sbufferData := RegNext(data(dcache_resp_id).asTypeOf(Vec(CacheLineBytes, UInt(8.W))))
       difftest.io.sbufferMask := RegNext(mask(dcache_resp_id).asUInt)
     }}
-    
   }
 
   // ---------------------- Load Data Forward ---------------------