This commit changes the lsrc/psrc of LUI in dispatch instead of
decode to optimize the timing of lsrc in DecodeStage, which is
critical for rename table.

lsrc/ldest should be directly get from instr for the timing. Fused
instructions change lsrc/ldest now, which will be optimized later.

* fix for chipsalliance/rocket-chip#2967

* decode: fix width of BitPat(?) in decode logic
Co-authored-by: NYinan Xu <xuyinan@ict.ac.cn>

* difftest: disable runahead to make vcs happy

* difftest: bump huancun to make vcs happy

* difftest: bump difftest and ready-to-run

* difftest support ramsize and paddr base config
* 8GB/16GB nemu so are provided by ready-to-run

* ci: update nightly ci, manually set ram_size

* difftest: bump huancun to make vcs happy

* difftest,nemu: support run-time assign mem size

* ci: polish nightly ci script

An instruction with exceptions may have arbitrary instr values and
may be decoded into WFI instructions, which cause errors.

* feat: parameterize load/store pipeline, etc.

* fix: use LoadPipelineWidth rather than LoadQueueSize

* fix: parameterize `rdataPtrExtNext`

* SBuffer: fix idx update logic

* atomic: parameterize atomic logic in `MemBlock`

* StoreQueue: update allow enque requirement

* feat: support one load/store pipeline

* feat: parameterize `EnsbufferWidth`

* chore: resharp codes for better generated name

XiangShan does not support fs=0 because when fs=0, all floating-point
states are not accessible. Spike supports fs=0. To diff with Spike,
we temporarily set fs to 1 when initialized.

This commit fixes the implementation of WFI. The WFI instruction
waits in the ROB until an interrupt might need servicing.

According to the RISC-V manual, the WFI must be unaffected by the
global interrupt bits in `mstatus` and the delegation register
`mideleg`.

The RISC-V WFI instruction is previously decoded as NOP. This commit
adds support for the real wait-for-interrupt (WFI).

We add a state_wfi FSM in the ROB. After WFI leaves the ROB, the next
instruction will wait in the ROB until an interrupt.

* difftest: fix false-positive difftest intRF writeback, adapt to new difftest API

* csr: skip mip difftest

* bump difftest

* bump difftest

* fix some typos
Signed-off-by: Ncuishuang <imcusg@gmail.com>

* mem: optimize missq reject to lq timing

DCache replay request is quite slow to generate, as it need to compare
load address with address in all valid miss queue entries.

Now we delay the usage of replay request from data cache.
Now replay request will not influence normal execuation flow until
load_s3 (1 cycle after load_s2, load result writeback to RS).

It is worth mentioning that "select refilling inst for load
writeback" will be disabled if dcacheRequireReplay in the
last cycle.

* dcache: compare probe block addr instead of full addr

* mem: do not replay from RS when ldld vio or fwd failed

ld-ld violation or forward failure will let an normal load inst replay
from fetch. If TLB hit and ld-ld violation / forward failure happens,
we write back that inst immediately. Meanwhile, such insts will not be
replayed from rs.

It should fix "mem: optimize missq reject to lq timing"

* mem: fix replay from rs condition

* mem: reduce refill to use latency

This commit update lq entry flag carefully in load_s3 to avoid extra
refill delay. It will remove the extra refill delay introduced by #1375
without harming memblock timing.

In #1375, we delayed load refill when dcache miss queue entry fails
to accept a miss. #1375 exchanges performance for better timing.

* mem: fix rs feedback priority

When dataInvalid && mshrFull, a succeed refill should not cancel
rs replay.

This commit fixes the block_commit condition when an instruction has
exception but labeled flushPipe. Previously such an instruction will
commit normally.

Previously the stepie bit won't take effect

CSRs are updated later after instructions commit from ROB. Thus, we
need to delay difftest commit for several cycles.

* Reduce trigger hit wires that goes into exceptiongen
* Fix frontend triggers rewriting hit wire
* Retrieved some accidentally dropped changes in branch dm-debug (mainly fixes to debug mode)
* Fix dmode in tdata1
* Fix ebreaks not causing exception in debug mode
* Fix dcsr field bugs
* Fix faulty distributed tEnable
* Fix store triggers not using vaddr
* Fix store trigger rewriting hit vector
* Initialize distributed tdata registers in MemBlock and Frontend to zero
* Fix load trigger select bit in mcontrol
* Fix singlestep bit valid in debug mode
* Mask all interrupts in debug mode

* mem: fix error csr update

* dcache: l2 error will now trigger atom error

* chore: fix cache error debug decoder

* mem: split L1CacheErrorInfo and L1BusErrorUnitInfo

XiangShan has registered an marchid of 25: https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md .
This value should be returned from CSR `marchid`.

* Add Prefetch and Parity enable register for ICache

* Add ICache parity enable control for pipe

This commit adds blocking logic for instructions when they enter
dispatch queues. If previous instructions have exceptions, any
following instructions should be enter dispatch queue.

Consider the following case. If uop(0) has an exception and is a load.
If uop(1) does not have an exception and is a load as well. Then the
allocation logic in dispatch queue will allocate an entry for both
uop(0) and uop(1). However, uop(0) will not set enq.valid and leave
the entry in dispatch queue empty. uop(1) will be allocated in dpq.
In dispatch queue, pointers are updated according to the real number
of instruction enqueue, which is one. While the second is actually
allocated. This causes errors.

* dcache: add source info in L1CacheErrorInfo

* ICache: fix valid signal and add source/opType

* dcache: fix bug in ecc error

* mem,csr: send full L1CacheErrorInfo to CSR

* icache: provide cache error info for CSR

* dcache: force resp hit if tag ecc error happens

* mem: reorg l1 cache error report path

Now dcache tag error will force trigger a hit

* dcache: fix readline ecc check error

* dcache: mainpipe will not be influenced by tag error

* dcache: fix data ecc check error

* dcache: if coh state is Nothing, do not raise error
Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>
Co-authored-by: NJinYue <jinyue20s@ict.ac.cn>

Valid should be set to true after atomic.exception.valid and cleared
after redirect is valid.

Exception address is used serveral cycles after flush. We delay it
by more cycles to ensure its flush safety.

* mem: optimize missq reject to lq timing

DCache replay request is quite slow to generate, as it need to compare
load address with address in all valid miss queue entries.

Now we delay the usage of replay request from data cache.
Now replay request will not influence normal execution flow until
load_s3 (1 cycle after load_s2, load result writeback to RS).

Note1: It is worth mentioning that "select refilling inst for load
writeback" will be disabled if dcacheRequireReplay in the
last cycle.

Note2: ld-ld violation or forward failure will let an normal load inst replay
from fetch. If TLB hit and ld-ld violation / forward failure happens,
we write back that inst immediately. Meanwhile, such insts will not be
replayed from rs.

* dcache: compare probe block addr instead of full addr

This commit adds an LsqEnqCtrl module to add one more clock cycle
between dispatch and load/store queue.

LsqEnqCtrl maintains the lqEnqPtr/sqEnqPtr and lqCounter/sqCounter.
They are used to determine whether load/store queue can accept new
instructions. After that, instructions are sent to load/store queue.
This module decouples queue allocation and real enqueue.

Besides, uop storage in load/store queue are optimized. In dispatch,
only robIdx is required. Other information is naturally conveyed in
the pipeline and can be stored later in load/store queue if needed.
For example, exception vector, trigger, ftqIdx, pdest, etc are
unnecessary before the instruction leaves the load/store pipeline.