- 20 6月, 2022 2 次提交
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由 Yinan Xu 提交于
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由 William Wang 提交于
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- 18 6月, 2022 2 次提交
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由 Yinan Xu 提交于
This commit changes the lsrc/psrc of LUI in dispatch instead of decode to optimize the timing of lsrc in DecodeStage, which is critical for rename table. lsrc/ldest should be directly get from instr for the timing. Fused instructions change lsrc/ldest now, which will be optimized later.
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由 wakafa 提交于
* buspmu: avoid inner space in perf-cnt name * perfcnt: judge regularity of perfname * perfcnt: fix some irregular perfname * bump huancun
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- 17 6月, 2022 1 次提交
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由 Ziyue-Zhang 提交于
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- 11 6月, 2022 1 次提交
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由 Guokai Chen 提交于
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- 09 6月, 2022 1 次提交
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由 Steve Gou 提交于
last_may_be_rvi_call in case that a call comes after a taken branch
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- 08 6月, 2022 1 次提交
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由 Lingrui98 提交于
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- 06 6月, 2022 4 次提交
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由 Jenius 提交于
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由 Jenius 提交于
* add SRAM ready (resetfinish) condition for *Array (metaArray/dataArray) req.ready
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由 Jenius 提交于
* fix mmio_resend_af wrong assignment * fix wb_half_flush missOffset(using wb_lastIdx instead of PredictWidth -1) * change pipeline ready condition (this_ready = this_stage_fire || this_stage_empty) * delete 500-cycle ready condition (toICache(*).ready means the SRAM has been reset and ready for read)
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由 Lemover 提交于
* bump huancun, update Chisel3, revert sram hazard enhancement * util.sram: rm a r/w hazard mux which is not needed. bump huancun
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- 02 6月, 2022 1 次提交
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由 Lingrui98 提交于
Previous logic checked the value of old_ctr to select between old target and new target when updating ittage table. However, when we need to alloc a new entry, the value of old_ctr is X because we do not reset ittage table. So we would definitely write an X to the target field, which is the output of the mux, as the selector is X.
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- 31 5月, 2022 2 次提交
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由 Yinan Xu 提交于
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由 Jiuyang Liu 提交于
* fix for chipsalliance/rocket-chip#2967 * decode: fix width of BitPat(?) in decode logic Co-authored-by: NYinan Xu <xuyinan@ict.ac.cn>
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- 29 5月, 2022 1 次提交
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由 Jenius 提交于
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- 27 5月, 2022 1 次提交
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由 Yinan Xu 提交于
Previously we made a mistake to connect rtc_clock to rtcTick for CLINT. rtcTick should be on io_clock clock domain and asserted only one clock cycle in io_clock for every cycle in rtc_clock. We add sampling registers in this commit to fix this.
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- 26 5月, 2022 1 次提交
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由 Jiuyang Liu 提交于
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- 25 5月, 2022 1 次提交
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由 Lingrui98 提交于
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- 24 5月, 2022 1 次提交
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由 Lingrui98 提交于
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- 12 5月, 2022 1 次提交
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由 Hazard 提交于
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- 11 5月, 2022 2 次提交
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由 William Wang 提交于
* difftest: disable runahead to make vcs happy * difftest: bump huancun to make vcs happy * difftest: bump difftest and ready-to-run * difftest support ramsize and paddr base config * 8GB/16GB nemu so are provided by ready-to-run * ci: update nightly ci, manually set ram_size * difftest: bump huancun to make vcs happy * difftest,nemu: support run-time assign mem size * ci: polish nightly ci script
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由 Yinan Xu 提交于
An instruction with exceptions may have arbitrary instr values and may be decoded into WFI instructions, which cause errors.
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- 09 5月, 2022 3 次提交
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由 Li Qianruo 提交于
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由 Jenius 提交于
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由 Steve Gou 提交于
* sc: fix a performance bug * tage: fix number of use-alt-on-na counters * tage: update provider u-bit according to provider results
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- 07 5月, 2022 1 次提交
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由 Guokai Chen 提交于
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- 06 5月, 2022 2 次提交
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由 Haojin Tang 提交于
* feat: parameterize load/store pipeline, etc. * fix: use LoadPipelineWidth rather than LoadQueueSize * fix: parameterize `rdataPtrExtNext` * SBuffer: fix idx update logic * atomic: parameterize atomic logic in `MemBlock` * StoreQueue: update allow enque requirement * feat: support one load/store pipeline * feat: parameterize `EnsbufferWidth` * chore: resharp codes for better generated name
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由 William Wang 提交于
* chore: remove sc too many fail assertion * chore: use XSWarn()
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- 05 5月, 2022 2 次提交
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由 William Wang 提交于
s1_tag_match_way is vaild iff tag_read.valid and meta_read.valid in s0 for the same req
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由 Yinan Xu 提交于
XiangShan does not support fs=0 because when fs=0, all floating-point states are not accessible. Spike supports fs=0. To diff with Spike, we temporarily set fs to 1 when initialized.
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- 04 5月, 2022 2 次提交
- 29 4月, 2022 1 次提交
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由 Yinan Xu 提交于
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- 28 4月, 2022 2 次提交
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由 Yinan Xu 提交于
To test WFI, we delay the interrupts for more cycles.
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由 Yinan Xu 提交于
The RISC-V WFI instruction is previously decoded as NOP. This commit adds support for the real wait-for-interrupt (WFI). We add a state_wfi FSM in the ROB. After WFI leaves the ROB, the next instruction will wait in the ROB until an interrupt.
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- 25 4月, 2022 2 次提交
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由 wakafa 提交于
* difftest: fix false-positive difftest intRF writeback, adapt to new difftest API * csr: skip mip difftest * bump difftest * bump difftest
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由 cui fliter 提交于
* fix some typos Signed-off-by: Ncuishuang <imcusg@gmail.com>
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- 14 4月, 2022 1 次提交
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由 Lemover 提交于
old missqueue: cache req miss slot and mem access-er Problem: these two func are totally different, make mq hard to handle in a single select policy. Solution: divide these two funciton into two module. new MissQueue: only hold reqs that page cache miss and need re-req cache, a simple flushable queue llptw: Last level ptw, only access ptes, priorityMux queue * mmu: rename PTW.scala to L2TLB.scala * mmu: rename PTW to L2TLB * mmu: rename PtwFsm to PTW * mmu.l2tlb: divide missqueue into 'missqueue' and llptw old missqueue: cache req miss slot and mem access-er Problem: these two func are totally different, make mq hard to handle in single select policy. Solution: divide these two funciton into two module. new MissQueue: only hold reqs that page cache miss and new re-req cache llptw: Last level ptw, only access ptes * mmu.l2tlb: syntax bug that misses io assign * mmu.l2tlb: fix bug that mistakes ptw's block signal
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- 02 4月, 2022 1 次提交
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由 William Wang 提交于
* mem: optimize missq reject to lq timing DCache replay request is quite slow to generate, as it need to compare load address with address in all valid miss queue entries. Now we delay the usage of replay request from data cache. Now replay request will not influence normal execuation flow until load_s3 (1 cycle after load_s2, load result writeback to RS). It is worth mentioning that "select refilling inst for load writeback" will be disabled if dcacheRequireReplay in the last cycle. * dcache: compare probe block addr instead of full addr * mem: do not replay from RS when ldld vio or fwd failed ld-ld violation or forward failure will let an normal load inst replay from fetch. If TLB hit and ld-ld violation / forward failure happens, we write back that inst immediately. Meanwhile, such insts will not be replayed from rs. It should fix "mem: optimize missq reject to lq timing" * mem: fix replay from rs condition * mem: reduce refill to use latency This commit update lq entry flag carefully in load_s3 to avoid extra refill delay. It will remove the extra refill delay introduced by #1375 without harming memblock timing. In #1375, we delayed load refill when dcache miss queue entry fails to accept a miss. #1375 exchanges performance for better timing. * mem: fix rs feedback priority When dataInvalid && mshrFull, a succeed refill should not cancel rs replay.
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