ctrlblock: remove redirect_cfiUpdate port, and use stage3Redirect

src/main/scala/xiangshan/Bundle.scala

@@ -379,7 +379,6 @@ class FrontendToCtrlIO(implicit p: Parameters) extends XSBundle {
   val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow))
   val fromFtq = new FtqToCtrlIO
   // from backend
-  val redirect_cfiUpdate = Flipped(ValidIO(new Redirect))
   val toFtq = Flipped(new CtrlToFtqIO)
 }
 

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -248,7 +248,6 @@ class CtrlBlock(implicit p: Parameters) extends XSModule
   }
   io.frontend.toFtq.stage2Redirect <> stage2Redirect
   io.frontend.toFtq.roqFlush <> RegNext(roq.io.flushOut)
-  io.frontend.toFtq.stage3Redirect <> stage3Redirect
   io.frontend.toFtq.loadReplay <> loadReplay
 
   val roqPcRead = io.frontend.fromFtq.getRoqFlushPcRead
@@ -267,7 +266,7 @@ class CtrlBlock(implicit p: Parameters) extends XSModule
   flushRedirectReg.valid := RegNext(flushRedirect.valid, init = false.B)
   flushRedirectReg.bits := RegEnable(flushRedirect.bits, enable = flushRedirect.valid)
 
-  io.frontend.redirect_cfiUpdate := Mux(flushRedirectReg.valid, flushRedirectReg, stage3Redirect)
+  io.frontend.toFtq.stage3Redirect := Mux(flushRedirectReg.valid, flushRedirectReg, stage3Redirect)
 
   decode.io.in <> io.frontend.cfVec
   // currently, we only update wait table when isReplay
@@ -287,7 +286,7 @@ class CtrlBlock(implicit p: Parameters) extends XSModule
   // pipeline between decode and dispatch
   for (i <- 0 until RenameWidth) {
     PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready,
-      flushReg || io.frontend.redirect_cfiUpdate.valid)
+      flushReg || io.frontend.toFtq.stage3Redirect.valid)
   }
 
   rename.io.redirect <> stage2Redirect

src/main/scala/xiangshan/decoupled-frontend/Frontend.scala

@@ -80,7 +80,7 @@ class FrontendImp (outer: Frontend) extends LazyModuleImp(outer)
   val instrUncache = outer.instrUncache.module
   val l1plusPrefetcher = Module(new L1plusPrefetcher)
 
-  val needFlush = io.backend.redirect_cfiUpdate.valid
+  val needFlush = io.backend.toFtq.stage3Redirect.valid
 
   //IFU-Ftq
   ifu.io.ftqInter.fromFtq <> ftq.io.toIfu