- 24 6月, 2022 1 次提交
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由 LinJiawei 提交于
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- 18 6月, 2022 2 次提交
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由 Yinan Xu 提交于
This commit changes the lsrc/psrc of LUI in dispatch instead of decode to optimize the timing of lsrc in DecodeStage, which is critical for rename table. lsrc/ldest should be directly get from instr for the timing. Fused instructions change lsrc/ldest now, which will be optimized later.
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由 wakafa 提交于
* buspmu: avoid inner space in perf-cnt name * perfcnt: judge regularity of perfname * perfcnt: fix some irregular perfname * bump huancun
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- 17 6月, 2022 1 次提交
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由 Ziyue-Zhang 提交于
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- 11 6月, 2022 1 次提交
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由 Guokai Chen 提交于
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- 09 6月, 2022 5 次提交
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由 Steve Gou 提交于
FoldedSRAMTemplate: hold ridx when holdRead is set
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由 Steve Gou 提交于
<bug-fix>: fix IFU misOffset bug and optimize code
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由 Steve Gou 提交于
ubtb: fix write waymask of fallThruPred
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由 Steve Gou 提交于
ittage: we should write new target when alloc
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由 Steve Gou 提交于
last_may_be_rvi_call in case that a call comes after a taken branch
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- 08 6月, 2022 2 次提交
- 06 6月, 2022 4 次提交
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由 Jenius 提交于
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由 Jenius 提交于
* add SRAM ready (resetfinish) condition for *Array (metaArray/dataArray) req.ready
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由 Jenius 提交于
* fix mmio_resend_af wrong assignment * fix wb_half_flush missOffset(using wb_lastIdx instead of PredictWidth -1) * change pipeline ready condition (this_ready = this_stage_fire || this_stage_empty) * delete 500-cycle ready condition (toICache(*).ready means the SRAM has been reset and ready for read)
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由 Lemover 提交于
* bump huancun, update Chisel3, revert sram hazard enhancement * util.sram: rm a r/w hazard mux which is not needed. bump huancun
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- 02 6月, 2022 1 次提交
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由 Lingrui98 提交于
Previous logic checked the value of old_ctr to select between old target and new target when updating ittage table. However, when we need to alloc a new entry, the value of old_ctr is X because we do not reset ittage table. So we would definitely write an X to the target field, which is the output of the mux, as the selector is X.
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- 31 5月, 2022 2 次提交
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由 Yinan Xu 提交于
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由 Jiuyang Liu 提交于
* fix for chipsalliance/rocket-chip#2967 * decode: fix width of BitPat(?) in decode logic Co-authored-by: NYinan Xu <xuyinan@ict.ac.cn>
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- 29 5月, 2022 1 次提交
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由 Jenius 提交于
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- 27 5月, 2022 1 次提交
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由 Yinan Xu 提交于
Previously we made a mistake to connect rtc_clock to rtcTick for CLINT. rtcTick should be on io_clock clock domain and asserted only one clock cycle in io_clock for every cycle in rtc_clock. We add sampling registers in this commit to fix this.
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- 26 5月, 2022 1 次提交
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由 Jiuyang Liu 提交于
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- 25 5月, 2022 2 次提交
- 24 5月, 2022 1 次提交
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由 Lingrui98 提交于
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- 22 5月, 2022 1 次提交
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由 wakafa 提交于
Provide two issue template.
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- 21 5月, 2022 1 次提交
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由 Lemover 提交于
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- 12 5月, 2022 1 次提交
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由 Hazard 提交于
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- 11 5月, 2022 3 次提交
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由 William Wang 提交于
* difftest: disable runahead to make vcs happy * difftest: bump huancun to make vcs happy * difftest: bump difftest and ready-to-run * difftest support ramsize and paddr base config * 8GB/16GB nemu so are provided by ready-to-run * ci: update nightly ci, manually set ram_size * difftest: bump huancun to make vcs happy * difftest,nemu: support run-time assign mem size * ci: polish nightly ci script
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由 wakafa 提交于
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由 Yinan Xu 提交于
An instruction with exceptions may have arbitrary instr values and may be decoded into WFI instructions, which cause errors.
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- 09 5月, 2022 4 次提交
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由 Li Qianruo 提交于
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由 Jenius 提交于
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由 Yinan Xu 提交于
Use 16GB memory as default. SPEC CPU2017 requires more than 8GB memory.
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由 Steve Gou 提交于
* sc: fix a performance bug * tage: fix number of use-alt-on-na counters * tage: update provider u-bit according to provider results
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- 07 5月, 2022 1 次提交
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由 Guokai Chen 提交于
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- 06 5月, 2022 4 次提交
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由 Haojin Tang 提交于
* feat: parameterize load/store pipeline, etc. * fix: use LoadPipelineWidth rather than LoadQueueSize * fix: parameterize `rdataPtrExtNext` * SBuffer: fix idx update logic * atomic: parameterize atomic logic in `MemBlock` * StoreQueue: update allow enque requirement * feat: support one load/store pipeline * feat: parameterize `EnsbufferWidth` * chore: resharp codes for better generated name
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由 Yinan Xu 提交于
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由 William Wang 提交于
* chore: remove sc too many fail assertion * chore: use XSWarn()
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由 Yinan Xu 提交于
difftest: fix support for Spike
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