- 16 1月, 2021 2 次提交
- 15 1月, 2021 9 次提交
- 14 1月, 2021 22 次提交
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由 Yinan Xu 提交于
ci: add make verilog test
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Yinan Xu 提交于
Trace debug
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由 ljw 提交于
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
CSR: add hardware performance counter framework
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
DCache: fixed sync bus between probe and LoadPipe, StorePipe and Atom…
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由 wangkaifan 提交于
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由 Allen 提交于
Now, every pipe directly carries the old_repl_meta to missQueue. So probe should block every pipe with same set req. In case they try to replace the block probe was manipulating. The buggy case happens this way: 1. Probe block A, which resides in set x, way y. 2. Probe has done almost everything except meta data update. 3. StorePipe handles block B, which missed in cache, so it try to replace set x, way y. Because Probe haven't update meta data, StorePipe gets a old copy of meta data, which means it will try to evict block A. 4. Probe finally update meta. 5. MissQueue accept miss request for block B from StorePipe, with the old_repl_meta, MissQueue tries to evict block A, although it's already probed out.
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由 Yinan Xu 提交于
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由 wangkaifan 提交于
* values of hardware performance counters can hardly be emulated by NEMU
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由 Yinan Xu 提交于
rs: remove buggy `if FPGAPlatform else ...` code
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由 YikeZhou 提交于
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由 Yinan Xu 提交于
LoadQueueData: use separate data module
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由 Yinan Xu 提交于
ci: add make verilog test ci: add make verilog test
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
Revert "LoadQueue: select load refilled this cycle for wb"
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- 13 1月, 2021 7 次提交
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由 William Wang 提交于
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由 William Wang 提交于
Now we have: * paddrModule * maskModule * exceptionModule * coredataModule (data & fwdmask)
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由 William Wang 提交于
This reverts commit 2e0406ca.
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由 Fa_wang 提交于
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由 YikeZhou 提交于
Rs: use SyncDataModuleTemplate
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由 Yinan Xu 提交于
remove commit id in .gitmodules
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由 Fa_wang 提交于
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