Merge pull request #425 from RISCVERS/perfcnt

CSR: add hardware performance counter framework

src/main/scala/xiangshan/Bundle.scala

@@ -283,6 +283,7 @@ class ReplayPregReq extends XSBundle {
 
 class DebugBundle extends XSBundle{
   val isMMIO = Bool()
+  val isPerfCnt = Bool()
 }
 
 class ExuInput extends XSBundle {

src/main/scala/xiangshan/XSCore.scala

@@ -425,6 +425,7 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
   integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr
   integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt
   integerBlock.io.csrio.tlb <> memBlock.io.tlbCsr
+  integerBlock.io.csrio.perfinfo <> ctrlBlock.io.roqio.toCSR.perfinfo
   integerBlock.io.fenceio.sfence <> memBlock.io.sfence
   integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer
 

src/main/scala/xiangshan/backend/IntegerBlock.scala

@@ -82,6 +82,9 @@ class IntegerBlock
       val memExceptionVAddr = Input(UInt(VAddrBits.W)) // from lsq
       val externalInterrupt = new ExternalInterruptIO  // from outside
       val tlb = Output(new TlbCsrBundle) // from tlb
+      val perfinfo = new Bundle {
+        val retiredInstr = Input(UInt(3.W))
+      }
     }
     val fenceio = new Bundle {
       val sfence = Output(new SfenceBundle) // to front,mem

src/main/scala/xiangshan/backend/brq/Brq.scala

@@ -269,16 +269,16 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
   val mbpRWrong = predWrong && isRType
 
   if(!env.FPGAPlatform){
-    ExcitingUtils.addSource(mbpInstr, "perfCntCondMbpInstr", Perf)
-    ExcitingUtils.addSource(mbpRight, "perfCntCondMbpRight", Perf)
-    ExcitingUtils.addSource(mbpWrong, "perfCntCondMbpWrong", Perf)
-    ExcitingUtils.addSource(mbpBRight, "perfCntCondMbpBRight", Perf)
-    ExcitingUtils.addSource(mbpBWrong, "perfCntCondMbpBWrong", Perf)
-    ExcitingUtils.addSource(mbpJRight, "perfCntCondMbpJRight", Perf)
-    ExcitingUtils.addSource(mbpJWrong, "perfCntCondMbpJWrong", Perf)
-    ExcitingUtils.addSource(mbpIRight, "perfCntCondMbpIRight", Perf)
-    ExcitingUtils.addSource(mbpIWrong, "perfCntCondMbpIWrong", Perf)
-    ExcitingUtils.addSource(mbpRRight, "perfCntCondMbpRRight", Perf)
-    ExcitingUtils.addSource(mbpRWrong, "perfCntCondMbpRWrong", Perf)
+    ExcitingUtils.addSource(mbpInstr, "perfCntCondBpInstr", Perf)
+    ExcitingUtils.addSource(mbpRight, "perfCntCondBpRight", Perf)
+    ExcitingUtils.addSource(mbpWrong, "perfCntCondBpWrong", Perf)
+    ExcitingUtils.addSource(mbpBRight, "perfCntCondBpBRight", Perf)
+    ExcitingUtils.addSource(mbpBWrong, "perfCntCondBpBWrong", Perf)
+    ExcitingUtils.addSource(mbpJRight, "perfCntCondBpJRight", Perf)
+    ExcitingUtils.addSource(mbpJWrong, "perfCntCondBpJWrong", Perf)
+    ExcitingUtils.addSource(mbpIRight, "perfCntCondBpIRight", Perf)
+    ExcitingUtils.addSource(mbpIWrong, "perfCntCondBpIWrong", Perf)
+    ExcitingUtils.addSource(mbpRRight, "perfCntCondBpRRight", Perf)
+    ExcitingUtils.addSource(mbpRWrong, "perfCntCondBpRWrong", Perf)
   }
 }

src/main/scala/xiangshan/backend/exu/Exu.scala

@@ -183,6 +183,7 @@ abstract class Exu(val config: ExuConfig) extends XSModule {
     out.fflags := DontCare
     out.debug <> DontCare
     out.debug.isMMIO := false.B
+    out.debug.isPerfCnt := false.B
     out.redirect <> DontCare
     out.redirectValid := false.B
   }

src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala

@@ -21,6 +21,9 @@ class JumpExeUnit extends Exu(jumpExeUnitCfg)
     val memExceptionVAddr = Input(UInt(VAddrBits.W))
     val externalInterrupt = new ExternalInterruptIO
     val tlb = Output(new TlbCsrBundle)
+    val perfinfo = new Bundle {
+      val retiredInstr = Input(UInt(3.W))
+    }
   })
   val fenceio = IO(new Bundle {
     val sfence = Output(new SfenceBundle)
@@ -42,6 +45,7 @@ class JumpExeUnit extends Exu(jumpExeUnitCfg)
   }.get
 
   csr.csrio.perf <> DontCare
+  csr.csrio.perf.retiredInstr <> csrio.perfinfo.retiredInstr
   csr.csrio.fpu.fflags <> csrio.fflags
   csr.csrio.fpu.isIllegal := false.B
   csr.csrio.fpu.dirty_fs <> csrio.dirty_fs
@@ -73,6 +77,7 @@ class JumpExeUnit extends Exu(jumpExeUnitCfg)
     io.toInt.bits.redirect.roqIdx := uop.roqIdx
     io.toInt.bits.redirect.target := csr.csrio.redirectOut.bits
     io.toInt.bits.redirect.pc := uop.cf.pc
+    io.toInt.bits.debug.isPerfCnt := csr.csrio.isPerfCnt
   }.elsewhen(jmp.io.out.valid){
     io.toInt.bits.redirectValid := jmp.redirectOutValid
     io.toInt.bits.redirect := jmp.redirectOut

src/main/scala/xiangshan/backend/fu/util/CSRConst.scala

+package xiangshan.backend.fu.util
+
+import chisel3._
+import chisel3.ExcitingUtils.{ConnectionType, Debug}
+import chisel3.util._
+import utils._
+import xiangshan._
+import xiangshan.backend._
+import utils.XSDebug
+
+trait HasCSRConst {
+
+  // User Trap Setup
+  val Ustatus       = 0x000
+  val Uie           = 0x004
+  val Utvec         = 0x005
+
+  // User Trap Handling
+  val Uscratch      = 0x040
+  val Uepc          = 0x041
+  val Ucause        = 0x042
+  val Utval         = 0x043
+  val Uip           = 0x044
+
+  // User Floating-Point CSRs (not implemented)
+  val Fflags        = 0x001
+  val Frm           = 0x002
+  val Fcsr          = 0x003
+
+  // User Counter/Timers
+  val Cycle         = 0xC00
+  val Time          = 0xC01
+  val Instret       = 0xC02
+
+  // Supervisor Trap Setup
+  val Sstatus       = 0x100
+  val Sedeleg       = 0x102
+  val Sideleg       = 0x103
+  val Sie           = 0x104
+  val Stvec         = 0x105
+  val Scounteren    = 0x106
+
+  // Supervisor Trap Handling
+  val Sscratch      = 0x140
+  val Sepc          = 0x141
+  val Scause        = 0x142
+  val Stval         = 0x143
+  val Sip           = 0x144
+
+  // Supervisor Protection and Translation
+  val Satp          = 0x180
+
+  // Machine Information Registers
+  val Mvendorid     = 0xF11
+  val Marchid       = 0xF12
+  val Mimpid        = 0xF13
+  val Mhartid       = 0xF14
+
+  // Machine Trap Setup
+  val Mstatus       = 0x300
+  val Misa          = 0x301
+  val Medeleg       = 0x302
+  val Mideleg       = 0x303
+  val Mie           = 0x304
+  val Mtvec         = 0x305
+  val Mcounteren    = 0x306
+
+  // Machine Trap Handling
+  val Mscratch      = 0x340
+  val Mepc          = 0x341
+  val Mcause        = 0x342
+  val Mtval         = 0x343
+  val Mip           = 0x344
+
+  // Machine Memory Protection
+  // TBD
+  val Pmpcfg0       = 0x3A0
+  val Pmpcfg1       = 0x3A1
+  val Pmpcfg2       = 0x3A2
+  val Pmpcfg3       = 0x3A3
+  val PmpaddrBase   = 0x3B0
+
+  // Machine Counter/Timers
+  // Currently, we uses perfcnt csr set instead of standard Machine Counter/Timers
+  // 0xB80 - 0x89F are also used as perfcnt csr
+  val Mcycle   = 0xb00
+  val Minstret = 0xb02
+  
+  val Mhpmcounter3  = 0xB03
+  val Mhpmcounter4  = 0xB04
+  val Mhpmcounter5  = 0xB05
+  val Mhpmcounter6  = 0xB06
+  val Mhpmcounter7  = 0xB07
+  val Mhpmcounter8  = 0xB08
+  val Mhpmcounter9  = 0xB09
+  val Mhpmcounter10 = 0xB0A
+  val Mhpmcounter11 = 0xB0B
+  val Mhpmcounter12 = 0xB0C
+  val Mhpmcounter13 = 0xB0D
+  val Mhpmcounter14 = 0xB0E
+  val Mhpmcounter15 = 0xB0F
+  val Mhpmcounter16 = 0xB10
+  val Mhpmcounter17 = 0xB11
+  val Mhpmcounter18 = 0xB12
+  val Mhpmcounter19 = 0xB13
+  val Mhpmcounter20 = 0xB14
+  val Mhpmcounter21 = 0xB15
+  val Mhpmcounter22 = 0xB16
+  val Mhpmcounter23 = 0xB17
+  val Mhpmcounter24 = 0xB18
+  val Mhpmcounter25 = 0xB19
+  val Mhpmcounter26 = 0xB1A
+  val Mhpmcounter27 = 0xB1B
+  val Mhpmcounter28 = 0xB1C
+  val Mhpmcounter29 = 0xB1D
+  val Mhpmcounter30 = 0xB1E
+  val Mhpmcounter31 = 0xB1F
+  
+  // Machine Counter Setup (not implemented)
+  val Mcountinhibit = 0x320
+  val Mhpmevent3    = 0x323
+  val Mhpmevent4    = 0x324
+  val Mhpmevent5    = 0x325
+  val Mhpmevent6    = 0x326
+  val Mhpmevent7    = 0x327
+  val Mhpmevent8    = 0x328
+  val Mhpmevent9    = 0x329
+  val Mhpmevent10   = 0x32A
+  val Mhpmevent11   = 0x32B
+  val Mhpmevent12   = 0x32C
+  val Mhpmevent13   = 0x32D
+  val Mhpmevent14   = 0x32E
+  val Mhpmevent15   = 0x32F
+  val Mhpmevent16   = 0x330
+  val Mhpmevent17   = 0x331
+  val Mhpmevent18   = 0x332
+  val Mhpmevent19   = 0x333
+  val Mhpmevent20   = 0x334
+  val Mhpmevent21   = 0x335
+  val Mhpmevent22   = 0x336
+  val Mhpmevent23   = 0x337
+  val Mhpmevent24   = 0x338
+  val Mhpmevent25   = 0x339
+  val Mhpmevent26   = 0x33A
+  val Mhpmevent27   = 0x33B
+  val Mhpmevent28   = 0x33C
+  val Mhpmevent29   = 0x33D
+  val Mhpmevent30   = 0x33E
+  val Mhpmevent31   = 0x33F
+
+  // Debug/Trace Registers (shared with Debug Mode) (not implemented)
+  // Debug Mode Registers (not implemented)
+
+  def privEcall  = 0x000.U
+  def privEbreak = 0x001.U
+  def privMret   = 0x302.U
+  def privSret   = 0x102.U
+  def privUret   = 0x002.U
+
+  def ModeM     = 0x3.U
+  def ModeH     = 0x2.U
+  def ModeS     = 0x1.U
+  def ModeU     = 0x0.U
+
+  def IRQ_UEIP  = 0
+  def IRQ_SEIP  = 1
+  def IRQ_MEIP  = 3
+
+  def IRQ_UTIP  = 4
+  def IRQ_STIP  = 5
+  def IRQ_MTIP  = 7
+
+  def IRQ_USIP  = 8
+  def IRQ_SSIP  = 9
+  def IRQ_MSIP  = 11
+
+  val IntPriority = Seq(
+    IRQ_MEIP, IRQ_MSIP, IRQ_MTIP,
+    IRQ_SEIP, IRQ_SSIP, IRQ_STIP,
+    IRQ_UEIP, IRQ_USIP, IRQ_UTIP
+  )
+
+  def csrAccessPermissionCheck(addr: UInt, wen: Bool, mode: UInt): Bool = {
+    val readOnly = addr(11,10) === "b11".U
+    val lowestAccessPrivilegeLevel = addr(9,8)
+    mode >= lowestAccessPrivilegeLevel && !(wen && readOnly)
+  }
+}
\ No newline at end of file

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -38,6 +38,9 @@ class RoqCSRIO extends XSBundle {
 
   val fflags = Output(Valid(UInt(5.W)))
   val dirty_fs = Output(Bool())
+  val perfinfo = new Bundle {
+    val retiredInstr = Output(UInt(3.W))
+  }
 }
 
 class RoqEnqIO extends XSBundle {
@@ -696,10 +699,11 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
       val uop = debug_microOp(idx)
       val DifftestSkipSC = false
       if(!DifftestSkipSC){
-        skip(i) := debug_exuDebug(idx).isMMIO && io.commits.valid(i)
+        skip(i) := (debug_exuDebug(idx).isMMIO || debug_exuDebug(idx).isPerfCnt) && io.commits.valid(i)
       }else{
         skip(i) := (
             debug_exuDebug(idx).isMMIO ||
+            debug_exuDebug(idx).isPerfCnt ||
             uop.ctrl.fuType === FuType.mou && uop.ctrl.fuOpType === LSUOpType.sc_d ||
             uop.ctrl.fuType === FuType.mou && uop.ctrl.fuOpType === LSUOpType.sc_w
           ) && io.commits.valid(i)
@@ -720,6 +724,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
     val instrCnt = RegInit(0.U(64.W))
     val retireCounter = Mux(state === s_idle, commitCnt, 0.U)
     instrCnt := instrCnt + retireCounter
+    io.csr.perfinfo.retiredInstr := RegNext(retireCounter);
 
     XSDebug(difftestIntrNO =/= 0.U, "difftest intrNO set %x\n", difftestIntrNO)
     val retireCounterFix = Mux(io.redirectOut.valid, 1.U, retireCounter)

src/main/scala/xiangshan/cache/dtlb.scala

@@ -5,7 +5,7 @@ import chisel3.util._
 import xiangshan._
 import utils._
 import xiangshan.backend.roq.RoqPtr
-import xiangshan.backend.fu.HasCSRConst
+import xiangshan.backend.fu.util.HasCSRConst
 import chisel3.ExcitingUtils._
 
 trait HasTlbConst extends HasXSParameter {

src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala

@@ -362,6 +362,7 @@ class LoadQueue extends XSModule
     io.ldout(i).bits.redirect := DontCare
     io.ldout(i).bits.brUpdate := DontCare
     io.ldout(i).bits.debug.isMMIO := debug_mmio(loadWbSel(i))
+    io.ldout(i).bits.debug.isPerfCnt := false.B
     io.ldout(i).bits.fflags := DontCare
     io.ldout(i).valid := loadWbSelV(i)
 

src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala

@@ -264,6 +264,7 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
   io.mmioStout.bits.redirect := DontCare
   io.mmioStout.bits.brUpdate := DontCare
   io.mmioStout.bits.debug.isMMIO := true.B
+  io.mmioStout.bits.debug.isPerfCnt := false.B
   io.mmioStout.bits.fflags := DontCare
   when (io.mmioStout.fire()) {
     writebacked(deqPtr) := true.B

src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala

@@ -280,6 +280,7 @@ class LoadUnit extends XSModule with HasLoadHelper {
   intHitLoadOut.bits.redirect := DontCare
   intHitLoadOut.bits.brUpdate := DontCare
   intHitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio
+  intHitLoadOut.bits.debug.isPerfCnt := false.B
   intHitLoadOut.bits.fflags := DontCare
 
   load_s2.io.out.ready := true.B

src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala

@@ -114,6 +114,7 @@ class StoreUnit_S2 extends XSModule {
   io.stout.bits.redirect := DontCare
   io.stout.bits.brUpdate := DontCare
   io.stout.bits.debug.isMMIO := io.in.bits.mmio
+  io.stout.bits.debug.isPerfCnt := false.B
   io.stout.bits.fflags := DontCare
 
 }

src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala

@@ -49,12 +49,9 @@ class ChooseReplace(nWay: Int) extends XSModule {
   val nextWay = PriorityEncoder(Cat(stateMask, loMask))(log2Up(nWay)-1, 0)
   XSDebug(p"nextWay[${nextWay}]\n")
 
+  wayReg := nextWay
   io.way := wayReg
 
-  when(io.fire){
-    wayReg := nextWay
-  }
-
   when(io.flush){
     wayReg := 0.U
   }