Perf: Modify predictor counter logic

src/main/scala/xiangshan/backend/brq/Brq.scala

@@ -196,6 +196,7 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
     mergeData.brUpdate.target := wb.brUpdate.target
     mergeData.brUpdate.brTarget := wb.brUpdate.brTarget
     mergeData.brUpdate.taken := wb.brUpdate.taken
+    mergeData.brUpdate.bpuMeta.predictor:= wb.brUpdate.bpuMeta.predictor
     mergeData
   }
 
@@ -270,16 +271,16 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
 
   val predictor = brUpdateReadEntry.brUpdate.bpuMeta.predictor
 
-  val ubtbRight = predRight && predictor === 0.U
+  val ubtbRight =  predRight && predictor === 0.U
   val ubtbWrong = !predRight && predictor === 0.U
 
-  val btbRight = predRight && predictor === 1.U
-  val btbWrong = !predRight && predictor === 1.U
+  val btbRight  =  predRight && predictor === 1.U
+  val btbWrong  = !predRight && predictor === 1.U
 
-  val tageRight = predRight && predictor === 2.U
+  val tageRight =  predRight && predictor === 2.U
   val tageWrong = !predRight && predictor === 2.U
 
-  val loopRight = predRight && predictor === 3.U
+  val loopRight =  predRight && predictor === 3.U
   val loopWrong = !predRight && predictor === 3.U
 
   if(!env.FPGAPlatform){

src/main/scala/xiangshan/frontend/IFU.scala

@@ -477,11 +477,9 @@ class IFU extends XSModule with HasIFUConst
   io.fetchPacket.valid := fetchPacketValid
 
   if(IFUDebug) {
-    val predictor = PriorityMux(Seq(
-      if4_redirect -> 2.U,
-      if3_redirect -> 1.U,
-      true.B -> 0.U
-    ))
+    val predictor_s3 = RegEnable(Mux(if3_redirect, 1.U(log2Up(4).W), 0.U(log2Up(4).W)), if3_fire)
+    val predictor_s4 = Mux(if4_redirect, 2.U, predictor_s3)
+    val predictor = predictor_s4
 
     fetchPacketWire.bpuMeta.map(_.predictor := predictor)
   }