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e3089591
编写于
1月 14, 2021
作者:
L
Lingrui98
浏览文件
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电子邮件补丁
差异文件
util: use the same base datamodule both for sync and async version
上级
460c8e77
变更
1
隐藏空白更改
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并排
Showing
1 changed file
with
8 addition
and
33 deletion
+8
-33
src/main/scala/utils/DataModuleTemplate.scala
src/main/scala/utils/DataModuleTemplate.scala
+8
-33
未找到文件。
src/main/scala/utils/DataModuleTemplate.scala
浏览文件 @
e3089591
...
...
@@ -3,7 +3,7 @@ package utils
import
chisel3._
import
chisel3.util._
class
AsyncDataModuleTemplate
[
T
<:
Data
](
gen
:
T
,
numEntries
:
Int
,
numRead
:
Int
,
numWrite
:
Int
)
extends
Module
{
class
DataModuleTemplate
[
T
<:
Data
](
gen
:
T
,
numEntries
:
Int
,
numRead
:
Int
,
numWrite
:
Int
,
isSync
:
Boolean
)
extends
Module
{
val
io
=
IO
(
new
Bundle
{
val
raddr
=
Vec
(
numRead
,
Input
(
UInt
(
log2Up
(
numEntries
).
W
)))
val
rdata
=
Vec
(
numRead
,
Output
(
gen
))
...
...
@@ -12,43 +12,15 @@ class AsyncDataModuleTemplate[T <: Data](gen: T, numEntries: Int, numRead: Int,
val
wdata
=
Vec
(
numWrite
,
Input
(
gen
))
})
val
data
=
Mem
(
numEntries
,
gen
)
// read ports
for
(
i
<-
0
until
numRead
)
{
io
.
rdata
(
i
)
:=
data
(
io
.
raddr
(
i
))
}
// below is the write ports (with priorities)
for
(
i
<-
0
until
numWrite
)
{
when
(
io
.
wen
(
i
))
{
data
(
io
.
waddr
(
i
))
:=
io
.
wdata
(
i
)
}
}
// DataModuleTemplate should not be used when there're any write conflicts
for
(
i
<-
0
until
numWrite
)
{
for
(
j
<-
i
+
1
until
numWrite
)
{
assert
(!(
io
.
wen
(
i
)
&&
io
.
wen
(
j
)
&&
io
.
waddr
(
i
)
===
io
.
waddr
(
j
)))
}
}
}
class
SyncDataModuleTemplate
[
T
<:
Data
](
gen
:
T
,
numEntries
:
Int
,
numRead
:
Int
,
numWrite
:
Int
)
extends
Module
{
val
io
=
IO
(
new
Bundle
{
val
raddr
=
Vec
(
numRead
,
Input
(
UInt
(
log2Up
(
numEntries
).
W
)))
val
rdata
=
Vec
(
numRead
,
Output
(
gen
))
val
wen
=
Vec
(
numWrite
,
Input
(
Bool
()))
val
waddr
=
Vec
(
numWrite
,
Input
(
UInt
(
log2Up
(
numEntries
).
W
)))
val
wdata
=
Vec
(
numWrite
,
Input
(
gen
))
})
val
n
=
if
(
isSync
)
"SyncDataModuleTemplate"
else
"AsyncDataModuleTemplate"
this
.
suggestName
(
n
)
val
data
=
Mem
(
numEntries
,
gen
)
// read ports
val
raddr
_reg
=
RegNext
(
io
.
raddr
)
val
raddr
=
if
(
isSync
)
(
RegNext
(
io
.
raddr
))
else
io
.
raddr
for
(
i
<-
0
until
numRead
)
{
io
.
rdata
(
i
)
:=
data
(
raddr
_reg
(
i
))
io
.
rdata
(
i
)
:=
data
(
raddr
(
i
))
}
// below is the write ports (with priorities)
...
...
@@ -65,3 +37,6 @@ class SyncDataModuleTemplate[T <: Data](gen: T, numEntries: Int, numRead: Int, n
}
}
}
class
SyncDataModuleTemplate
[
T
<:
Data
](
gen
:
T
,
numEntries
:
Int
,
numRead
:
Int
,
numWrite
:
Int
,
isSync
:
Boolean
=
true
)
extends
DataModuleTemplate
(
gen
,
numEntries
,
numRead
,
numWrite
,
true
)
class
AsyncDataModuleTemplate
[
T
<:
Data
](
gen
:
T
,
numEntries
:
Int
,
numRead
:
Int
,
numWrite
:
Int
,
isSync
:
Boolean
=
true
)
extends
DataModuleTemplate
(
gen
,
numEntries
,
numRead
,
numWrite
,
false
)
\ No newline at end of file
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