perfcnt, csr: support hardware mcycle & minstret

src/main/scala/xiangshan/XSCore.scala

@@ -425,6 +425,7 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
   integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr
   integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt
   integerBlock.io.csrio.tlb <> memBlock.io.tlbCsr
+  integerBlock.io.csrio.perfinfo <> ctrlBlock.io.roqio.toCSR.perfinfo
   integerBlock.io.fenceio.sfence <> memBlock.io.sfence
   integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer
 

src/main/scala/xiangshan/backend/IntegerBlock.scala

@@ -82,6 +82,9 @@ class IntegerBlock
       val memExceptionVAddr = Input(UInt(VAddrBits.W)) // from lsq
       val externalInterrupt = new ExternalInterruptIO  // from outside
       val tlb = Output(new TlbCsrBundle) // from tlb
+      val perfinfo = new Bundle {
+        val retiredInstr = Input(UInt(3.W))
+      }
     }
     val fenceio = new Bundle {
       val sfence = Output(new SfenceBundle) // to front,mem

src/main/scala/xiangshan/backend/brq/Brq.scala

@@ -269,16 +269,16 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
   val mbpRWrong = predWrong && isRType
 
   if(!env.FPGAPlatform){
-    ExcitingUtils.addSource(mbpInstr, "perfCntCondMbpInstr", Perf)
-    ExcitingUtils.addSource(mbpRight, "perfCntCondMbpRight", Perf)
-    ExcitingUtils.addSource(mbpWrong, "perfCntCondMbpWrong", Perf)
-    ExcitingUtils.addSource(mbpBRight, "perfCntCondMbpBRight", Perf)
-    ExcitingUtils.addSource(mbpBWrong, "perfCntCondMbpBWrong", Perf)
-    ExcitingUtils.addSource(mbpJRight, "perfCntCondMbpJRight", Perf)
-    ExcitingUtils.addSource(mbpJWrong, "perfCntCondMbpJWrong", Perf)
-    ExcitingUtils.addSource(mbpIRight, "perfCntCondMbpIRight", Perf)
-    ExcitingUtils.addSource(mbpIWrong, "perfCntCondMbpIWrong", Perf)
-    ExcitingUtils.addSource(mbpRRight, "perfCntCondMbpRRight", Perf)
-    ExcitingUtils.addSource(mbpRWrong, "perfCntCondMbpRWrong", Perf)
+    ExcitingUtils.addSource(mbpInstr, "perfCntCondBpInstr", Perf)
+    ExcitingUtils.addSource(mbpRight, "perfCntCondBpRight", Perf)
+    ExcitingUtils.addSource(mbpWrong, "perfCntCondBpWrong", Perf)
+    ExcitingUtils.addSource(mbpBRight, "perfCntCondBpBRight", Perf)
+    ExcitingUtils.addSource(mbpBWrong, "perfCntCondBpBWrong", Perf)
+    ExcitingUtils.addSource(mbpJRight, "perfCntCondBpJRight", Perf)
+    ExcitingUtils.addSource(mbpJWrong, "perfCntCondBpJWrong", Perf)
+    ExcitingUtils.addSource(mbpIRight, "perfCntCondBpIRight", Perf)
+    ExcitingUtils.addSource(mbpIWrong, "perfCntCondBpIWrong", Perf)
+    ExcitingUtils.addSource(mbpRRight, "perfCntCondBpRRight", Perf)
+    ExcitingUtils.addSource(mbpRWrong, "perfCntCondBpRWrong", Perf)
   }
 }

src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala

@@ -21,6 +21,9 @@ class JumpExeUnit extends Exu(jumpExeUnitCfg)
     val memExceptionVAddr = Input(UInt(VAddrBits.W))
     val externalInterrupt = new ExternalInterruptIO
     val tlb = Output(new TlbCsrBundle)
+    val perfinfo = new Bundle {
+      val retiredInstr = Input(UInt(3.W))
+    }
   })
   val fenceio = IO(new Bundle {
     val sfence = Output(new SfenceBundle)
@@ -42,6 +45,7 @@ class JumpExeUnit extends Exu(jumpExeUnitCfg)
   }.get
 
   csr.csrio.perf <> DontCare
+  csr.csrio.perf.retiredInstr <> csrio.perfinfo.retiredInstr
   csr.csrio.fpu.fflags <> csrio.fflags
   csr.csrio.fpu.isIllegal := false.B
   csr.csrio.fpu.dirty_fs <> csrio.dirty_fs

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -58,6 +58,7 @@ class FpuCsrIO extends XSBundle {
 
 
 class PerfCounterIO extends XSBundle {
+  val retiredInstr = Input(UInt(3.W))
   val value = Input(UInt(XLEN.W))
 }
 
@@ -66,7 +67,7 @@ class CSR extends FunctionUnit with HasCSRConst
   val csrio = IO(new Bundle {
     // output (for func === CSROpType.jmp)
     val redirectOut = ValidIO(UInt(VAddrBits.W))
-    val perf = Vec(NumPerfCounters, new PerfCounterIO)
+    val perf = new PerfCounterIO
     val isPerfCnt = Output(Bool())
     // to FPU
     val fpu = Flipped(new FpuCsrIO)
@@ -331,6 +332,10 @@ class CSR extends FunctionUnit with HasCSRConst
   val perfCnts   = List.fill(nrPerfCnts)(RegInit(0.U(XLEN.W)))
   val perfEvents = List.fill(nrPerfCnts)(RegInit(0.U(XLEN.W)))
   val mcountinhibit = RegInit(0.U(XLEN.W))
+  val mcycle = RegInit(0.U(XLEN.W))
+  mcycle := mcycle + 1.U
+  val minstret = RegInit(0.U(XLEN.W))
+  minstret := minstret + RegNext(csrio.perf.retiredInstr)
   
   // CSR reg map
   val basicPrivMapping = Map(
@@ -405,7 +410,11 @@ class CSR extends FunctionUnit with HasCSRConst
     MaskedRegMap(PmpaddrBase + 3, pmpaddr3)
   )
 
-  var perfCntMapping = Map(MaskedRegMap(Mcountinhibit, mcountinhibit))
+  var perfCntMapping = Map(
+    MaskedRegMap(Mcountinhibit, mcountinhibit),
+    MaskedRegMap(Mcycle, mcycle),
+    MaskedRegMap(Minstret, minstret),
+  )
   val MhpmcounterStart = Mhpmcounter3
   val MhpmeventStart   = Mhpmevent3
   for (i <- 0 until nrPerfCnts) {
@@ -708,17 +717,17 @@ class CSR extends FunctionUnit with HasCSRConst
   val emuPerfCntList = Map(
     // "Mcycle"    -> (0x1000, "perfCntCondMcycle"     ),
     // "Minstret"  -> (0x1002, "perfCntCondMinstret"   ),
-    "MbpInstr"    -> (0x1003, "perfCntCondMbpInstr" ),
-    "MbpRight"    -> (0x1004, "perfCntCondMbpRight" ),
-    "MbpWrong"    -> (0x1005, "perfCntCondMbpWrong" ),
-    "MbpBRight"   -> (0x1006, "perfCntCondMbpBRight"),
-    "MbpBWrong"   -> (0x1007, "perfCntCondMbpBWrong"),
-    "MbpJRight"   -> (0x1008, "perfCntCondMbpJRight"),
-    "MbpJWrong"   -> (0x1009, "perfCntCondMbpJWrong"),
-    "MbpIRight"   -> (0x100a, "perfCntCondMbpIRight"),
-    "MbpIWrong"   -> (0x100b, "perfCntCondMbpIWrong"),
-    "MbpRRight"   -> (0x100c, "perfCntCondMbpRRight"),
-    "MbpRWrong"   -> (0x100d, "perfCntCondMbpRWrong"),
+    "BpInstr"     -> (0x1003, "perfCntCondBpInstr" ),
+    "BpRight"     -> (0x1004, "perfCntCondBpRight" ),
+    "BpWrong"     -> (0x1005, "perfCntCondBpWrong" ),
+    "BpBRight"    -> (0x1006, "perfCntCondBpBRight"),
+    "BpBWrong"    -> (0x1007, "perfCntCondBpBWrong"),
+    "BpJRight"    -> (0x1008, "perfCntCondBpJRight"),
+    "BpJWrong"    -> (0x1009, "perfCntCondBpJWrong"),
+    "BpIRight"    -> (0x100a, "perfCntCondBpIRight"),
+    "BpIWrong"    -> (0x100b, "perfCntCondBpIWrong"),
+    "BpRRight"    -> (0x100c, "perfCntCondBpRRight"),
+    "BpRWrong"    -> (0x100d, "perfCntCondBpRWrong"),
     "RoqWalk"     -> (0x100f, "perfCntCondRoqWalk"  ),
     "DTlbReqCnt0" -> (0x1015, "perfCntDtlbReqCnt0"  ),
     "DTlbReqCnt1" -> (0x1016, "perfCntDtlbReqCnt1"  ),
@@ -740,7 +749,7 @@ class CSR extends FunctionUnit with HasCSRConst
     // "ExitLoop1" -> (0x102c, "CntExitLoop1"),
     // "ExitLoop2" -> (0x102d, "CntExitLoop2"),
     // "ExitLoop3" -> (0x102e, "CntExitLoop3")
-    // "Ml2cacheHit" -> (0x1023, "perfCntCondMl2cacheHit")
+    // "L2cacheHit" -> (0x1023, "perfCntCondL2cacheHit")
   ) ++ (
     (0 until dcacheParameters.nMissEntries).map(i => 
       ("DCacheMissQueuePenalty" + Integer.toString(i, 10), (0x102d + i, "perfCntDCacheMissQueuePenaltyEntry" + Integer.toString(i, 10)))

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -38,6 +38,9 @@ class RoqCSRIO extends XSBundle {
 
   val fflags = Output(Valid(UInt(5.W)))
   val dirty_fs = Output(Bool())
+  val perfinfo = new Bundle {
+    val retiredInstr = Output(UInt(3.W))
+  }
 }
 
 class RoqEnqIO extends XSBundle {
@@ -721,6 +724,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
     val instrCnt = RegInit(0.U(64.W))
     val retireCounter = Mux(state === s_idle, commitCnt, 0.U)
     instrCnt := instrCnt + retireCounter
+    io.csr.perfinfo.retiredInstr := RegNext(retireCounter);
 
     XSDebug(difftestIntrNO =/= 0.U, "difftest intrNO set %x\n", difftestIntrNO)
     val retireCounterFix = Mux(io.redirectOut.valid, 1.U, retireCounter)