This commit adds load balance strategy in issue selection logic for
reservation stations.

Previously we have a load balance option in ExuBlock, but it cannot work
if the function units have feedbacks to RS. In this commit it is
removed.

This commit adds a victim index option for oldestFirst. For LOAD, the
first issue port has better performance and thus we set the victim index
to 0. For other function units, we use the last issue port.

This commit adds timer counters for some important pipeline stages,
including rename, dispatch, dispatch2, select, issue, execute, commit.
We add performance counters for different types of instructions to see
the latency in different pipeline stages.

This PR replaces coremark, microbench, and all perfromence test workloads by corresponding RV64GCB workloads.

Fix fencei and physical tag bugs in ICache

* Using get_phy_tag function instead of get_tag
* This bug happens when using VIPT ICache and setting lage set number

* add top IOs

* modify dma bus data width from 256 to 128 bits

* add top single to SimTop.scala

This commit adds manual reset for every register in Regfile. Previously
the reset is done by add reset values to the registers. However,
physically general-purpose register file does not have reset values.

Since all the regfile always has the same writeback data, we don't need
to explicitly assign reset data.

This commit adds critical_wakeup_*_* counters to indicate which function
units wake up the instructions in RS. Previously we have wait_for_src_*
counters but they cannot represent where the critical operand (the last
waiting operand) comes from.

We need these counters to optimize fast wakeup logic. If some
instructions critically depend on some other instructions, we can think
of how we can optimize the wakeup process.

Furthermore, this commit also adds a specific counter for FMAs that
wakeup other FMAs' third operand. This helps us to decide which strategy
is used for FMA fast issue.

nothing changed but add one parameter to control if ldtlb and sttlb are the same
now there two similar parameters:

outReplace: when this is true, two ldtlb are 'same', two sttlb are 'same'
refillBothTlb: when this is true, the four tlb are same(require outReplace to be true)

* mmu.tlb: add param refillBothTlb to refill both ld & st tlb

* mmu.tlb: set param refillBothTlb to false

This commit cleans up exception vector usages in backend.

Previously the exception vector will go through the pipeline with the
uop. However, instructions with exceptions will enter ROB when they are
dispatched. Thus, actually we don't need the exception vector when an
instruction enters a function unit.

* exceptionVec, flushPipe, replayInst are reset when an instruction
enters function units.

* For execution units that don't have exceptions, we reset their output
exception vectors to avoid ROB to record them.

* Move replayInst to CtrlSignals.

BPU: Fix bug and significantly reduce false_hit 

This commit moves issue select logic in reservation stations to stage 0
from stage 1. It helps timing of stage 1, which load-to-load requires.

Now, reservation stations have the following stages:

* S0: enqueue and wakeup, select. Selection results are RegNext-ed.
* S1: data/uop read and data bypass. Bypassed results are RegNext-ed.
* S2: issue instructions to function units.

This commit adds 3-bit shift fused instructions. When the program
tries to add 8-byte index, these may be used.

List of fused instructions added in this commit:

* szewl3: `slli r1, r0, 32` + `srli r1, r0, 29`

* sr29add: `srli r1, r0, 29` + `add r1, r1, r2`

* MissQueue: send GrantAck immediately after first beat of GrantData

* MissQueue: add perf cnts

* MissQueue: fix assertion failure in perf cnt

* MissQueue: add perf cnts for proportion of load merge / load reject

* MissQueue: add perf cnt

* MissQueue: fix merge-conflict error

* mmu.l2tlb: add object TimeOutAssert

* mmu.l2tlb: add TimeOutAssert to Repeater

* mmu.l2tlb: cut down mem req buffer from 8 ptes to 1 pte each

* util: move some utils from MMUBundle to utils

This commit simplifies status logic in reservations stations. Module
StatusArray is mostly rewritten.

The following optimizations are applied:

* Wakeup now has higher priority than enqueue. This reduces the length
of the critical path of ALU back-to-back wakeup.

* Don't compare fpWen/rfWen if the reservation station does not have
float/int operands.

* Ignore status.valid or redirect for srcState update. For data capture,
these are necessary and not changed.

* Remove blocked and scheduled conditions in issue logic when the
reservation station does not have loadWait bit and feedback.

* misc: add submodule huancun

* huancun: integrate huancun to SoC as L3

* remove l2prefetcher

* update huancun

* Bump HuanCun

* Use HuanCun instead old L2/L3

* bump huancun

* bump huancun

* Set L3NBanks to 4

* Update rocketchip

* Bump huancun

* Bump HuanCun

* Optimize debug configs

* Configs: fix L3 bug

* Add TLLogger

* TLLogger: fix release ack address

* Support write prefix into database

* Recoding more tilelink info

* Add a database output format converter

* missqueue: add difftest port for memory difftest during refill

* misc: bump difftest

* misc: bump difftest & huancun

* missqueue: do not check refill data when get Grant

* Add directory debug tool

* config: increase client dir size for non-inclusive cache

* Bump difftest and huancun

* Update l2/l3 cache configs

* Remove deprecated fpga/*

* Remove cache test

* Remove L2 preftecher

* bump huancun

* Params: turn on l2 prefetch by default

* misc: remove duplicate chisel-tester2

* misc: remove sifive inclusive cache

* bump difftest

* bump huancun

* config: use 4MB L3 cache

* bump huancun

* bump difftest

* bump difftest
Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>
Co-authored-by: NTangDan <tangdan@ict.ac.cn>

This commit changes how uop and data are read in reservation stations.
It helps the issue timing.

Previously, we access payload array and data array after we decide the
instructions that we want to issue. This method makes issue selection
and array access serialized and brings critial path.

In this commit, we add one more read port to payload array and data
array. This extra read port is for the oldest instruction. We decide
whether to issue the oldest instruction and read uop/data
simultaneously. This change reduces the critical path to each selection
logic + read + Mux (previously it's selection + arbitration + read).

Variable oldestOverride indicates whether we choose the oldest ready
instruction instead of the normal selection. An oldestFirst option is
added to RSParams to parameterize whether we need the age logic. By
default, it is set to true unless the RS is for ALU. If the timing for
aged ALU rs meets, we will enable it later.

* mmu.l2tlb: l2tlb now support multiple parallel mem accesses

8 missqueue entry and 1 page table worker
mq entry only supports page leaf entry
ptw supports all the three level entries

* mmu.tlb: fix bug of mq.refill_vpn and out.ready

* mmu.tlb: fix bug of perf counter

* mmu.tlb: l2tlb's l3 now 128 sets and 4 ways

* mmu.tlb: miss queue now will 'merge' same mem req addr

* mmu.l2tlb: ptw doesn't access last level pte

* mmu.l2tlb: add mem req mask into ptw

func block_decoupled doesn't work well and has bug in signal ready

* mmu.l2tlb: fix bug of sfence to fsm

add a new state s_check_pte to ptw
fsm now take memPte from outside, doesn't store it inside
mem_resp_valid will arrive a cycle before mem_resp_data

* mmu.l2tlb: rm some state in fsm

* mmu.tlb: set itlb default size

* mmu.l2tlb: unkonwn mq wait bug, change code style to avoid it

* mmu.l2tlb: opt, mq's entry with cache_l3 would not be blocked

* mmu.l2tlb: add many time out assert

* mmu.l2tlb: fix bug of mq enq state change & wait_id

* Revert "mmu.tlb: l2tlb's l3 now 128 sets and 4 ways"

This reverts commit 216e4192e4b01e68ce5502135318bc2473434907.

* Revert "mmu.tlb: set itlb default size"

This reverts commit 670bf1e408384964c601c0a55defbc767eb80698.

* mmu.l2tlb: set miss queue size to 9 and set filter size to 8

if they are equal, itlb may loss its req

This commit adds some simple instruction fusion cases in decode stage.
Currently we only implement instruction pairs that can be fused into
RV64GCB instructions.

Instruction fusions are detected in the decode stage by FusionDecoder.
The decoder checks every two instructions and marks the first
instruction fused if they can be fused into one instruction. The second
instruction is removed by setting the valid field to false.

Simple fusion cases include sh1add, sh2add, sh3add, sexth, zexth, etc.

Currently, ftq in frontend needs every instruction to commit. However,
the second instruction is removed from the pipeline and will not commit.
To solve this issue, we temporarily add more bits to isFused to indicate
the offset diff of the two fused instruction. There are four
possibilities now. This feature may be removed later.

This commit also adds more instruction fusion cases that need changes
in both the decode stage and the funtion units. In this commit, we add
some opcode to the function units and fuse the new instruction pairs
into these new internal uops.

The list of opcodes we add in this commit is shown below:
- szewl1: `slli r1, r0, 32` + `srli r1, r0, 31`
- szewl2: `slli r1, r0, 32` + `srli r1, r0, 30`
- byte2: `srli r1, r0, 8` + `andi r1, r1, 255`
- sh4add: `slli r1, r0, 4` + `add r1, r1, r2`
- sr30add: `srli r1, r0, 30` + `add r1, r1, r2`
- sr31add: `srli r1, r0, 31` + `add r1, r1, r2`
- sr32add: `srli r1, r0, 32` + `add r1, r1, r2`
- oddadd: `andi r1, r0, 1`` + `add r1, r1, r2`
- oddaddw: `andi r1, r0, 1`` + `addw r1, r1, r2`
- orh48: mask off the first 16 bits and or with another operand
         (`andi r1, r0, -256`` + `or r1, r1, r2`)

Furthermore, this commit adds some complex instruction fusion cases to
the decode stage and function units. The complex instruction fusion cases
are detected after the instructions are decoded into uop and their
CtrlSignals are used for instruction fusion detection.

We add the following complex instruction fusion cases:
- addwbyte: addw and mask it with 0xff (extract the first byte)
- addwbit: addw and mask it with 0x1 (extract the first bit)
- logiclsb: logic operation and mask it with 0x1 (extract the first bit)
- mulw7: andi 127 and mulw instructions.
        Input to mul is AND with 0x7f if mulw7 bit is set to true.

* mmu.tlb: l2tlb's l3 now 128 sets and 4 ways

* mmu.tlb: set itlb default size

* Alu: fix andn, orn, xnor

* Decode: change instruction name

add new ittage indirect target predictor

dcache,lq: make dcache to lq refill faster

This commit assigns exu.io.out.fflags to RegNext(fu.io.fflags) if the
function unit has fastUopOut but has not implemented it. Previously
it causes a bug that fflags may be one cycle earlier than expected.

This commit also removes the extra logic in FmacExeUnit and
FmiscExeUnit. They are exactly the same as ExeUnit now.

* backend, rename: support elimination of mv inst whose lsrc=0
[known bug] instr page fault not properly raised after sfence.vma

* backend, roq: [bug fix] won't label me with exception as writebacked

This commit adds support for load balance between different issue ports
when the function unit is not pipelined and the reservation station has
more than one issue ports.

We use a ping pong bit to decide which port to issue the instruction. At
every clock cycle, the bit is flipped.

* mmu.l2tlb: l2tlb now support multiple parallel mem accesses

8 missqueue entry and 1 page table worker
mq entry only supports page leaf entry
ptw supports all the three level entries

* mmu.tlb: fix bug of mq.refill_vpn and out.ready

This commit adds assertion in MaskData to check the width of mask
and data. When the width of mask is smaller than the width of data,
(~mask & data) and (mask & data) will always clear the upper bits
of the data. This usually causes unexpected behavior.

This commit adds explicit width declarations where MaskData is used.

* Makefile: add '--gen-mem-verilog'

* FMA: spearate fadd/fmul/fma

* exu: enable fast uop out from fmacExeUnit
Co-authored-by: NYinan Xu <xuyinan@ict.ac.cn>