mmu.tlb: set itlb's and l2tlb's size (#1014)

* mmu.tlb: l2tlb's l3 now 128 sets and 4 ways

* mmu.tlb: set itlb default size

src/main/scala/xiangshan/Parameters.scala

@@ -148,7 +148,9 @@ case class XSCoreParameters
     fetchi = true,
     useDmode = false,
     sameCycle = true,
+    normalNWays = 32,
     normalReplacer = Some("plru"),
+    superNWays = 4,
     superReplacer = Some("plru"),
     shouldBlock = true
   ),

src/main/scala/xiangshan/cache/mmu/MMUConst.scala

@@ -56,8 +56,8 @@ case class L2TLBParameters
   l2nWays: Int = 4,
   l2Replacer: Option[String] = Some("setplru"),
   // l3
-  l3nSets: Int = 64,
-  l3nWays: Int = 8,
+  l3nSets: Int = 128,
+  l3nWays: Int = 4,
   l3Replacer: Option[String] = Some("setplru"),
   // sp
   spSize: Int = 16,