This commit re-pipelines ECC check logic in data cache and exception generate logic for better timing.
Now ecc error is checked 1 cycle after reading result from data sram. An extra cycle is added for load
writeback to ROB.

Future work: move the pipeline to https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/backend/CtrlBlock.scala#L266-L277, which add a regnext.

* dcache: repipeline ecc check logic for timing

* chore: fix normal loadAccessFault logic

* wbu: delay load unit wb for 1 cycle

* dcache: add 1 extra cycle for beu error report

* dcache: do not access plru when refill

Now we have accessed plru when load miss, we should not access plru
when refill

* dcache: not not access plru when miss queue full

It will help avoid invalid plru access when miss queue full

* feat: parameterize load/store pipeline, etc.

* fix: use LoadPipelineWidth rather than LoadQueueSize

* fix: parameterize `rdataPtrExtNext`

* SBuffer: fix idx update logic

* atomic: parameterize atomic logic in `MemBlock`

* StoreQueue: update allow enque requirement

* feat: support one load/store pipeline

* feat: parameterize `EnsbufferWidth`

* chore: resharp codes for better generated name

* mem: optimize missq reject to lq timing

DCache replay request is quite slow to generate, as it need to compare
load address with address in all valid miss queue entries.

Now we delay the usage of replay request from data cache.
Now replay request will not influence normal execuation flow until
load_s3 (1 cycle after load_s2, load result writeback to RS).

It is worth mentioning that "select refilling inst for load
writeback" will be disabled if dcacheRequireReplay in the
last cycle.

* dcache: compare probe block addr instead of full addr

* mem: do not replay from RS when ldld vio or fwd failed

ld-ld violation or forward failure will let an normal load inst replay
from fetch. If TLB hit and ld-ld violation / forward failure happens,
we write back that inst immediately. Meanwhile, such insts will not be
replayed from rs.

It should fix "mem: optimize missq reject to lq timing"

* mem: fix replay from rs condition

* mem: reduce refill to use latency

This commit update lq entry flag carefully in load_s3 to avoid extra
refill delay. It will remove the extra refill delay introduced by #1375
without harming memblock timing.

In #1375, we delayed load refill when dcache miss queue entry fails
to accept a miss. #1375 exchanges performance for better timing.

* mem: fix rs feedback priority

When dataInvalid && mshrFull, a succeed refill should not cancel
rs replay.

dcache.resp.bits.miss used to depend on tag_error, it causes severe
timing problem. That dependence is now removed.

Now when tag_error, we:

* Set access fault bit in exception vec
* Do not update miss queue. That is to say, if miss, that inst
may not be refilled
* Mark that inst as dataForwarded so it will not wait for refill
* Report error to CSR and BEU

If tag_error come with a miss, writeback taht inst from load
queue. Otherwise, writeback it from load pipeline.

* mem: fix ldld vio mask gen logic

* mem: fix lq released flag update logic

Make sure that every load before a probe has correct released flag

See the PR of this commit for illustration

* mem: fix ld-ld violation check logic

* ci: clean up workspace before do real test

* mem: reduce lq released flag update delay for 1 cycle

* chore: bump difftest to run no-smp diff

* ci: add mc test

* mem: fix lq released flag update logic

* chore: set difftest firstCommit_limit to 10000

* ci: use dual-nemu-so for mc test

* dcache: add source info in L1CacheErrorInfo

* ICache: fix valid signal and add source/opType

* dcache: fix bug in ecc error

* mem,csr: send full L1CacheErrorInfo to CSR

* icache: provide cache error info for CSR

* dcache: force resp hit if tag ecc error happens

* mem: reorg l1 cache error report path

Now dcache tag error will force trigger a hit

* dcache: fix readline ecc check error

* dcache: mainpipe will not be influenced by tag error

* dcache: fix data ecc check error

* dcache: if coh state is Nothing, do not raise error
Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>
Co-authored-by: NJinYue <jinyue20s@ict.ac.cn>

* dcache: use sram to build ecc array

* MainPipe: latch s1_encTag to last until s1_fire
Authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>

* dcache: let ecc error and l2 corrupt raise load af

If CSR.smblockctl.cache_error_enable is disabled, ecc error and l2 corrupt
will not raise any exception.

* mem: enable cache error by default

* mem: support store ecc check, add ecc error csr

Support store / atom ecc check (early version)
Add ecc error csr to distingush ecc error and other access fault

Timing opt and unit tests to be added.

* MissQueue: loose merging condition to ease timing stress

* MissQueue: remove grant_beats

* MissQueue: compare block addr, not the whole addr bits

* dcache: optimize timing for generating ready to sbuffer
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

This commit optimizes the coding style and timing for hardware
performance counters.

By default, performance counters are RegNext(RegNext(_)).

Now we RegNext(refill_req) for 1 cycle. It will provide more
time for refillShouldBeBlocked calcuation

* Add 1 cycle in refill pipe
Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>

* dcache: merge replace pipe with main pipe for timing reason

* MainPipe: fix bug in s3_fire

* MainPipe: fix bug in delay_release sent to wbq

* MainPipe: fix bug in blocking policy

* MainPipe: send io.replace_resp in stage 3

* MainPipe: fix bug in miss_id sent to wbq

* MainPipe: fix bug
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

* sbuffer: do flush correctly while draining sbuffer

* mem: disable EnableFastForward for timing reasons

* sbuffer: optimize forward mask gen timing

* dcache: block main pipe req if refill req is valid

Refill req comes from refill arbiter. There is not time left for index
conflict check. Now we block all main pipe req when refill
req comes from miss queue.

* dcache: delay some resp signals for better timing

* dcache: optimize wbq enq entry select timing

* dcache: decouple missq req.valid to valid & cancel

* valid is fast, it is used to select which miss req will be sent to
miss queue
* cancel can be slow to generate, it will cancel miss queue req in the
last moment

* sbuffer: optimize noSameBlockInflight check timing

* FDivSqrt: use hierarchy API to avoid dedup bug

* Dedup: use hartId from io port instead of core parameters

* Bump fudian

* dcache: do not check readline rmask

This should opt bank_conflict check timing

* dcache: block replace if store s1 valid

It takes quite long to generate way_en in mainpipe s1. As a result,
use s1 way_en to judge if replace should be blocked will cause severe
timing problem

Now we simply block replace if mainpipe.s1.valid

Refill timing to be optmized later

* sbuffer: delay sbuffer enqueue for 1 cycle

With store queue growing larger, read data from datamodule nearly
costs a whole cycle. Hence we delay sbuffer enqueue for 1 cycle
for better timing.

* dcache: reduce probe queue size

* dcache: replace probe pipe req RRArbiter with Arbiter

* dcache: reduce writeback queue size for timing opt

* dcache: delay wbqueue enqueue req for 1 cycle

Addr enqueue req will compare its addr with addrs in all writeback
entries to check if it should be blocked. Delay enqueue req will
give that process more time.

* dcache: set default replacer to setplru

It does not change current design

* dcache: fix wbqueue req_delayed deadlock

We delayed writeback queue enq for 1 cycle, missQ req does not
depend on wbQ enqueue. As a result, missQ req may be blocked
in req_delayed. When grant comes, that req should also be updated

* dcache: remove outdated require

* dcache: replace missReqArb RRArbiter with Arbiter

* perf: add detailed histogram for low dcache latency

* dcache: fix wbqueue entry alloc logic

* dcache: opt probe req timing

In current design, resv_set is maintained in dcache. All probe req
will be blocked if that addr is in resv_set.

However, checking if that addr is in resv_set costs almost half a cycle,
which causes severe timing problem.

Now when we update update_resv_set, all probe reqs will be blocked
in the next cycle. It should give Probe reservation set addr compare an
independent cycle, which will lead to better timing

* Add perf counters
* add reg from hpm counter source
* add print perfcounter enable

* mem: support ld-ld violation check
* mem: do not fast wakeup if ld vio check failed
* mem: disable ld-ld vio check after core reset

In the latest version of dcache, replace pipe is blocked by main pipe according to set, because replace and store/probe should not try to modify data or meta at the same time, which might result in inconsistency between data and meta. For performance reasons, replace is blocked by store, not the other way around, because replace can be delayed so it can bring dirty data written by store down to L2.

Now this consideration brings another dead-lock. Store buffer keeps sending store request without a break, so main pipe stays occupied handling store. In the meantime, miss queue rejects these store request so store buffer keeps replaying all the time. Replace pipe cannot advance because of set conflict with main pipe, so the corresponding miss entry cannot be released and keeps rejecting new store request.

To break this dead-lock, this pull request tries to set replace pipe higher priority than main pipe, and let write-back queue handle consistency between data and meta if a store interrupts.

Now we merge them for timing opt, unit test to be added later

* L1D: provide independent meta array for load pipe

* misc: reorg files in cache dir

* chore: reorg l1d related files

* bump difftest: use clang to compile verialted files

* dcache: add BankedDataArray

* dcache: fix data read way_en

* dcache: fix banked data wmask

* dcache: replay conflict correctly

 When conflict is detected:
* Report replay
* Disable fast wakeup

* dcache: fix bank addr match logic

* dcache: add bank conflict perf counter

* dcache: fix miss perf counters

* chore: make lsq data print perttier

* dcache: enable banked ecc array

* dcache: set dcache size to 128KB

* dcache: read mainpipe data from banked data array

* dcache: add independent mainpipe data read port

* dcache: revert size change

* Size will be changed after main pipe refactor

* Merge remote-tracking branch 'origin/master' into l1-size

* dcache: reduce banked data load conflict

* MainPipe: ReleaseData for all replacement even if it's clean

* dcache: set dcache size to 128KB

BREAKING CHANGE: l2 needed to provide right vaddr index to probe l1,
and it has to help l1 to avoid addr alias problem

* chore: fix merge conflict

* Change L2 to non-inclusive / Add alias bits in L1D

* debug: hard coded dup data array for debuging

* dcache: fix ptag width

* dcache: fix amo main pipe req

* dcache: when probe, use vaddr for main pipe req

* dcache: include vaddr in atomic unit req

* dcache: fix get_tag() function

* dcache: fix writeback paddr

* huancun: bump version

* dcache: erase block offset bits in release addr

* dcache: do not require probe vaddr != 0

* dcache: opt banked data read timing

* bump huancun

* dcache: fix atom unit pipe req vaddr

* dcache: simplify main pipe writeback_vaddr

* bump huancun

* dcache: remove debug data array

* Turn on all usr bits in L1

* Bump huancun

* Bump huancun

* enable L2 prefetcher

* bump huancun

* set non-inclusive L2/L3 + 128KB L1 as default config

* Use data in TLBundleB to hint ProbeAck beeds data

* mmu.l2tlb: mem_resp now fills multi mq pte buffer

mq entries can just deq without accessing l2tlb cache

* dcache: handle dirty userbit

* bump huancun

* chore: l1 cache code clean up

* Remove l1plus cache
* Remove HasBankedDataArrayParameters

* Add bus pmu between L3 and Mem

* bump huncun

* IFU: add performance counters and mmio af

* icache replacement policy moniter

* ifu miss situation moniter

* icache miss rate

* raise access fault when found mmio req

* Add framework for seperated main pipe and reg meta array

* Rewrite miss queue for seperated pipes

* Add RefillPipe

* chore: rename NewSbuffer.scala

* cache: add CacheInstruction opcode and reg list

* CSR: add cache control registers

* Add Replace Pipe

* CacheInstruction: add CSRs for cache instruction

* mem: remove store replay unit

* Perf counter to be added
* Timing opt to be done

* mem: update sbuffer to support new dcache

* sbuffer: fix missqueue time out logic

* Merge remote-tracking branch 'origin/master' into dcache-rm-sru

* chore: fix merge conflict, remove nStoreReplayEntries

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)

* Rewrite main pipe

* ReplacePipe: read meta to decide whether data should be read

* RefillPipe: add a store resp port

* MissQueue: new req should be rejected according to set+way

* Add replacement policy interface

* sbuffer: give missq replay the highest priority

Now we give missqReplayHasTimeOut the highest priority, as eviction
has already happened
Besides, it will fix the problem that fix dcache eviction generate logic
gives the wrong sbuffer id

* Finish DCache framework

* Split meta & tag and use regs to build meta array

* sbuffer: use new dcache io

* dcache: update dcache resp in memblock and fake d$

* Add atomics processing flow

* Refactor Top

* Bump huancun

* DCacheWrapper: disable ld fast wakeup only when bank conflict

* sbuffer: update dcache_resp difftest io

* MainPipe: fix combinational loop

* Sbuffer: fix bug in assert

* RefillPipe: fix bug of getting tag from addr

* dcache: ~0.U should restrict bit-width

* LoadPipe: fix bug in assert

* ReplacePipe: addr to be replaced should be block-aligned

* MainPipe: fix bug in required coh sending to miss queue

* DCacheWrapper: tag write in refill pipe should always be ready

* MainPipe: use replacement way_en when the req is from miss queue

* MissQueue: refill data should be passed on to main pipe

* MainPipe: do not use replacement way when tag match

* CSR: clean up cache op regs

* chore: remove outdated comments

* ReplacePipe: fix stupid bug

* dcache: replace checkOneHot with assert

* alu: fix bug of rev8 & orc.b instruction

* MissQueue: fix bug in the condition of mshr accepting a req

* MissQueue: add perf counters

* chore: delete out-dated code

* chore: add license

* WritebackQueue: distinguish id from miss queue

* AsynchronousMetaArray: fix bug

* Sbuffer: fix difftest io

* DCacheWrapper: duplicate one more tag copy for main pipe

* Add perf cnt to verify whether replacing is too early

* dcache: Release needs to wait for refill pipe

* WritebackQueue: fix accept condition

* MissQueue: remove unnecessary assert

* difftest: let refill check ingore illegal mem access

* Parameters: enlarge WritebackQueue to break dead-lock

* DCacheWrapper: store hit wirte should not be interrupted by refill

* Config: set nReleaseEntries to twice of nMissEntries

* DCacheWrapper: main pipe read should block refill pipe by set
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
Co-authored-by: NLinJiawei <linjiav@outlook.com>
Co-authored-by: NTangDan <tangdan@ict.ac.cn>
Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>
Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>
Co-authored-by: NJinYue <jinyue20s@ict.ac.cn>
Co-authored-by: Zhangfw <471348957@qq.com>

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)

* Refactor Top

* Bump huancun

* alu: fix bug of rev8 & orc.b instruction
Co-authored-by: Zhangfw <471348957@qq.com>

* [WIP] PMP: add pmp to tlb & csr(ptw part is not added)

* pmp: add pmp, unified

* pmp: add pmp, distributed but same cycle

* pmp: pmp resp next cycle

* [WIP] PMP: add l2tlb missqueue pmp support

* pmp: add pmp to ptw and regnext pmp for frontend

* pmp: fix bug of napot-match

* pmp: fix bug of method aligned

* pmp: when write cfg, update mask

* pmp: fix bug of store af getting in store unit

* tlb: fix bug, add af check(access fault from ptw)

* tlb: af may have higher priority than pf when ptw has af

* ptw: fix bug of sending paddr to pmp and recv af

* ci: add pmp unit test

* pmp: change PMPPlatformGrain to 6 (512bits)

* pmp: fix bug of read_addr

* ci: re-add pmp unit test

* l2tlb: lazymodule couldn't use @chiselName

* l2tlb: fix bug of l2tlb missqueue duplicate req's logic

filt the duplicate req:
old: when enq, change enq state to different state
new: enq + mem.req.fire, more robust

* pmp: pmp checker now supports samecycle & regenable

Make bank conflict feedback 1 cycle earlier

* add soft prefetch
Add the softprefetch. Actually, prefetch.r&w are an ORI which's ldest is x0, we distinguish it in decodeUnit and send it to ld func unit. Then, we modified some interaction signals in ordinary Load steps.

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

* L1D: provide independent meta array for load pipe

* misc: reorg files in cache dir

* chore: reorg l1d related files

* bump difftest: use clang to compile verialted files

* dcache: add BankedDataArray

* dcache: fix data read way_en

* dcache: fix banked data wmask

* dcache: replay conflict correctly

 When conflict is detected:
* Report replay
* Disable fast wakeup

* dcache: fix bank addr match logic

* dcache: add bank conflict perf counter

* dcache: fix miss perf counters

* chore: make lsq data print perttier

* dcache: enable banked ecc array

* dcache: set dcache size to 128KB

* dcache: read mainpipe data from banked data array

* dcache: add independent mainpipe data read port

* dcache: revert size change

* Size will be changed after main pipe refactor

* Merge remote-tracking branch 'origin/master' into l1-size

* dcache: reduce banked data load conflict

* MainPipe: ReleaseData for all replacement even if it's clean

* dcache: set dcache size to 128KB

BREAKING CHANGE: l2 needed to provide right vaddr index to probe l1,
and it has to help l1 to avoid addr alias problem

* chore: fix merge conflict

* Change L2 to non-inclusive / Add alias bits in L1D

* debug: hard coded dup data array for debuging

* dcache: fix ptag width

* dcache: fix amo main pipe req

* dcache: when probe, use vaddr for main pipe req

* dcache: include vaddr in atomic unit req

* dcache: fix get_tag() function

* dcache: fix writeback paddr

* huancun: bump version

* dcache: erase block offset bits in release addr

* dcache: do not require probe vaddr != 0

* dcache: opt banked data read timing

* bump huancun

* dcache: fix atom unit pipe req vaddr

* dcache: simplify main pipe writeback_vaddr

* bump huancun

* dcache: remove debug data array

* Turn on all usr bits in L1

* Bump huancun

* Bump huancun

* enable L2 prefetcher

* bump huancun

* set non-inclusive L2/L3 + 128KB L1 as default config

* Use data in TLBundleB to hint ProbeAck beeds data

* mmu.l2tlb: mem_resp now fills multi mq pte buffer

mq entries can just deq without accessing l2tlb cache

* dcache: handle dirty userbit

* bump huancun

* chore: l1 cache code clean up

* Remove l1plus cache
* Remove HasBankedDataArrayParameters

* Add bus pmu between L3 and Mem

* bump huncun

* dcache: fix l1 probe index generate logic

* Now right probe index will be used according to the len of alias bits

* dcache: clean up amo pipeline

* DCacheParameter rowBits will be removed in the future, now we set it to 128
to make dcache work

* dcache: fix amo word index

* bump huancun
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>
Co-authored-by: NTangDan <tangdan@ict.ac.cn>
Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>

* misc: add submodule huancun

* huancun: integrate huancun to SoC as L3

* remove l2prefetcher

* update huancun

* Bump HuanCun

* Use HuanCun instead old L2/L3

* bump huancun

* bump huancun

* Set L3NBanks to 4

* Update rocketchip

* Bump huancun

* Bump HuanCun

* Optimize debug configs

* Configs: fix L3 bug

* Add TLLogger

* TLLogger: fix release ack address

* Support write prefix into database

* Recoding more tilelink info

* Add a database output format converter

* missqueue: add difftest port for memory difftest during refill

* misc: bump difftest

* misc: bump difftest & huancun

* missqueue: do not check refill data when get Grant

* Add directory debug tool

* config: increase client dir size for non-inclusive cache

* Bump difftest and huancun

* Update l2/l3 cache configs

* Remove deprecated fpga/*

* Remove cache test

* Remove L2 preftecher

* bump huancun

* Params: turn on l2 prefetch by default

* misc: remove duplicate chisel-tester2

* misc: remove sifive inclusive cache

* bump difftest

* bump huancun

* config: use 4MB L3 cache

* bump huancun

* bump difftest

* bump difftest
Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>
Co-authored-by: NTangDan <tangdan@ict.ac.cn>

* bump chisel to 3.5

* Remove deprecated 'toBool' && disable tl monitor

* Update RocketChip / Re-enable TLMonitor

* Makefile: remove '--infer-rw'