mem: let lq refill width be equal to l1d bus width

src/main/scala/xiangshan/cache/DCacheWrapper.scala

@@ -85,7 +85,7 @@ class DCacheLineResp(implicit p: Parameters) extends DCacheBundle
 class Refill(implicit p: Parameters) extends DCacheBundle
 {
   val addr   = UInt(PAddrBits.W)
-  val data   = UInt((cfg.blockBytes * 8).W)
+  val data   = UInt(l1BusDataWidth.W)
   def dump() = {
     XSDebug("Refill: addr: %x data: %x\n", addr, data)
   }

src/main/scala/xiangshan/cache/L1Cache.scala

@@ -39,11 +39,13 @@ trait HasL1CacheParameters extends HasXSParameter
   def nSets = cacheParams.nSets
   def nWays = cacheParams.nWays
   def blockBytes = cacheParams.blockBytes
+  def refillBytes = l1BusDataWidth / 8
   def blockBits = blockBytes * 8
 
   def idxBits = log2Up(cacheParams.nSets)
   def wayBits = log2Up(nWays)
   def blockOffBits = log2Up(cacheParams.blockBytes)
+  def refillOffBits = log2Up(l1BusDataWidth / 8)
 
   def untagBits = blockOffBits + idxBits
   // 4K page
@@ -71,6 +73,7 @@ trait HasL1CacheParameters extends HasXSParameter
   def wordOffBits = log2Up(wordBytes)
   // the number of words in a block
   def blockWords = blockBytes / wordBytes
+  def refillWords = refillBytes / wordBytes
 
   def idxMSB = untagBits-1
   def idxLSB = blockOffBits
@@ -81,6 +84,7 @@ trait HasL1CacheParameters extends HasXSParameter
   def get_idx(addr: UInt) = addr(untagBits-1, blockOffBits)
   def get_block(addr: UInt) = addr >> blockOffBits
   def get_block_addr(addr: UInt) = (addr >> blockOffBits) << blockOffBits
+  def get_refill_addr(addr: UInt) = (addr >> refillOffBits) << refillOffBits
 
   def get_beat(addr: UInt) = addr(blockOffBits - 1, beatOffBits)
   def get_row(addr: UInt) = addr(blockOffBits - 1, rowOffBits)

src/main/scala/xiangshan/cache/MissQueue.scala

@@ -308,9 +308,23 @@ class MissEntry(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule
   // put should_refill_data out of RegNext
   // so that when load miss are merged at refill_done
   // we can still refill data back
-  io.refill.valid := RegNext(state === s_refill_resp && refill_done) && should_refill_data
-  io.refill.bits.addr := req.addr
-  io.refill.bits.data := refill_data.asUInt
+  //
+  // Now refill to load queue width l1BusDataWidth, to load queue refill req
+  // will be issued as soon as data is ready (stored in regs in miss queue)
+  val refill_data_splited = WireInit(VecInit(Seq.tabulate(cfg.blockBytes * 8 / l1BusDataWidth)(i => {
+    val data = refill_data.asUInt
+    data((i + 1) * l1BusDataWidth - 1, i * l1BusDataWidth)
+  })))
+  // val refill_addr_splited = WireInit(VecInit(Seq.tabulate(cfg.blockBytes * 8 / l1BusDataWidth)(i =>
+  //   req.addr + (i << refillOffBits)
+  // )))
+  io.refill.valid := RegNext(state === s_refill_resp && io.mem_grant.fire()) && should_refill_data
+  io.refill.bits.addr := RegNext(req.addr + (refill_count << refillOffBits))
+  io.refill.bits.data := refill_data_splited(RegNext(refill_count))
+  when(io.refill.fire()){
+    io.refill.bits.dump()
+    XSDebug("refill_count %d\n", RegNext(refill_count));
+  }
 
   when (state === s_main_pipe_req) {
     io.pipe_req.valid := true.B

src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala

@@ -708,7 +708,7 @@ class LoadQueue(implicit p: Parameters) extends XSModule
 
   for (i <- 0 until LoadQueueSize) {
     if (i % 4 == 0) XSDebug("")
-    XSDebug(false, true.B, "%x [%x] ", uop(i).cf.pc, dataModule.io.debug(i).paddr)
+    XSDebug(false, true.B, "%x [%x] ", uop(i).cf.pc, debug_paddr(i))
     PrintFlag(allocated(i), "a")
     PrintFlag(allocated(i) && datavalid(i), "v")
     PrintFlag(allocated(i) && writebacked(i), "w")

src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala

@@ -71,7 +71,7 @@ class LQPaddrModule(numEntries: Int, numRead: Int, numWrite: Int)(implicit p: Pa
   }
 
   for (j <- 0 until numEntries) {
-    io.refillMmask(j) := get_block_addr(io.refillMdata) === get_block_addr(data(j))
+    io.refillMmask(j) := get_refill_addr(io.refillMdata) === get_refill_addr(data(j))
   }
 
   // DataModuleTemplate should not be used when there're any write conflicts
@@ -180,7 +180,7 @@ class CoredataModule(numEntries: Int, numRead: Int, numWrite: Int)(implicit p: P
     val wdata = Input(Vec(numWrite, UInt(XLEN.W)))
     // masked write
     val mwmask = Input(Vec(numEntries, Bool()))
-    val refillData = Input(UInt((cfg.blockBytes * 8).W))
+    val refillData = Input(UInt(l1BusDataWidth.W))
 
     // fwdMask io
     val fwdMaskWdata = Input(Vec(numWrite, UInt(8.W)))
@@ -188,14 +188,14 @@ class CoredataModule(numEntries: Int, numRead: Int, numWrite: Int)(implicit p: P
     // fwdMaskWaddr = waddr
 
     // paddr io
-    // 3 bits in paddr need to be stored in CoredataModule for refilling
+    // refillOffBits - wordOffBits bits in paddr need to be stored in CoredataModule for refilling
     val paddrWdata = Input(Vec(numWrite, UInt((PAddrBits).W)))
     val paddrWen = Input(Vec(numWrite, Bool()))
   })
 
-  val data8 = Seq.fill(8)(Module(new MaskedSyncDataModuleTemplate(UInt(8.W), numEntries, numRead, numWrite, numMWrite = blockWords)))
+  val data8 = Seq.fill(8)(Module(new MaskedSyncDataModuleTemplate(UInt(8.W), numEntries, numRead, numWrite, numMWrite = refillWords)))
   val fwdMask = Reg(Vec(numEntries, UInt(8.W)))
-  val wordIndex = Reg(Vec(numEntries, UInt((blockOffBits - wordOffBits).W)))
+  val wordIndex = Reg(Vec(numEntries, UInt((refillOffBits - wordOffBits).W)))
 
   // read ports
   for (i <- 0 until numRead) {
@@ -227,16 +227,16 @@ class CoredataModule(numEntries: Int, numRead: Int, numWrite: Int)(implicit p: P
 
   // select refill data
   // split dcache result into words
-  val words = VecInit((0 until blockWords) map { i => io.refillData(DataBits * (i + 1) - 1, DataBits * i)})
+  val words = VecInit((0 until refillWords) map { i => io.refillData(DataBits * (i + 1) - 1, DataBits * i)})
   // select refill data according to wordIndex (paddr)
   for (i <- 0 until 8) {
-    for (j <- 0 until blockWords) {
+    for (j <- 0 until refillWords) {
       data8(i).io.mwdata(j) := words(j)(8*(i+1)-1, 8*i)
     }
   }
 
   // gen refill wmask
-  for (j <- 0 until blockWords) {
+  for (j <- 0 until refillWords) {
     for (k <- 0 until numEntries) {
       val wordMatch = wordIndex(k) === j.U
       for (i <- 0 until 8) {
@@ -272,7 +272,7 @@ class LoadQueueData(size: Int, wbNumRead: Int, wbNumWrite: Int)(implicit p: Para
     val refill = new Bundle() {
       val valid = Input(Bool())
       val paddr = Input(UInt(PAddrBits.W))
-      val data = Input(UInt((cfg.blockBytes * 8).W))
+      val data = Input(UInt(l1BusDataWidth.W))
       val refillMask = Input(Vec(size, Bool()))
       val matchMask = Output(Vec(size, Bool()))
     }