Refactor top (#1093)

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)

* Refactor Top

* Bump huancun

* alu: fix bug of rev8 & orc.b instruction
Co-authored-by: Zhangfw <471348957@qq.com>

huancun @ 8560bc62

-Subproject commit 59a7febb43f9c8e6bb15e62712af5e3a6cb44a37
+Subproject commit 8560bc6265bbefc85cfb648cdfa90c92e1aa2a57

src/main/scala/device/AXI4RAM.scala

@@ -22,8 +22,6 @@ import chisel3.util._
 import chisel3.experimental.ExtModule
 import freechips.rocketchip.amba.axi4.{AXI4EdgeParameters, AXI4MasterNode, AXI4SlaveNode}
 import freechips.rocketchip.diplomacy.{AddressSet, InModuleBody, LazyModule, LazyModuleImp, RegionType}
-import top.HaveAXI4MemPort
-import xiangshan.HasXSParameter
 import utils.MaskExpand
 
 class RAMHelper(memByte: BigInt) extends ExtModule {
@@ -112,9 +110,6 @@ class AXI4RAMWrapper
   ram.node := mnode
 
   val io_axi4 = InModuleBody{ mnode.makeIOs() }
-  def connectToSoC(soc: HaveAXI4MemPort) = {
-    io_axi4 <> soc.memory
-  }
 
   lazy val module = new LazyModuleImp(this){}
 }

src/main/scala/system/SoC.scala

@@ -19,9 +19,17 @@ package system
 import chipsalliance.rocketchip.config.{Field, Parameters}
 import chisel3._
 import chisel3.util._
+import device.DebugModule
+import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4MasterNode, AXI4MasterParameters, AXI4MasterPortParameters, AXI4SlaveNode, AXI4SlaveParameters, AXI4SlavePortParameters, AXI4ToTL, AXI4UserYanker}
+import freechips.rocketchip.devices.tilelink.{CLINT, CLINTParams, DevNullParams, PLICParams, TLError, TLPLIC}
+import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
+import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
 import xiangshan.{DebugOptionsKey, HasXSParameter, XSBundle, XSCore, XSCoreParameters}
 import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, L1BusErrors}
+import freechips.rocketchip.tilelink.{BankBinder, TLBuffer, TLCacheCork, TLFIFOFixer, TLTempNode, TLToAXI4, TLWidthWidget, TLXbar}
+import huancun.debug.TLLogger
 import huancun.{CacheParameters, HCCacheParameters}
+import top.BusPerfMonitor
 
 case object SoCParamsKey extends Field[SoCParameters]
 
@@ -68,26 +76,188 @@ trait HasSoCParameter {
 class ILABundle extends Bundle {}
 
 
-class L1CacheErrorInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {
-  val paddr = Valid(UInt(soc.PAddrBits.W))
-  // for now, we only detect ecc
-  val ecc_error = Valid(Bool())
+abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
+  val bankedNode = BankBinder(L3NBanks, L3BlockSize)
+  val peripheralXbar = TLXbar()
+  val l3_xbar = TLXbar()
 }
 
-class XSL1BusErrors(val nCores: Int)(implicit val p: Parameters) extends BusErrors {
-  val icache = Vec(nCores, new L1CacheErrorInfo)
-  val l1plus = Vec(nCores, new L1CacheErrorInfo)
-  val dcache = Vec(nCores, new L1CacheErrorInfo)
-
-  override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] =
-    List.tabulate(nCores){i =>
-      List(
-        Some(icache(i).paddr, s"IBUS_$i", s"Icache_$i bus error"),
-        Some(icache(i).ecc_error, s"I_ECC_$i", s"Icache_$i ecc error"),
-        Some(l1plus(i).paddr, s"L1PLUS_$i", s"L1PLUS_$i bus error"),
-        Some(l1plus(i).ecc_error, s"L1PLUS_ECC_$i", s"L1PLUS_$i ecc error"),
-        Some(dcache(i).paddr, s"DBUS_$i", s"Dcache_$i bus error"),
-        Some(dcache(i).ecc_error, s"D_ECC_$i", s"Dcache_$i ecc error")
-      )
-    }.flatten
+// We adapt the following three traits from rocket-chip.
+// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
+trait HaveSlaveAXI4Port {
+  this: BaseSoC =>
+
+  val idBits = 14
+
+  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
+    Seq(AXI4MasterParameters(
+      name = "dma",
+      id = IdRange(0, 1 << idBits)
+    ))
+  )))
+  private val errorDevice = LazyModule(new TLError(
+    params = DevNullParams(
+      address = Seq(AddressSet(0x0, 0x7fffffffL)),
+      maxAtomic = 8,
+      maxTransfer = 64),
+    beatBytes = L3InnerBusWidth / 8
+  ))
+  private val error_xbar = TLXbar()
+
+  error_xbar :=
+    TLFIFOFixer() :=
+    TLWidthWidget(16) :=
+    AXI4ToTL() :=
+    AXI4UserYanker(Some(1)) :=
+    AXI4Fragmenter() :=
+    AXI4IdIndexer(1) :=
+    l3FrontendAXI4Node
+  errorDevice.node := error_xbar
+  l3_xbar :=
+    TLBuffer() :=
+    error_xbar
+
+  val dma = InModuleBody {
+    l3FrontendAXI4Node.makeIOs()
+  }
+}
+
+trait HaveAXI4MemPort {
+  this: BaseSoC =>
+  val device = new MemoryDevice
+  // 40-bit physical address
+  val memRange = AddressSet(0x00000000L, 0xffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
+  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
+    AXI4SlavePortParameters(
+      slaves = Seq(
+        AXI4SlaveParameters(
+          address = memRange,
+          regionType = RegionType.UNCACHED,
+          executable = true,
+          supportsRead = TransferSizes(1, L3BlockSize),
+          supportsWrite = TransferSizes(1, L3BlockSize),
+          interleavedId = Some(0),
+          resources = device.reg("mem")
+        )
+      ),
+      beatBytes = L3OuterBusWidth / 8
+    )
+  ))
+
+  val mem_xbar = TLXbar()
+  mem_xbar :=* TLBuffer() :=* TLCacheCork() :=* bankedNode
+  memAXI4SlaveNode :=
+    AXI4UserYanker() :=
+    AXI4Deinterleaver(L3BlockSize) :=
+    TLToAXI4() :=
+    TLWidthWidget(L3OuterBusWidth / 8) :=
+    mem_xbar
+
+  val memory = InModuleBody {
+    memAXI4SlaveNode.makeIOs()
+  }
+}
+
+trait HaveAXI4PeripheralPort { this: BaseSoC =>
+  // on-chip devices: 0x3800_0000 - 0x3fff_ffff 0x0000_0000 - 0x0000_0fff
+  val onChipPeripheralRange = AddressSet(0x38000000L, 0x07ffffffL)
+  val uartRange = AddressSet(0x40600000, 0xf)
+  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
+  val uartParams = AXI4SlaveParameters(
+    address = Seq(uartRange),
+    regionType = RegionType.UNCACHED,
+    supportsRead = TransferSizes(1, 8),
+    supportsWrite = TransferSizes(1, 8),
+    resources = uartDevice.reg
+  )
+  val peripheralRange = AddressSet(
+    0x0, 0x7fffffff
+  ).subtract(onChipPeripheralRange).flatMap(x => x.subtract(uartRange))
+  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
+    Seq(AXI4SlaveParameters(
+      address = peripheralRange,
+      regionType = RegionType.UNCACHED,
+      supportsRead = TransferSizes(1, 8),
+      supportsWrite = TransferSizes(1, 8),
+      interleavedId = Some(0)
+    ), uartParams),
+    beatBytes = 8
+  )))
+
+  peripheralNode :=
+    AXI4UserYanker() :=
+    AXI4Deinterleaver(8) :=
+    TLToAXI4() :=
+    peripheralXbar
+
+  val peripheral = InModuleBody {
+    peripheralNode.makeIOs()
+  }
+
+}
+
+class SoCMisc()(implicit p: Parameters) extends BaseSoC
+  with HaveAXI4MemPort
+  with HaveAXI4PeripheralPort
+  with HaveSlaveAXI4Port
+{
+  val peripheral_ports = Array.fill(NumCores) { TLTempNode() }
+  val core_to_l3_ports = Array.fill(NumCores) { TLTempNode() }
+
+  val l3_in = TLTempNode()
+  val l3_out = TLTempNode()
+  val l3_mem_pmu = BusPerfMonitor(enable = !debugOpts.FPGAPlatform)
+
+  l3_in :*= TLBuffer() :*= l3_xbar
+  bankedNode :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform) :*= l3_mem_pmu :*= l3_out
+
+  if(soc.L3CacheParamsOpt.isEmpty){
+    l3_out :*= l3_in
+  }
+
+  for(port <- peripheral_ports) {
+    peripheralXbar := port
+  }
+
+  for ((core_out, i) <- core_to_l3_ports.zipWithIndex){
+    l3_xbar :=* TLBuffer() :=* TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform) :=* core_out
+  }
+
+  val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8))
+  clint.node := peripheralXbar
+
+  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
+    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
+    lazy val module = new LazyModuleImp(this){
+      val in = IO(Input(Vec(num, Bool())))
+      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
+    }
+  }
+
+  val plic = LazyModule(new TLPLIC(PLICParams(0x3c000000L), 8))
+  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
+
+  plic.intnode := plicSource.sourceNode
+  plic.node := peripheralXbar
+
+  val debugModule = LazyModule(new DebugModule(NumCores)(p))
+  debugModule.debug.node := peripheralXbar
+  debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
+    l3_xbar := TLBuffer() := TLWidthWidget(1) := sb2tl.node
+  }
+
+  lazy val module = new LazyModuleImp(this){
+
+    val debug_module_io = IO(chiselTypeOf(debugModule.module.io))
+    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
+
+    debugModule.module.io <> debug_module_io
+    plicSource.module.in := ext_intrs.asBools
+
+    val freq = 100
+    val cnt = RegInit(freq.U)
+    val tick = cnt === 0.U
+    cnt := Mux(tick, freq.U, cnt - 1.U)
+    clint.module.io.rtcTick := tick
+  }
 }

src/main/scala/top/BusPerfMonitor.scala

 package top
 
 import chipsalliance.rocketchip.config.Parameters
-import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
+import freechips.rocketchip.diplomacy.{AdapterNode, LazyModule, LazyModuleImp}
 import freechips.rocketchip.tilelink._
 import chisel3._
 import chisel3.util._
 import utils.{XSPerfAccumulate, XSPerfPrint}
 
-class BusPerfMonitor(enable: Boolean)(implicit p: Parameters) extends LazyModule {
-
+class BusPerfMonitor()(implicit p: Parameters) extends LazyModule {
   val node = TLAdapterNode()
-
-  lazy val module = if(enable) {
-    new BusPerfMonitorImp(this)
-  } else new BaseBusPerfMonitorImp(this)
-
+  lazy val module = new BusPerfMonitorImp(this)
 }
 
-class BaseBusPerfMonitorImp(outer: BusPerfMonitor)
+class BusPerfMonitorImp(outer: BusPerfMonitor)
   extends LazyModuleImp(outer)
 {
+
   outer.node.in.zip(outer.node.out).foreach{
     case ((in, edgeIn), (out, edgeOut)) =>
       out <> in
   }
-}
-
-class BusPerfMonitorImp(outer: BusPerfMonitor)
-  extends BaseBusPerfMonitorImp(outer)
-{
 
   def PERF_CHN[T <: TLChannel](clientName: String, chn: DecoupledIO[T]) = {
 
@@ -89,8 +80,12 @@ class BusPerfMonitorImp(outer: BusPerfMonitor)
 }
 
 object BusPerfMonitor {
-  def apply(enable: Boolean = false)(implicit p: Parameters): TLAdapterNode = {
-    val busPMU = LazyModule(new BusPerfMonitor(enable))
-    busPMU.node
+  def apply(enable: Boolean = false)(implicit p: Parameters) = {
+    if(enable){
+      val busPMU = LazyModule(new BusPerfMonitor())
+      busPMU.node
+    } else {
+      TLTempNode()
+    }
   }
 }

src/main/scala/top/Configs.scala

@@ -245,7 +245,7 @@ class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1
         inclusive = inclusive,
         clientCaches = upParams.cores.map{ core =>
           val l2params = core.L2CacheParamsOpt.get.toCacheParams
-          l2params.copy(sets = 2 * l2params.sets, ways = l2params.ways + 1)
+          l2params.copy(sets = 2 * l2params.sets, ways = l2params.ways)
         },
         enablePerf = true
       ))
@@ -279,7 +279,7 @@ class DefaultConfig(n: Int = 1) extends Config(
 )
 
 class LargeConfig(n: Int = 1) extends Config(
-  new WithNKBL3(16 * 1024, inclusive = false, banks = 4)
+  new WithNKBL3(10 * 1024, inclusive = false, banks = 4, ways = 10)
     ++ new WithNKBL2(2 * 512, inclusive = false, banks = 2, alwaysReleaseData = true)
     ++ new WithNKBL1D(128)
     ++ new BaseConfig(n)

src/main/scala/top/Top.scala

@@ -34,199 +34,20 @@ import freechips.rocketchip.interrupts._
 import freechips.rocketchip.jtag.JTAGIO
 import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen}
 import freechips.rocketchip.tilelink
-import freechips.rocketchip.util.{ElaborationArtefacts, HasRocketChipStageUtils}
+import freechips.rocketchip.util.{ElaborationArtefacts, HasRocketChipStageUtils, UIntToOH1}
 import huancun.debug.TLLogger
 import huancun.{HCCacheParamsKey, HuanCun}
 import freechips.rocketchip.devices.debug.{DebugIO, ResetCtrlIO}
 
-class XSCoreWithL2()(implicit p: Parameters) extends LazyModule
-  with HasXSParameter with HasSoCParameter {
-  private val core = LazyModule(new XSCore)
-  private val busPMU = BusPerfMonitor(enable = !debugOpts.FPGAPlatform)
-  private val l2cacheOpt = coreParams.L2CacheParamsOpt.map(l2param =>
-    LazyModule(new HuanCun()(new Config((_, _, _) => {
-      case HCCacheParamsKey => l2param
-    })))
-  )
-  // (icache/ptw/dcache) => l2 or mem
-  private val l1_xbar = TLXbar()
-
-  val memory_port = TLIdentityNode()
-  val uncache = TLXbar()
-
-  if (coreParams.dcacheParametersOpt.nonEmpty) {
-    busPMU := TLLogger(s"L2_L1D_$hardId", !debugOpts.FPGAPlatform) := core.memBlock.dcache.clientNode
-  }
-  busPMU := core.frontend.icache.clientNode
-  if (!coreParams.softPTW) {
-    busPMU := core.ptw.node
-  }
-  l1_xbar :=* busPMU
-  l2cacheOpt match {
-    case Some(l2) =>
-      val l2_binder = BankBinder(coreParams.L2NBanks, 64)
-      memory_port :=* l2_binder :*= l2.node :*= l1_xbar
-    case None =>
-      memory_port := l1_xbar
-  }
-
-  uncache := TLBuffer() := core.frontend.instrUncache.clientNode
-  uncache := TLBuffer() := core.memBlock.uncache.clientNode
-
-  lazy val module = new LazyModuleImp(this) {
-    val io = IO(new Bundle {
-      val hartId = Input(UInt(64.W))
-      val externalInterrupt = new ExternalInterruptIO
-      val l1plus_error, icache_error, dcache_error = new L1CacheErrorInfo
-    })
-
-    core.module.io.hartId := io.hartId
-    core.module.io.externalInterrupt := io.externalInterrupt
-
-    io.l1plus_error <> core.module.io.l1plus_error
-    io.icache_error <> core.module.io.icache_error
-    io.dcache_error <> core.module.io.dcache_error
-
-    val core_reset_gen = Module(new ResetGen(1, !debugOpts.FPGAPlatform))
-    core.module.reset := core_reset_gen.io.out
-
-    val l2_reset_gen = Module(new ResetGen(1, !debugOpts.FPGAPlatform))
-    l2cacheOpt.foreach( _.module.reset := l2_reset_gen.io.out)
-  }
-}
-
 abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
-  with HasSoCParameter
   with BindingScope
 {
-  val bankedNode = BankBinder(L3NBanks, L3BlockSize)
-  val peripheralXbar = TLXbar()
-  val l3_xbar = TLXbar()
+  val misc = LazyModule(new SoCMisc())
   lazy val dts = DTS(bindingTree)
   lazy val json = JSON(bindingTree)
 }
 
-// We adapt the following three traits from rocket-chip.
-// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
-trait HaveSlaveAXI4Port {
-  this: BaseXSSoc =>
-
-  val idBits = 14
-
-  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
-    Seq(AXI4MasterParameters(
-      name = "dma",
-      id = IdRange(0, 1 << idBits)
-    ))
-  )))
-  private val errorDevice = LazyModule(new TLError(
-    params = DevNullParams(
-      address = Seq(AddressSet(0x0, 0x7fffffffL)),
-      maxAtomic = 8,
-      maxTransfer = 64),
-    beatBytes = L3InnerBusWidth / 8
-  ))
-  private val error_xbar = TLXbar()
-
-  error_xbar :=
-    TLFIFOFixer() :=
-    TLWidthWidget(16) :=
-    AXI4ToTL() :=
-    AXI4UserYanker(Some(1)) :=
-    AXI4Fragmenter() :=
-    AXI4IdIndexer(1) :=
-    l3FrontendAXI4Node
-  errorDevice.node := error_xbar
-  l3_xbar :=
-    TLBuffer() :=
-    error_xbar
-
-  val dma = InModuleBody {
-    l3FrontendAXI4Node.makeIOs()
-  }
-}
-
-trait HaveAXI4MemPort {
-  this: BaseXSSoc =>
-  val device = new MemoryDevice
-  // 40-bit physical address
-  val memRange = AddressSet(0x00000000L, 0xffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
-  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
-    AXI4SlavePortParameters(
-      slaves = Seq(
-        AXI4SlaveParameters(
-          address = memRange,
-          regionType = RegionType.UNCACHED,
-          executable = true,
-          supportsRead = TransferSizes(1, L3BlockSize),
-          supportsWrite = TransferSizes(1, L3BlockSize),
-          interleavedId = Some(0),
-          resources = device.reg("mem")
-        )
-      ),
-      beatBytes = L3OuterBusWidth / 8
-    )
-  ))
-
-  val mem_xbar = TLXbar()
-  mem_xbar :=* TLBuffer() :=* TLCacheCork() :=* bankedNode
-  memAXI4SlaveNode :=
-    AXI4UserYanker() :=
-    AXI4Deinterleaver(L3BlockSize) :=
-    TLToAXI4() :=
-    TLWidthWidget(L3OuterBusWidth / 8) :=
-    mem_xbar
-
-  val memory = InModuleBody {
-    memAXI4SlaveNode.makeIOs()
-  }
-}
-
-
-trait HaveAXI4PeripheralPort { this: BaseXSSoc =>
-  // on-chip devices: 0x3800_0000 - 0x3fff_ffff 0x0000_0000 - 0x0000_0fff
-  val onChipPeripheralRange = AddressSet(0x38000000L, 0x07ffffffL)
-  val uartRange = AddressSet(0x40600000, 0xf)
-  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
-  val uartParams = AXI4SlaveParameters(
-    address = Seq(uartRange),
-    regionType = RegionType.UNCACHED,
-    supportsRead = TransferSizes(1, 8),
-    supportsWrite = TransferSizes(1, 8),
-    resources = uartDevice.reg
-  )
-  val peripheralRange = AddressSet(
-    0x0, 0x7fffffff
-  ).subtract(onChipPeripheralRange).flatMap(x => x.subtract(uartRange))
-  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
-    Seq(AXI4SlaveParameters(
-      address = peripheralRange,
-      regionType = RegionType.UNCACHED,
-      supportsRead = TransferSizes(1, 8),
-      supportsWrite = TransferSizes(1, 8),
-      interleavedId = Some(0)
-    ), uartParams),
-    beatBytes = 8
-  )))
-
-  peripheralNode :=
-    AXI4UserYanker() :=
-    AXI4Deinterleaver(8) :=
-    TLToAXI4() :=
-    peripheralXbar
-
-  val peripheral = InModuleBody {
-    peripheralNode.makeIOs()
-  }
-
-}
-
-class XSTop()(implicit p: Parameters) extends XSTopWithoutDMA
-  with HaveSlaveAXI4Port
-
-class XSTopWithoutDMA()(implicit p: Parameters) extends BaseXSSoc()
-  with HaveAXI4MemPort
-  with HaveAXI4PeripheralPort
+class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
 {
   ResourceBinding {
     val width = ResourceInt(2)
@@ -242,88 +63,37 @@ class XSTopWithoutDMA()(implicit p: Parameters) extends BaseXSSoc()
         manager.resources.foreach(r => r.bind(manager.toResource))
       }
     }
-    bindManagers(l3_xbar.asInstanceOf[TLNexusNode])
-    bindManagers(peripheralXbar.asInstanceOf[TLNexusNode])
+    bindManagers(misc.l3_xbar.asInstanceOf[TLNexusNode])
+    bindManagers(misc.peripheralXbar.asInstanceOf[TLNexusNode])
   }
 
   println(s"FPGASoC cores: $NumCores banks: $L3NBanks block size: $L3BlockSize bus size: $L3OuterBusWidth")
 
   val core_with_l2 = soc.cores.map(coreParams =>
-    LazyModule(new XSCoreWithL2()(p.alterPartial({
+    LazyModule(new XSTile()(p.alterPartial({
       case XSCoreParamsKey => coreParams
     })))
   )
 
   for (i <- 0 until NumCores) {
-    peripheralXbar := TLBuffer() := core_with_l2(i).uncache
-    val l2_l3_pmu = BusPerfMonitor(enable = !debugOpts.FPGAPlatform)
-    l3_xbar :=* TLBuffer() :=* TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform) :=* l2_l3_pmu :=* core_with_l2(i).memory_port
-  }
-
-  val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8))
-  clint.node := peripheralXbar
-
-  val clintIntSinks = Array.fill(NumCores){
-    val clintSink = LazyModule(new IntSinkNodeToModule(2))
-    clintSink.sinkNode := clint.intnode
-    clintSink
-  }
-
-  val fakeTreeNode = new GenericLogicalTreeNode
-  val beu = LazyModule(
-    new BusErrorUnit(new XSL1BusErrors(NumCores), BusErrorUnitParams(0x38010000), fakeTreeNode))
-  beu.node := peripheralXbar
-
-  class IntSinkNodeToModule(val sinks: Int)(implicit p: Parameters) extends LazyModule {
-    val sinkNode = IntSinkNode(IntSinkPortSimple(1, sinks))
-    lazy val module = new LazyModuleImp(this){
-      val out = IO(Output(Vec(sinks, Bool())))
-      out.zip(sinkNode.in.head._1).foreach{ case (o, i) => o := i }
-    }
-  }
-
-  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
-    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
-    lazy val module = new LazyModuleImp(this){
-      val in = IO(Input(Vec(num, Bool())))
-      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
-    }
-  }
-
-  val plic = LazyModule(new TLPLIC(PLICParams(0x3c000000L), 8))
-  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
-  val plicIntSinks = Array.fill(NumCores){
-    val plicSink = LazyModule(new IntSinkNodeToModule(1))
-    plicSink.sinkNode := plic.intnode
-    plicSink
+    core_with_l2(i).clint_int_sink := misc.clint.intnode
+    core_with_l2(i).plic_int_sink := misc.plic.intnode
+    core_with_l2(i).debug_int_sink := misc.debugModule.debug.dmOuter.dmOuter.intnode
+    misc.plic.intnode := core_with_l2(i).beu_int_source
+    misc.peripheral_ports(i) := core_with_l2(i).uncache
+    misc.core_to_l3_ports(i) :=* core_with_l2(i).memory_port
   }
-  plic.intnode := beu.intNode
-  plic.intnode := plicSource.sourceNode
-
-  plic.node := peripheralXbar
 
   val l3cacheOpt = soc.L3CacheParamsOpt.map(l3param =>
     LazyModule(new HuanCun()(new Config((_, _, _) => {
       case HCCacheParamsKey => l3param
     })))
   )
-  val l3_mem_pmu = BusPerfMonitor(enable = !debugOpts.FPGAPlatform)
 
   l3cacheOpt match {
     case Some(l3) =>
-      bankedNode :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform) :*= l3_mem_pmu :*= l3.node :*= TLBuffer() :*= l3_xbar
-    case None => bankedNode :*= TLAdapterNode() :*= l3_xbar
-  }
-
-  val debugModule = LazyModule(new DebugModule(NumCores)(p))
-  debugModule.debug.node := peripheralXbar
-  val debugIntSink = Array.fill(NumCores){
-    val debugSink = LazyModule(new IntSinkNodeToModule(1))
-    debugSink.sinkNode := debugModule.debug.dmOuter.dmOuter.intnode
-    debugSink
-  }
-  debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
-    l3_xbar := TLBuffer() := TLWidthWidget(1) := sb2tl.node
+      misc.l3_out :*= l3.node :*= misc.l3_in
+    case None =>
   }
 
   lazy val module = new LazyRawModuleImp(this) {
@@ -332,6 +102,14 @@ class XSTopWithoutDMA()(implicit p: Parameters) extends BaseXSSoc()
     ElaborationArtefacts.add("json", json)
     ElaborationArtefacts.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
 
+    val dma = IO(Flipped(misc.dma.cloneType))
+    val peripheral = IO(misc.peripheral.cloneType)
+    val memory = IO(misc.memory.cloneType)
+
+    misc.dma <> dma
+    peripheral <> misc.peripheral
+    memory <> misc.memory
+
     val io = IO(new Bundle {
       val clock = Input(Bool())
       val reset = Input(Bool())
@@ -339,8 +117,6 @@ class XSTopWithoutDMA()(implicit p: Parameters) extends BaseXSSoc()
       val osc_clock = Input(Bool())
       val pll_output = Output(UInt(14.W))
       val extIntrs = Input(UInt(NrExtIntr.W))
-      // val meip = Input(Vec(NumCores, Bool()))
-      val ila = if(debugOpts.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
       val systemjtag = new Bundle {
         val jtag = Flipped(new JTAGIO(hasTRSTn = false))
         val reset = Input(Bool()) // No reset allowed on top
@@ -348,35 +124,27 @@ class XSTopWithoutDMA()(implicit p: Parameters) extends BaseXSSoc()
         val part_number = Input(UInt(16.W))
         val version = Input(UInt(4.W))
       }
-      // val resetCtrl = new ResetCtrlIO(NumCores)(p)
     })
     io.pll_output := DontCare
     dontTouch(io.sram_config)
     dontTouch(io.osc_clock)
     dontTouch(io.pll_output)
-    childClock := io.clock.asClock()
+    childClock := io.clock.asClock
 
     withClockAndReset(childClock, io.reset) {
       val resetGen = Module(new ResetGen(1, !debugOpts.FPGAPlatform))
       resetGen.suggestName("top_reset_gen")
-      childReset := resetGen.io.out | debugModule.module.io.debugIO.ndreset
+      childReset := resetGen.io.out | misc.module.debug_module_io.debugIO.ndreset
     }
 
     withClockAndReset(childClock, childReset) {
-      plicSource.module.in := io.extIntrs.asBools()
+      misc.module.ext_intrs := io.extIntrs
 
       for (i <- 0 until NumCores) {
         val core_reset_gen = Module(new ResetGen(1, !debugOpts.FPGAPlatform))
         core_reset_gen.suggestName(s"core_${i}_reset_gen")
         core_with_l2(i).module.reset := core_reset_gen.io.out
         core_with_l2(i).module.io.hartId := i.U
-        core_with_l2(i).module.io.externalInterrupt.msip := clintIntSinks(i).module.out(0)
-        core_with_l2(i).module.io.externalInterrupt.mtip := clintIntSinks(i).module.out(1)
-        core_with_l2(i).module.io.externalInterrupt.meip := plicIntSinks(i).module.out(0)
-        core_with_l2(i).module.io.externalInterrupt.debug := debugIntSink(i).module.out(0)
-        beu.module.io.errors.l1plus(i) := core_with_l2(i).module.io.l1plus_error
-        beu.module.io.errors.icache(i) := core_with_l2(i).module.io.icache_error
-        beu.module.io.errors.dcache(i) := core_with_l2(i).module.io.dcache_error
       }
 
       if (l3cacheOpt.nonEmpty) {
@@ -384,22 +152,16 @@ class XSTopWithoutDMA()(implicit p: Parameters) extends BaseXSSoc()
         l3_reset_gen.suggestName("l3_reset_gen")
         l3cacheOpt.get.module.reset := l3_reset_gen.io.out
       }
-      // TODO: wrap this in a module
-      val freq = 100
-      val cnt = RegInit(freq.U)
-      val tick = cnt === 0.U
-      cnt := Mux(tick, freq.U, cnt - 1.U)
-      clint.module.io.rtcTick := tick
 
-      debugModule.module.io.resetCtrl.hartIsInReset.foreach {x => x := childReset.asBool() }
-      debugModule.module.io.clock := io.clock
-      debugModule.module.io.reset := io.reset
+      misc.module.debug_module_io.resetCtrl.hartIsInReset.foreach {x => x := childReset.asBool() }
+      misc.module.debug_module_io.clock := io.clock
+      misc.module.debug_module_io.reset := io.reset
 
-      debugModule.module.io.debugIO.reset := io.systemjtag.reset // TODO: use synchronizer?
-      debugModule.module.io.debugIO.clock := childClock
-      debugModule.module.io.debugIO.dmactiveAck  := debugModule.module.io.debugIO.dmactive // TODO: delay 3 cycles?
+      misc.module.debug_module_io.debugIO.reset := io.systemjtag.reset // TODO: use synchronizer?
+      misc.module.debug_module_io.debugIO.clock := childClock
+      misc.module.debug_module_io.debugIO.dmactiveAck  := misc.module.debug_module_io.debugIO.dmactive // TODO: delay 3 cycles?
       // jtag connector
-      debugModule.module.io.debugIO.systemjtag.foreach { x =>
+      misc.module.debug_module_io.debugIO.systemjtag.foreach { x =>
         x.jtag <> io.systemjtag.jtag
         x.reset  := io.systemjtag.reset
         x.mfr_id := io.systemjtag.mfr_id

src/main/scala/xiangshan/XSCore.scala

@@ -26,8 +26,9 @@ import xiangshan.cache.mmu._
 import chipsalliance.rocketchip.config
 import chipsalliance.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
+import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple}
 import freechips.rocketchip.tile.HasFPUParameters
-import system.{HasSoCParameter, L1CacheErrorInfo, SoCParamsKey}
+import system.HasSoCParameter
 import utils._
 
 abstract class XSModule(implicit val p: Parameters) extends MultiIOModule
@@ -62,6 +63,10 @@ case class EnviromentParameters
 abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule
   with HasXSParameter with HasExuWbMappingHelper
 {
+  // interrupt sinks
+  val clint_int_sink = IntSinkNode(IntSinkPortSimple(1, 2))
+  val debug_int_sink = IntSinkNode(IntSinkPortSimple(1, 1))
+  val plic_int_sink = IntSinkNode(IntSinkPortSimple(1, 1))
   // outer facing nodes
   val frontend = LazyModule(new Frontend())
   val ptw = LazyModule(new PTWWrapper())
@@ -166,9 +171,8 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
   with HasExeBlockHelper {
   val io = IO(new Bundle {
     val hartId = Input(UInt(64.W))
-    val externalInterrupt = new ExternalInterruptIO
     val l2_pf_enable = Output(Bool())
-    val l1plus_error, icache_error, dcache_error = Output(new L1CacheErrorInfo)
+    val beu_errors = Output(new XSL1BusErrors())
   })
 
   println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}")
@@ -212,9 +216,8 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
 
   val rfWriteback = VecInit(intArbiter.io.out ++ fpArbiter.io.out)
 
-  io.l1plus_error <> DontCare
-  io.icache_error <> frontend.io.error
-  io.dcache_error <> memBlock.io.error
+  io.beu_errors.icache <> frontend.io.error
+  io.beu_errors.dcache <> memBlock.io.error
 
   require(exuBlocks.count(_.fuConfigs.map(_._1).contains(JumpCSRExeUnitCfg)) == 1)
   val csrFenceMod = exuBlocks.filter(_.fuConfigs.map(_._1).contains(JumpCSRExeUnitCfg)).head
@@ -298,7 +301,11 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
   csrioIn.trapTarget <> ctrlBlock.io.robio.toCSR.trapTarget
   csrioIn.interrupt <> ctrlBlock.io.robio.toCSR.intrBitSet
   csrioIn.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr
-  csrioIn.externalInterrupt <> io.externalInterrupt
+
+  csrioIn.externalInterrupt.msip := outer.clint_int_sink.in.head._1(0)
+  csrioIn.externalInterrupt.mtip := outer.clint_int_sink.in.head._1(1)
+  csrioIn.externalInterrupt.meip := outer.plic_int_sink.in.head._1(0)
+  csrioIn.externalInterrupt.debug := outer.debug_int_sink.in.head._1(0)
 
   fenceio.sfence <> memBlock.io.sfence
   fenceio.sbuffer <> memBlock.io.fenceToSbuffer

src/main/scala/xiangshan/XSTile.scala

+package xiangshan
+
+import chisel3._
+import chipsalliance.rocketchip.config.{Config, Parameters}
+import chisel3.util.{Valid, ValidIO}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyModuleImpLike}
+import freechips.rocketchip.diplomaticobjectmodel.logicaltree.GenericLogicalTreeNode
+import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortParameters, IntSinkPortSimple}
+import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors}
+import freechips.rocketchip.tilelink.{BankBinder, TLBuffer, TLIdentityNode, TLTempNode, TLXbar}
+import huancun.debug.TLLogger
+import huancun.{HCCacheParamsKey, HuanCun}
+import system.HasSoCParameter
+import top.BusPerfMonitor
+import utils.ResetGen
+
+class L1CacheErrorInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {
+  val paddr = Valid(UInt(soc.PAddrBits.W))
+  // for now, we only detect ecc
+  val ecc_error = Valid(Bool())
+}
+
+class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors {
+  val icache = new L1CacheErrorInfo
+  val dcache = new L1CacheErrorInfo
+
+  override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] =
+    List(
+      Some(icache.paddr, s"IBUS", s"Icache bus error"),
+      Some(icache.ecc_error, s"I_ECC", s"Icache ecc error"),
+      Some(dcache.paddr, s"DBUS", s"Dcache bus error"),
+      Some(dcache.ecc_error, s"D_ECC", s"Dcache ecc error")
+    )
+}
+
+/**
+  *   XSTileMisc contains every module except Core and L2 Cache
+  */
+class XSTileMisc()(implicit p: Parameters) extends LazyModule
+  with HasXSParameter
+  with HasSoCParameter
+{
+  val l1_xbar = TLXbar()
+  val mmio_xbar = TLXbar()
+  val memory_port = TLIdentityNode()
+  val beu = LazyModule(new BusErrorUnit(
+    new XSL1BusErrors(), BusErrorUnitParams(0x38010000), new GenericLogicalTreeNode
+  ))
+  val busPMU = BusPerfMonitor(enable = !debugOpts.FPGAPlatform)
+  val l1d_logger = TLLogger(s"L2_L1D_$hardId", !debugOpts.FPGAPlatform)
+  val l2_binder = coreParams.L2CacheParamsOpt.map(_ => BankBinder(coreParams.L2NBanks, 64))
+
+  val i_mmio_port = TLTempNode()
+  val d_mmio_port = TLTempNode()
+
+  busPMU := l1d_logger
+  l1_xbar :=* busPMU
+
+  l2_binder match {
+    case Some(binder) =>
+      memory_port :=* binder
+    case None =>
+      memory_port := l1_xbar
+  }
+
+  mmio_xbar := TLBuffer() := i_mmio_port
+  mmio_xbar := TLBuffer() := d_mmio_port
+  beu.node := TLBuffer() := mmio_xbar
+
+  lazy val module = new LazyModuleImp(this){
+    val beu_errors = IO(Input(chiselTypeOf(beu.module.io.errors)))
+    beu.module.io.errors <> beu_errors
+  }
+}
+
+class XSTile()(implicit p: Parameters) extends LazyModule
+  with HasXSParameter
+  with HasSoCParameter
+{
+  private val core = LazyModule(new XSCore())
+  private val misc = LazyModule(new XSTileMisc())
+  private val l2cache = coreParams.L2CacheParamsOpt.map(l2param =>
+    LazyModule(new HuanCun()(new Config((_, _, _) => {
+      case HCCacheParamsKey => l2param
+    })))
+  )
+
+  // public ports
+  val memory_port = misc.memory_port
+  val uncache = misc.mmio_xbar
+  val clint_int_sink = core.clint_int_sink
+  val plic_int_sink = core.plic_int_sink
+  val debug_int_sink = core.debug_int_sink
+  val beu_int_source = misc.beu.intNode
+
+  if (coreParams.dcacheParametersOpt.nonEmpty) {
+    misc.l1d_logger := core.memBlock.dcache.clientNode
+  }
+  misc.busPMU := core.frontend.icache.clientNode
+  if (!coreParams.softPTW) {
+    misc.busPMU := core.ptw.node
+  }
+  l2cache match {
+    case Some(l2) =>
+      misc.l2_binder.get :*= l2.node :*= misc.l1_xbar
+    case None =>
+  }
+
+  misc.i_mmio_port := core.frontend.instrUncache.clientNode
+  misc.d_mmio_port := core.memBlock.uncache.clientNode
+
+  lazy val module = new LazyModuleImp(this){
+    val io = IO(new Bundle {
+      val hartId = Input(UInt(64.W))
+    })
+
+    core.module.io.hartId := io.hartId
+
+    misc.module.beu_errors <> core.module.io.beu_errors
+
+    val core_reset_gen = Module(new ResetGen(1, !debugOpts.FPGAPlatform))
+    core.module.reset := core_reset_gen.io.out
+
+    val l2_reset_gen = Module(new ResetGen(1, !debugOpts.FPGAPlatform))
+    l2cache.foreach( _.module.reset := l2_reset_gen.io.out)
+  }
+}

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -21,7 +21,6 @@ import chisel3.util._
 import chipsalliance.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import freechips.rocketchip.tile.HasFPUParameters
-import system.L1CacheErrorInfo
 import xiangshan._
 import xiangshan.backend.rob.RobLsqIO
 import xiangshan.cache._

src/main/scala/xiangshan/backend/fu/Alu.scala

@@ -291,7 +291,7 @@ class AluDataModule(implicit p: Parameters) extends XSModule {
   val and     = src1 & logicSrc2
   val or      = src1 | logicSrc2
   val xor     = src1 ^ logicSrc2
-  val orcb    = Cat((7 to 0).map(i => Fill(8, src1(i * 8 + 7, i * 8).orR)))
+  val orcb    = Cat((0 until 8).map(i => Fill(8, src1(i * 8 + 7, i * 8).orR)).reverse)
   val orh48   = Cat(src1(63, 8), 0.U(8.W)) | src2
 
   val sextb = SignExt(src1(7, 0), XLEN)
@@ -299,7 +299,7 @@ class AluDataModule(implicit p: Parameters) extends XSModule {
   val sexth = SignExt(src1(15, 0), XLEN)
   val packw = SignExt(Cat(src2(15, 0), src1(15, 0)), XLEN)
 
-  val revb = Cat((7 to 0).map(i => Reverse(src1(8 * i + 7, 8 * i))))
+  val revb = Cat((0 until 8).map(i => Reverse(src1(8 * i + 7, 8 * i))).reverse)
   val pack = Cat(src2(31, 0), src1(31, 0))
   val rev8 = Cat((0 until 8).map(i => src1(8 * i + 7, 8 * i)))
 

src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala

@@ -25,7 +25,6 @@ import utils._
 import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp, TransferSizes}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util.BundleFieldBase
-import system.L1CacheErrorInfo
 import device.RAMHelper
 import huancun.{AliasField, AliasKey, PreferCacheField, PrefetchField, DirtyField}
 

src/main/scala/xiangshan/cache/dcache/FakeDCache.scala

@@ -23,7 +23,6 @@ import xiangshan._
 import utils._
 import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp, TransferSizes}
 import freechips.rocketchip.tilelink._
-import system.L1CacheErrorInfo
 import device.RAMHelper
 
 class FakeDCache()(implicit p: Parameters) extends XSModule with HasDCacheParameters {

src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala

@@ -20,8 +20,8 @@ import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink.{ClientMetadata, TLClientParameters, TLEdgeOut}
-import system.L1CacheErrorInfo
 import utils.{Code, ParallelOR, ReplacementPolicy, SRAMTemplate, XSDebug}
+import xiangshan.L1CacheErrorInfo
 
 import scala.math.max
 

src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala

@@ -20,8 +20,8 @@ import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink.{ClientMetadata, TLClientParameters, TLEdgeOut}
-import system.L1CacheErrorInfo
 import utils.{Code, ParallelOR, ReplacementPolicy, SRAMTemplate, XSDebug, XSPerfAccumulate}
+import xiangshan.L1CacheErrorInfo
 
 import scala.math.max
 

src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala

@@ -20,7 +20,6 @@ import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink.{ClientMetadata, TLClientParameters, TLEdgeOut}
-import system.L1CacheErrorInfo
 import utils.{Code, ParallelOR, ReplacementPolicy, SRAMTemplate, XSDebug}
 
 import scala.math.max

src/main/scala/xiangshan/cache/dcache/meta/MetaArray.scala

@@ -20,8 +20,8 @@ import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink.{ClientMetadata, TLClientParameters, TLEdgeOut}
-import system.L1CacheErrorInfo
 import utils.{Code, ParallelOR, ReplacementPolicy, SRAMTemplate, XSDebug}
+import xiangshan.L1CacheErrorInfo
 
 // basic building blocks for L1 DCache
 class L1Metadata(implicit p: Parameters) extends DCacheBundle {

src/main/scala/xiangshan/frontend/Frontend.scala

@@ -22,9 +22,8 @@ import chipsalliance.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import xiangshan._
 import xiangshan.cache._
-import xiangshan.cache.mmu.{TLB, TlbPtwIO, TlbRequestIO}
+import xiangshan.cache.mmu.{TlbRequestIO, TlbPtwIO,TLB}
 import xiangshan.backend.fu.{HasExceptionNO, PMP, PMPChecker}
-import system.L1CacheErrorInfo
 
 
 class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter{

src/test/scala/top/SimMMIO.scala

@@ -51,10 +51,6 @@ class SimMMIO(edge: AXI4EdgeParameters)(implicit p: config.Parameters) extends L
     node.makeIOs()
   }
 
-  def connectToSoC(soc: HaveAXI4PeripheralPort) = {
-    io_axi4 <> soc.peripheral
-  }
-
   lazy val module = new LazyModuleImp(this){
     val io = IO(new Bundle() {
       val uart = new UARTIO

src/test/scala/top/SimTop.scala

@@ -31,23 +31,25 @@ class SimTop(implicit p: Parameters) extends Module {
   val debugOpts = p(DebugOptionsKey)
   val useDRAMSim = debugOpts.UseDRAMSim
 
-  val l_soc = LazyModule(new XSTopWithoutDMA())
+  val l_soc = LazyModule(new XSTop())
   val soc = Module(l_soc.module)
 
-  val l_simMMIO = LazyModule(new SimMMIO(l_soc.peripheralNode.in.head._2))
+  l_soc.module.dma <> DontCare
+
+  val l_simMMIO = LazyModule(new SimMMIO(l_soc.misc.peripheralNode.in.head._2))
   val simMMIO = Module(l_simMMIO.module)
-  l_simMMIO.connectToSoC(l_soc)
+  l_simMMIO.io_axi4 <> soc.peripheral
 
   if(!useDRAMSim){
     val l_simAXIMem = LazyModule(new AXI4RAMWrapper(
-      l_soc.memAXI4SlaveNode, 8L * 1024 * 1024 * 1024, useBlackBox = true
+      l_soc.misc.memAXI4SlaveNode, 8L * 1024 * 1024 * 1024, useBlackBox = true
     ))
     val simAXIMem = Module(l_simAXIMem.module)
-    l_simAXIMem.connectToSoC(l_soc)
+    l_simAXIMem.io_axi4 <> soc.memory
   }
 
-  soc.io.clock := clock.asBool()
-  soc.io.reset := reset.asBool()
+  soc.io.clock := clock.asBool
+  soc.io.reset := reset.asBool
   soc.io.extIntrs := simMMIO.io.interrupt.intrVec
   soc.io.osc_clock := false.B
   soc.io.sram_config := 0.U
@@ -63,13 +65,13 @@ class SimTop(implicit p: Parameters) extends Module {
     val logCtrl = new LogCtrlIO
     val perfInfo = new PerfInfoIO
     val uart = new UARTIO
-    val memAXI = if(useDRAMSim) l_soc.memory.cloneType else null
+    val memAXI = if(useDRAMSim) soc.memory.cloneType else null
   })
 
   simMMIO.io.uart <> io.uart
 
   if(useDRAMSim){
-    io.memAXI <> l_soc.memory
+    io.memAXI <> soc.memory
   }
 
   if (debugOpts.EnableDebug || debugOpts.EnablePerfDebug) {