- 15 3月, 2023 1 次提交
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由 zhanglyGit 提交于
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- 13 3月, 2023 1 次提交
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由 czw 提交于
1. fix bug that connection of fuOpType in VIPU 2. vadd vmin vminu vmax vmaxu vand vor vxor vsub vrsub test pass
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- 11 3月, 2023 1 次提交
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由 maliao 提交于
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- 10 3月, 2023 2 次提交
- 08 3月, 2023 2 次提交
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由 czw 提交于
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由 zhanglyGit 提交于
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- 06 3月, 2023 1 次提交
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由 zhanglyGit 提交于
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- 02 3月, 2023 2 次提交
- 28 2月, 2023 3 次提交
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由 zhanglyGit 提交于
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由 zhanglyGit 提交于
* add DecodeUnitComp.scala and modify DecodeStage.scala for vector uop Div support(LMUL=8) * changes made to implement a uop Div supporting with a cleaner code style(support Config) * MaxNumOfUop parameterization supporting
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由 czw 提交于
* func(vrsub):support vrsub.vv TODO: 1. depends on yunsuan'commit of func(vrsub) 2. require difftest * func(adc): support vmadc.vv vmadc.vi vmadc.vx TODO: 1. NEMU need to update
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- 27 2月, 2023 1 次提交
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由 czw 提交于
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- 24 2月, 2023 2 次提交
- 22 2月, 2023 4 次提交
- 18 2月, 2023 1 次提交
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由 Guokai Chen 提交于
Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>
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- 17 2月, 2023 2 次提交
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由 Haoyuan Feng 提交于
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由 Guokai Chen 提交于
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- 15 2月, 2023 1 次提交
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由 Maxpicca 提交于
Besides adding load/store arch database, this PR also fixed a bug which caused prefetch using l1 info failed to work. Former RTL change break `isFirstIssue` flag gen logic, which caused prefetcher failed to receive prefetch train info from L1. This commit should fix that. * ROB: add inst db drop globalID signal output is still duplicated * TLB: TLB will carry mem idx when req and resp * InstDB: update the TLBFirstIssue * InstDB: the first version is complete * InstDB: update decode logic * InstDB: update ctrlBlock writeback * Merge: fix bug * merge: fix compile bug * code rule: rename debug signals and add db's FPGA signal control * code rule: update db's FPGA signal control * ldu: fix isFirstIssue flag for ldflow from rs * ldu: isFirstIssue flag for hw pf is always false --------- Co-authored-by: Ngood-circle <fenghaoyuan19@mails.ucas.ac.cn> Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
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- 14 2月, 2023 2 次提交
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由 Ziyue-Zhang 提交于
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由 bugGenerator 提交于
* test: add example to genenrate verilog for a small module Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop * test: add DecodeUnitTest as an example for xs' chiseltest * ctrlblock: <> usage has changed, unidirection should use := * bump huancun * makefile: mv new makefile cmd into Makefile.test
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- 13 2月, 2023 3 次提交
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由 maliao 提交于
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由 bugGenerator 提交于
Here is a bug cause by EnableUncacheWriteOutstanding: The case is extintr in Nexus-AM. Three steps of the test: clear intrGen's intr: Stop pass interrupt. A mmio write. clear plic claim: complete intr. A mmio write. read plic claim to check: claim should be 0. A mmio read. The corner case: intrGen's mmio write is to slow. The instruction after it executes and plic claim's mmio's write & read execute before it. On the side of core with plic, claim is cleared. But on the side of intrGen with plic, the source of interrupt is still enabled and trigger interrupt. So the "read plic claim to check" get a valid claim and failed.
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由 ZhangZifei 提交于
Here is a bug cause by EnableUncacheWriteOutstanding: The case is extintr in Nexus-AM. Three steps of the test: clear intrGen's intr: Stop pass interrupt. A mmio write. clear plic claim: complete intr. A mmio write. read plic claim to check: claim should be 0. A mmio read. The corner case: intrGen's mmio write is to slow. The instruction after it executes and plic claim's mmio's write & read execute before it. On the side of core with plic, claim is cleared. But on the side of intrGen with plic, the source of interrupt is still enabled and trigger interrupt. So the "read plic claim to check" get a valid claim and failed.
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- 12 2月, 2023 1 次提交
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由 ZhangZifei 提交于
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- 11 2月, 2023 4 次提交
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由 maliao 提交于
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由 ZhangZifei 提交于
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由 maliao 提交于
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由 ZhangZifei 提交于
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- 10 2月, 2023 4 次提交
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由 maliao 提交于
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由 ZhangZifei 提交于
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由 ZhangZifei 提交于
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由 xiwenx 提交于
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- 09 2月, 2023 1 次提交
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由 ZhangZifei 提交于
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- 08 2月, 2023 1 次提交
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由 xiwenx 提交于
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