test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890)

* test: add example to genenrate verilog for a small module

Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop

* test: add DecodeUnitTest as an example for xs' chiseltest

* ctrlblock: <> usage has changed, unidirection should use :=

* bump huancun

* makefile: mv new makefile cmd into Makefile.test

Makefile

@@ -150,4 +150,6 @@ emu-run:
 simv:
 	$(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
 
+include Makefile.test
+
 .PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO)

Makefile.test

+# only generate a small module: example
+verilog-decode:
+	mill -i XiangShan.test.runMain xiangshan.DecodeMain -td build --output-file DecodeUnit.v
+
+# chiseltest
+# autorun all the chiselTest case
+test:
+	mill -i XiangShan.test.test
+
+# only run DecodeUnitTest
+test-DecodeUnit:
+	mill -i XiangShan.test.testOnly xiangshan.DecodeUnitTest

build.sc

@@ -27,7 +27,7 @@ object ivys {
   val sv = "2.12.13"
   val chisel3 = ivy"edu.berkeley.cs::chisel3:3.5.0"
   val chisel3Plugin = ivy"edu.berkeley.cs:::chisel3-plugin:3.5.0"
-  val chiseltest = ivy"edu.berkeley.cs::chiseltest:0.3.2"
+  val chiseltest = ivy"edu.berkeley.cs::chiseltest:0.5.2"
   val chiselCirct = ivy"com.sifive::chisel-circt:0.6.0"
   val scalatest = ivy"org.scalatest::scalatest:3.2.2"
   val macroParadise = ivy"org.scalamacros:::paradise:2.1.1"
@@ -99,7 +99,7 @@ object rocketchip extends `rocket-chip`.common.CommonRocketChip {
     def chisel3IvyDeps = if(chisel3Module.isEmpty) Agg(
       common.getVersion("chisel3")
     ) else Agg.empty[Dep]
-    
+
     def chisel3PluginIvyDeps = Agg(common.getVersion("chisel3-plugin", cross=true))
   }
 

huancun @ 719ec090

-Subproject commit 2f788976682d341eec7d55e7aa063f9894d9108d
+Subproject commit 719ec0904f56f6a71fc63b1fd0f6994965e52505

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -472,7 +472,7 @@ class CtrlBlockImp(outer: CtrlBlock)(implicit p: Parameters) extends LazyModuleI
     }
   }
 
-  rename.io.redirect <> stage2Redirect
+  rename.io.redirect := stage2Redirect
   rename.io.robCommits <> rob.io.commits
   rename.io.ssit <> ssit.io.rdata
   rename.io.debug_int_rat <> rat.io.debug_int_rat
@@ -484,7 +484,7 @@ class CtrlBlockImp(outer: CtrlBlock)(implicit p: Parameters) extends LazyModuleI
   }
 
   dispatch.io.hartId := io.hartId
-  dispatch.io.redirect <> stage2Redirect
+  dispatch.io.redirect := stage2Redirect
   dispatch.io.enqRob <> rob.io.enq
   dispatch.io.toIntDq <> intDq.io.enq
   dispatch.io.toFpDq <> fpDq.io.enq
@@ -550,10 +550,10 @@ class CtrlBlockImp(outer: CtrlBlock)(implicit p: Parameters) extends LazyModuleI
 
   rob.io.hartId := io.hartId
   io.cpu_halt := DelayN(rob.io.cpu_halt, 5)
-  rob.io.redirect <> stage2Redirect
+  rob.io.redirect := stage2Redirect
   outer.rob.generateWritebackIO(Some(outer), Some(this))
 
-  io.redirect <> stage2Redirect
+  io.redirect := stage2Redirect
 
   // rob to int block
   io.robio.toCSR <> rob.io.csr

src/main/scala/xiangshan/frontend/NewFtq.scala

@@ -1029,7 +1029,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   // **************************** to bpu ****************************
   // ****************************************************************
 
-  io.toBpu.redirect <> Mux(fromBackendRedirect.valid, fromBackendRedirect, ifuRedirectToBpu)
+  io.toBpu.redirect := Mux(fromBackendRedirect.valid, fromBackendRedirect, ifuRedirectToBpu)
 
   val may_have_stall_from_bpu = Wire(Bool())
   val bpu_ftb_update_stall = RegInit(0.U(2.W)) // 2-cycle stall, so we need 3 states

src/test/scala/fu/IntDiv.scala

@@ -19,9 +19,8 @@ package futest
 import chisel3._
 import chiseltest._
 import chiseltest.ChiselScalatestTester
-import chiseltest.experimental.TestOptionBuilder._
-import chiseltest.internal.{LineCoverageAnnotation, ToggleCoverageAnnotation, VerilatorBackendAnnotation}
-import chiseltest.legacy.backends.verilator.VerilatorFlags
+import chiseltest.VerilatorBackendAnnotation
+import chiseltest.simulator.VerilatorFlags
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.must.Matchers
 import firrtl.stage.RunFirrtlTransformAnnotation
@@ -68,10 +67,12 @@ class IntDividerTest extends AnyFlatSpec with ChiselScalatestTester with Matcher
   it should "run" in {
     val rand = new Random(0x14226)
     val testNum = 1000
+
     test(new SRT4DividerWrapper).withAnnotations(Seq(VerilatorBackendAnnotation,
-      LineCoverageAnnotation,
-      ToggleCoverageAnnotation,
-      VerilatorFlags(Seq("--output-split 5000", "--output-split-cfuncs 5000",
+      // LineCoverageAnnotation,
+      // ToggleCoverageAnnotation,
+      VerilatorFlags(Seq(
+        // "--output-split 20", "--output-split-cfuncs 20",
         "+define+RANDOMIZE_REG_INIT", "+define+RANDOMIZE_MEM_INIT", "--trace")),
       RunFirrtlTransformAnnotation(new PrintModuleName))){ m =>
       println("Test started!")

src/test/scala/xiangshan/DecodeTest.scala

+package xiangshan
+
+import chisel3._
+import chisel3.stage._
+import chiseltest._
+import chiseltest.ChiselScalatestTester
+import chiseltest.VerilatorBackendAnnotation
+import chiseltest.simulator.{VerilatorFlags, VerilatorCFlags}
+import freechips.rocketchip.util.{ElaborationArtefacts, HasRocketChipStageUtils}
+import org.scalatest.flatspec.AnyFlatSpec
+import org.scalatest.matchers.must.Matchers
+import firrtl.stage.RunFirrtlTransformAnnotation
+import xstransforms.PrintModuleName
+
+import firrtl.options.TargetDirAnnotation
+
+import top.ArgParser
+import xiangshan.backend.decode.DecodeUnit
+
+object DecodeMain extends App with HasRocketChipStageUtils {
+  override def main(args: Array[String]): Unit = {
+    val (config, firrtlOpts, firrtlComplier) = ArgParser.parse(args)
+    // //val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
+    // If Complex Params are needed, wrap it with a Top Module to do dirty works,
+    // and use "chisel3.aop.Select.collectDeep[ModuleWanted](WrapperModule){case a: ModuleWanted => a}.head.Params"
+    val defaultConfig = config.alterPartial({
+      // Get XSCoreParams and pass it to the "small module"
+      case XSCoreParamsKey => config(XSTileKey).head.copy(
+        // Example of how to change params
+        IssQueSize = 12
+      )
+    })
+    (new ChiselStage).execute(args, Seq(
+      ChiselGeneratorAnnotation(() => new DecodeUnit()(defaultConfig)
+    )))
+//    // Generate files when compiling. Used by ChiselDB.
+//    ElaborationArtefacts.files.foreach{ case (extension, contents) =>
+//      writeOutputFile("./build", s"DecodeUnit.${extension}", contents())
+//    }
+  }
+}
+
+class DecodeUnitTest extends XSTester {
+  behavior of "DecodeUnit"
+  it should "pass" in {
+    test(new DecodeUnit()(config)).withAnnotations(Seq(
+      VerilatorBackendAnnotation,
+      VerilatorFlags(Seq()),
+      WriteVcdAnnotation,
+      TargetDirAnnotation("./build"),
+      RunFirrtlTransformAnnotation(new PrintModuleName)
+    )){ dut =>
+      dut.clock.step(10)
+    }
+  }
+}
\ No newline at end of file

src/test/scala/xiangshan/XSTester.scala

+package xiangshan
+
+import chisel3._
+import chipsalliance.rocketchip.config.Config
+import chiseltest._
+import chiseltest.{VerilatorBackendAnnotation, WriteVcdAnnotation}
+import chiseltest.simulator.{VerilatorCFlags, VerilatorFlags}
+import firrtl.AnnotationSeq
+import firrtl.stage.RunFirrtlTransformAnnotation
+import org.scalatest.flatspec._
+import org.scalatest.matchers.should._
+
+import top.{ArgParser, DefaultConfig}
+
+abstract class XSTester extends AnyFlatSpec with ChiselScalatestTester with Matchers with HasTestAnnos {
+  behavior of "XiangShan Module"
+  val defaultConfig = (new DefaultConfig)
+  implicit val config = defaultConfig.alterPartial({
+    // Get XSCoreParams and pass it to the "small module"
+    case XSCoreParamsKey => defaultConfig(XSTileKey).head.copy(
+      // Example of how to change params
+      IssQueSize = 12
+    )
+  })
+}
+
+trait HasTestAnnos {
+  var testAnnos: AnnotationSeq = Seq()
+}
+
+trait DumpVCD { this: HasTestAnnos =>
+  testAnnos = testAnnos :+ WriteVcdAnnotation
+}
+
+trait UseVerilatorBackend { this: HasTestAnnos =>
+  testAnnos = testAnnos ++ Seq(VerilatorBackendAnnotation)
+}
\ No newline at end of file