support vmv.s.x and vx instruction(vadd.vx, vsub.vx) (#1951)

src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala

@@ -25,8 +25,9 @@ import utils._
 import utility._
 import xiangshan.ExceptionNO.illegalInstr
 import xiangshan._
+import xiangshan.backend.fu.fpu.FPU
 import freechips.rocketchip.rocket.Instructions._
-
+import yunsuan.VppuType
 import scala.collection.Seq
 
 class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle {
@@ -81,9 +82,10 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
   ))
   //number of uop
   val numOfUop = MuxLookup(typeOfDiv, 1.U, Array(
+    UopDivType.VEC_MV -> 2.U,
     UopDivType.DIR -> 2.U,
     UopDivType.VEC_LMUL -> lmul,
-    UopDivType.VEC_MV_LMUL -> (lmul + 1.U)
+    UopDivType.VEC_MV_LMUL -> (lmul + 2.U)
   ))
 
   //uop div up to maxNumOfUop
@@ -110,6 +112,96 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
       }
       csBundle(numOfUop - 1.U).ctrl.uopIdx := "b11111".U
     }
+    is(UopDivType.VEC_MV) {
+      /*
+      FMV.D.X
+       */
+      csBundle(0).ctrl.srcType(0) := SrcType.reg
+      csBundle(0).ctrl.srcType(1) := SrcType.imm
+      csBundle(0).ctrl.lsrc(1) := 0.U
+      csBundle(0).ctrl.ldest := 33.U
+      csBundle(0).ctrl.uopIdx := 0.U
+      csBundle(0).ctrl.fuType := FuType.i2f
+      csBundle(0).ctrl.rfWen := false.B
+      csBundle(0).ctrl.fpWen := true.B
+      csBundle(0).ctrl.vecWen := false.B
+      csBundle(0).ctrl.fpu.isAddSub := false.B
+      csBundle(0).ctrl.fpu.typeTagIn := FPU.D
+      csBundle(0).ctrl.fpu.typeTagOut := FPU.D
+      csBundle(0).ctrl.fpu.fromInt := true.B
+      csBundle(0).ctrl.fpu.wflags := false.B
+      csBundle(0).ctrl.fpu.fpWen := true.B
+      csBundle(0).ctrl.fpu.div := false.B
+      csBundle(0).ctrl.fpu.sqrt := false.B
+      csBundle(0).ctrl.fpu.fcvt := false.B
+      /*
+      vfmv.s.f
+       */
+      csBundle(1).ctrl.srcType(0) := SrcType.fp
+      csBundle(1).ctrl.srcType(1) := SrcType.vp
+      csBundle(1).ctrl.srcType(2) := SrcType.vp
+      csBundle(1).ctrl.lsrc(0) := 33.U
+      csBundle(1).ctrl.lsrc(1) := 0.U
+      csBundle(1).ctrl.lsrc(2) := ctrl_flow.instr(11, 7)
+      csBundle(1).ctrl.ldest := ctrl_flow.instr(11, 7)
+      csBundle(1).ctrl.uopIdx := "b11111".U
+      csBundle(1).ctrl.fuType := FuType.vppu
+      csBundle(1).ctrl.fuOpType := VppuType.f2s
+      csBundle(1).ctrl.rfWen := false.B
+      csBundle(1).ctrl.fpWen := false.B
+      csBundle(1).ctrl.vecWen := true.B
+    }
+    is(UopDivType.VEC_MV_LMUL) {
+      /*
+      FMV.D.X
+       */
+      csBundle(0).ctrl.srcType(0) := SrcType.reg
+      csBundle(0).ctrl.srcType(1) := SrcType.imm
+      csBundle(0).ctrl.lsrc(1) := 0.U
+      csBundle(0).ctrl.ldest := 33.U
+      csBundle(0).ctrl.uopIdx := 0.U
+      csBundle(0).ctrl.fuType := FuType.i2f
+      csBundle(0).ctrl.rfWen := false.B
+      csBundle(0).ctrl.fpWen := true.B
+      csBundle(0).ctrl.vecWen := false.B
+      csBundle(0).ctrl.fpu.isAddSub := false.B
+      csBundle(0).ctrl.fpu.typeTagIn := FPU.D
+      csBundle(0).ctrl.fpu.typeTagOut := FPU.D
+      csBundle(0).ctrl.fpu.fromInt := true.B
+      csBundle(0).ctrl.fpu.wflags := false.B
+      csBundle(0).ctrl.fpu.fpWen := true.B
+      csBundle(0).ctrl.fpu.div := false.B
+      csBundle(0).ctrl.fpu.sqrt := false.B
+      csBundle(0).ctrl.fpu.fcvt := false.B
+      /*
+      vfmv.s.f
+       */
+      csBundle(1).ctrl.srcType(0) := SrcType.fp
+      csBundle(1).ctrl.srcType(1) := SrcType.vp
+      csBundle(1).ctrl.srcType(2) := SrcType.vp
+      csBundle(1).ctrl.lsrc(0) := 33.U
+      csBundle(1).ctrl.lsrc(1) := 0.U
+      csBundle(1).ctrl.lsrc(2) := 33.U
+      csBundle(1).ctrl.ldest := 33.U
+      csBundle(1).ctrl.uopIdx := 1.U
+      csBundle(1).ctrl.fuType := FuType.vppu
+      csBundle(1).ctrl.fuOpType := VppuType.f2s
+      csBundle(1).ctrl.rfWen := false.B
+      csBundle(1).ctrl.fpWen := false.B
+      csBundle(1).ctrl.vecWen := true.B
+      /*
+      LMUL
+       */
+      for (i <- 0 until 8) {
+        csBundle(i + 2).ctrl.srcType(0) := SrcType.vp
+        csBundle(i + 2).ctrl.srcType(3) := 0.U
+        csBundle(i + 2).ctrl.lsrc(0) := 33.U
+        csBundle(i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U
+        csBundle(i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U
+        csBundle(i + 2).ctrl.uopIdx := (i + 2).U
+      }
+      csBundle(numOfUop - 1.U).ctrl.uopIdx := "b11111".U
+    }
   }
 
   //uops dispatch

src/main/scala/xiangshan/backend/decode/VecDecoder.scala

@@ -346,7 +346,7 @@ object VecDecoder extends DecodeConstants {
     VMULH_VX       -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F),
     VMULHSU_VX     -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F),
     VMULHU_VX      -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F),
-    VMV_S_X        -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F),
+    VMV_S_X        -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F, UopDivType.VEC_MV),
 
     VNMSAC_VX      -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F),
     VNMSUB_VX      -> OPMVX(F, FuType.vipu, VipuType.dummy, F, T, F),

src/main/scala/xiangshan/backend/fu/vector/VIPU.scala

@@ -25,7 +25,7 @@ import utils._
 import utility._
 import yunsuan.vector.VectorIntAdder
 import yunsuan.{VipuType, VectorElementFormat}
-import xiangshan.{SrcType, SelImm}
+import xiangshan.{SrcType, SelImm, UopDivType}
 import xiangshan.backend.fu.FunctionUnit
 import xiangshan.XSCoreParamsKey
 
@@ -39,7 +39,7 @@ class VIPU(implicit p: Parameters) extends FunctionUnit(p(XSCoreParamsKey).VLEN)
   // TODO: mv VecImmExtractor from exe stage to read rf stage(or forward stage).
   val imm = VecInit(Seq.fill(VLEN/XLEN)(VecImmExtractor(ctrl.selImm, vtype.vsew, ctrl.imm))).asUInt
 
-  val _src1 = Mux(SrcType.isImm(ctrl.srcType(0)), imm, io.in.bits.src(0))
+  val _src1 = Mux(SrcType.isImm(ctrl.srcType(0)), imm, Mux(ctrl.uopDivType === UopDivType.VEC_MV_LMUL, VecExtractor(vtype.vsew, io.in.bits.src(0)), io.in.bits.src(0)))
   val _src2 = io.in.bits.src(1)
   val src1 = Mux(VipuType.needReverse(ctrl.fuOpType), _src2, _src1)
   val src2 = Mux(VipuType.needReverse(ctrl.fuOpType), _src1, _src2)

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -56,7 +56,7 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
   // create free list and rat
   val intFreeList = Module(new MEFreeList(NRPhyRegs))
   val intRefCounter = Module(new RefCounter(NRPhyRegs))
-  val fpFreeList = Module(new StdFreeList(NRPhyRegs - 64))
+  val fpFreeList = Module(new StdFreeList(NRPhyRegs - 68))
 
   intRefCounter.io.commit        <> io.robCommits
   intRefCounter.io.redirect      := io.redirect.valid

src/main/scala/xiangshan/backend/rename/RenameTable.scala

@@ -62,8 +62,8 @@ class RenameTable(reg_t: RegType)(implicit p: Parameters) extends XSModule {
   // fp and vec share the same free list, so the first init value of vecRAT is 32
   val rename_table_init = reg_t match {
     case Reg_I => VecInit.fill    (33)(0.U(PhyRegIdxWidth.W))
-    case Reg_F => VecInit.tabulate(32)(_.U(PhyRegIdxWidth.W))
-    case Reg_V => VecInit.tabulate(32)(x => (x + 32).U(PhyRegIdxWidth.W))
+    case Reg_F => VecInit.tabulate(34)(_.U(PhyRegIdxWidth.W))
+    case Reg_V => VecInit.tabulate(34)(x => (x + 34).U(PhyRegIdxWidth.W))
   }
   val spec_table = RegInit(rename_table_init)
   val spec_table_next = WireInit(spec_table)

src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala

@@ -26,7 +26,7 @@ import utility._
 
 class StdFreeList(size: Int)(implicit p: Parameters) extends BaseFreeList(size) with HasPerfEvents {
 
-  val freeList = RegInit(VecInit(Seq.tabulate(size)( i => (i + 64).U(PhyRegIdxWidth.W) )))
+  val freeList = RegInit(VecInit(Seq.tabulate(size)( i => (i + 68).U(PhyRegIdxWidth.W) )))
   val headPtr  = RegInit(FreeListPtr(false, 0))
   val headPtrOH = RegInit(1.U(size.W))
   val headPtrOHShift = CircularShift(headPtrOH)

src/main/scala/xiangshan/package.scala

@@ -557,15 +557,16 @@ package object xiangshan {
   }
 
   object UopDivType {
-    def SCA_SIM = "b000".U
-    def DIR = "b001".U
-    def VEC_LMUL = "b010".U
-    def VEC_MV_LMUL = "b011".U
-    def dummy = "b111".U
+    def SCA_SIM = "b00000".U
+    def DIR = "b00001".U
+    def VEC_LMUL = "b00010".U
+    def VEC_MV_LMUL = "b00011".U
+    def VEC_MV = "b00100".U
+    def dummy = "b11111".U
 
-    def X = BitPat("b000")
+    def X = BitPat("b00000")
 
-    def apply() = UInt(3.W)
+    def apply() = UInt(5.W)
   }
 
   object ExceptionNO {