func(vxsat): add vxsat form VIPU to CSR

src/main/scala/xiangshan/Bundle.scala

@@ -367,6 +367,7 @@ class ExuOutput(isVpu: Boolean = false)(implicit p: Parameters) extends XSBundle
 
   val data = UInt(dataWidth.W)
   val fflags = UInt(5.W)
+  val vxsat = UInt(1.W)
   val redirectValid = Bool()
   val redirect = new Redirect
   val debug = new DebugBundle

src/main/scala/xiangshan/XSCore.scala

@@ -449,6 +449,7 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
   csrioIn.fpu.dirty_fs <> ctrlBlock.io.robio.toCSR.dirty_fs
   csrioIn.fpu.frm <> vecExuBlock.extraio.fuExtra.frm
 
+  csrioIn.vpu.set_vxsat <> ctrlBlock.io.robio.toCSR.vxsat
   csrioIn.vpu.set_vstart.valid <> ctrlBlock.io.robio.toCSR.vcsrFlag
   csrioIn.vpu.set_vl.valid     <> ctrlBlock.io.robio.toCSR.vcsrFlag
   csrioIn.vpu.set_vtype.valid  <> ctrlBlock.io.robio.toCSR.vcsrFlag

src/main/scala/xiangshan/backend/exu/ExeUnit.scala

@@ -104,6 +104,7 @@ class ExeUnit(config: ExuConfig)(implicit p: Parameters) extends Exu(config) {
   if (vipuModules.nonEmpty) {
     vipuModules.map(_._1.asInstanceOf[VIPU]).foreach(mod => {
       mod.vxrm := csr_vxrm
+      io.out.bits.vxsat := mod.vxsat
     })
   }
   val fmaModules = functionUnits.filter(_.isInstanceOf[FMA]).map(_.asInstanceOf[FMA])

src/main/scala/xiangshan/backend/exu/Exu.scala

@@ -74,6 +74,7 @@ case class ExuConfig
   val writeVecRf = fuConfigs.map(_.writeVecRf).reduce(_ || _)
   val writeFpVecRf = writeFpRf || writeVecRf
   val writeFflags = fuConfigs.map(_.writeFflags).reduce(_ || _)
+  val writeVxsat = fuConfigs.map(_.writeVxsat).reduce(_ || _)
   val hasRedirect = fuConfigs.map(_.hasRedirect).reduce(_ || _)
   val hasFastUopOut = fuConfigs.map(_.fastUopOut).reduce(_ || _)
   val exceptionOut = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted
@@ -273,6 +274,7 @@ abstract class Exu(cfg: ExuConfig)(implicit p: Parameters) extends XSModule {
 
   def assignDontCares(out: ExuOutput) = {
     out.fflags := DontCare
+    out.vxsat := DontCare
     out.debug <> DontCare
     out.debug.isMMIO := false.B
     out.debug.isPerfCnt := false.B

src/main/scala/xiangshan/backend/exu/WbArbiter.scala

@@ -37,6 +37,7 @@ class ExuWbArbiter(n: Int, hasFastUopOut: Boolean, fastVec: Seq[Boolean], isVpu:
   class ExuCtrl extends Bundle{
     val uop = new MicroOp
     val fflags = UInt(5.W)
+    val vxsat = UInt(1.W)
     val redirectValid = Bool()
     val redirect = new Redirect
     val debug = new DebugBundle

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -84,6 +84,7 @@ class VpuCsrIO(implicit p: Parameters) extends XSBundle {
   val set_vstart = Output(Valid(UInt(XLEN.W)))
   val set_vl = Output(Valid(UInt(XLEN.W)))
   val set_vtype = Output(Valid(UInt(XLEN.W)))
+  val set_vxsat = Output(Valid(UInt(1.W)))
 
   val dirty_vs = Output(Bool())
 }
@@ -684,11 +685,16 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
   }
   def vxrm_rfn(rdata: UInt): UInt = rdata(2,1)
 
-  def vxsat_wfn(wdata: UInt): UInt = {
+  def vxsat_wfn(update: Boolean)(wdata: UInt): UInt = {
     val vcsrOld = WireInit(vcsr.asTypeOf(new VcsrStruct))
+    val vcsrNew = WireInit(vcsrOld)
     csrw_dirty_vs_state := true.B
-    vcsrOld.vxsat := wdata(0)
-    vcsrOld.asUInt
+    if (update) {
+      vcsrNew.vxsat := wdata(0) | vcsrOld.vxsat
+    } else {
+      vcsrNew.vxsat := wdata(0)
+    }
+    vcsrNew.asUInt
   }
   def vxsat_rfn(rdata: UInt): UInt = rdata(0)
 
@@ -703,7 +709,7 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
   val vcsrMapping = Map(
     MaskedRegMap(Vstart, vstart),
     MaskedRegMap(Vxrm, vcsr, wfn = vxrm_wfn, rfn = vxrm_rfn),
-    MaskedRegMap(Vxsat, vcsr, wfn = vxsat_wfn, rfn = vxsat_rfn),
+    MaskedRegMap(Vxsat, vcsr, wfn = vxsat_wfn(false), rfn = vxsat_rfn),
     MaskedRegMap(Vcsr, vcsr, wfn = vcsr_wfn),
     MaskedRegMap(Vl, vl),
     MaskedRegMap(Vtype, vtype),
@@ -930,6 +936,9 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
   when (RegNext(csrio.fpu.fflags.valid)) {
     fcsr := fflags_wfn(update = true)(RegNext(csrio.fpu.fflags.bits))
   }
+  when(RegNext(csrio.vpu.set_vxsat.valid)) {
+    vcsr := vxsat_wfn(update = true)(RegNext(csrio.vpu.set_vxsat.bits))
+  }
   // set fs and sd in mstatus
   when (csrw_dirty_fp_state || RegNext(csrio.fpu.dirty_fs)) {
     val mstatusNew = WireInit(mstatus.asTypeOf(new MstatusStruct))

src/main/scala/xiangshan/backend/fu/FunctionUnit.scala

@@ -49,6 +49,7 @@ case class FuConfig
   writeFpRf: Boolean,
   writeVecRf: Boolean = false,
   writeFflags: Boolean = false,
+  writeVxsat: Boolean = false,
   hasRedirect: Boolean = false,
   latency: HasFuLatency = CertainLatency(0),
   fastUopOut: Boolean = false,
@@ -72,7 +73,8 @@ case class FuConfig
     (if(writeFpRf) "fp|" else "") +
     (if(writeVecRf) "vec|" else "") +
     (if(writeFflags) "fflags" else "") +
-    (if(!writeIntRf && !writeFpRf && !writeVecRf && !writeFflags) "none" else "") + ") " +
+    (if(writeVxsat) "vxsat" else "") +
+    (if(!writeIntRf && !writeFpRf && !writeVecRf && !writeFflags && !writeVxsat) "none" else "") + ") " +
     (if(hasRedirect) "hasRedirect " else "") +
     (if(latency.latencyVal.getOrElse(99) != 99) "latency " + latency.latencyVal.get+" " else "") +
     (if(fastUopOut) "hasFastUopOut " else "") +

src/main/scala/xiangshan/backend/fu/vector/VIPU.scala

@@ -35,6 +35,7 @@ class VIPU(implicit p: Parameters) extends VPUSubModule(p(XSCoreParamsKey).VLEN)
 
 // extra io
   val vxrm = IO(Input(UInt(2.W)))
+  val vxsat = IO(Output(UInt(1.W)))
 
 // def some signal
   val dataReg = Reg(io.out.bits.data.cloneType)
@@ -74,6 +75,7 @@ class VIPU(implicit p: Parameters) extends VPUSubModule(p(XSCoreParamsKey).VLEN)
   vialu.vxrm := vxrm
   io.out.bits.data :=  Mux(state === s_compute && outFire, dataWire, dataReg)
   io.out.bits.uop := s0_uopReg
+  vxsat := vialu.vxsat
 
   vialu.io.in.valid := io.in.valid && state === s_idle
   io.out.valid := state === s_compute && outValid || state === s_finish
@@ -118,6 +120,7 @@ class VIAluWrapper(implicit p: Parameters)  extends VPUSubModule(p(XSCoreParamsK
 
 // extra io
   val vxrm = IO(Input(UInt(2.W)))
+  val vxsat = IO(Output(UInt(1.W)))
 
 // rename signal
   val in = io.in.bits
@@ -162,6 +165,7 @@ class VIAluWrapper(implicit p: Parameters)  extends VPUSubModule(p(XSCoreParamsK
 // connect io
   io.out.bits.data := vdOut
   io.out.bits.uop := DontCare
+  vxsat := vxsatOut
   io.out.valid := vialu.io.out.valid
   io.in.ready := DontCare
 }

src/main/scala/xiangshan/backend/rob/Rob.scala

@@ -142,6 +142,7 @@ class RobCSRIO(implicit p: Parameters) extends XSBundle {
   val wfiEvent   = Input(Bool())
 
   val fflags     = Output(Valid(UInt(5.W)))
+  val vxsat      = Output(Valid(UInt(1.W)))
   val dirty_fs   = Output(Bool())
   val perfinfo   = new Bundle {
     val retiredInstr = Output(UInt(3.W))
@@ -410,6 +411,8 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
   val exeWbSel = outer.selWritebackSinks(_.exuConfigs.length)
   val fflagsWbSel = outer.selWritebackSinks(_.exuConfigs.count(_.exists(_.writeFflags)))
   val fflagsPorts = selectWb(fflagsWbSel, _.exists(_.writeFflags))
+  val vxsatWbSel = outer.selWritebackSinks(_.exuConfigs.count(_.exists(_.writeVxsat)))
+  val vxsatPorts = selectWb(vxsatWbSel, _.exists(_.writeVxsat))
   val exceptionWbSel = outer.selWritebackSinks(_.exuConfigs.count(_.exists(_.needExceptionGen)))
   val exceptionPorts = selectWb(exceptionWbSel, _.exists(_.needExceptionGen))
   val exuWbPorts = selectWb(exeWbSel, _.forall(_ != StdExeUnitCfg))
@@ -418,6 +421,7 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
   println(s"exuPorts: ${exuWbPorts.map(_._1.map(_.name))}")
   println(s"stdPorts: ${stdWbPorts.map(_._1.map(_.name))}")
   println(s"fflags: ${fflagsPorts.map(_._1.map(_.name))}")
+  println(s"vxsat: ${vxsatPorts.map(_._1.map(_.name))}")
 
 
   val exuWriteback = exuWbPorts.map(_._2)
@@ -479,6 +483,7 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
   val exceptionGen = Module(new ExceptionGen)
   val exceptionDataRead = exceptionGen.io.state
   val fflagsDataRead = Wire(Vec(CommitWidth, UInt(5.W)))
+  val vxsatDataRead = Wire(Vec(CommitWidth, UInt(1.W)))
 
   io.robDeqPtr := deqPtr
 
@@ -716,6 +721,11 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
   fflags.bits := wflags.zip(fflagsDataRead).map({
     case (w, f) => Mux(w, f, 0.U)
   }).reduce(_|_)
+  val vxsat = Wire(Valid(UInt(1.W)))
+  vxsat.valid := io.commits.isCommit && VecInit(wflags).asUInt.orR
+  vxsat.bits := wflags.zip(vxsatDataRead).map({
+    case (w, f) => Mux(w, f, 0.U)
+  }).reduce(_|_)
   val dirty_fs = io.commits.isCommit && VecInit(fpWen).asUInt.orR
 
   // when mispredict branches writeback, stop commit in the next 2 cycles
@@ -756,14 +766,15 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
     }
 
     XSInfo(io.commits.isCommit && io.commits.commitValid(i),
-      "retired pc %x wen %d ldest %d pdest %x old_pdest %x data %x fflags: %b\n",
+      "retired pc %x wen %d ldest %d pdest %x old_pdest %x data %x fflags: %b vxsat: %b\n",
       debug_microOp(deqPtrVec(i).value).cf.pc,
       io.commits.info(i).rfWen,
       io.commits.info(i).ldest,
       io.commits.info(i).pdest,
       io.commits.info(i).old_pdest,
       debug_exuData(deqPtrVec(i).value),
-      fflagsDataRead(i)
+      fflagsDataRead(i),
+      vxsatDataRead(i)
     )
     XSInfo(state === s_walk && io.commits.walkValid(i), "walked pc %x wen %d ldst %d data %x\n",
       debug_microOp(walkPtrVec(i).value).cf.pc,
@@ -776,9 +787,10 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
     io.commits.info.map(info => dontTouch(info.pc))
   }
 
-  // sync fflags/dirty_fs to csr
+  // sync fflags/dirty_fs/vxsat to csr
   io.csr.fflags := RegNext(fflags)
   io.csr.dirty_fs := RegNext(dirty_fs)
+  io.csr.vxsat := RegNext(vxsat)
 
   // sync v csr to csr
 //  io.csr.vcsrFlag := RegNext(isVsetFlushPipe)
@@ -1058,6 +1070,18 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
   fflagsDataModule.io.raddr := VecInit(deqPtrVec_next.map(_.value))
   fflagsDataRead := fflagsDataModule.io.rdata
 
+  val vxsat_wb = vxsatPorts.map(_._2)
+  val vxsatDataModule = Module(new SyncDataModuleTemplate(
+    UInt(1.W), RobSize, CommitWidth, vxsat_wb.size)
+  )
+  for(i <- vxsat_wb.indices){
+    vxsatDataModule.io.wen  (i) := vxsat_wb(i).valid
+    vxsatDataModule.io.waddr(i) := vxsat_wb(i).bits.uop.robIdx.value
+    vxsatDataModule.io.wdata(i) := vxsat_wb(i).bits.vxsat
+  }
+  vxsatDataModule.io.raddr := VecInit(deqPtrVec_next.map(_.value))
+  vxsatDataRead := vxsatDataModule.io.rdata
+
   val instrCntReg = RegInit(0.U(64.W))
   val fuseCommitCnt = PopCount(io.commits.commitValid.zip(io.commits.info).map{ case (v, i) => RegNext(v && CommitType.isFused(i.commitType)) })
   val trueCommitCnt = RegNext(commitCnt) +& fuseCommitCnt

src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala

@@ -988,6 +988,7 @@ def detectRollback(i: Int) = {
   io.ldout(0).bits.debug.paddr := debug_paddr(deqPtr)
   io.ldout(0).bits.debug.vaddr := vaddrModule.io.rdata(1)
   io.ldout(0).bits.fflags := DontCare
+  io.ldout(0).bits.vxsat := DontCare
 
   io.ldout(0).valid := (uncacheState === s_wait) && !uncacheCommitFired
 

src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala

@@ -525,6 +525,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule
   io.mmioStout.bits.debug.paddr := DontCare
   io.mmioStout.bits.debug.isPerfCnt := false.B
   io.mmioStout.bits.fflags := DontCare
+  io.mmioStout.bits.vxsat := DontCare
   io.mmioStout.bits.debug.vaddr := DontCare
   // Remove MMIO inst from store queue after MMIO request is being sent
   // That inst will be traced by uncache state machine

src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala

@@ -1117,6 +1117,7 @@ class LoadUnit(implicit p: Parameters) extends XSModule
   hitLoadOut.bits.debug.paddr := load_s2.io.out.bits.paddr
   hitLoadOut.bits.debug.vaddr := load_s2.io.out.bits.vaddr
   hitLoadOut.bits.fflags := DontCare
+  hitLoadOut.bits.vxsat := DontCare
 
   load_s2.io.out.ready := true.B
 

src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala

@@ -221,6 +221,7 @@ class StoreUnit_S3(implicit p: Parameters) extends XSModule {
   io.stout.bits.debug.vaddr := io.in.bits.vaddr
   io.stout.bits.debug.isPerfCnt := false.B
   io.stout.bits.fflags := DontCare
+  io.stout.bits.vxsat := DontCare
 
 }
 

src/main/scala/xiangshan/package.scala

@@ -841,7 +841,7 @@ package object xiangshan {
     fuGen = vipuGen,
     fuSel = (uop: MicroOp) => FuType.vipu === uop.ctrl.fuType,
     fuType = FuType.vipu,
-    numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false,
+    numIntSrc = 0, numFpSrc = 0, writeIntRf = false, writeFpRf = false, writeFflags = false, writeVxsat = true,
     numVecSrc = 4, writeVecRf = true,
     fastUopOut = false, // TODO: check
     fastImplemented = true, //TODO: check