decode: modify vx instruction uops and fix bug (#1952)

src/main/scala/xiangshan/Parameters.scala

@@ -130,6 +130,9 @@ case class XSCoreParameters
   FtqSize: Int = 64,
   EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false
   IssQueSize: Int = 16,
+  IntLogicRegs: Int = 33,
+  FpLogicRegs: Int = 34,
+  VecLogicRegs: Int = 34,
   NRPhyRegs: Int = 192,
   IntPhyRegs: Int = 192,
   VfPhyRegs: Int = 192,
@@ -392,6 +395,9 @@ trait HasXSParameter {
   val FtqSize = coreParams.FtqSize
   val IssQueSize = coreParams.IssQueSize
   val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp
+  val IntLogicRegs = coreParams.IntLogicRegs
+  val FpLogicRegs = coreParams.FpLogicRegs
+  val VecLogicRegs = coreParams.VecLogicRegs
   val NRPhyRegs = coreParams.NRPhyRegs
   val PhyRegIdxWidth = log2Up(NRPhyRegs)
   val IntPhyRegs = coreParams.IntPhyRegs

src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala

@@ -85,7 +85,7 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
     UopDivType.VEC_MV -> 2.U,
     UopDivType.DIR -> 2.U,
     UopDivType.VEC_LMUL -> lmul,
-    UopDivType.VEC_MV_LMUL -> (lmul + 2.U)
+    UopDivType.VEC_MV_LMUL -> (lmul + 1.U)
   ))
 
   //uop div up to maxNumOfUop
@@ -162,43 +162,27 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
       csBundle(0).ctrl.uopIdx := 0.U
       csBundle(0).ctrl.fuType := FuType.i2f
       csBundle(0).ctrl.rfWen := false.B
-      csBundle(0).ctrl.fpWen := true.B
-      csBundle(0).ctrl.vecWen := false.B
+      csBundle(0).ctrl.fpWen := false.B
+      csBundle(0).ctrl.vecWen := true.B
       csBundle(0).ctrl.fpu.isAddSub := false.B
       csBundle(0).ctrl.fpu.typeTagIn := FPU.D
       csBundle(0).ctrl.fpu.typeTagOut := FPU.D
       csBundle(0).ctrl.fpu.fromInt := true.B
       csBundle(0).ctrl.fpu.wflags := false.B
-      csBundle(0).ctrl.fpu.fpWen := true.B
+      csBundle(0).ctrl.fpu.fpWen := false.B
       csBundle(0).ctrl.fpu.div := false.B
       csBundle(0).ctrl.fpu.sqrt := false.B
       csBundle(0).ctrl.fpu.fcvt := false.B
       /*
-      vfmv.s.f
-       */
-      csBundle(1).ctrl.srcType(0) := SrcType.fp
-      csBundle(1).ctrl.srcType(1) := SrcType.vp
-      csBundle(1).ctrl.srcType(2) := SrcType.vp
-      csBundle(1).ctrl.lsrc(0) := 33.U
-      csBundle(1).ctrl.lsrc(1) := 0.U
-      csBundle(1).ctrl.lsrc(2) := 33.U
-      csBundle(1).ctrl.ldest := 33.U
-      csBundle(1).ctrl.uopIdx := 1.U
-      csBundle(1).ctrl.fuType := FuType.vppu
-      csBundle(1).ctrl.fuOpType := VppuType.f2s
-      csBundle(1).ctrl.rfWen := false.B
-      csBundle(1).ctrl.fpWen := false.B
-      csBundle(1).ctrl.vecWen := true.B
-      /*
       LMUL
        */
       for (i <- 0 until 8) {
-        csBundle(i + 2).ctrl.srcType(0) := SrcType.vp
-        csBundle(i + 2).ctrl.srcType(3) := 0.U
-        csBundle(i + 2).ctrl.lsrc(0) := 33.U
-        csBundle(i + 2).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U
-        csBundle(i + 2).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U
-        csBundle(i + 2).ctrl.uopIdx := (i + 2).U
+        csBundle(i + 1).ctrl.srcType(0) := SrcType.vp
+        csBundle(i + 1).ctrl.srcType(3) := 0.U
+        csBundle(i + 1).ctrl.lsrc(0) := 33.U
+        csBundle(i + 1).ctrl.lsrc(1) := ctrl_flow.instr(24, 20) + i.U
+        csBundle(i + 1).ctrl.ldest := ctrl_flow.instr(11, 7) + i.U
+        csBundle(i + 1).ctrl.uopIdx := (i + 1).U
       }
       csBundle(numOfUop - 1.U).ctrl.uopIdx := "b11111".U
     }
@@ -217,7 +201,7 @@ class DecodeUnitComp(maxNumOfUop : Int)(implicit p : Parameters) extends XSModul
       when(!io.validFromIBuf(0)) {
         stateReg := normal
         uopRes := 0.U
-      }.elsewhen(numOfUop > readyCounter && !readyCounter){
+      }.elsewhen((numOfUop > readyCounter) && (readyCounter =/= 0.U)){
         stateReg := ext
         uopRes := numOfUop - readyCounter
       }.otherwise {

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -56,7 +56,7 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
   // create free list and rat
   val intFreeList = Module(new MEFreeList(NRPhyRegs))
   val intRefCounter = Module(new RefCounter(NRPhyRegs))
-  val fpFreeList = Module(new StdFreeList(NRPhyRegs - 68))
+  val fpFreeList = Module(new StdFreeList(NRPhyRegs - FpLogicRegs - VecLogicRegs))
 
   intRefCounter.io.commit        <> io.robCommits
   intRefCounter.io.redirect      := io.redirect.valid

src/main/scala/xiangshan/backend/rename/RenameTable.scala

@@ -61,9 +61,9 @@ class RenameTable(reg_t: RegType)(implicit p: Parameters) extends XSModule {
   // speculative rename table
   // fp and vec share the same free list, so the first init value of vecRAT is 32
   val rename_table_init = reg_t match {
-    case Reg_I => VecInit.fill    (33)(0.U(PhyRegIdxWidth.W))
-    case Reg_F => VecInit.tabulate(34)(_.U(PhyRegIdxWidth.W))
-    case Reg_V => VecInit.tabulate(34)(x => (x + 34).U(PhyRegIdxWidth.W))
+    case Reg_I => VecInit.fill    (IntLogicRegs)(0.U(PhyRegIdxWidth.W))
+    case Reg_F => VecInit.tabulate(FpLogicRegs)(_.U(PhyRegIdxWidth.W))
+    case Reg_V => VecInit.tabulate(VecLogicRegs)(x => (x + FpLogicRegs).U(PhyRegIdxWidth.W))
   }
   val spec_table = RegInit(rename_table_init)
   val spec_table_next = WireInit(spec_table)

src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala

@@ -26,7 +26,7 @@ import utility._
 
 class StdFreeList(size: Int)(implicit p: Parameters) extends BaseFreeList(size) with HasPerfEvents {
 
-  val freeList = RegInit(VecInit(Seq.tabulate(size)( i => (i + 68).U(PhyRegIdxWidth.W) )))
+  val freeList = RegInit(VecInit(Seq.tabulate(size)( i => (i + FpLogicRegs + VecLogicRegs).U(PhyRegIdxWidth.W) )))
   val headPtr  = RegInit(FreeListPtr(false, 0))
   val headPtrOH = RegInit(1.U(size.W))
   val headPtrOHShift = CircularShift(headPtrOH)