1. fix bug that connection of fuOpType in VIPU
2. vadd vmin vminu vmax vmaxu vand vor vxor vsub vrsub test pass

1. add end flag for uopIdx
2. fix(VFPU): io.in.ready should be ture.B
3. func(VIAlu):add VIAlu code v2

* add DecodeUnitComp.scala and modify DecodeStage.scala for vector uop Div support(LMUL=8)

* changes made to implement a uop Div supporting with a cleaner code style(support Config)

* MaxNumOfUop parameterization supporting

* func(vrsub):support vrsub.vv

TODO:
1. depends on yunsuan'commit of func(vrsub)
2. require difftest

* func(adc): support vmadc.vv vmadc.vi vmadc.vx

TODO:
1. NEMU need to update

TODO:ready-to-run need to update after 243c4e5ae53fe4(Ziyue-Zhang/NEMU_RVV/tree/master)

1. style(isVpu): delete isVpu in FuType
2. support VppuType.f2s & VppuType.vslide1up & generate verilog sucessful

Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>

Besides adding load/store arch database, this PR also fixed a bug which caused
prefetch using l1 info failed to work.

Former RTL change break `isFirstIssue` flag gen logic, which caused prefetcher
failed to receive prefetch train info from L1. This commit should fix that.

* ROB: add inst db drop

globalID signal output is still duplicated

* TLB: TLB will carry mem idx when req and resp

* InstDB: update the TLBFirstIssue

* InstDB: the first version is complete

* InstDB: update decode logic

* InstDB: update ctrlBlock writeback

* Merge: fix bug

* merge: fix compile bug

* code rule: rename debug signals and add db's FPGA signal control

* code rule: update db's FPGA signal control

* ldu: fix isFirstIssue flag for ldflow from rs

* ldu: isFirstIssue flag for hw pf is always false

---------
Co-authored-by: Ngood-circle <fenghaoyuan19@mails.ucas.ac.cn>
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

* test: add example to genenrate verilog for a small module

Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop

* test: add DecodeUnitTest as an example for xs' chiseltest

* ctrlblock: <> usage has changed, unidirection should use :=

* bump huancun

* makefile: mv new makefile cmd into Makefile.test

Here is a bug cause by EnableUncacheWriteOutstanding:
The case is extintr in Nexus-AM.
Three steps of the test:
  clear intrGen's intr: Stop pass interrupt. A mmio write.
  clear plic claim: complete intr. A mmio write.
  read plic claim to check: claim should be 0. A mmio read.
The corner case:
  intrGen's mmio write is to slow. The instruction after it executes
and plic claim's mmio's write & read execute before it. On the side of
core with plic, claim is cleared. But on the side of intrGen with plic,
the source of interrupt is still enabled and trigger interrupt.
So the "read plic claim to check" get a valid claim and failed.

Here is a bug cause by EnableUncacheWriteOutstanding:
The case is extintr in Nexus-AM.
Three steps of the test:
  clear intrGen's intr: Stop pass interrupt. A mmio write.
  clear plic claim: complete intr. A mmio write.
  read plic claim to check: claim should be 0. A mmio read.
The corner case:
  intrGen's mmio write is to slow. The instruction after it executes
and plic claim's mmio's write & read execute before it. On the side of
core with plic, claim is cleared. But on the side of intrGen with plic,
the source of interrupt is still enabled and trigger interrupt.
So the "read plic claim to check" get a valid claim and failed.