ExuInput is used to flush the function unit itself.
  ExuOutput is used to flush other function units.
  Just ROB, bru(can exec jal/jalr/csr instrs) and alu(can exec
branch instrs) can generate redirect.

Use fake Icache to fetch 8 instructions per cycle.

FPU can run at 200+MHz on axu3cg board now :)

[IntToFloat]: Count leading zeros of positive and negative number in parallel because IntToFloat is in the critical path

FPUv0.1 can pass all rvf/rvd tests in both riscv-tests and berkeley-softfloat
Signed-off-by: NLinJiawei <linjiav@outlook.com>

* now mainargs is supported by nexus-am

* refer to the RAS prediction hints in RV32I in the RISC-V manual

This reverts commit 2dfc501e.

This reverts merge request !72

* if we disable dcache, the compilation will fail

* This can help to generate desired frequency of timer interrupt, no
  matter what frequency of the clock is.

* According to The RISC-V Instruction Set Manual Volume II:
Privileged Architecture, for instruction-fetch access or
page-fault exceptions on systems with variable-length instructions,
m/stval will contain the virtual address of the portion
of the instruction that caused the fault while m/sepc will
point to the beginning of the instruction.