noop: move the source of lsuMMIO from dcache to dtlb

* if we disable dcache, the compilation will fail

src/main/scala/noop/Cache.scala

@@ -236,11 +236,6 @@ sealed class CacheStage3(implicit val cacheConfig: CacheConfig) extends CacheMod
   val meta = Mux1H(io.in.bits.waymask, io.in.bits.metas)
   assert(!(mmio && hit), "MMIO request should not hit in cache")
 
-  // this is ugly
-  if (cacheName == "dcache") {
-    BoringUtils.addSource(mmio, "lsuMMIO")
-  }
-
   val useForwardData = io.in.bits.isForwardData && io.in.bits.waymask === io.in.bits.forwardData.waymask.getOrElse("b1".U)
   val dataReadArray = Mux1H(io.in.bits.waymask, io.in.bits.datas).data
   val dataRead = Mux(useForwardData, io.in.bits.forwardData.data.data, dataReadArray)

src/main/scala/noop/TLB.scala

@@ -299,6 +299,8 @@ class TLB(implicit val tlbConfig: TLBConfig) extends TlbModule{
   PipelineConnectTLB(io.in.req, tlbExec.io.in, mdUpdate, tlbExec.io.isFinish, io.flush, vmEnable)
   if(tlbname == "dtlb") {
     PipelineConnect(tlbExec.io.out, tlbEmpty.io.in, tlbEmpty.io.out.fire(), io.flush)
+    val mmio = AddressSpace.isMMIO(io.out.req.bits.addr)
+    BoringUtils.addSource(mmio, "lsuMMIO")
   }
   when(!vmEnable) {
     tlbExec.io.out.ready := true.B // let existed request go out