提交 · 57c4f8d6c40b210d99a6e8c1f324345547eb16db · OpenXiangShan / XiangShan

20 6月, 2020 8 次提交
- L
  
  Rename: send phy-reg status(rdy/busy) to dispatch-2 · 57c4f8d6
  由 LinJiawei 提交于 6月 20, 2020
  
  57c4f8d6
- P
  Merge pull request #6 from RISCVERS/alu · d8a48a5f
  由 poemonsense 提交于 6月 20, 2020
```
Bundle/ExuIO: add redirect to ExuInput and ExuOutput
```
  d8a48a5f
- Z
  Bundle/ExuIO: add redirect to ExuInput and ExuOutput · c2430064
  由 ZhangZifei 提交于 6月 20, 2020
```
  ExuInput is used to flush the function unit itself.
  ExuOutput is used to flush other function units.
  Just ROB, bru(can exec jal/jalr/csr instrs) and alu(can exec
branch instrs) can generate redirect.
```
  c2430064
- L
  Merge pull request #5 from RISCVERS/add-freelist-ptr-in-uOp · 4673d306
  由 ljw 提交于 6月 20, 2020
```
Add freelist ptr in MicroOp
```
  4673d306
- L
  
  xiangshan/Bundle: add freelist alloc ptr in MicroOp · 54658d36
  由 LinJiawei 提交于 6月 20, 2020
  
  54658d36
- L
  
  xiangshan/Bundle: update exu io · db34a189
  由 LinJiawei 提交于 6月 20, 2020
  
  db34a189
- L
  Merge pull request #3 from RISCVERS/add-isException-in-Redirect · f5c553d7
  由 ljw 提交于 6月 20, 2020
```
Bundle: Add 'isException' in Redirect
```
  f5c553d7
- L
  
  Bundle: Add 'isException' in Redirect · 37fcf7fb
  由 LinJiawei 提交于 6月 20, 2020
  
  37fcf7fb
19 6月, 2020 7 次提交
- L
  Add CI Support for XiangShan (#2) · 1229115c
  由 ljw 提交于 6月 19, 2020
```
* Create core_ci.yml

* Update core_ci.yml
```
  1229115c
- P
  Merge pull request #1 from RISCVERS/remove-xsqueue · f897bc5d
  由 poemonsense 提交于 6月 19, 2020
```
utils: remove multi-input multi-output queue
```
  f897bc5d
- Y
  
  utils: remove multi-input multi-output queue · 7a018719
  由 Yinan Xu 提交于 6月 19, 2020
  
  7a018719
- L
  
  Merge branch 'dev-xs' into 'master' · 1115dc06
  由 LinJiawei 提交于 6月 19, 2020
  
  1115dc06
- Y
  
  Merge branch 'dev-xs' of github.com:RISCVERS/XiangShan into dev-xs · 88efb71b
  由 Yinan Xu 提交于 6月 19, 2020
  
  88efb71b
- Y
  
  utils: add multi-input multi-output queue · 676992d8
  由 Yinan Xu 提交于 6月 19, 2020
  
  676992d8
- L
  
  Add roq walk signal. Fix issue queue bypass logic. · 296e7422
  由 LinJiawei 提交于 6月 19, 2020
  
  296e7422
18 6月, 2020 1 次提交
- L
  
  Adjust pipeline, refactor EXU, IssueQueue · 9a2e6b8a
  由 LinJiawei 提交于 6月 18, 2020
  
  9a2e6b8a
16 6月, 2020 2 次提交
- L
  
  Initially completed the module interface design · 5844fcf0
  由 LinJiawei 提交于 6月 16, 2020
  
  5844fcf0
- L
  
  Remove chiseltest and FPU test to make compiler happy · 98d97dd3
  由 LinJiawei 提交于 6月 16, 2020
  
  98d97dd3
13 6月, 2020 1 次提交
- L
  Initial Commit of XiangShan CPU · 1e3fad10
  由 LinJiawei 提交于 6月 13, 2020
```
Use fake Icache to fetch 8 instructions per cycle.
```
  1e3fad10
05 6月, 2020 1 次提交
- L
  
  [FMA]: Set 'UseRealArraryMult' to false by default. · 6a549612
  由 LinJiawei 提交于 6月 05, 2020
  
  6a549612
01 6月, 2020 1 次提交
- L
  
  Implement Float Point RVC Instructions and Compare FP-Regs in Diff-test · a9058a0d
  由 LinJiawei 提交于 6月 01, 2020
  
  a9058a0d
10 5月, 2020 3 次提交
- L
  
  [FMA] fix a bug in stage 2 · bf16ffe4
  由 LinJiawei 提交于 5月 10, 2020
  
  bf16ffe4
- L
  
  Update FPU readme · 05ff9d21
  由 LinJiawei 提交于 5月 10, 2020
  
  05ff9d21
- L
  [FMA]: Use a Leading Zero Anticipator to reduce cycle time in pipeline stage 3 · b05b0d70
  由 LinJiawei 提交于 5月 09, 2020
```
FPU can run at 200+MHz on axu3cg board now :)
```
  b05b0d70
09 5月, 2020 1 次提交
- L
  [IntToFloat]: Count leading zeros of positive and negative number in parallel... · 6010ee9f
  由 LinJiawei 提交于 5月 09, 2020
```
[IntToFloat]: Count leading zeros of positive and negative number in parallel because IntToFloat is in the critical path
```
  6010ee9f
08 5月, 2020 1 次提交

FPUv0.1 · 6aea7ec5

由 LinJiawei 提交于 5月 07, 2020

FPUv0.1 can pass all rvf/rvd tests in both riscv-tests and berkeley-softfloat
Signed-off-by: NLinJiawei <linjiav@outlook.com>

6aea7ec5

08 3月, 2020 4 次提交
- Z
  Merge branch 'misc' into 'master' · e5a89aa0
  由 Zihao Yu 提交于 3月 08, 2020
```
Misc

See merge request projectn/noop!80
```
  e5a89aa0
- Z
  
  emu,ram: remove unused code · ceca72d3
  由 Zihao Yu 提交于 3月 08, 2020
  
  ceca72d3
- Z
  
  fpga,axu3cg: use macro to control the usage of HDMI · d9ad7a31
  由 Zihao Yu 提交于 3月 08, 2020
  
  d9ad7a31
- Z
  emu: remove mainargs · 19ea7381
  由 Zihao Yu 提交于 3月 08, 2020
```
* now mainargs is supported by nexus-am
```
  19ea7381
24 12月, 2019 10 次提交
- Z
  Merge branch 'fpga' into 'master' · 83e5cd66
  由 Zihao Yu 提交于 12月 24, 2019
```
README.md: update doc

See merge request projectn/noop!77
```
  83e5cd66
- Z
  
  README.md: update doc · 5c647eb5
  由 Zihao Yu 提交于 12月 24, 2019
  
  5c647eb5
- Z
  Merge branch 'fpga' into 'master' · 37c18e5d
  由 Zihao Yu 提交于 12月 24, 2019
```
Fpga

See merge request projectn/noop!76
```
  37c18e5d
- Z
  
  fpga,boot,README: update doc · f8c1200b
  由 Zihao Yu 提交于 12月 24, 2019
  
  f8c1200b
- Z
  
  fpga,resource: add ddr-loader · 5a28a192
  由 Zihao Yu 提交于 12月 24, 2019
  
  5a28a192
- Z
  
  fpga,noop.tcl: add AXI4Flash and ILA · dfa3bd7f
  由 Zihao Yu 提交于 12月 24, 2019
  
  dfa3bd7f
- Z
  
  system,SoC; enable ILA · 0fbc6212
  由 Zihao Yu 提交于 12月 24, 2019
  
  0fbc6212
- Z
  
  top,TopMain: add AXI4Flash · 30b5c5b6
  由 Zihao Yu 提交于 12月 24, 2019
  
  30b5c5b6
- Z
  Merge branch 'asic' into 'master' · 1c929a0f
  由 Zihao Yu 提交于 12月 24, 2019
```
Asic

See merge request projectn/noop!75
```
  1c929a0f
- Z
  
  system,SoC: clean up external CLINT · 6c199c4e
  由 Zihao Yu 提交于 12月 24, 2019
  
  6c199c4e

OpenXiangShan / XiangShan 10 个月 前同步成功

OpenXiangShan / XiangShan
10 个月前同步成功