Implement Float Point RVC Instructions and Compare FP-Regs in Diff-test

src/main/scala/noop/IDU2.scala

@@ -3,7 +3,7 @@ package noop
 import chisel3._
 import chisel3.util._
 import chisel3.util.experimental.BoringUtils
-import noop.isa.{RVFInstr, RVDInstr}
+import noop.isa.{RVDInstr, RVFInstr, RVF_LSUInstr, RVD_LSUInstr}
 import utils._
 
 class IDU2(implicit val p: NOOPConfig) extends NOOPModule with HasInstrType {
@@ -25,8 +25,29 @@ class IDU2(implicit val p: NOOPConfig) extends NOOPModule with HasInstrType {
   val fpExtraDecodeTable = RVFInstr.extraTable ++ RVDInstr.extraTable
   val isFp :: fpSrc1Type :: fpSrc2Type :: fpSrc3Type :: fpRfWen :: fpWen :: fpFuOpType :: fpInputFunc :: fpOutputFunc :: Nil =
     if(HasFPU) ListLookup(instr, RVFInstr.extraTableDefault, fpExtraDecodeTable) else RVFInstr.extraTableDefault
-  // flw/fsw/fld/fsd
-  val isFloatLdSd = if(HasFPU) instr(6,0)==="b0000111".U || instr(6,0)==="b0100111".U else false.B
+
+  val floatLdStInstrs = List(
+    RVF_LSUInstr.FLW,
+    RVF_LSUInstr.FSW,
+    RVD_LSUInstr.FLD,
+    RVCInstr.C_FLD,
+    RVCInstr.C_FLDSP,
+    RVD_LSUInstr.FSD,
+    RVCInstr.C_FSD,
+    RVCInstr.C_FSDSP
+  )
+
+  def treeCmp(key: UInt, cmpList: List[BitPat]): Bool = {
+    cmpList.size match {
+      case 1 =>
+        key === cmpList.head
+      case n =>
+        treeCmp(key, cmpList take n/2) || treeCmp(key, cmpList drop n/2)
+    }
+  }
+
+  val isFloatLdSd = if(HasFPU) treeCmp(instr, floatLdStInstrs) else false.B
+
   val isRVFD = isFp.asBool()
   val instrType = Mux(hasIntrOrExceptino,
     intrInstrType,
@@ -111,7 +132,7 @@ class IDU2(implicit val p: NOOPConfig) extends NOOPModule with HasInstrType {
   // TODO: refactor decode logic
   // make non-register addressing to zero, since isu.sb.isBusy(0) === false.B
   io.out.bits.ctrl.rfSrc1 := Mux(src1Type === SrcType.pc, 0.U, rfSrc1)
-  io.out.bits.ctrl.rfSrc2 := Mux(src2Type === SrcType.reg, rfSrc2, 0.U)
+  io.out.bits.ctrl.rfSrc2 := Mux(src2Type === SrcType.imm, 0.U, rfSrc2)
   io.out.bits.ctrl.rfWen  := rfWen
   io.out.bits.ctrl.fpWen := fpWen.asBool()
   io.out.bits.ctrl.rfDest := Mux(fpWen.asBool() || rfWen, rfDest, 0.U)

src/main/scala/noop/ISU.scala

@@ -62,17 +62,14 @@ class ISU(implicit val p: NOOPConfig) extends NOOPModule with HasRegFileParamete
   val src1Ready = !sb.isBusy(rfSrc1) || src1ForwardNextCycle || src1Forward
   val src2Ready = !sb.isBusy(rfSrc2) || src2ForwardNextCycle || src2Forward
 
+  val fpr = new RegFile(width = XLEN, hasZero = false)
+
   val (fprSrcReady,fprSrcData):(Bool,Array[UInt]) = if(HasFPU){
-    val fpr = new RegFile(width = XLEN, hasZero = false)
     val fsb = new ScoreBoard(hasZero = false)
     val forwardFpWen = io.forward.wb.fpWen && io.forward.valid
 
     when (io.wb.fpWen) {
       fpr.write(io.wb.rfDest, io.wb.rfData)
-      Debug(){
-        printf(p"[isu] write fpr:${io.wb.rfDest} value=${Hexadecimal(io.wb.rfData)} " +
-          p"at pc=${Hexadecimal(io.in.bits.cf.pc)}\n")
-      }
     }
 
     val fsbClearMask = Mux(io.wb.fpWen && !isDepend(io.wb.rfDest, io.forward.wb.rfDest, forwardFpWen),
@@ -82,7 +79,8 @@ class ISU(implicit val p: NOOPConfig) extends NOOPModule with HasRegFileParamete
       .otherwise { fsb.update(fsbSetMask, fsbClearMask) }
 
     val instr = io.in.bits.cf.instr
-    val (fpSrc1,fpSrc2,fpSrc3) = (instr(19, 15), instr(24, 20), instr(31, 27))
+
+    val (fpSrc1,fpSrc2,fpSrc3) = (rfSrc1, rfSrc2, instr(31, 27))
     val srcs = Seq(fpSrc1, fpSrc2, fpSrc3).zip(Seq(
       io.in.bits.ctrl.src1Type,
       io.in.bits.ctrl.src2Type,
@@ -154,6 +152,8 @@ class ISU(implicit val p: NOOPConfig) extends NOOPModule with HasRegFileParamete
   BoringUtils.addSource(io.out.valid && !io.out.fire(), "perfCntCondMexuBusy")
 
   if (!p.FPGAPlatform) {
-    BoringUtils.addSource(VecInit((0 until NRReg).map(i => rf.read(i.U))), "difftestRegs")
+    val gRegs = (0 until NRReg).map(i => rf.read(i.U))
+    val fRegs = (0 until NRReg).map(i => if(HasFPU) fpr.read(i.U) else  0.U)
+    BoringUtils.addSource(VecInit(gRegs ++ fRegs), "difftestRegs")
   }
 }

src/main/scala/noop/isa/RVC.scala

@@ -60,13 +60,13 @@ object RVCInstr extends HasInstrType with HasRVCConst {
   def C_FLD      = BitPat("b????????????????_001_?_??_???_??_???_00")
 //   def C_LQ    = BitPat("b????????????????_001_?_??_???_??_???_00")
   def C_LW       = BitPat("b????????????????_010_?_??_???_??_???_00")
-//   def C_FLW   = BitPat("b????????????????_011_?_??_???_??_???_00")
+//   def C_FLW   = BitPat("b????????????????_011_?_??_???_??_???_00") // RV32FC Only
   def C_LD       = BitPat("b????????????????_011_?_??_???_??_???_00")
   // def C_LI    = BitPat("b????????????????_100_?_??_???_??_???_00") //reserved
   def C_FSD      = BitPat("b????????????????_101_?_??_???_??_???_00")
 //   def C_SQ    = BitPat("b????????????????_101_?_??_???_??_???_00")
   def C_SW       = BitPat("b????????????????_110_?_??_???_??_???_00")
-//   def C_FSW   = BitPat("b????????????????_111_?_??_???_??_???_00")
+//   def C_FSW   = BitPat("b????????????????_111_?_??_???_??_???_00") // RV32FC Only
   def C_SD       = BitPat("b????????????????_111_?_??_???_??_???_00")
 
   // RVC 01
@@ -100,7 +100,7 @@ object RVCInstr extends HasInstrType with HasRVCConst {
   def C_FLDSP   = BitPat("b????????????????_001_?_??_???_??_???_10")
 //   def C_LQSP    = BitPat("b????????????????_001_?_??_???_??_???_10")
   def C_LWSP    = BitPat("b????????????????_010_?_??_???_??_???_10")
-  def C_FLWSP   = BitPat("b????????????????_011_?_??_???_??_???_10")
+//  def C_FLWSP   = BitPat("b????????????????_011_?_??_???_??_???_10") // RV32FC Only
   def C_LDSP    = BitPat("b????????????????_011_?_??_???_??_???_10")
   def C_JR      = BitPat("b????????????????_100_0_??_???_00_000_10")
   def C_MV      = BitPat("b????????????????_100_0_??_???_??_???_10")
@@ -110,7 +110,7 @@ object RVCInstr extends HasInstrType with HasRVCConst {
   def C_FSDSP   = BitPat("b????????????????_101_?_??_???_??_???_10")
 //   def C_SQSP    = BitPat("b????????????????_101_?_??_???_??_???_10")
   def C_SWSP    = BitPat("b????????????????_110_?_??_???_??_???_10")
-  def C_FSWSP   = BitPat("b????????????????_111_?_??_???_??_???_10")
+//  def C_FSWSP   = BitPat("b????????????????_111_?_??_???_??_???_10") // RV32FC Only
   def C_SDSP    = BitPat("b????????????????_111_?_??_???_??_???_10")
 
   // TODO: HINT
@@ -121,10 +121,8 @@ object RVCInstr extends HasInstrType with HasRVCConst {
   val table = Array(
     C_ILLEGAL    -> List(InstrN, FuType.csr, CSROpType.jmp),
     C_ADDI4SPN   -> List(InstrI, FuType.alu, ALUOpType.add),
-    // C_FLD        -> List(InstrI, FuType.alu, ALUOpType.add),
     C_LW         -> List(InstrI, FuType.lsu, LSUOpType.lw),
     C_LD         -> List(InstrI, FuType.lsu, LSUOpType.ld),
-    // C_FSD        -> List(InstrI, FuType.alu, ALUOpType.add),
     C_SW         -> List(InstrS, FuType.lsu, LSUOpType.sw),
     C_SD         -> List(InstrS, FuType.lsu, LSUOpType.sd),
     C_NOP        -> List(InstrI, FuType.alu, ALUOpType.add),
@@ -147,27 +145,23 @@ object RVCInstr extends HasInstrType with HasRVCConst {
     C_BEQZ       -> List(InstrB, FuType.alu, ALUOpType.beq),
     C_BNEZ       -> List(InstrB, FuType.alu, ALUOpType.bne),
     C_SLLI       -> List(InstrI, FuType.alu, ALUOpType.sll),
-    // C_FLDSP      -> List(InstrI, FuType.alu, ALUOpType.add),
     C_LWSP       -> List(InstrI, FuType.lsu, LSUOpType.lw),
-    // C_FLWSP      -> List(InstrI, FuType.alu, ALUOpType.add),
     C_LDSP       -> List(InstrI, FuType.lsu, LSUOpType.ld),
     C_JR         -> List(InstrI, FuType.alu, ALUOpType.jalr),
     C_MV         -> List(InstrR, FuType.alu, ALUOpType.add),
     C_EBREAK     -> List(InstrI, FuType.alu, ALUOpType.add),
     C_JALR       -> List(InstrI, FuType.alu, ALUOpType.jalr),
     C_ADD        -> List(InstrR, FuType.alu, ALUOpType.add),
-    // C_FSDSP      -> List(InstrI, FuType.alu, ALUOpType.add),
     C_SWSP       -> List(InstrS, FuType.lsu, LSUOpType.sw),
-    // C_FSWSP      -> List(InstrI, FuType.alu, ALUOpType.add),
     C_SDSP       -> List(InstrS, FuType.lsu, LSUOpType.sd)
   )
 
    val cExtraTable = Array(
     C_ADDI4SPN   -> List(ImmADD4SPN, REGx2, DtCare, REGrs2p),
-    // C_FLD        -> List(),
+    C_FLD        -> List(ImmLD, REGrs1p, DtCare, REGrs2p),
     C_LW         -> List(ImmLW, REGrs1p, DtCare, REGrs2p),
     C_LD         -> List(ImmLD, REGrs1p, DtCare, REGrs2p),
-    // C_FSD        -> List(),
+    C_FSD        -> List(ImmSD, REGrs1p, REGrs2p, DtCare),
     C_SW         -> List(ImmSW, REGrs1p, REGrs2p, DtCare),
     C_SD         -> List(ImmSD, REGrs1p, REGrs2p, DtCare),
     C_NOP        -> List(ImmNone, DtCare, DtCare, DtCare),
@@ -190,20 +184,18 @@ object RVCInstr extends HasInstrType with HasRVCConst {
     C_BEQZ       -> List(ImmB, REGrs1p, DtCare, DtCare), // rd: x0
     C_BNEZ       -> List(ImmB, REGrs1p, DtCare, DtCare), // rd: x0
     C_SLLI       -> List(ImmLI, REGrd, DtCare, REGrd),
-    // C_FLDSP      -> List(),
+    C_FLDSP      -> List(ImmLDSP, REGx2, DtCare, REGrd),
     // C_LQSP       -> List(),
     C_LWSP       -> List(ImmLWSP, REGx2, DtCare, REGrd),
-    // C_FLWSP      -> List(),
     C_LDSP       -> List(ImmLDSP, REGx2, DtCare, REGrd),
     C_JR         -> List(ImmNone, REGrs1, DtCare, DtCare),
     C_MV         -> List(ImmNone, REGrs2, DtCare, REGrd),
     C_EBREAK     -> List(ImmNone, DtCare, DtCare, DtCare), //not implemented
     C_JALR       -> List(ImmNone, REGrs1, DtCare, REGx1),
     C_ADD        -> List(ImmNone, REGrd, REGrs2, REGrd),
-    // C_FSDSP      -> List(),
+    C_FSDSP      -> List(ImmSDSP, REGx2, REGrs2, DtCare),
     // C_SQSP       -> List(),
     C_SWSP       -> List(ImmSWSP, REGx2, REGrs2, DtCare),
-    // C_FSWSP      -> List(),
     C_SDSP       -> List(ImmSDSP, REGx2, REGrs2, DtCare)
    )
 

src/main/scala/noop/isa/RVD.scala

@@ -4,6 +4,7 @@ import Chisel.BitPat
 import noop._
 import noop.SrcType.{fp, imm, reg}
 import RVF_FPUInstr.{Y, N}
+import RVCInstr._
 import fpu.FPUIOFunc._
 import fpu.FPUOpType._
 
@@ -12,7 +13,11 @@ object RVD_LSUInstr extends HasInstrType{
   def FSD = BitPat("b?????????????????011?????0100111")
   val table = Array(
     FLD -> List(InstrI, FuType.lsu, LSUOpType.ld),
-    FSD -> List(InstrS, FuType.lsu, LSUOpType.sd)
+    C_FLD -> List(InstrI, FuType.lsu, LSUOpType.ld),
+    C_FLDSP -> List(InstrI, FuType.lsu, LSUOpType.ld),
+    FSD -> List(InstrS, FuType.lsu, LSUOpType.sd),
+    C_FSD -> List(InstrS, FuType.lsu, LSUOpType.sd),
+    C_FSDSP -> List(InstrS, FuType.lsu, LSUOpType.sd)
   )
 }
 
@@ -52,7 +57,11 @@ object RVD_FPUInstr extends HasNOOPParameter {
   //  (isFp, src1Type, src2Type, src3Type, rfWen, fpWen, fuOpType, inputFunc, outputFunc)
   val table = Array(
     FLD -> List(Y, reg, imm, imm, N, Y, LSUOpType.ld, in_raw, out_raw),
+    C_FLD -> List(Y, reg, imm, imm, N, Y, LSUOpType.ld, in_raw, out_raw),
+    C_FLDSP -> List(Y, reg, imm, imm, N, Y, LSUOpType.ld, in_raw, out_raw),
     FSD -> List(Y, reg, fp, imm, N, N, LSUOpType.sd, in_raw, out_raw),
+    C_FSD -> List(Y, reg, fp, imm, N, N, LSUOpType.sd, in_raw, out_raw),
+    C_FSDSP -> List(Y, reg, fp, imm, N, N, LSUOpType.sd, in_raw, out_raw),
     // fp fp -> fp
     FADD_D   -> List(Y, fp, fp, imm, N, Y, fadd, in_raw, out_raw),
     FSUB_D   -> List(Y, fp, fp, imm, N, Y, fsub, in_raw, out_raw),

src/main/scala/noop/isa/RVF.scala

@@ -2,7 +2,6 @@ package noop.isa
 
 import Chisel.BitPat
 import chisel3._
-import fpu.FPUIOFunc
 import noop._
 import noop.SrcType._
 import fpu.FPUOpType._

src/test/csrc/difftest.cpp

@@ -74,6 +74,10 @@ static const char *reg_name[DIFFTEST_NR_REG] = {
   "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
   "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
   "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6",
+  "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
+  "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
+  "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
+  "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11",
   "this_pc",
   "mstatus", "mcause", "mepc",
   "sstatus", "scause", "sepc"
@@ -114,7 +118,7 @@ int difftest_step(uint64_t *reg_scala, uint32_t this_inst,
 
   ref_difftest_getregs(&ref_r);
 
-  uint64_t next_pc = ref_r[32];
+  uint64_t next_pc = ref_r[DIFFTEST_THIS_PC];
   pc_retire_pointer = (pc_retire_pointer+1) % DEBUG_RETIRE_TRACE_SIZE;
   pc_retire_queue[pc_retire_pointer] = this_pc;
   inst_retire_queue[pc_retire_pointer] = this_inst;

src/test/csrc/difftest.h

@@ -14,9 +14,9 @@ typedef uint16_t ioaddr_t;
 
 #include "macro.h"
 
-// 0~31: GPRs
+// 0~31: GPRs, 32~63 FPRs
 enum {
-  DIFFTEST_THIS_PC = 32,
+  DIFFTEST_THIS_PC = 64,
   DIFFTEST_MSTATUS,
   DIFFTEST_MCAUSE,
   DIFFTEST_MEPC,

src/test/csrc/emu.h

@@ -37,6 +37,10 @@ class Emulator {
     macro(8); macro(9); macro(10); macro(11); macro(12); macro(13); macro(14); macro(15);
     macro(16); macro(17); macro(18); macro(19); macro(20); macro(21); macro(22); macro(23);
     macro(24); macro(25); macro(26); macro(27); macro(28); macro(29); macro(30); macro(31);
+    macro(32); macro(33); macro(34); macro(35); macro(36); macro(37); macro(38); macro(39);
+    macro(40); macro(41); macro(42); macro(43); macro(44); macro(45); macro(46); macro(47);
+    macro(48); macro(49); macro(50); macro(51); macro(52); macro(53); macro(54); macro(55);
+    macro(56); macro(57); macro(58); macro(59); macro(60); macro(61); macro(62); macro(63);
     r[DIFFTEST_THIS_PC] = dut_ptr->io_difftest_thisPC;
     r[DIFFTEST_MSTATUS] = dut_ptr->io_difftest_mstatus;
     r[DIFFTEST_SSTATUS] = dut_ptr->io_difftest_sstatus;

src/test/scala/top/NOOPSim.scala

@@ -11,7 +11,7 @@ import bus.axi4._
 import device.AXI4RAM
 
 class DiffTestIO extends Bundle {
-  val r = Output(Vec(32, UInt(64.W)))
+  val r = Output(Vec(64, UInt(64.W)))
   val commit = Output(Bool())
   val thisPC = Output(UInt(64.W))
   val thisINST = Output(UInt(32.W))