Rename: send phy-reg status(rdy/busy) to dispatch-2

src/main/scala/xiangshan/Bundle.scala

@@ -57,6 +57,7 @@ class Redirect extends XSBundle {
   val brTag = UInt(BrTagWidth.W)
   val isException = Bool()
   val roqIdx = UInt(RoqIdxWidth.W)
+  val freelistAllocPtr = UInt(PhyRegIdxWidth.W)
 }
 
 class Dp1ToDp2IO extends XSBundle {

src/main/scala/xiangshan/backend/Backend.scala

@@ -12,7 +12,7 @@ import xiangshan.backend.brq.Brq
 import xiangshan.backend.dispatch.{Dispatch1, Dispatch2}
 import xiangshan.backend.exu._
 import xiangshan.backend.issue.IssueQueue
-import xiangshan.backend.regfile.Regfile
+import xiangshan.backend.regfile.{Regfile, RfWritePort}
 import xiangshan.backend.roq.Roq
 
 
@@ -89,6 +89,8 @@ class Backend(implicit val p: XSConfig) extends XSModule
   dispatch1.io.roqIdxs <> roq.io.roqIdxs
 
   dispatch2.io.in <> dispatch1.io.out
+  dispatch2.io.intPregRdy <> rename.io.intPregRdy
+  dispatch2.io.fpPregRdy <> rename.io.fpPregRdy
   intRf.io.readPorts <> dispatch2.io.readIntRf
   fpRf.io.readPorts <> dispatch2.io.readFpRf
 
@@ -98,12 +100,25 @@ class Backend(implicit val p: XSConfig) extends XSModule
   val wbFpReqs = (fmacExeUnits ++ fmiscExeUnits ++ fmiscDivSqrtExeUnits).map(_.io.out)
   val intWbArb = Module(new WriteBackArbMtoN(wbIntReqs.length, NRWritePorts))
   val fpWbArb = Module(new WriteBackArbMtoN(wbFpReqs.length, NRWritePorts))
+  val wbIntResults = intWbArb.io.out
+  val wbFpResults = fpWbArb.io.out
+
+  def exuOutToRfWrite(x: Valid[ExuOutput]) = {
+    val rfWrite = Wire(new RfWritePort)
+    rfWrite.wen := x.valid
+    rfWrite.addr := x.bits.uop.pdest
+    rfWrite.data := x.bits.data
+    rfWrite
+  }
 
   intWbArb.io.in <> wbIntReqs
-  intRf.io.writePorts <> intWbArb.io.out
+  intRf.io.writePorts <> wbIntResults.map(exuOutToRfWrite)
 
   fpWbArb.io.in <> wbFpReqs
-  fpRf.io.writePorts <> fpWbArb.io.out
+  fpRf.io.writePorts <> wbFpResults.map(exuOutToRfWrite)
+
+  rename.io.wbIntResults <> wbIntResults
+  rename.io.wbFpResults <> wbFpResults
 
   roq.io.exeWbResults <> exeWbReqs
 

src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala

@@ -13,6 +13,9 @@ class Dispatch2 extends XSModule with NeedImpl {
     // read regfile
     val readIntRf = Vec(NRReadPorts, Flipped(new RfReadPort))
     val readFpRf = Vec(NRReadPorts, Flipped(new RfReadPort))
+    // read reg status (busy/ready)
+    val intPregRdy = Vec(NRReadPorts, Input(Bool()))
+    val fpPregRdy = Vec(NRReadPorts, Input(Bool()))
 
     // enq Issue Queue
     val enqIQCtrl = Vec(exuConfig.ExuCnt, DecoupledIO(new MicroOp))

src/main/scala/xiangshan/backend/exu/Exu.scala

@@ -4,7 +4,6 @@ import chisel3._
 import chisel3.util._
 import xiangshan._
 import xiangshan.FuType._
-import xiangshan.backend.regfile.RfWritePort
 
 case class ExuConfig
 (
@@ -113,7 +112,7 @@ trait HasExeUnits{
 class WriteBackArbMtoN(m: Int, n: Int) extends XSModule with NeedImpl {
   val io = IO(new Bundle() {
     val in = Vec(m, Flipped(DecoupledIO(new ExuOutput)))
-    val out = Vec(n, Flipped(new RfWritePort))
+    val out = Vec(n, ValidIO(new ExuOutput))
   })
 }
 

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -8,7 +8,13 @@ class Rename extends XSModule with NeedImpl {
   val io = IO(new Bundle() {
     val redirect = Flipped(ValidIO(new Redirect))
     val roqCommits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit)))
+    val wbIntResults = Vec(NRWritePorts, Flipped(ValidIO(new ExuOutput)))
+    val wbFpResults = Vec(NRWritePorts, Flipped(ValidIO(new ExuOutput)))
+    val intPregRdy = Vec(NRReadPorts, Output(Bool()))
+    val fpPregRdy = Vec(NRReadPorts, Output(Bool()))
+    // from decode buffer
     val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl)))
+    // to dispatch1
     val out = Vec(RenameWidth, DecoupledIO(new MicroOp))
   })
 }