Background:
dtlb has 128 entries stored in sram. 128 sets, 1 ways.
advantage: large volume & 1 ways means no tag match logic at data select path
disadvantage: 128 sets means long latency at valid select, which is a Vec-Register.

Optimization: divide valid select into two-cycles

This commit optimizes the timing of freelist by changing the updating
function of headPtr and tailPtr.

We maintains an one-hot representation of headPtr and further uses it to
read the free registers from the list, which should be better than the
previous implementation where headPtr is used to indexed into the queue.

The update of tailPtr and the freelist is delayed by one cycle to
optimize the timing. Because freelist allocates new registers in the
next cycle iff there are more than RenameWidth free registers in this
cycle. The freed registers in this cycle will never be used in the next
cycle. Thus, we can delay the updating of queue data to the next cycle.
We also move the update of tailPtr to the next cycle, since PopCount
takes a long timing and we move the last adder to the next cycle. Now
the adder works parallely with PopCount. That is, the updating of
tailPtr is pipelined.

Added chisel-db to dump hw data into a database automatically

This commit adds a buffer after the function unit that operate across
the integer block and the floating-point block, such as f2i and i2f.

For example, previously the out.ready of f2i depends on whether
mul/div/csr/jump has a valid instruction out, since f2i has lower
priority than them. This ready back-propagates from the integer function
units to the floating-point function units, and finally to the
floating-point reservation stations (since f2i is fully pipelined).

We add a buffer after the function unit to break this ready
back-propagation. It incurs one more cycle of execution latency, but we
leave it not-fully-optimized for now.

Timing can be further optimized if we separates the int writeback and fp
writeback in function units. In the current version, the ready of f2i
affects the ready of f2f pipelines, which is unnecessary. This is the
future work.

This commit adds some registers for performance counters to optimize
the timing. Pipelines are added.

This commit changes the lsrc/psrc of LUI in dispatch instead of
decode to optimize the timing of lsrc in DecodeStage, which is
critical for rename table.

lsrc/ldest should be directly get from instr for the timing. Fused
instructions change lsrc/ldest now, which will be optimized later.

* buspmu: avoid inner space in perf-cnt name

* perfcnt: judge regularity of perfname

* perfcnt: fix some irregular perfname

* bump huancun

FoldedSRAMTemplate: hold ridx when holdRead is set

<bug-fix>: fix IFU misOffset bug and optimize code

ubtb: fix write waymask of fallThruPred

ittage: we should write new target when alloc

last_may_be_rvi_call in case that a call comes after a taken branch

* bump difftest

* ci: support basic simv emulation

* ci: use exact ip address to ssh

* ci: modify simv emulation timeout threshold

* add SRAM ready (resetfinish) condition for *Array (metaArray/dataArray)
req.ready

* fix mmio_resend_af wrong assignment
* fix wb_half_flush missOffset(using wb_lastIdx instead of PredictWidth
-1)
* change pipeline ready condition (this_ready =  this_stage_fire || this_stage_empty)
* delete 500-cycle ready condition (toICache(*).ready means the SRAM has
been reset and ready for read)

* bump huancun, update Chisel3, revert sram hazard enhancement

* util.sram: rm a r/w hazard mux which is not needed. bump huancun

Previous logic checked the value of old_ctr to select between old target and
new target when updating ittage table. However, when we need to alloc a new
entry, the value of old_ctr is X because we do not reset ittage table. So we
would definitely write an X to the target field, which is the output of the
mux, as the selector is X.

* fix for chipsalliance/rocket-chip#2967

* decode: fix width of BitPat(?) in decode logic
Co-authored-by: NYinan Xu <xuyinan@ict.ac.cn>

Previously we made a mistake to connect rtc_clock to rtcTick for CLINT.

rtcTick should be on io_clock clock domain and asserted only one
clock cycle in io_clock for every cycle in rtc_clock. We add sampling
registers in this commit to fix this.

sramtemplate: fix waymask in FoldedSRAMTemplate

Provide two issue template.

* difftest: disable runahead to make vcs happy

* difftest: bump huancun to make vcs happy

* difftest: bump difftest and ready-to-run

* difftest support ramsize and paddr base config
* 8GB/16GB nemu so are provided by ready-to-run

* ci: update nightly ci, manually set ram_size

* difftest: bump huancun to make vcs happy

* difftest,nemu: support run-time assign mem size

* ci: polish nightly ci script

An instruction with exceptions may have arbitrary instr values and
may be decoded into WFI instructions, which cause errors.