Merge pull request #1587 from OpenXiangShan/chisel-db

Added chisel-db to dump hw data into a database automatically

difftest @ 7204a60b

-Subproject commit 540af7a595fa86f8585ffe97c9a82000c1d9cb68
+Subproject commit 7204a60b2e52453fdac0877402a8bbc09bec6e44

huancun @ a47ce2c2

-Subproject commit 1c8a3bfac0d40a25f4d5b6a5549313c0a5eed906
+Subproject commit a47ce2c2872a667330fcf50b04668a6db3a18e23

src/test/scala/top/SimTop.scala

@@ -21,9 +21,13 @@ import chisel3._
 import chisel3.util._
 import chisel3.stage.ChiselGeneratorAnnotation
 import device.{AXI4RAMWrapper, SimJTAG}
+import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule, LazyModuleImp}
+import utils.GTimer
+import xiangshan.{DebugOptions, DebugOptionsKey}
 import difftest._
 import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule}
 import freechips.rocketchip.util.ElaborationArtefacts
+import huancun.utils.ChiselDB
 import top.TopMain.writeOutputFile
 import utils.GTimer
 import xiangshan.DebugOptionsKey
@@ -119,8 +123,14 @@ object SimTop extends App {
       DisableMonitors(p => new SimTop()(p))(config),
       firrtlComplier
     )
-    ElaborationArtefacts.files.foreach{ case (extension, contents) =>
-      writeOutputFile("./build", s"XSTop.${extension}", contents())
+    ChiselDB.addToElaborationArtefacts
+    ElaborationArtefacts.files.foreach{
+      case (extension, contents) =>
+        val prefix = extension match {
+          case "h" | "cpp" => "chisel_db"
+          case _ => "XSTop"
+        }
+        writeOutputFile("./build", s"$prefix.${extension}", contents())
     }
   }
 }